Extended Line Driver DSLAM applications Using standard CMOS techn
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39705/3LQ Preliminary
Extended Line Driver DSLAM applications
Using standard CMOS technologies Seven power modes (0.4 enables optimized line card power dissipation Typically (VBAT power dissipation during full rate COoperation when device operating idle mode Analog echo cancellation (better than relaxes requirements AD/DA converter high integration level requires minimum external components more robust design LQFP package (0°C 85°C) Figure Line driver application.
750k
6-11V
VDD1 OTPO OTPR
SUBH
VDD2
VBAT
45.3 Line transformer
OTPR IREF Receive
AD/DA
05/3
VSS3 VSS3
POTS Splitter
Line
45.3
RVREF2.2 VSS1 DCLK VSS2 VBAT
6-11V
Description
Ericsson Analog Receive/Transmit Interface Circuit (ARTIC) DSLAM applications analog line driver receiver circuit providing driving terminating functions needed implementation ADSL transceiver. interface circuit includes line driver, receiver, echo cancellation, termination programmable gain controllers. ARTIC line driver serve both full rate ADSL ADSL Lite, according recommendations G.dmt G.Lite respectively, supports annex (ADSL over POTS) annex (ADSL over ISDN). ARTIC line driver designed CO-applications. Power consumption minimized line driver architecture design optimized ADSL. optimized design ARTIC line driver also ensures compact board design with minimum area wiring. CO-application, dual power supply used provide full line drive capability. applied supply voltage driver output varied between depending required output swing 16.5 differential). Further, design ARTIC line driver relaxes requirements mixed signal part ADSL transceiver, with integrated analog echo cancellation, which cancel more than transmitted signal, intelligent programmable feedback loop providing optimal line termination. further reduce power dissipation, seven power modes introduced, which used shorter lines reduce power dissipation when bitrate demands lower.
05/3 Absolute Maximum Ratings
Parameter Condition Symbol Unit Comment
Storage Temperature Range Operating Junction Temperature Range Operating Ambient Temperature Range Thermal Resistance, junction ambient, LQFP-32 Supply Voltages VDD1, VDD2, with respect VSS1 Supply Voltages VBAT, with respect VSS1 Analog Voltage Input Range, with respect VSS1 Digital Voltage Input Range, with respect VSS1 Continuous Power Dissipation 0°C< TAmb <+85°C 0°C< TAmb <+85°C 0°C< TAmb <+85°C 0°C< TAmb <+85°C TAmb +85°C
TStg TAmb VDDx VBAT VAnalog VDigital PDmax
42.1 -0.3 -0.3 -0.3 -0.3
+150 +120
°C/W
Multilayer card 1m/s flow
+6.5 +11.5 VDD1+0.3 VDD1+0.3
Recommended Operating Conditions
Parameter Condition Symbol Unit Comment
Operating Ambient Temperature Range Supply Voltage With respect VSS1 With respect VSS2 With respect VSS3
TAmb VDD1 VDD2 VBAT
4.75 4.75 VDD1 10.5
5.25 5.25 11.0
figure
Maximum Ambient Temperature
Maximum power dissipation LQFP when transmitting multitone, assumed that maximum junction temperature maximum ambient temperature Rthja 47.9 °C/W with airflow liters/min Rthja 42.1 °C/W with airflow liters/min Rthja 39.4 °C/W with airflow liters/min
1400
Pdmax
Flow (l/min) Temp. 1040 1020
1300 1200 1100 1000
1070 1140 1190 1270
Figure Ambient temperature.
Default Conditions
Unless otherwise noted specification applies default general conditions using default external components default device programming. General Conditions
Condition Symbol Value Unit Comment
Power Supplies except VBAT Power Supply Receive bias voltage Ambient Temperature
VDD1, VDD2 VDD3 VRRef TAmb
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3
External Components application
Component Symbol Value Unit Tol. Comment
Line Transformer Line Capacitors series resistors shunt resistors series capacitors Bias Current Setting Resistor band Filter Capacitor Receive Path Capacitor CVDD Decoupling Capacitor VDD1 CVDD Decoupling Capacitors VDD2, Transmit Input Coupling Capacitor Receive Output Coupling Capacitor
CLA, RSA, RSHA, RSHB CSA,
45.3
RREF 24.3 CVDD1 VBAT, CVDD2, CVBAT CTP, CRP,
least 45dB balance better echo cancellation 0.25W 0.25W 63V, 0.03 @80kHz 0.1W
example Schott 32828 Fuse S560-6600-AB: values given application where this Schott transformer used.
External components application
Common lines
VBAT
DCLK VSS2 VBAT
VBAT
VBAT VBAT
VSS3 VSS3
VSS1 VREF2.2 VDD1
39705
LINE
IREF
CODEC
VBAT
VBAT
VBAT
VDD2
SUBH
OTPR
OTPO
ROTP
Figure External components application. External components during test
VBAT
DCLK
VSS2
VBAT
VBAT
VSS1 IREF VREF2.2 VDD1
VSS3 VSS3
39705/3
VBAT
VBAT
VBAT
VDD2
SUBH
OTPR
OTPO
ROTP
Figure External components during setup.
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3
External Components During Test
Component Symbol Value Unit Tol. Comment
Line Load series resistors Bias Current Setting Resistor CVDD Decoupling Capacitor VDD1 CVDD Decoupling Capacitors VDD2, VBAT Transmit Input Coupling Capacitor
RSA, RREF CVDD1 CVDD2, CVBAT
24.3
0.25W 0.25W 0.1W
Electrical Characteristics
Power Dissipation Supply Currents
Parameter Condition Symbol Unit
Supply Currents
VBAT 10.0V 6.0V Power Down mode (PD=5V), ADSL signal VBAT 10.0V Power mode (PD=0V), ADSL signal P2P1P0 "111" VBAT 10.0V Power mode (PD=0V), ADSL signal VBAT 10.0V Power mode transmitting ADSL signal -40dBm/Hz, 0.15-1.1MHz, TX-PGC +16.5dB
IDD1 IDD2 IBAT IDD1 IDD2 IBAT IDD1 IDD2 IBAT IDD1 IDD2 IBAT
11.5 11.5 10.0 24.0 23.0 69.0 20.0 25.0 72.0
10.0 10.0
On-chip Power Consumption Supply Currents
12.5 12.5
On-chip Power Consumption Supply Currents
25.0 24.5 73.0
mArms mArms mArms
On-chip Power Consumption Supply Currents
On-chip Power Dissipation
Note power dissipated external impedances included On-Chip power, since this power dissipated board.
Power Supply Rejection Ratio
Parameter Condition Symbol Unit Comment
PSRR Line)
VPSRR=0.1VPP, f=550kHz RX-PGC="00000"=+25.2dB, TX-PGC="00000"=+21.5dB from from VBAT
PSRRTDD PSRRTBAT
PSRR Receive output)
VPSRR=0.1VPP, 25kHz <138kHz, RX-PGC="00000"=+25.2dB, TX-PGC="00000"=+21.5dB from PSRRRDD from VBAT PSRRRBAT
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3
Digital Interface, levels
Parameter Condition Symbol Unit Comment
Input Voltage Input Voltage High Input Current Input Capacitance Output Voltage OutputVoltage High
VDD1 (@VIL), IIH(@VIH) IIL,
3.2mA
Digital Interface, timing
Parameter Condition Symbol Unit Comment
Data clock frequency Rise fall times
Applicable range with rise fall times <10ns digital input waveforms
fMCLK
Reference Voltages Currents
Parameter Condition Symbol Unit
VREF2.2 voltage IREF voltage
VVRef2.2 VIRef
1.20
1.25 1.30
Line Driver Characteristics
Parameter Condition Symbol Unit Comment
Differential Output Offset Voltage* Longitudinal Output Offset Voltage Differential Input Offset Voltage TXIN Common Mode input Offset Voltage TXIN
input signal, Input offset VVTXIN-VVTXINB TX-PGC="00000"=21.5dB Output Offset voltage, VSB1-VSB2, open circuit load input signal, Input offset VVTXIN-VVTXINB Relative VBAT/2, TX-PGC="00000"=21.5dB VLong (VSB1 VSB2)/2
VLIN
-1000
1000
VOLine
-150
VTXINO
Relative VREF2.2
VTXInLong
Note above table 'LINE' refers currents voltages primary (25W) side line output transformer. current flowing through transformer easily calculated from open circuit offset using Equation below. Open circuit offset voltage Shunt Resistor complex impedance network 11.5 Resistance transformer winding
Receive Path Characteristics
Parameter Condition Symbol Unit Commemt
RP-RN Differential Output Voltage Longitudinal Output Voltage
Input signal, RX-PGC "00000" (+25.2dB), Measured with RLoad input signal, Relative VRREF, RX-PGC "00000" (+25.2dB)
VRXDiff
-200
VRXLong
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3
Line Driver Termination Impedance
Parameter Condition Symbol Unit Comment
Differential output impedance
Measured differentially across load pins (SB1, SB2) with RAB=2.2W f=25kHz Control word "10000" (default) Control word "00000" (min) Control word "11111" (max) ZTLINE(10000) ZTLINE(00000) ZTLINE(11111) DZTLINE
Output impedance step size Termination impedance frequency response Termination impedance phase shift
Measured differentially across load pins (SB1, SB2) with RSX=2.2W f=500kHz Default control word ="10000" Impedance 1.1MHz relative impedance 25kHz Default control word ="10000" Impedance phase 1.1MHz relative impedance 25kHz Default control word ="10000"
ZTf1.1M
FZTf1.1M
Over Temperature Protection
Parameter Condition Symbol Unit
Temperature Temperature
TOFF
Line Driver Transmission Characteristics
Parameter Comment Driver output Clip voltage Slew rate Condition VTXIN, TX-PGC "00000" (+21.5dB), VDD1=VDD2=5.0V, VBAT 10.0V, measure VSB1-VSB2 2Vpp input square wave, Output measured differentially SB1, Slew rate measured rising falling edges between levels. =0.1Vrms fsine 25kHz, "00000" (21.5dB) fsine 1.1MHz, "00000" (21.5dB) fsine 25kHz, "01110" (7.5dB) fsine 1.1MHz, "01110" (7.5dB) fsine 25kHz, "10101" (0.5dB) fsine 1.1MHz, "10101" (0.5dB) Signal TXIN LINE Vin=0.1Vrms, fsine=1.1MHz DGTX=GTX(25kHz) (1100kHz) Signal TXIN/TXINB SB1/SB2 Symbol VOLCLIP 15.1 15.2 Unit
SRLINE
V/ms
Absolute differential voltage gain, TXIN LINE
GTX25 GTX1.1M GTX25 GTX1.1M GTX25 GTX1.1M
21.4 21.6
21.8 22.0
22.2 22.4
Frequency response TX-PGC step size Phase response Differential phase error*
DGTX TXSTP
-0.15
Vin=0.1Vrms, fsine=1.1MHz DfTXD=fTX(25kHz) fTX(1100kHz) Signal TXIN/TXINB SB1/SB2 Vin=0.1Vrms, fsine=1100kHz, phase VOLDC=40%of VOLCLIP rel. phaseatVOLDC=0V
fTXD
fTXDE
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3
Line Driver Transmission Characteristics continued
Parameter SFDR, sine output, single tone Condition TX-PGC= "00111" (+14.5dB) fsine fsine fsine fsine =25kHz, 8.0Vpp output =138kHz, 8.0Vpp output =250kHz, 8.0Vpp output =400kHz, 8.0Vpp output SFDR25k SFDR138k SFDR250k SFDR400k SFDR14 SFDR1 Symbol Unit Comment
fsine =400kHz, 14.0Vpp output fsine =400kHz, 1.0Vpp output MTPR transmit multitone
fmultitone=150kHz 1.1MHz, MTPR measured relative notches, Power Mode=2 TX-Band 150kHz-1.1MHz MTPR5.0TX @bin37=160kHz, bin57=245kHz, bin117=504kHz bin174=750kHz, bin234=1MHz, PAR=5.0 bin37=160kHz, bin57=245kHz, bin117=504kHz, MTPR3.8TX bin174=750kHz,bin234=1MHz, PAR=3.8 PAR=3.8, PSD=-40dBm/Hz (11.7Vpp), TX-PGC=15.5dB PAR=5.0, PSD=-40dBm/Hz (15.4Vpp), TX-PGC=17.5dB fmultitone=150kHz 1.1MHz, MTPR measured relative Rx-band, Power Mode=2 300Hz-4.3kHz, PAR=5.0 (Speech Band) MTPR 25-138kHz, PAR=5.0 Band) MTPR5RX 300Hz-4.3kHz, PAR=3.8 (Speech Band) MTPR 25-138kHz, PAR=3.8 Band) MTPR3RX driver output PAR=3.8, PSD=-40dBm/Hz (11.7Vpp), TX-PGC=15.5dB PAR=5.0, PSD=-40dBm/Hz (15.4Vpp), TX-PGC=17.5dB fmultitone=150kHz 1.1MHz, MTPR measured relative Of-band: 1.1MHz driver output Power Mode=2 MTPR5.0OB PAR=3.8, PSD=-40dBm/Hz (11.7Vpp) MTPR3.8OB PAR=5.0, PSD=-40dBm/Hz (15.4Vpp) input signal. TXP, connected VREF2.2. Noise floor measured across SB1, SB2, TX-PGC= "00111" (+14.5dB) 300Hz-4.3kHz 25kHz-138kHz 150kHz-1.1MHz 1.1MHz-11.04MHz
MTPR transmit multitone -into band
51.5 41.0
59.0 51.5
MTPR transmit multitone -into "out band" band Idle noise floor output
36.0
39.0
NFLINEidle
-92.0 -104.0 -107.5 -109.0
-87.0 dBm/Hz into -101.0 -106.0 -107.5
Unbalance_TL Vin=1Vrms, measured load midpoint, ratio (dB) Differential signal across load. 25kHz 500kHz 1.1MHz Unbalance_LT load 1Vrms, measure VSB1-VSB2, ratio (dB) Differential signal across load. 25kHz 500kHz 1.1MHz input impedance
UNBTL
-34.5 -34.5 -31.0
UNBLT
ZinTX
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3 Receive Path Transmission Characteristics
Parameter Receive output clip voltage Receive output slew rate Condition VLINE=2Vpp, fsine=25kHz, RxPGC "00000" (25.2dB), measured differentially ROUTP/ROUTN, *)VBAT 10V. Symbol VRXOCLIP Unit Comment
2Vpp input square wave, Output measured SRRO differentially ROUTP/ROUTN. Slew rate measured rising falling edges between levels, RX-PGC="10100" (6.2dB) VLINE=0.2Vpp (input SB1/SB2), fsine=25kHz, RX-PGC="10111" (3.2dB), measure LINE Receive output ROUTP/ROUTN, TX-PGC "00111" (+14.5dB) RX-PGC "00000" (+25.2dB), @25kHz VLINE=0.2Vpp, fsine=138kHz, RX-PGC="00110" (20.2dB) DGRX=GRX (25kHz) (138kHz) measure gain LINE ROUTP/ROUTN
V/ms
Absolute differential voltage gain
23.2
23.6
24.0 -0.3
Frequency response
Phase response
Vin=0.2Vpp, fsine=138kHz, RX-PGC="10001" DfRX (+9.2dB) DfRX fRX(25kHz) (138kHz) measure phase LINE ROUTP/ROUTN 0.2Vpp sine wave f=138kHz, RXPGC="10001" (+9.2dB), phase VRXOUTDC VRXOCLIP relative phase VRXOUTDC TX-PGC "00111" (+14.5dB) RX-PGC="00000" (+25.2dB) fsine 25kHz, ULINE 0.11Vpp, 2.0Vpp fsine =138kHz, ULINE 0.11Vpp, 2.0Vpp RX-PGC="00000" (+25.2dB) fsine 138kHz, ULINE 0.22Vpp, 4.0Vpp fsine =138kHz, ULINE =0.165Vpp, =3.0Vpp fsine =138kHz, ULINE =0.055Vpp, =1.0Vpp fRXE
Differential phase error*
0.25
RxPGC step size SFDR, sine
RxPGC_stp
SFDRRA25k SFDRRA138k
SFDRRC4 SFDRRC3 SFDRRC1
71.5
68.0 68.0 68.0
MTPR-into band, multitone
VinLINE 0.39Vpp, 3.8, RX-PGC="00110" (+20.2dB) fmultitone 25kHz 138kHz MTPR measured relative notches @bin13=56063kHz MTPRR6 @bin24=103.5kHz input signal, RxPGC= "00000" (+25.2dB) Noise Floor transformed LINE 300Hz 4.3kHz 25kHz 138kHz 150kHz 1.1MHz 1.1MHz 11.0MHz
idle noise floor
NFidleRX
-122.0 dBm/ -121.0 into -125.0 -128.0
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3 Transmit Receive Path Characteristics (Echo Cancellation)
Parameter Echo cancellation multitone Condition multitone 150kHz-1.1MHz applied TXP/TXN, 2.0Vpp, PAR=5.0, PSDLINE -40dBm/Hz, TX-PGC="00100" (+16.5dB), RxPGC= "00000" (+25.2dB) Power Mode Echo_cancellation spectrum(LINE)-spectrum(RXOUT) Echo Canc, @f=150kHz, Echo Canc, @f=500kHz, Echo Canc, @f=1.1MHz, MTPR transmit multitone -into band fmultitone=150kHz-1.1MHz, MTPR measured relative Rx-band: Power Mode=2 25kHz, PAR=5.0 138kHz, PAR=5.0 25kHz, PAR=3.8 138kHz, PAR=3.8 EC150k EC500k EC1.1M Symbol Unit Comment
MTPR 5RA1 MTPR 5RA2 MTPR 3RA1 MTPR 3RA2
Output, RX-PGC="00000" (+25.2dB) PAR=3.8, PSD=-40dBm/Hz (11.7Vpp), TX-PGC=+15.5dB PAR=5.0, PSD=-40dBm/Hz (15.4Vpp), TX-PGC=+17.5dB Echo cancellation singletone TX:single tone with applied TXP/TXN, 1.5Vpp, TX-PGC "00111"(+14.5dB), RxPGC "00000" (+25.2dB) Echo_cancellation RXOUT, transformed LINE Echo Canc, 150kHz, fundamental, first spurious, 2xfs second spurious, 3xfs Echo Canc, 400kHz, fundamental, first spurious, 2xfs second spurious, 3xfs EC150k0 EC150k1 EC150k2 EC40k0 EC400k1 EC400k2 25.5 19.5 30.5 28.0 26.0 35.0 30.0 31.0 33.0 34.0 40.0 41.0
Apply multitone measure fundamental levels LINE Transform this fundamental level RXOUT adding RX-PGC factor Measure spectrum RXOUT calculate MTPR from fundamental level calculated
Transmitter Output Spectral Mask
required spectral mask from standard met, provided that driver connected line proposed hybrid (transformer LINE capacitor combination) provided that driver driven from with least lower distortion noise floor than 39705/3 path. figure
Balance Longitudinal Transversal
39705/3 12.5
(dBm/Hz) -36.5dBm/Hz peak
12.5
uLONG
21dB/oct Transmit Band MTPR 38dB transmitted total :+19.8dBm
36dB/oct
Balance 20log(uT/uL)
Balance Transversal Longitudinal
-97.5dBm/Hz -110dBm/Hz
39705/3 12.5 12.5 Balance 20log(u L/uT) uLONG
25.875
1104
4545
(kHz)
Figure Transmitted spectral mask.
Figure Longitudinal balance measurement.
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3 Description
SUBH OTPO OTPR VDD2 VBAT VBAT
VDD1 VREF2.2 IREF VSS1
39705
VSS3 VSS3
DCLK
VSS2
VBAT
Name VSS3 VSS3 VBAT
Description current sense input pins B-wire define current gain. Current voltage sense input B-wire define current gain impedance. Drive output line, B-wire. Ground Driver High Current Output Stage. Ground Driver High Current Output Stage. Drive output line, A-wire. Current voltage sense input A-wire define current gain impedance. current sense input pins A-wire define current gain. Battery sourcing drive output current (VBAT). Battery setting half supply voltage level drive output pins This normal connected same supply VBAT. Main positive supply input signal currents, except drive output currents. Connection substrate used isolate high voltage high current output transistors from voltage side reduce crosstalk substrate. Transmit input voltage, ~2.4kW internal 2.2V reference Over temperature protection resistor Over temperature protection output indicator, active high, used directly power down chip indicate high chip temperature. Transmit input voltage, ~2.4kW internal 2.2V reference. supply bias network digital serial register.
VBAT
Supply/GND
A/in
A/out
D/in
Misc Sensitive Sensitive
High High High High Sensitive Sensitive High High High Sensitive Sensitive
VBAT VDD2 SUBH OTPR OTPO VDD1
Sensitive High
VREF2.2 Buffered output internal 2.2Volt reference, used bias input circuit package bond-out arrangement also provide receive reference voltage, pin22, receive output. IREF use. Current bias generation. resistor ground, sets bias current internal circuits. Nominal resistor value used 25kW, could nearest preferred value. Receive output signal, differential with signal from receive signal appearing pins echo cancelled ~>20dB from transmit signal frequencies 300KHz. use. Receive output signal differential that Ground chip biasing connection substrate voltage side chip. also ground digital main ground chip. Active high, 3.3V compatible input power down chip except bandgap, on-chip temperature monitor other current circuits. Serial DATA signal input. 3.3V compatible Active pulsed DATA ENABLE input. 3.3V compatible. settings updated falling edge this signal. DATA CLOCK input. 3.3V compatible. Active high RESET input. 3.3V compatible. Resets defaults values Transmit gain, Receive gain, Impedance Standby negative edge. must pulsed during reset. Main signal ground chip, except drive output currents. Battery sourcing drive output current (VBAT). Battery sourcing drive output current (VBAT).
Sensitive
Sensitive
VSS1
High
DCLK
High High High
VSS2 VBAT VBAT
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3 LQFP package outline
Common dimensions
1.40 0.05 1.35 0.30 0.09
1.50 0.10 1.40 0.37 9.00
1.60 0.15 1.45 0.45 0.20
7.00 9.00 7.00 0.45 0.60 1.00
0.75
Functional Description
05/3LQ complete ADSL line interface circuit, optimized used Central Office (CO) side. Standard Requirements 05/3LQ complete integrated Analog line driver receiver ADSL (Assymetrical Digital Subscriber Line). device handles both full-rate ADSL (G.DMT standardized G.992.1 ANSI T1.413 Issue ADSL-Lite (G.Lite standardized G.992.2) Power Supplies 05/3LQ requires power supplies: VBAT (6-11V) final drive output stage, (5V) rest device. shall always 5.0V. applications with long lines recommended typical supply voltage VBAT 10.5V, line gets shorter, power supply (and thus power consumption) reduced. recommended power supply voltage
VDD(+5V) VBAT(+10V)
different output voltages given table drive outputs centred VBAT/2 level using longitudal loop. figure Serial digital control interface driver programmable order maximize performance minimize Power consumption. programmability controlled serial control interface. interface chip select signal (DEN), that enables same digital used line drivers line card, reducing board area. digital interface programmed from either 3.3V circuits. Figure following functions programmed Transmit gain (-1.7db +21.3dB steps). order able perform Power Back steps between -38dBm/Hz -52dBm/Hz, according ADSL standard. Receive gain (-4.7dB +25.3dB steps) order give high (Signal Noise Ratio) before converter line lengths.
2.2V TXIN 2.2V 2.2V 2.2V
Line Length (AWG
VBAT/2 VBAT/2 LINE
Uout (Vpp)
VBATmin
Figure Power supplies levels 05/3LQ.
GROUND
RXOUT
800m 600m 500m 400m 300m
16.4 13.3 10.7
10.5
Table Line length.
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3
Termination impedance (17-32.5W 0.5W steps) case user wants able tune impedance without changing external components. However, recommended, achieve best performance programmable impedance complex termination impedance described application drawing. Power mode device either power mode full ADSL transmission. remaining power modes (3-7), ADSL transmission also possible, with limited performance (could used example short lines lines which very noisy when data sent). figure Active Drive/Termination Impedance circuit able deliver 15.5Vpp into load, enough transmit ADSL signals between 150kHz 1.1MHz with Power Spectral Density (PSD) -40dBm/ into 100W transformer total power 19.8dBm (3.08Vrms) with (Peak Average Ratio) value 5.2, while receiving upstream band between 25kHz 138kHz, according ANSI (T1.413 Issue ETSI ADSL standards. line driver manages meet this performance with output stage between 10.5V total power consumption 850mW. This possible Ericsson Microelectronics patented active termination/ drive impedance scheme ADSL. figure active drive/termination impedance principle. active termination concept means that high ohmic series resistors needed series with driver output, which reduces power suppy voltage needed transmit given power line. that needed low-ohmic ADSL band) sense impedance series with output. Programmable transmit gain Programmable transmit gain enables power cut-back according standard easy implementation extended power cut-back. ANSI T1.413 requires that Transmitted Power Spectral Density (PSD) line should reduced steps from -40dBm/Hz down -52dBm/Hz when line length (and line damping) reduced.
Power Down
05/3LQ power down function (through pin), that completely shuts down circuit. This directly connected OTPO (the Over Temperature detection Output), that circuit automatically shut down during error conditions. Integrated Over Temperature Protection order protect circuit from damage during error conditions, such short circuit, there on-chip over temperature detection circuit (OTP). During overtemperature conditions digital over temperature detector output (OTPO) high either monitored system processor connected directly Power Down 05/3LQ. degrees centigrade built-in hysteresis avoid thermal oscillation effects. figure
VBAT VBAT 6-11V
ROTP
VDD2 SUBH VDD2 VBAT VBAT
OTPO OTPRTVP
VDD1 VDD1
39705/3
Drive
gain
VREF2.2 RREF TX-PGC
VSS3 VSS3
Bias
IREF
STBY
RSHA
LINE
+25dB
RX-PGC
RSHB
VSS1
Drive Control
DCLK
VSS2
VBAT
VBAT VBAT 6-11V
VBAT
Overview.
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3
05/3LQ been designed meet this requirement when connected converters amplifiers) with output swing between 1.5Vpp 4.0Vpp. also possible adjust transmit power, since TX-PGC step 1dB. TX-PGC controlled through serial control interface. principle calculating internal Transmit Gain shown figure Differential Input- Output Interfaces transmit input interface differential voltage interface. driver should connected output from coupling capacitors. maximum transmit input swing 4Vpp, inputs have common-mode level 2.2V. figure Receive output interface also differential voltage type. outputs should connected external AC-coupling capacitors converter input. maximum output swing 4Vpp. outputs have common mode level 2.2V. figure Integrated echo cancellation circuit ADSL system, performance parameter MTPR (Multi Tone Power Ratio) receive signal. order maximize MTPR, 05/3LQ integrated echo canceller that removes around 25dB transmitted signal from Receive Path. order further reduce transmitted echo signal receiver, first order pass filter with corner frequency 300kHz been integrated. 10kHz high pass filter also integrated receive path reduce POTS signals. important note that only fundamental transmitted tones that echocancelled, also noise distortion from driver will cancelled receive path. This enables higher transmit distortion noise transmit path without sacrificing bitrate. figure
choose
good echo cancellation achieved when drive/ termination impedance 39705 matches load impedance (the line seen through transformer high-pass filter LINE capacitors). expression termination impedance given ZOut 11.5
signal either tied ground, connected OTPO each LINE (reset) signal tied Ground.
PBM39705/3
LINE1
DIN/DCLK (Common) DEN1
PBM39705/3
DSP/ Control
digital levels
DEN2
LINE2
OTPO High
PBM39705/3
LINE3
DEN3
Hyst
PBM39705/3
LINE#N
DEN#N
=130 =145
Figure Digital control routing multiline board.
Figure Over Temperature Protection (OTP).
Static
1200 1000
Dynamic
1200 1000
Figure Static dynamic power consumption active mode VBAT (VDD=5.0V).
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3
optimum performance, must chosen specific transformer line capacitor combination. proposed solution from Ericsson Microelectronics Schott transformer 32828 combination with 150nF LINE high pass filter capacitors. Ericsson Microelectronics also provide other transformer/LINE capacitor combinations request. propsed optimized give best impedance matching ADSL-band AWG26 (0.4mm) cable, proposed will work fine AWG24 (0.5mm) cable well. figure termination/drive impedance 39705/3LQ obtained using: ZOut 11.5 (1+2pf Rsh) impedance equation above shall matched with load impedance driver, terminated transmission line seen through transformer LINE high-pass filter capacitors. High range Receive Programmable Gain (PGC) signal levels after echo cancellation very low. order maximal MTPR converter input, signal level must boosted match optimal input swing converter. This achieved using Programmabe Receive Gain (PGC). gain from line driver output Receive outputs varied serial digital interface steps between -4.7dB +25.3dB. Normally lower values used shorter lines higher PGC's used longer lines. used will from during training sequence ADSL connection.
factor 11.5 valid nominal impedance setting: "10000" varied between 15.0.
Equivalent Circuit
Spectrum LINE
TXIN
LINE
Noise Dist
MTPR
Ohmic Sense Impedance,
ZT=ZL/2
MTPR 4.3kHz
Noise Dist Floor
Ohmic Sense Impedance, ZT=ZL/2
Figure Drive impedance.
DRIVE1 05/3 RXOUT DRIVE2
TX-PGC=20log(uo/uin)
Figure spectrum LINE.
Spectrum RXOUT
Echo Cancellation
TXIN
LINE
MTPR
Dist Cancellation Noise Dist Floor
Figure Calculating transmit gain (TX-PGC).
Figure spectrum receive output.
SA1,2
4.0Vpp Common Mode 2.2V
SB1,2
Schott 32828 BelFuse S560-6600_AB 45.3 680nF
Rsh)
4.8k
Figure differential transmit input interface.
4.0Vpp Common Mode 2.2V
Figure Proposed
05/3
Secondary Protection
Primary Protection
Figure differential receive output interface.
Figure Over Voltage Protection.
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3
Over Voltage Protection Central Office protection, recommended primary protection outside transformer secondary protection inside transformer, moment, Ericsson Microelectronics proposal scheme 39705/3LQ, this scheme need verified practically. Resetting device There default programming device. This default word automatically loaded into register when device reset. figure There ways resetting device without sending serial data Power Reset Once power supply applied device, 05/3LQ will reset automatically. Reset Provided that held low, 05/3LQ reset once high. Once reset been made, must brought again, ensure proper function programming.
Programming Device
device programmed using Serial Data Control Interface (DIN, DCLK DEN). Serial Control Word bits wide. sent first sent last. Data clocked each clock cycle, positive edge. After bits have been read signal should pulsed settings take effect. figure Important! board with many lines must high, before serial data word could sent.
Transmit Gain bits)
Receive Gain bits)
Term. Impedance bits)
Power bits)
fmax 35MHz fmin 100kHz
DCLK
Programming Settings Take Effect
Figure function serial control interface.
fmax 35MHz fmin 100kHz
Reset taking effect
Driver
Line Through Hybrid
100k
frequency (Hz)
Figure Resetting device.
Figure Impedance matching between line driver line (AWG cable) seen through transformer high pass filter capacitors.
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3 Transmit Gain Control (TX-PGC) Supporting Full Power Back
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 TxPGC (res TxPGC (complex 21.5 20.5 19.5 18.5 17.5 16.5 15.5 14.5 13.5 12.5 11.5 10.5 -0.5 -1.5 21.3 20.3 19.3 18.3 17.3 16.3 15.3 14.3 13.3 12.3 11.3 10.3 -0.7 -1.7dB Valid -"-"-"-"-"-"-"Use when transmitting with dBm/Hz 5.3x from when transmitting with dBm/Hz 5.3x from when transmitting with dBm/Hz 5.3x from Default when reset when transmitting with dBm/Hz 5.3x from Comments 150kHz
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3 Receive Gain Control (RX-PGC)
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11010 11011 11100 11101 11110 11111 (res +25.2 +25.2 +24.2 +23.2 +22.2 +21.2 +20.2 +19.2 +18.2 +17.2 +16.2 +15.2 +14.2 +13.2 +12.2 +11.2 +10.2 +9.2 +8.2 +7.2 +6.2 +5.2 +4.2 +3.2 +2.2 +0.2 -0.8 -1.8 -2.8 -3.8 -4.8
(complex
Comments 80kHz upstream Receive Band) used long lines
+25.3 +25.3 +24.3 +23.3 +22.3 +21.3 +20.3 +19.3 +18.3 +17.3 +16.3 +15.3 +14.3 +13.3 +12.3 +11.3 +10.3 +9.3 +8.3 +7.3 +6.3 +5.3 +4.3 +3.3 +2.3 +0.3 -0.7 -1.7 -2.7 -3.7 -4.7
Default when reset
used line when using with Uinmax 4.0Vpp used line when using with Uinmax 3.0Vpp
high Receive needed take full advantage built-in echo cancellation echo filtering 39705. Receive used should decided during ADSL training sequence. total signal line dominated transmitted downstream signal compared received upstream signal, except very short lines. fully integrated echo cancellation circuitry effectively removes around 30dB transmitted signal from
receiver, which means improved dynamic range upstream receive signal convertor, relaxing requirements converter linearity resolution. lowest shall ensure that ADSL connection line without clipping output signal.
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3 Termination Impedance Control (ZT)
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 after transformer. 68.0W 70.0W 72.0W 74.0W 76.0W 78.0W 80.0W 82.0W 84.0W 86.0W 88.0W 90.0W 92.0W 94.0W 96.0W 98.0W 100.0W 102.0W 104.0W 106.0W 108.0W 110.0W 112.0W 114.0W 116.0W 118.0W 120.0W 122.0W 124.0W 126.0W 128.0W 130.0W transformer. 17.0W 17.5W 18.0W 18.5W 19.0W 19.5W 20.0W 20.5W 21.0W 21.5W 22.0W 22.5W 23.0W 23.5W 24.0W 24.5W 25.0W 25.5W 26.0W 26.5W 27.0W 27.5W 28.0W 28.5W 29.0W 29.5W 30.0W 30.5W 31.0W 31.5W 32.0W 32.5W Default when reset Comment
impedances given table achieved when using pure resistive 2.2W. order achieve higher upstream bitrate, recommended complex termination impedance making complex figure doing echo cancellation improved considerably, enabling higher RX-PGC increasing MTPR converter, relaxing converter resolution requirements. When using complex termination impedance scheme, target should make output impedance equal
impedance line seen through transformer LINE capacitors. proposed values from figure give best impedance matching cable ADSL band values used assumed that programmable impedance code "10000" 25W). When using complex termination impedance, value programmable impedance less.
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
05/3 Power modes
76mA 67mA 58mA 49mA 40mA 31mA 21mA 13mA IBATqui* 40mA 36mA 32mA 29mA 25mA 22mA 18mA 14mA IDDqui** Power Power Power Power Power Power Power Power Function Comment Allowing full transmission both directions Full transmission Recommended high applications (lines with noice), Default when reset Full transmission Good enough 400kbit/s, 4Mbit/s with ETSI noise Slight degradation bitrate Only recommended "sleep mode" Tx-path disabled, Rx-path active, Should used
Standing Current high voltage part Standing Current voltage part order save power sleep mode, "100" code recommended power consumption then reduced 525mW. this mode, still possible receive wake-up signal from CPE.
Terminology
ADDA: Analogue Digital, Digital Analogue converter circuit ADSL: Assymetric Digital Subscriber Line Central Office CPE: Customer Premises Equipment Echo Cancellation FDM: Frequency Division Multiplex GBD: Guaranteed Design MTPR: Multi-Tone Power Ratio OTP: Over-Temperature Protection OVP: Over Voltage Protection PAR: Peak-to-Average Ratio PGC: Programmable Gain Control POTS: Plain Telephony System Receive Direction SFDR: Spurious Free Dynamic Range SNR: Signal Noise Ratio TBD: Defined
Ordering Information
Package 32-pin LQFP temp range part 05/3LQ
EN/LZT 83R1A ©Ericsson Microelectronics, November 2001
Ericsson Microelectronics
SE-164 Kista, Sweden Telephone: 5000 Internet: local sales contacts, please refer website call: 4700, Fax: 4776
Preliminary Data Sheet
EN/LZT Ericsson Microelectronics January 2002
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