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SN54AHC16245, SN74AHC16245 16-BIT TRANSCEIVERS WITH 3-STATE OUTPUTS
Members Texas Instruments Widebus Family Operating Range 5.5-V EPIC (Enhanced-Performance Implanted CMOS) Process Distributed Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes Layout Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54AHC16245 PACKAGE SN74AHC16245 DGG, DGV, PACKAGE (TOP VIEW)
description
'AHC16245 devices 16-bit (dual-octal) noninverting 3-state transceivers designed synchronous two-way communication between data buses. control-function implementation minimizes external timing requirements. These devices used 8-bit transceivers 16-bit transceiver. They allow data transmission from from bus, depending logic level direction-control (DIR) input. output-enable (OE) input used disable device that buses effectively isolated.
ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. SN54AHC16245 characterized operation over full military temperature range -55°C 125°C. SN74AHC16245 characterized operation from -40°C 85°C.
FUNCTION TABLE (each 8-bit section) INPUTS OPERATION data data Isolation
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PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
Copyright 1998, Texas Instruments Incorporated
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PRODUCT PREVIEW
1DIR 2DIR
SN54AHC16245, SN74AHC16245 16-BIT TRANSCEIVERS WITH 3-STATE OUTPUTS
logic symbol
1DIR 2DIR [BA] [AB] [BA] [AB]
PRODUCT PREVIEW
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
logic diagram (positive logic)
1DIR 2DIR
Seven Other Channels
Seven Other Channels
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SN54AHC16245, SN74AHC16245 16-BIT TRANSCEIVERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Output voltage range, (see Note -0.5 Input clamp current, Output clamp current, VCC) Continuous output current, VCC) Continuous current through each Package thermal impedance, (see Note package 89°C/W package 93°C/W package 94°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD
SN54AHC16245 Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current 3.85 1.65
SN74AHC16245 3.85 1.65
UNIT
ns/V
Input transition rise fall rate
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
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recommended operating conditions (see Note
SN54AHC16245, SN74AHC16245 16-BIT TRANSCEIVERS WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS inputs GND, (OE) inputs GND, 2.58 3.94 0.36 0.36 ±0.1 ±0.1 ±0.25 25°C SN54AHC16245 2.48 ±2.5 SN74AHC16245 2.48 0.44 0.44 ±2.5 UNIT
PRODUCT PREVIEW
parameter includes input leakage current.
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER tPLH* tPHL* tPZH* tPZL* tPHZ* tPLZ* tPLH tPHL tPZH tPZL tPHZ tPLZ tsk(o) FROM (INPUT) (OUTPUT) LOAD CAPACITANCE 25°C 11.5 11.5 13.2 13.2 12.5 12.5 11.9 11.9 16.7 16.7 15.8 15.8 1.5** SN54AHC16245 15.5 15.5 15.5 15.5 13.5 13.5 SN74AHC16245 15.5 15.5 15.5 15.5 13.5 13.5 UNIT
products compliant MIL-PRF-38535, this parameter production tested. products compliant MIL-PRF-38535, this parameter does apply. Skew between outputs same package switching same direction
POST OFFICE 655303
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SN54AHC16245, SN74AHC16245 16-BIT TRANSCEIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER tPLH* tPHL* tPZH* tPZL* tPHZ* tPLZ* tPLH tPHL tPZH tPZL tPHZ tPLZ tsk(o) FROM (INPUT) (OUTPUT) LOAD CAPACITANCE 25°C 10.6 10.6 SN54AHC16245 SN74AHC16245 UNIT
products compliant MIL-PRF-38535, this parameter production tested. products compliant MIL-PRF-38535, this parameter does apply. Skew between outputs same package switching same direction
noise characteristics, 25°C (see Note
PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic Quiet output, minimum dynamic Quiet output, minimum dynamic High-level dynamic input voltage SN74AHC16245 -0.9 UNIT
VIL(D) Low-level dynamic input voltage NOTE Characteristics surface-mount packages only.
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS load, UNIT
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SN54AHC16245, SN74AHC16245 16-BIT TRANSCEIVERS WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
Open
From Output Under Test (see Note
Test Point
From Output Under Test (see Note
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain
Open
LOAD CIRCUIT TOTEM-POLE OUTPUTS
LOAD CIRCUIT 3-STATE OPEN-DRAIN OUTPUTS Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES tPZL Output Waveform (see Note Output Waveform (see Note tPZH tPLZ tPHZ
Input
PRODUCT PREVIEW
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
tPHL
Output Control
tPLH
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement.
Figure Load Circuit Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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