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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.

Renesas Technology Corp. Customer Support Dept. April 1, 2003

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
1. DESCRIPTION
The M37151M6 / M8 / MA / MC / MF-XXXFP and M37151EFFP are single-chip microcomputers designed with CMOS silicon gate technology. They have an OSD, data slicer, and I2C-BUS interface, making them perfect for TV channel selection systems with a closed caption decoder. The M37151EFFP has a built-in PROM that can be written electrically.
(It is possible to display 3 lines or more by software) Kinds of characters ............................ 254 kinds (coloring unit) (per charactor unit) Character display area .............. CC mode: 16 26 dots OSD mode: 16 20 dots Kinds of character sizes ................... CC mode: 1 kind OSD mode: 8 kinds Kinds of character colors ................. 8 colors (R, G, B) Coloring unit .......... character, character background, raster Display position Horizontal: 128 levels Vertical: 512 levels Attribute ............................................ CC mode: smooth italic, underline, flash, automatic solid space OSD mode: border Smooth roll-up Window function
2. FEATURES
3. APPLICATION
TV with closed caption decoder
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
TABLE OF CONTENTS
1. DESCRIPTION ................................ 1 2. FEATURES .................................. 1 3. APPLICATION ................................ 1 4. PIN CONFIGURATION ......................... 3 5. FUNCTIONAL BLOCK DIAGRAM ................. 4 6. PERFORMANCE OVERVIEW .................... 5 7. PIN DESCRIPTION ............................ 7 8. FUNCTIONAL DESCRIPTION ................... 11 8.1 CENTRAL PROCESSING UNIT (CPU) ..... 11 8.2 MEMORY ............................ 12 8.3 INTERRUPTS ......................... 17 8.4 TIMERS ............................. 22 8.5 SERIAL I / O ........................... 26 8.6 MULTI-MASTER I2C-BUS INTERFACE ..... 29 8.7 PWM OUTPUT FUNCTION .............. 42 8.8 A-D COMPARATOR .................... 46 8.9 ROM CORRECTION FUNCTION .......... 48 8.10 DATA SLICER ........................ 49 8.11 OSD FUNCTIONS .................... 60 8.11.1 Display Position ................. 65 8.11.2 Dot Size ....................... 69 8.11.3 Clock for OSD .................. 70 8.11.4 Field Determination Display ........ 71 8.11.5 Memory for OSD ................ 73 8.11.6 Character color ................. 77 8.11.7 Character background color ........ 77 8.11.8 OUT signals .................... 78 8.11.9 Attribute ....................... 79 8.11.10 Multiline Display ................ 84 8.11.11 Automatic Solid Space Function .... 85 8.11.12 Window Function ............... 86 8.11.13 OSD Output Pin Control .......... 88 8.11.14 Raster Coloring Function ......... 89 8.12 SOFTWARE RUNAWAY DETECT FUNCTION .. 91 8.13 RESET CIRCUIT ..................... 92 8.14 CLOCK GENERATING CIRCUIT ......... 93 8.15 OSD OSCILLATION CIRCUIT ........... 97 8.16 AUTO-CLEAR CIRCUIT ................ 98 8.17 ADDRESSING MODE ................. 98 8.18 MACHINE INSTRUCTIONS ............. 98 9. PROGRAMMING NOTES ...................... 98 10. ABSOLUTE MAXIMUM RATINGS ............... 99 11. RECOMMENDED OPERATING CONDITIONS ..... 99 12. ELECTRIC CHARACTERISTICS .............. 100 13. A-D CONVERTER CHARACTERISTICS ......... 102
Rev. 1.0
14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS ... 102 15. PROM PROGRAMMING METHOD ............. 103 16. DATA REQUIRED FOR MASK ORDERS ........ 103 17. ONE TIME PROM VERSION M37151EFFP MARKING ....... 104 18. APPENDIX ................................ 105 19. PACKAGE OUTLINE ........................ 136
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
4. PIN CONFIGURATION
P11 / SCL1 P00 / PWM0 P01 / PWM1 P02 / PWM2 P03 / PWM3 / AD1 P04 / PWM4 / AD2 P05 / AD3 P06 / INT2 / AD4 P07 / INT1 P20 / SCLK / AD5 P21 / SOUT / AD6 P22 / SIN / AD7 P23 / TIM3 P24 / TIM2 P25 / INT3 P26 / XCIN P27 / XCOUT CNVSS XIN XOUT VSS
P12 / SCL2 P13 / SDA1 P14 / SDA2 P16 / AD8 / TIM2 P50 / HSYNC P51 / VSYNC P52 / B P53 / G P54 / R P55 / OUT CLKCONT / P10 P30 / SDA3 P31 / SCL3 P15 10K
Outline 42P2R
Fig. 4.1 Pin Configuration (Top View)
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
RESET CVIN VHOLD HLF FLIT VCC
Rev. 1.0
INT1 INT2 INT3
AD1-8
PWM4 PWM3 PWM2 PWM1 PWM0
I / O port P30, P31
Output for display Output port
P52-P55
OUT R G B VSYNC HSYNC
I / O ports P26, P27 Pins for data slicer
V CC V SS CNVSS
Clock Clock input output sub-clock input sub-clock output
XC OUT XC IN CV IN V HOLD HLF
Reset input
RESET
Clock generating circuit
TIM2 TIM3
Data slicer
Fig. 5.1 Functional Block Diagram of M37151
Timer count source selection circuit Timer 1 T1 (8) Timer 2 T2 (8) Timer 3 T3 (8) Timer 4 T4 (8) Timer 5 T5 (8) Timer 6 T6 (8) Instruction register (8) Instruction decoder OSD circuit Control signal
Program counter
Data bus
5. FUNCTIONAL BLOCK DIAGRAM
ROM correction circuit ROM PCL (8)
Progam counter
PCH (8)
Address bus
8-bit arithmetic and logical unit
Index register
Accumulator A (8) Y (8)
Index register
Processor status register PS (8)
Stack pointer S (8)
A-D comparator
Multi-master I 2 C-BUS interface
Correction function
P0 (8) P2 (8) P3 (2)
P1 (7)
Synchronous signal input Input port
P50, P51
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
6. PERFORMANCE OVERVIEW
P20-P27
P30, P31 P50, P51 P52-P55 Serial I / O Multi-master A-D comparator PWM output circuit Timers ROM correction function Subroutine nesting Interrupt
I / O Input Output
Clock generating circuit Data slicer
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
7. PIN DESCRIPTION
Table 7.1 PIN DESCRIPTION Pin VCC, VSS CNVSS
Name Power source CNVSS Reset input
Input / Output This is connected to VSS. Input
RESET
XIN XOUT
Clock input Clock output
Input Output
P00 / PWM0- P02 / PWM2, P03 / PWM3 / AD1, P04 / PWM4 / AD2, P05 / AD3, P06 / INT2 / AD4, P07 / INT1
PWM output External interrupt input Analog input
Output Input Input I / O I / O Output Input Input I / O I / O Output Input Input Input Input Output Input I / O I / O
P10 / CLK CONT, I / O port P1 P11 / SCL1, P12 / SCL2, P13 / SDA1, P14 / SDA2, P15, P16 / AD8 / TIM2 Multi-master I2C-BUS interface Clock control External clock input for timer Analog input P20 / SCLK / AD5, I / O port P2 P21 / SOUT / AD6, P22 / SIN / AD7, Serial I / O synchronous clock input / output port P23 / TIM3, P24 / TIM2, P25 / INT3, P26 / XCIN, P27 / XCOUT Serial I / O data output Serial I / O data input External clock input for timer Analog input Sub-clock input Sub-clock output External interrupt input P30 / SDA3 P31 / SCL3 I / O port P3 Multi-master I2C-BUS Interface
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Table 7.2 PIN DESCRIPTION (continued) Pin Name Input / Output Input Input Input output output Port P5 is a 2-bit input port. The P50 pin is also used as a horizontal synchronous signal input HSYNC for OSD. The P51 pin is also used as a vertical synchronous signal input VSYNC for OSD. Pins P52-P55 are a 4-bit output port. The output structure is CMOS output. Pins P52-P55 are also used as OSD output pins R, G, B and OUT respectively. The output structure is CMOS output. Input the composite video signal through a capacitor. Connect a capacitor between VHOLD and Vss. Connect a filter consisting of a capacitor and a resistor, between HLF and Vss. Connect a capacitor between FILT and Vss. Functions
P50 / HSYNC Input P5 P51 / VSYNC Horizonta synchronous signal Vertical synchronous signal P52 / B, P53 / G, P54 / R, P55 / OUT CVIN VHOLD HLF FILT Clock oscillation filter Output P5 OSD output
I / O for data slicer
Input Input I / O Input
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Ports P00-P07 Direction register
N-channel open-drain output
Data bus
Port latch
Ports P00-P07 Note : Each port is also used as follows :
P0 0-P04 : PWM0-PWM4 P05: AD3 P06: INT2 / AD4 P07: INT1
Ports P1, P2, P30, P31 Direction register
Data bus
Port latch
CMOS output
Ports P1, P2, P30, P31
Notes 1 : Each port is also used as follows : P20 : SCLK / AD5 P10 : CLKCONT P21 : SOUT / AD6 P11 : SCL1 P22 : SIN / AD7 P12 : SCL2 P13 : SDA1 P23 : TIM3 P24 : TIM2 P14 : SDA2 P25 : INT3 P16 : AD8 / TIM2 P26 : XCIN
P27 : XCOUT P30 : SDA3 P31 : SCL3
2: The output structure of ports P11-P14, P30-P31 is N-channel open-drain output when using as multi-master I2C-BUS interface (it is the same with P00-P07). 3: The output structure of ports P20 and P21 is N-channel open-drain output when using as serial output (it is the same as P00-P07).
Fig. 7.1 I / O Pin Block Diagram (1)
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
P50, P51
P52-P55
CMOS input
CMOS output Ports P52-P55 Note : Each pin is also used as follows : P52 : B P53 : G P54 : R P55 : OUT
Internal circuit
Ports P50, P51 Note : Each pin is also used as follows : P50 : HSYNC P51 : VSYNC
Internal circuit
Fig. 7.2 I / O Pin Block Diagram (2)
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8. FUNCTIONAL DESCRIPTION 8.1 CENTRAL PROCESSING UNIT (CPU)
8.1.1 CPU Mode Register
The CPU mode register includes the stack page selection bit and internal system clock selection bit. The CPU mode register is allocated at address 00FB16.
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 1 1 0 0 CPU mode register (CM) Address 00FB16 B Name 0, 1 Processor mode bits (CM0, CM1) Functions
After reset R W 0 R W
Stack page selection bit (CM2) (See note)
0 0: Single-chip mode 0 1: 1 0: Not available 1 1: 0: 0 page 1: 1 page
3, 4 Fix these bits to "1." 5 XCOUT drivability selection bit (CM5) 6 Main Clock (XIN-XOUT) stop bit (CM6) 7 Internal system clock selection bit (CM7) 0: LOW drive 1: HIGH drive 0: Oscillating 1: Stopped 0: XIN selected (high-speed mode) 1: XCIN-XCOUT selected (low-speed mode)
Note. This bit is set to "1" after the reset release.
Fig. 8.1.1 CPU Mode Register
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.2 MEMORY 8.2.1 Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains control registers such as I / O ports and timers.
8.2.6 Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
8.2.7 Zero Page
The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
8.2.2 RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
8.2.8 Special Page 8.2.3 ROM
ROM is used for storing user programs as well as the interrupt vector area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
8.2.4 OSD RAM
RAM for display is used for specifying the character codes and colors to display.
8.2.9 ROM Correction Memory (RAM)
This is used as the program area for ROM correction.
8.2.5 OSD ROM
ROM for display is used for storing character data.
s M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
000016 M37151MF-XXXFP, M37151EFFP RAM (2048 bytes) M37151M6XXXFP RAM (1024 bytes) M37151MB-XXXFP RAM (1152 bytes) M37151MA / MCXXXFP RAM (1472 bytes) 00BF16 00C016 00FF16 010016 01FF16 020016 020F16 030016 032016 053F 16 05BF16 06FF16 Not used OSD RAM (128 bytes) 080016 087F16 Not used 090016 0B3F 16 M37151MF-XXXFP, M37151EFFP ROM (60K bytes) M37151MC-XXXFP ROM (48K bytes) M37151MA-XXXFP ROM (40K bytes) M37151M8-XXXFP ROM (32K bytes) M37151M6-XXXFP ROM (24K bytes) 100016 4000 16 6000 16 8000 16 A00016 FF0016 FFDE16 FFFF16 Interrupt vector area 1FFFF16 Special page OSD ROM (10K bytes) (See note) 11400 16 13BFF16 Zero page SFR1 area 1000016
SFR2 area Not used ROM correction function Vector 1: address 0300 16 Vector 2: address 0320 16
Not used
Fig. 8.2.1 Memory Map (M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP)
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
s SFR1 Area (addresses C0 16 to DF16)
: No function bit 0 : Fix this bit to (do not write 1 : Fix this bit to (do not write 0 1) 1 0)
Address Register
C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 OSD control register 2(OC2) Interrupt input polarity control register (RE) Port P5(P5) OSD port control register (PF) Timer return set register (TMS) Clock control register 1 (CC1) Caption data register 3 (CD3) Caption data register 4 (CD4) OSD control register (OC) Horizontal position register (HP) Block control register 1(BC1) Block control register 2(BC2) Vertical position register 1(VP1) Vertical position register 2(VP2) Window register 1(WN1) Window register 2(WN2) I / O polarity control register (PC) Raster color register (RC) Port P0(P0) Port P0 direction register (D0) Port P1(P1) Port P1 direction register (D1) Port P2(P2) Port P2 direction register (D2) Port P3(P3) Port P3 direction register (D3)
Bit allocation
State immediately after reset
BSEL21 BSEL20
T2SC T3SC
OUTS P31D P30D
CDL26
CDL21
CDL20
PF5 PF4 PF3 PF2
CDL25
CDL24
CDL23
CDL22
CDL27
CDH27 CDH26 CDH25 CDH24 CDH23 CDH22 CDH21 CDH20
OC4 OC3 OC2 OC1 OC0
HP6 HP5 HP4 HP3 HP2 HP1 HP0
BC17 BC16 BC15 BC14 BC13 BC12 BC11 BC10 BC27 BC26 BC25 BC24 BC23 BC22 BC21 BC20 VP17 VP16 VP15 VP14 VP13 VP12 VP11 VP10 VP27 VP26 VP25 VP24 VP23 VP22 VP21 VP20 WN17 WN16 WN15 WN14 WN13 WN12 WN11 WN10 WN27 WN26 WN25 WN24 WN23 WN22 WN21 WN20
PC6 PC5
PC3 PC2 PC1 PC0 RC3 RC2 RC1 RC0
OC21 OC20
INT3 INT2 INT1
Fig. 8.2.2 Memory Map of Special Function Register 1 (SFR1) (1)
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
s SFR1 Area (addresses E0 16 to FF16)
: No function bit 0 : Fix this bit to (do not write 1 : Fix this bit to (do not write 0 1) 1 0)
Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA 16 FB16 FC16 FD16 FE16 FF16
Register
Bit allocation 1 0 1 0 0
DSC25 DSC24 DSC23
Data slicer control register 1 (DSC1) Data slicer control register 2 (DSC2) Caption data register 1 (CD1) Caption data register 2 (CD2) Clock run-in detect register (CRD) Data clock position register (DPS) Caption position register (CPS) Data slicer test register 2 Data slicer test register 1 Synchronous signal counter register (HC) Serial I / O register (SIO) Serial I / O mode register (SM) A-D control register 1 (AD1) A-D control register 2 (AD2) Timer 5 (T5) Timer 6 (T6) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer mode register 1 (TM1) Timer mode register 2 (TM2) I2C data shift register (S0) I2C address register (S0D) I2C status register (S1) I2C control register (S1D) I2C clock control register (S2)
DSC12 DSC11 DSC10
DSC20
CDL17 CDL16 CDL15 CDL14 CDL13 CDL12 CDL11 CDL10 CDH17 CDH16 CDH15 CDH14 CDH13 CDH12 CDH11 CDH10
CRD7 CRD6 CRD5 CRD4 CRD3 DPS7 DPS6 DPS5 DPS4 DPS3
CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0
HC5 HC4 HC3 HC2 HC1 HC0
SM6 SM5
ADC14
SM3 SM2 SM1 SM0
ADC12 ADC11 ADC10
ADC26 ADC25 ADC24 ADC23 ADC22 ADC21 ADC20
TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10 TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
MST TRX BB
AL AAS AD0 LRB
BSEL1 BSEL0 10BIT ALS ESO BC2 BC1 BC0 SAD FAST ACK ACK MODE CCR4 CCR3 CCR2 CCR1 CCR0 BIT
CM7 CM6 CM5 1 1 CM2 0 0 CPU mode register (CPUM) VSCR OSDR TM4R TM3R TM2R TM1R IN3R Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
TM56R IICR IN2R CKR S1R DSR IN1R CK0
IN3E VSCE OSDE TM4E TM3E TM2E TM1E
TM56C TM56E
IICE IN2E CKE S1E DSE IN1E
Fig. 8.2.3 Memory Map of Special Function Register 1 (SFR1) (2)
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
sSFR2 Area (addresses 20016 to 20F16)
: No function bit 0 : Fix this bit to (do not write 1 : Fix this bit to (do not write 0 1) 1 0)
Address
20016 20116 20216 20316 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16
Register
Bit allocation
State immediately after reset
PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4)
PWM mode register 1 (PM1) PWM mode register 2 (PM2) ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR)
PM24 PM23 PM22 PM21 PM20
RC1 RC0
20F16 210 Clock frequency set register (CFS) 211 Clock control register 2(CC2) 212 Clock control register 3(CC3)
Fig. 8.2.4 Memory Map of Special Function Register 2 (SFR2)
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Function bit
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Register
b7 Processor status register (PS) Program counter (PCH) Program counter (PCL)
Bit allocation N V T B D I Z C
State immediately after reset
Fig. 8.2.5 Internal State of Processor Status Register and Program Counter at Reset
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.3 INTERRUPTS
Interrupts can be caused by 17 different sources consisting of 4 external, 11 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities as shown in Table 8.3.1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, The contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag I is set to "1" and the corresponding interrupt request bit is set to "0." The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to "1." All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. Figures 8.3.2 to 8.3.6 show the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is "1, " interrupt request bit is "1, " and the interrupt disable flag is "0." The interrupt request bit can be set to "0" by a program, but not set to "1." The interrupt enable bit can be set to "0" and "1" by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 8.3.1 shows interrupt control.
8.3.1 Interrupt Causes (1) VSYNC, OSD interrupts
The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The OSD interrupt occurs after character block display to the CRT is completed.
(2) INT1 to INT3 external interrupts
The INT1 to INT3 interrupts are external interrupt inputs, the system detects that the level of a pin changes from LOW to HIGH or from HIGH to LOW, and generates an interrupt request. The input active edge can be selected by bits 3 to 5 of the interrupt input polarity register (address 00DC16) : when this bit is "0, " a change from LOW to HIGH is detected when it is "1, " a change from HIGH to LOW is detected. Note that both bits are cleared to "0" at reset.
(3) Timers 1 to 4 interrupts
An interrupt is generated by an overflow of timers 1 to 4.
Table 8.3.1 Interrupt Vector Addresses and Priority Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Reset OSD interrupt INT1 external interrupt Data slicer interrupt Serial I / O interrupt Timer 4 interrupt f(XIN) / 4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt INT3 external interrupt INT2 external interrupt Multi-master I2C-BUS interface interrupt Timer 5 · 6 interrupt BRK instruction interrupt Interrupt Source Vector Addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF716, FFF616 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFE316, FFE216 FFDF16, FFDE16 Source switch by software (see note) Non-maskable Active edge selectable Active edge selectable Active edge selectable Non-maskable Remarks
Note: Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program.
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(4) Serial I / O interrupt
This is an interrupt request from the clock synchronous serial I / O function.
(5) f(XIN) / 4096 interrupt
The f (XIN) / 4096 interrupt occurs regularly with a f(XIN) / 4096 period. Set bit 0 of the PWM mode register 1 to "0."
Interrupt request bit Interrupt enable bit
(6) Data slicer interrupt
An interrupt occurs when slicing data is completed.
Interrupt disable flag I
(7) Multi-master
I2C-BUS
interface interrupt
BRK instruction Reset
Interrupt request
This is an interrupt request related to the multi-master I2C-BUS interface.
(8) Timer 5 · 6 interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their priorities are same, and can be switched by software. Fig. 8.3.1 Interrupt Control
(9) BRK instruction interrupt
This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable).
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Request Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) Address 00FC16 B 0 1 2 3 4 5 6 7 Name Timer 1 interrupt request bit (TM1R) Timer 2 interrupt request bit (TM2R) Timer 3 interrupt request bit (TM3R) Timer 4 interrupt request bit (TM4R) OSD interrupt request bit (OSDR) VSYNC interrupt request bit (VSCR) INT3 external interrupt request bit (IN3R) Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Afrer reset R W 0 0 0 0 0 0 0 0 R R R R R R R R -
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
: "0" can be set by software, but "1" cannot be set.
Fig. 8.3.2 Interrupt Request Register 1
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) Address 00FD16 B 0 Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued
After reset R W
INT1 external interrupt request bit (IN1R) Data slicer interrupt 1 request bit (DSR) 2 Serial I / O interrupt request bit (SIR) 3 f(XIN) / 4096 interrupt request bit (CKR) 4 INT2 external interrupt request bit (IN2R) 2 5 Multi-master I C-BUS interrupt request bit (IICR) 6 Timer 5 · 6 interrupt request bit (TM56R) 7 Fix this bit to "0."
: "0" can be set by software, but "1" cannot be set.
Fig. 8.3.3 Interrupt Request Register 2
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) Address 00FE16 B Name Functions After reset R W 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R -
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 4 OSD interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled (OSDE) 5 VSYNC interrupt enable 0 : Interrupt disabled 1 : Interrupt enabled bit (VSCE) 0 : Interrupt disabled 6 INT3 external interrupt enable bit (IN3E) 1 : Interrupt enabled 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
0 Timer 1 interrupt enable bit (TM1E) 1 Timer 2 interrupt enable bit (TM2E) Timer 3 interrupt 2 enable bit (TM3E) 3 Timer 4 interrupt enable bit (TM4E)
Fig. 8.3.4 Interrupt Control Register 1
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) Address 00FF16 B 0 1 2 3 4 5 Name INT1 external interrupt enable bit (IN1E) Data slicer interrupt enable bit (DSE) Serial I / O interrupt enable bit (SIE) f(XIN) / 4096 interrupt enable bit (CKE) INT2 external interrupt enable bit (IN2E) Multi-master I2C-BUS interface interrupt enable bit (IICE)
After reset Functions 0 : Interrupt disabled 0 1 : Interrupt enabled 0 : Interrupt disabled 0 1 : Interrupt enabled 0 : Interrupt disabled 0 1 : Interrupt enabled 0 : Interrupt disabled 0 1 : Interrupt enabled 0 : Interrupt disabled 0 1 : Interrupt enabled
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Timer 5 1 : Timer 6
Timer 5 · 6 interrupt enable bit (TM56E) 7 Timer 5 · 6 interrupt switch bit (TM56C) 6
Fig. 8.3.5 Interrupt Control Register 2
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt input polarity register (RE) Address 00DC 16
Name INT1 polarity switch bit (INT1) INT2 polarity switch bit (INT2) INT3 polarity switch bit (INT3)
Functions 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity
After reset 0 0 0 0
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
Fig. 8.3.6 Interrupt Input Polarity Register
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.4 TIMERS
This microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 8.4.3. All of the timers count down and their divide ratio is 1 / (n+1), where n is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses 00EE16 and 00EF16 : timers 5 and 6), the value is also set to a timer, simultaneously. The count value is decremented by 1. The timer interrupt request bit is set to "1" by a timer overflow at the next count pulse, after the count value reaches "0016".
8.4.5 Timer 5
Timer 5 can select one of the following count sources: · f(XIN) / 16 or f(XCIN) / 16 · Timer 2 overflow signal · Timer 4 overflow signal The count source of timer 3 is selected by setting bit 6 of timer mode register 1 (address 00F416) and bit 7 of the timer mode register 2 (address 00F516). When overflow of timer 2 or 4 is a count source for timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 5 interrupt request occurs at timer 5 overflow.
8.4.6 Timer 6 8.4.1 Timer 1
8.4.2 Timer 2
Timer 2 can select one of the following count sources: · f(XIN) / 16 or f(XCIN) / 16 · Timer 1 overflow signal · External clock from the TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow.
8.4.3 Timer 3
Timer 3 can select one of the following count sources: · f(XIN) / 16 or f(XCIN) / 16 · f(XCIN) · External clock from the TIM3 pin The count source of timer 3 is selected by setting bit 0 of timer mode register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 3 interrupt request occurs at timer 3 overflow.
8.4.4 Timer 4
Timer 4 can select one of the following count sources: · f(XIN) / 16 or f(XCIN) / 16 · f(XIN) / 2 or f(XCIN) / 2 · f(XCIN) The count source of timer 3 is selected by setting bits 1 and 4 of the timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow.
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Timer Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 1 (TM1) Address 00F4 16 Name B 0 Timer 1 count source selection bit 1 (TM10) 1 2 3 4 Timer 2 count source selection bit 1 (TM11) Timer 1 count stop bit (TM12) Timer 2 count stop bit (TM13) Timer 2 count source selection bit 2 (TM14) Timer 1 count source selection bit 2 (TM15) Timer 5 count source selection bit 2 (TM16) Timer 6 internal count source selection bit (TM17) Functions 0: f(XIN) / 16 or f(X CIN) / 16 (See note) 1: Count source selected by bit 5 of TM1 0: Count source selected by bit 4 of TM1 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN) / 16 or f(X CIN) / 16 (See note) 1: Timer 1 overflow 0: f(XIN) / 4096 or f(X CIN) / 4096 (See note) 1: External clock from TIM2 pin 0: Timer 2 overflow 1: Timer 4 overflow 0: f(XIN) / 16 or f(X CIN) / 16 (See note) 1: Timer 5 overflow
After reset
Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register.
Fig. 8.4.1 Timer Mode Register 1
Timer Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 2 (TM2) Address 00F516 Name B 0 Timer 3 count source selection bit (TM20) Functions (b6 at address 00C7 16) 0 1 0 1 1, 4 Timer 4 count source selection bits (TM21, TM24) b4 0 0 1 1 b0 0 : f(X IN) / 16 or f(X CIN) / 16 (See note) 0 : f(X CIN) 1: 1 : External clock from TIM3 pin b1 0 : Timer 3 overflow signal 1 : f(X IN) / 16 or f(X CIN) / 16 (See note) 0 : f(X IN) / 2 or f(X CIN) / 2 (See note) 1 : f(X CIN) 0 R W
After reset R W
Timer 3 count stop bit (TM22) Timer 4 count stop bit (TM23) Timer 5 count stop bit (TM25) Timer 6 count stop bit (TM26) Timer 5 count source selection bit 1 (TM27)
0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN) / 16 or f(X CIN) / 16 (See note) 1: Count source selected by bit 6 of TM1
Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register.
Fig. 8.4.2 Timer Mode Register 2
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Port P3 direction register
b7 b6 b5 b4 b3 b2 b1 b0 0 Port P3 direction register (D3) Address 00C716 B 0 1 2 3 4 , 5 6 7 Name Port P3 direction register (See note 1) Functions 0 : Port P30 input 1 : Port P30 output 0 : Port P31 input 1 : Port P31 output Output amplitude level selection bit 0 : 2 value output (See note 2) (OUTS) 1 : 3 value output Fix this bit to "0." Nothing is assigned fix these bits When this bit are read out, the value are "0." Timer 3 (T3SC) Timer 2 (T2SC) Refer to explanation of a timer 0 : P24 input 1 : P16 input After reset R W 0 0 0 0 0 0 0 R W R W R W R W R - R W R W
Notes 1: When using the port as the I2C-BUS interface, set the Port P3 Direction Register to 1. 2: Use the Clock Control Register 3 (address 021216) bit 5 to select the binary output level of OUT.
Fig. 8.4.3 Port P3 direction register
Timer return setting register
b7 b6 b5 b4 b3 b2 b1 b0 1 1 0 0 0 0 0 Timer return setting register (TMS) Address 00CC16
Name Fix these bits to "0." Fix these bits to "1." STOP mode return selection bit (TMS)
Functions
0: Timer Count "07FF16" 1: Timer Count Variable
Fig. 8.4.4 Timer return setting register
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Data bus
CM7 TM15 1 / 4096 Timer 1 latch (8)
TM10 TM12 TM14
Timer 1 (8)
Timer 1 interrupt request
Timer 2 latch (8)
TIM2 TM11 TM13
Timer 2 (8) 8
Timer 2 interrupt request
FF16 T3SC Timer 3 latch (8)
Reset STP instruction
TIM3 TM20 TM22
Timer 3 (8) 8
Timer 3 interrupt request
07 16 Timer 4 latch (8)
Timer 4 (8) TM21 TM24 TM23 TM16 Selection gate: Connected to black side at reset TM1 : Timer mode register 1 TM2 : Timer mode register 2 T3SC : Timer 3 count source switch bit (address 00C716) CM : CPU mode register TM27 TM25 8
Timer 4 interrupt request
Timer 5 latch (8)
Timer 5 (8) 8
Timer 5 interrupt request
Timer 6 latch (8)
Timer 6 (8) TM17 TM26 8
Timer 6 interrupt request
Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Fig. 8.4.5 Timer Block Diagram
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.5 SERIAL I / O
This microcomputer has a built-in serial I / O which can either transmit or receive 8-bit data serially in the clock synchronous mode. The serial I / O block diagram is shown in Figure 8.5.1. The synchronous clock I / O pin (SCLK), and data output pin (SOUT) also function as port P4, data input pin (SIN) also functions as port P20-P22. Bit 3 of the serial I / O mode register (address 00EB16) selects whether the synchronous clock is supplied internally or externally (from the SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use the SIN pin for serial I / O, set the corresponding bit of the port P2 direction register (address 00C516) to "0."
The operation of the serial I / O is described below. The operation of the serial I / O differs depending on the clock source external clock or internal clock.
Synchronous circuit
Data bus 1 / 2 Frequency divider
SM1 SM0
Selection gate: Connect to black side at reset.
P20 Latch SCLK SM3 P21 Latch SOUT SIN SM6 SM3 SM5 : LSB MSB (See note) Serial I / O shift register (8) 8 Serial I / O counter (8)
CM : CPU mode register SM : Serial I / O mode register Serial I / O interrupt request
Note : When the data is set in the serial I / O register (address 00EA 16), the register functions as the serial I / O shift register.
Fig. 8.5.1 Serial I / O Block Diagram
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Internal clock : The serial I / O counter is set to "7" during the write cycle into the serial I / O register (address 00EA16), and the transfer clock goes HIGH forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I / O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I / O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I / O counter becomes "0" and the transfer clock stops at HIGH. At this time the interrupt request bit is set to "1."
Notes 1: On programming, note that the serial I / O counter is set by writing to the serial I / O register with the bit managing instructions, such as SEB and CLB. 2: When an external clock is used as the synchronous clock, write transmit data to the serial I / O register when the transfer clock input level is HIGH.
Synchronous clock
Transfer clock Serial I / O register write signal (Note) Serial I / O output SOUT Serial I / O input SIN D0 D1 D2 D3 D4 D5 D6 D7
Interrupt request bit is set to "1" Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed.
Fig. 8.5.2 Serial I / O Timing (for LSB first)
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Serial I / O Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 0 0 Serial I / O mode register (SM) Address 00EB16 B Name Functions b1 b0 0 0: f(XIN) / 8 or f(XCIN) / 8 0 1: f(XIN) / 16 or f(XCIN) / 16 1 0: f(XIN) / 32 or f(XCIN) / 32 1 1: f(XIN) / 64 or f(XCIN) / 64 0: External clock 1: Internal clock 0: P20, P21 1: SCLK, SOUT After reset R W 0 R W
0, 1 Internal synchronous clock selection bits (SM0, SM1)
Synchronous clock selection bit (SM2) Port function selection bit (SM3)
4 Fix this bit to "0." 5 Transfer direction selection bit (SM5) 0: LSB first 1: MSB first
0: Input signal from SIN pin 6 Transfer clock input pin selection bit (SM6) 1: Input signal from SOUT pin 7 Fix this bit to "0."
Fig. 8.5.3 Serial I / O Mode Register
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.6 MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and synchronous function, is useful for multi-master serial communications. Figure 8.6.1 shows a block diagram of the multi-master I2C-BUS interface and Table 8.6.1 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the address register, the data shift register, the clock control register, the control register, the status register and other control circuits.
Format
Communication mode
SCL clock frequency
I2C address register (S0D) b0
Interrupt generating circuit Interrupt request signal (IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Address comparator Serial data
(SDA)
Noise elimination circuit
Data control circuit
I2C data shift register S0
I2C control register (S1D) MST TRX BB PIN
AL AAS AD0 LRB
AL circuit
Internal data bus
I2C status register (S1)
BB circuit
Serial clock
(SCL)
Noise elimination circuit
Clock control circuit
ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE BIT
BSEL1 BSEL0 10BIT SAD ALS
ESO BC2 BC1 BC0
I2C clock control register (S2) Clock division
I2C control register (S1D) System clock () Bit counter
Fig. 8.6.1 Block Diagram of Multi-master I2C-BUS Interface
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.6.1 I2C Data Shift Register
The I2C data shift register (S0 : address 00F616) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00F916) is "1." The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00F816) are "1, " the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value.
Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
I2C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C data shift register 1(S0) Address 00F616 B 0 to 7 Name D0 to D7 Functions This is an 8-bit shift register to store receive data and write transmit data. After reset R W
Indeterminate R W
Note : To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
Fig. 8.6.2 I2C Data Shift Register
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.6.2 I2C Address Register
The I2C address register (address 00F716) consists of a 7-bit slave address and a read / write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition is detected.
(1) Bit 0: read / write bit (RBW)
Not used when comparing addresses in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register. The RBW bit is cleared to "0" automatically when the stop condition is detected.
(2) Bits 1 to 7: slave address (SAD0-SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits.
I2C Address Register
I2C address register (S0D) Address 00F716
Read / write bit (RBW)
Functions
After reset R W 0 R -
Fig. 8.6.3 I2C Address Register
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.6.3 I2C Clock Control Register
The I2C clock control register (address 00FA16) is used to set ACK control, SCL mode and SCL frequency.
(4) Bit 7: ACK clock bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to "0, " the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to "1, " the ACK clock mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device.
Note: Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I2C clock generator is reset, so that data cannot be transmitted normally.
(1) Bits 0 to 4: SCL frequency control bits (CCR0-CCR4)
These bits control the SCL frequency.
(2) Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to "0, " the standard clock mode is set. When the bit is set to "1, " the high-speed clock mode is set.
(3) Bit 6: ACK bit (ACK BIT)
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2) Address 00FA16
SCL frequency control Setup value of CCR4- bits CCR0 (CCR0 to CCR4) 00 to 02 03 04 05 06 1D 1E 1F
Functions
Standard clock mode
Setup disabled Setup disabled
After reset R W
High speed clock mode 0
Setup disabled Setup disabled
400 (See note)
500 / CCR value 1000 / CCR value
Fig. 8.6.4 I2C Clock Control Register
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.6.4 I2C Control Register
The I2C control register (address 00F916) controls the data communication format.
(3) Bit 4: data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses. When this bit is set to "0, " the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to "8.6.5 I2C Status Register, " bit 1) is received, transmission processing can be performed. When this bit is set to "1, " the free data format is selected, so that slave addresses are not recognized.
(1) Bits 0 to 2: bit counter (BC0-BC2)
These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become "0002" and the address data is always transmitted and received in 8 bits.
(2) Bit 3: I2C interface use enable bit (ESO)
(4) Bit 5: addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is set to "0, " the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 00F716) are compared with address data. When this bit is set to "1, " the 10-bit addressing format is selected and all the bits of the I2C address register are compared with the address data.
(5) Bits 6 and 7: connection control bits between I 2 C-BUS interface and ports (BSEL0, BSEL1)
These bits control the connection between SCL and ports or SDA and ports (refer to Figure 8.6.5).
Note: To connect with SCL3 and SDA3, set bits 2 and 3 of the port P3 register (00C616) .
"0" "1" BSEL20
SCL3 / P31
Notes · The paths SCL1, SCL2, SDA1, and SDA2, as well as the paths SCL3 and SDA3 cannot be connected at the same time. · Port P3 Register (address 00C616) bit 3 is used to control the pin connections of SCL3 / P31 and SCL1 / P11 and those of SDA3 / P30 and SDA1 / P13. · Set the corresponding direction register to "1" to use the port as multi-master I2C-BUS interface.
SCL Multi-master I2C-BUS interface SDA
"0" "1" BSEL21 "0" "1" BSEL0 "0" "1" BSEL1 "0" "1" BSEL20
SCL1 / P11 SCL2 / P12
SDA3 / P30
"0" BSEL21
"1" "0" "1" BSEL0 "0" "1" BSEL1
SDA1 / P13 SDA2 / P14
Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D) Address 00F916
Bit counter (Number of transmit / recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions
b0 0:8 1:7 0:6 1:5 0:4 1:3 0:2 1:1
After reset 0
I2C-BUS interface use enable bit (ESO) Data format selection bit(ALS) Addressing format selection bit (10BIT SAD)
0 : Disabled 1 : Enabled 0 : Addressing mode 1 : Free data format 0 : 7-bit addressing format 1 : 10-bit addressing format b7 b6 Connection port (See note) 0 0: None 0 1: SCL1, SDA1 1 0: SCL2, SDA2 1 1: SCL1, SDA1 SCL2, SDA2
6, 7 Connection control bits between I2C-BUS interface and ports (BSEL0, BSEL1)
Note: · Set the corresponding direction register to "1" to use the port as multi-master I2C-BUS interface. · To use SCL1, SDA1, SCL2 and SDA2, set the port P3 Register (address 00C616) bit 2 to 0.
Fig. 8.6.6 I2C Control Register
Port P3 register
Port P3 register (P3) Address 00C616
Port P3 register
Functions
Port P30 data Port P31 data
After reset
Indeterminate R W Indeterminate R W
Switch bit of I C-BUS interface and port P3 (See note) (BSEL20)
0 : Port P30, Port P31 1 : I2CBUS (SDA3, SCL3) 0 : Cutting 1 : Connection
SCL3 / P31-SCL1 / P11 SDA3 / P30-SDA1 / P13 Connection control bit (BSEL21)
Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is "0."
Notes · For the ports used as the Multi-master I2C-BUS interface, set their direction registers to 1. · To use SCL3 and SDA3, set the I2C Control Register (address 00F916) bits 6-7 to 0.
Fig. 8.6.7 Port P3 Register
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.6.5 I2C Status Register
The I2C status register (address 00F816) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to.
(5) Bit 4: I2C-BUS interface interrupt request bit (PIN)
(1) Bit 0: last receive bit (LRB)
This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to "0." If ACK is not returned, this bit is set to "1." Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00F616).
(2) Bit 1: general call detecting flag (AD0)
This bit is set to "1" when a general call whose address data is all "0" is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to "0" by detecting the STOP condition or START condition. General call: The master transmits the general call address "0016" to all slaves.
(3) Bit 2: slave address comparison flag (AAS)
This flag indicates a comparison result of address data. s In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to "1" in either of the following conditions. · The address data immediately after occurrence of a START condition matches the slave address stored in the high-order 7 bits of the I2C address register (address 00F716). · A general call is received. s In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to "1" in the following condition. · When the address data is compared with the I2C address register (8 bits consisting of slave address and RBW), the first bytes match. s The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00F616).
(6) Bit 5: bus busy flag (BB)
This bit indicates the status of the bus system. When this bit is set to "0, " this bus system is not busy and a START condition can be generated. When this bit is set to "1, " this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (See note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to "1" by detecting a START condition and set to "0" by detecting a STOP condition. When the ESO bit of the I2C control register (address 00F916) is "0" at reset, the BB flag is kept in the "0" state.
(7) Bit 6: communication mode specification bit (transfer direction specification bit: TRX)
(4) Bit 3: arbitration lost detecting flag (AL)
In the master transmission mode, when a device other than the microcomputer sets the SDA to "L, " arbitration is judged to have been lost, so that this bit is set to "1." At the same time, the TRX bit is set to "0, " so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to "0." When arbitration is lost during slave address transmission, the TRX bit is set to "0" and the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. Arbitration lost: The status in which communication as a master is disabled.
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(8) Bit 7: Communication mode specification bit (master / slave specification bit: MST)
This bit is used for master / slave specification in data communications. When this bit is "0, " the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is "1, " the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL. The MST bit is cleared to "0" in any of the following conditions. · Immediately after completion of 1-byte data transmission when arbitration lost is detected · When a STOP condition is detected. · When occurence of a START condition is disabled by the START condition duplication prevention function (Note). · At reset
Note: The START condition duplication prevention function disables the START condition generation, bit counter reset, and SCL output, when the following condition is satisfied: a START condition is set by another master device.
I2C Status Register
I2C status register (S1) Address 00F816 B
Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB)
Functions
After reset R W
Indeterminate 0 0 0 1 0 0
0 : No general call detected 1 : General call detected (See note) 0 : Address mismatch 1 : Address match (See note) 0 : Not detected 1 : Detected (See note) 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode
6, 7 Communication mode specification bits (TRX, MST)
Note : These bits and flags can be read out, but cannnot be written.
Fig. 8.6.8 I2C Status Register
SCL PIN
IICIRQ
Fig. 8.6.9 Interrupt Request Signal Generation Timing
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.6.6 START Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is "1, " execute a write instruction to the I2C status register (address 00F816) to set the MST, TRX and BB bits to "1." A START condition will then be generated. After that, the bit counter becomes "0002" and an SCL is output for 1 byte. The START condition generation timing and BB bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 8.6.10 for the START condition generation timing diagram, and Table 8.6.2 for the START condition / STOP condition generation timing table.
I2C status register write signal SCL SDA BB flag Setup time Hold time
Set time for BB flag
Fig. 8.6.10 START Condition Generation Timing Diagram
8.6.7 STOP Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is "1, " execute a write instruction to the I2C status register (address 00F816) to set the MST bit and the TRX bit to "1" and the BB bit to "0". A STOP condition will then be generated. The STOP condition generation timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 8.6.11 for the STOP condition generation timing diagram, and Table 8.6.2 for the START condition / STOP condition generation timing table.
I2C status register write signal SCL SDA BB flag Setup time Hold time
Reset time for BB flag
Fig. 8.6.11 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition / STOP Condition Generation Timing Table Item Setup time (START condition) Setup time (STOP condition) Hold time Set / reset time for BB flag Standard Clock Mode 5.0 µs (20 cycles) 4.25 µs (17 cycles) 5.0 µs (20 cycles) 3.0 µs (12 cycles) High-speed Clock Mode 2.5 µs (10 cycles) 1.75 µs (7 cycles) 2.5 µs (10 cycles) 1.5 µs (6 cycles)
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.6.8 START / STOP Condition Detect Conditions
The START / STOP condition detect conditions are shown in Figure 8.6.12 and Table 8.6.3. Only when the 3 conditions of Table 8.6.3 are satisfied, a START / STOP condition can be detected.
8.6.9 Address Data Communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats are described below.
(1) 7-bit addressing format
To support the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to "0." The first 7-bit address data transmitted from the master is compared with the high-order 7bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00F716) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 8.6.13, (1) and (2).
SCL release time SCL SDA (START condition) SDA (STOP condition) Setup time Setup time Hold time
(2) 10-bit addressing format
Hold time
Fig. 8.6.12 START Condition / STOP Condition Detect Timing Diagram
To support the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to "1." An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, an address comparison is performed between the RBW bit of the I2C address regis- ter (address 00F716) and the R / W bit, which is the last bit of the address data transmitted from the master. In the 10-bit addressing - mode, the R / W bit not only specifies the direction of communication for control data but is also processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00F816) is set to "1." After the second-byte address data is stored into the I2C data shift register (address 00F616), perform an address comparison between the second-byte data and the slave address by software. When the address data of the 2nd byte matches the slave address, set the RBW bit of the I2C address register (address 00F716) to "1" by software. This - processing can match the 7-bit slave address and R / W data, which are received after a RESTART condition is detected, with the value of the I2C address register (address 00F716). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 8.6.13, (3) and (4).
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.6.10 Example of Master Transmission
8.6.11 Example of Slave Reception
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Slave address R / W
7 bits " 0" 1 to 8 bits 1 to 8 bits (1) A master-transmitter transmits data to a slave-receiver
Slave address R / W
7 bits " 1" 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter Slave address R / W 1st 7 bits Slave address 2nd byte
1 to 8 bits 7 bits "0" 8 bits 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address R / W 1st 7 bits Slave address 2nd byte Slave address R / W 1st 7 bits
Data 1 to 8 bits
7 bits "0" 8 bits 7 bits "1" 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R / W : Read / Write bit From master to slave From slave to master
Fig. 8.6.13 Address Data Communication Format
8.6.12 Precautions when using multi-master I2C-BUS interface (1) Read-modify-write instruction
(2) START condition generating procedure using multi-master
Procedure example (The necessary conditions for the procedure are described in to below). · · -
(Take at slave address value) (Interrupt disabled) (BB flag confirmation and branch process) (Write slave address value) (Trigger START condition generation) (Interrupt enabled)
(Interrupt enabled)
Use "STA, " "STX" or "STY" of the zero page addressing instruction for writing the slave address value to the I2C data shift register. Use "LDM" instruction for setting trigger of START condition generation. Write the slave address value of and set trigger of START condition generation as in continuously, as shown in the procedure example. Disable interrupts during the following three process steps: · BB flag confirmation · Write slave address value · Trigger of START condition generation When the condition of the BB flag is bus busy, enable interrupts immediately.
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(3) RESTART condition generation procedure
(4) STOP condition generating procedure
Procedure example (The necessary conditions for the procedure are described in to below.) · ·
LDM LDA SEI STA LDM CLI
(Select slave receive mode) (Take out slave address value) (Interrupt disabled) (Write slave address value) (Trigger RESTART condition generation) (Interrupt enabled)
(Interrupt disabled) (Select master transmit mode) (Set NOP) (Trigger STOP condition generation) (Interrupt enabled)
Write "0" to the PIN bit when master transmit mode is selected. Execute "NOP" instruction after master transmit mode is set. Also, set trigger of STOP condition generation within 10 cycles after selecting the master trasmit mode. Disable interrupts during the following two process steps: · Select master transmit mode · Trigger STOP condition generation
(5) Writing to I2C status register
Do not execute an instruction to set the PIN bit to "1" from "0" and an instruction to set the MST and TRX bits to "0" from "1" simultaneously as it may cause the SCL pin the SDA pin to be released after about one machine cycle. Also, do not execute an instruction to set the MST and TRX bits to "0" from "1" when the PIN bit is "1, " as it may cause the same problem.
(6) Process after STOP condition generation
Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes "0" after generating the STOP condition in the master mode. Doing so may cause the STOP condition waveform from being generated normally. Reading the registers does not cause the same problem.
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.7 PWM OUTPUT FUNCTION
8.7.1 Data Setting
When outputting PWM0-PWM4, set 8-bit output data to the PWMi register (i means 0 to 4 addresses 020016 to 020416).
8.7.2 Transmitting Data from Register to PWM circuit
Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is executed when writing data to the register. The signal output from the 8-bit PWM output pin corresponds to the contents of this register.
8.7.3 Operating of 8-bit PWM
The following explains the PWM operation. First, set bit 0 of PWM mode register 1 (address 020816) to "0" (at reset, bit 0 is already set to "0" automatically), so that the PWM count source is supplied. PWM0-PWM4 are also used as pins P00-P04. Set the corresponding bits of the port P0 direction register to "1" (output mode). And select each output polarity by bit 3 of PWM mode register 1 (address 020816). Then, set bits 4 to 0 of PWM mode register 2 (address 020916) to "1" (PWM output). The PWM waveform is output from the PWM output pins by setting these registers. Figure 8.7.2 shows the 8-bit PWM timing. One cycle (T) is composed of 256 (28) segments. 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. Refer to Figure 8.7.2 (a). The 8-bit PWM outputs a waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit PWM register. Several examples are shown in Figure 8.7.2 (b). 256 kinds of output (HIGH area: 0 / 256 to 255 / 256) are selected by changing the contents of the PWM register. An entirely HIGH section cannot be output, i.e. 256 / 256.
8.7.4 Output after Reset
At reset, the output of ports P00-P04 is in the high-impedance state, and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register.
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Data bus XIN 1 / 2 PM10 PWM0 register (Address 0200 16) b7
PWM timing generating circuit
PM13 8-bit PWM circuit
P00 PM20 P01 PM21 P02 PM22 P03 PM23 P04 PM24
PWM1 register (Address 0201 16)
PWM2 register (Address 0202 16)
PWM3 register (Address 0203 16)
PWM4 register (Address 0204 16)
Selection gate: Connected to black side at reset. Inside of is as same contents with the others.
PM1 : PWM mode register 1 (address 0208 16) PM2 : PWM mode register 2 (address 0209 16) P0 : Port P0 register (address 00C0 16) D0 : Port P0 direction register (address 00C1 16)
Fig. 8.7.1 PWM Block Diagram
Rev. 1.0
Fig. 8.7.2 PWM Timing
FF16 (255)
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Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PWM Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0 PWM mode register 1 (PM1) Address 020816 B 0 Name PWM counts source selection bit (PM10) Functions 0 : Count source supply 1 : Count source stop After reset R W 0 R W
1, 2 Nothing is assigned. These bits are write disable bits. Indeterminate R - When these bits are read out, the values are "0." 3 PWM output polarity selection bit (PM13) 0 : Positive polarity 1 : Negative polarity 0 R W
4 Nothing is assigned. These bits are write disable bits. Indeterminate R - to When these bits are read out, the values are "0." 7
Fig. 8.7.3 PWM Mode Register 1
PWM Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 PWM mode register 2 (PM2) Address 020916 B Name 0 P00 / PWM0 output selection bit (PM20) 1 2 3 4 P01 / PWM1 output selection bit (PM21) P02 / PWM2 output selection bit (PM22) P03 / PWM3 output selection bit (PM23) P04 / PWM4 output selection bit (PM24) Functions 0 : P0 0 output 1 : PWM0 output 0 : P0 1 output 1 : PWM1 output 0 : P0 2 output 1 : PWM2 output 0 : P0 3 output 1 : PWM3 output 0 : P0 4 output 1 : PWM4 output After reset R W 0 0 0 0 0 0 R W R W R W R W R W R W
5 to Fix these bits to "0." 7
Fig. 8.7.4 PWM Mode Register 2
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
8.8 A-D COMPARATOR
The A-D comparator consists of a 7-bit D-A converter and a comparator. The A-D comparator block diagram is shown in Figure 8.8.1. The reference voltage "Vref" for D-A conversion is set by bits 0 to 6 of A-D control register 2 (address 00ED16). The comparison result of the analog input voltage and the reference voltage "Vref" is stored in bit 4 of A-D control register 1 (address 00EC16). For A-D comparison, set "0" to corresponding bits of the direction register to use ports as analog input pins. Write the data to select analog input pins for bits 0 to 2 of A-D control register 1 and write the digital value corresponding to V ref to be compared to bits 0 to 4 of A-D control register 2. The voltage comparison is started by writing to A-D control register 2, and it is completed after 16 machine cycles (NOP instruction 8).
Data bus
A-D control register 1
Comparator control
AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8
A-D control register 1 Analog signal switch Comparator Bit 4 Bit 6 Bit 5 Bit 4
A-D control register 2 Bit 3 Bit 2 Bit 1 Bit 0
Switch tree
Resistor ladder
Fig. 8.8.1 A-D Comparator Block Diagram
Rev. 1.0
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A-D Control Register 1
A-D control register 1 (AD1) Address 00EC16
Analog input pin selection bits (ADC10 to ADC12) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions
After reset R W
0 Indeterminate 0
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
Fig. 8.8.2 A-D Control Register 1
A-D Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2 (AD2) Address 00ED 16
Name D-A converter set bits (ADC20 to ADC25) b6 b5 0 0 0 0 0 0 b4 0 0 0
After reset 0
1 : 251 / 256Vcc 0 : 253 / 256Vcc 1 : 255 / 256Vcc 0 R -
Nothing is assigned. This bit is a write disable bit. When these bits are reed out, the values are " 0."
Fig. 8.8.3 A-D Control Register 2
Rev. 1.0
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8.9 ROM CORRECTION FUNCTION
This can correct program data in the ROM. Up to 2 addresses can be corrected a program for correction is stored in the ROM correction vector in the RAM as the top address. There are 2 vectors for ROM correction:. Vector 1 : address 030016 Vector 2 : address 032016 Set the address of the ROM data to be corrected into the ROM correction address register. When the value of the counter matches the ROM data address in the top address of the ROM correction vector, the main program branches to the correction program stored in the ROM memory. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the end of the correction program. The ROM correction function is controlled by the ROM correction enable register.
Notes 1: S p e c i f y t h e f i r s t a d d r e s s ( o p c o d e a d d r e s s ) o f e a c h instruction as the ROM correction address. 2: Use the JMP instruction (total of 3 bytes) to return from the correction program to the main program. 3: Do not set the same ROM correction address to both vectors 1 and 2.
ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order)
020A 16 020B 16 020C 16 020D 16
Fig. 8.9.1 ROM Correction Address Registers
ROM Correction Enable Register
ROM correction enable register (RCR) Address 020E B
Vector 1 enable bit (RC0) Vector 2 enable bit (RC1)
Functions
0: Disabled 1: Enabled 0: Disabled 1: Enabled
After reset 0 0 0
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
Rev. 1.0
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8.10 DATA SLICER
When the data slicer function is not used, the data slicer circuit and the timing signal generating circuit can be cut off by setting bit 0 of data slicer control register 1 (address 00E016) to "0." These settings support low-power dissipation.
Composite video signal
470 560 pF 1 µF
1 k 200 pF Sync pulse counter register (address 00E9 16) HLF
HSYNC
Synchronizing signal counter Clamping circuit Low-pass filter Sync slice circuit
Synchronizing separation circuit
Data slicer control register 2 (address 00E1 16)
Data slicer control register 1 (address 00E0 16) Timing signal generating circuit
Data slicer ON / OFF
Reference voltage generating 1000 pF circuit
VHOLD
+ - Comparator
Clock run-in determination circuit
Data slice line specification circuit
Clock run-in defect register (address 00E4 16)
Start bit detecting circuit
External circuit Note : Make the length of wiring which is connected to V HOLD , HLF, and CV IN pin as short as possible so that a leakage current may not be generated when mounting a resistor or a capacitor on each pin.
Caption position register (address 00E6 16)
Data clock generating circuit Data clock position register (address 00E5 16) 16-bit shift register Interrupt request generating circuit
high-order low-order Caption data register 1 (address 00E216)
Data slicer interrupt request
Caption data register 2 (address 00E316)
Caption data register 4 (address 00CF16)
Caption data register 3 (address 00CE16)
Data bus
Fig. 8.10.1 Data Slicer Block Diagram
Rev. 1.0
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8.10.1 Notes When not Using Data Slicer
When bit 0 of data slicer control register 1 (address 00E016) is "0, " terminate the pins as shown in Figure 8.10.2.
Leave HLF pin open.
Open Open
HLF VHOLD CVIN
Leave V HOLD pin open. Pull-down CV IN pin to V SS through a resistor of 5 k or more.
Fig. 8.10.2 Termination of Data Slicer Input / Output Pins when Data Slicer Circuit and Timing Generating Circuit are in OFF State When both bits 0 and 2 of data slicer control register 1 (address 00E016) are "1, " terminate the pins as shown in Figure 8.10.3.
Connect the same external circuit as when using data slicer to HLF pin. Leave V HOLD pin open. Pull-up CV IN to V CC through a resistor of 5 k or more.
24 200pF
VHOLD
Fig. 8.10.3 Termination of Data Slicer Input / Output Pins when Timing Signal Generating Circuit Is in ON State
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Figures 8.10.4 and 8.10.5 the data slicer control registers.
Data Slicer Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 0 0 Data slicer control register 1(DSC1) Address 00E016 B 0 Name Functions 0: Stopped 1: Operating 0: F2 1: F1 0: Video signal 1: HSYNC signal After reset R W 0 0 0 0 0 0 R W R W R W R W R W R W
Data slicer and timing signal generating circuit control bit (DSC10) 1 Selection bit of data slice reference voltage generating field (DSC11) 2 Reference clock source selection bit (DSC12) 3, 4 Fix these bits to "0." 5, 6 Fix these bits to "1." 7 Fix this bit to "0."
Definition of fields 1 (F 1) and 2 (F 2) F1: Hsep Vsep F2: Hsep Vsep
Fig. 8.10.4 Data Slicer Control Register 1
Data Slicer Control Register 2
Data slicer control register 2 (DSC2) Address 00E116
Name Caption data latch completion flag 1 (DSC20)
Functions
After reset
0: Data is not latched yet Indeterminate R - and a clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. 0 Read-only 0: F2 1: F1 0: Method (1) 1: Method (2) R W
Fix this bit to "1." Test bit Field determination flag(DSC23) Vertical synchronous signal (Vsep) generating method selection bit (DSC24) V-pulse shape determination flag (DSC25) Fix this bit to "0." Test bit Read-only
Indeterminate R - Indeterminate R - 0 R W
0: Match 1: Mismatch
Indeterminate R - 0 R W
Indeterminate R -
Definition of fields 1 (F1) and 2 (F2) F1: Hsep Vsep F2: Hsep Vsep
Fig. 8.10.5 Data Slicer Control Register 2
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37151M6 / M8 / MA / MC / MF-XXXFP, M37151EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODE