MITSUBISHI MICROCOMPUTERS M37225M6/M8/MA/MC-XXXSP M37225ECSP
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MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
DESCRIPTION
M37225M6/M8/MA/MC-XXXSP single-chip microcomputers designed with CMOS silicon gate technology. They have OSD, I2C-BUS interface, output, withstand, useful channel selection system features M37225ECSP similar those M37225M6-XXXSP except that chip built-in PROM which written electrically. differences amang M37225M6/M8/ MA/MC-XXXSP ROM, size. Accordingly, following descriptions will M37225M6-XXXSP.
FEATURES
qNumber basic instructions qMemory size bytes (M37225M6-XXXSP) bytes (M37225M8-XXXSP) bytes (M37225MA-XXXSP) bytes (M37225MC-XXXSP, M37225ECSP) 1024 bytes (M37225M6/M8-XXXSP) 2048 bytes (M37225MA/MC-XXXSP, M37225ECSP) correction memory included) qMinimum instruction execution time oscillation frequency) qPower source voltage qSubroutine nesting levels (Max.) qInterrupts types, vectors q8-bit timers qProgrammable ports (Ports P30-P32, P35) qInput ports (Ports P33, P34, P50, P51) qOutput ports (Ports P52-P55) withstand ports qLED drive ports qSerial 8-bit channel qMulti-master I2C-BUS interface systems) qA-D converter (8-bit resolution) channels qPWM output circuit 14-bit 8-bit qPower dissipation operating 5.5V, oscillation frequency, qROM correction function vectors qImmediate return mode from wait state
qOSD function Display characters characters lines possible display lines more software) Kinds characters kinds Character display area dots Kinds character sizes Block display: kinds SPRITE display: kinds Kinds character colors. colors Coloring unit character, character background, raster Display position Horizontal: levels Vertical :255 levels Attribute Border (all-bordered, shadow-bordered), BUTTON SPRITE display function Wallpaper function Window function Corresponding bi-scan mode
APPLICATION
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
TABLE CONTENTS
DESCRIPTION FEAUTURES APPLICATION CONFIGURATION FUNCTIONAL BLOCK DIAGRAM PERFORMANCE OVERVIEW DESCRIPTION FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) MEMORY INTERRUPTS TIMERS SERIAL MULTI-MASTER I2C-BUS INTERFACE OUTPUT CIRCUIT CONVERTER CORRECTION FUNCTION 8.10 FUNCTIONS Clock Scan mode input/output control 8.10.1 Block Display Display position size Memory Character Color Character Background Color OUT1, OUT2 Signals Attribute Multiple Display Window Function 8.10.2 SPRITE Display 8.10.3 Raster Display 8.11. SOFTWARE RUNAWAY DETECT FUNCTION 8.12. RESET CIRCUIT 8.13. CLOCK GENERATING CIRCUIT 8.14. DISPLAY OSCILLATION CIRCUIT 8.15. AUTO-CLEAR CIRCUIT 8.16. ADDRESSING MODE 8.17. MACHINE INSTRUCTIONS PROGRAMMING NOTES ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRIC CHARACTERISTICS CONVERTER CHARACTERISTICS MULTI-MASTER I2C-BUS LINE CHARACTERISTICS PROM PROGRAMMING METHOD DATA REQUIRED MASK ORDERS TIME PROM VERSIONS M37225ECSP MARKING APPENDIX PACKAGE OUTLINE
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
CONFIGURATION
HSYNC/P50 VSYNC/P51 P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 DA1/P35 P32/A-D7 CNVSS XOUT
R/P52 G/P53 B/P54 OUT1/P55 P20/SCLK P21/SOUT(/SIN) P22/SIN P10/OUT2/A-D8 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/INT3/A-D1 P16/A-D2 P17/DA2/A-D3 P30/A-D5 P31/A-D6 RESET OSC1/P33 OSC2/P34
Outline 42P4B
M37225M6/M8/MA/MC-XXXSP M37225ECSP
Fig. Configuration (Top View)
Rev.
INT3
INT2 INT1
SCLK SOUT
PWM5 PWM4 PWM3
PWM2
PWM1
SDA2
SDA1
SCL2
SCL1
PWM0
OUT2
OUT1
MITSUBISHI MICROCOMPUTERS
port port ports P30-P32,
port
Output ports P52-P55 output Sync signal input Input ports P50,
VSYNC HSYNC
Input ports P33, Clock input Clock output OSC2
Clock input
Clock output
XOUT CNVSS OSC1
Reset input RESET
Clock generating circuit
TIM2 TIM3
Fig. Functional Block Diagram M37225
Timer count source selection circuit
Program counter
Data
FUNCTIONAL BLOCK DIAGRAM
Timer Timer Control signal Instruction decoder Instruction register circuit Timer Index register Stack pointer
Program
counter
Timer
Address
8-bit arithmetic logical unit
Accumulator
Processor status register
Index register
14-bit circuit 14-bit circuit
converter
Multi-master I2C-BUS interface
SI/O(8)
8-bit circuit
correction function
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
PERFORMANCE OVERVIEW
Table Performance Overview Parameter Number basic instructions Instruction execution time Clock frequency Memory size Functions (the minimum instruction execution time, oscillation frequency) (maximum) bytes bytes bytes bytes 1024 bytes (ROM correction memory included) 2048 bytes (ROM correction memory included) bytes bytes 6-bit (N-channel open-drain output structure, used output pins) 2-bit (N-channel open-drain output structure, used input pins, input pin) 8-bit (CMOS input/output structure, used output pin, input pin, input pins, output pin, multi-master I2C-BUS interface) 8-bit (CMOS input/output structure, used serial pins, timer external clock input pins) 3-bit (CMOS output structure, N-channel open-drain output structure, used input pins, output pin) 1-bit (N-channel open-drain output structure, used input pin) 2-bit (Can used clock input/output pins) 2-bit (N-channel open-drain output structure, used horizonal vertical synchronous sibnal input pins) 4-bit (CMOS output structure, used output pins) 8-bit systems) channels (8-bit resolution) 14-bit 8-bit 8-bit timer vectors levels (maximum) types> external interrupt Internal timer interrupt Serial interrupt interrupt Multi-master C-BUS interface interrupt f(XIN)/4096 interrupt SPRITE interrupt conversion interrupt VSYNC interrupt instruction interrupt reset built-in circuits (externally connected ceramic resonator quartzcrystal oscillator)
M37225M6-XXXSP M37225M8-XXXSP M37225MA-XXXSP M37225MC-XXXSP, M37225ECSP M37225M6/M8-XXXSP M37225MA/MC-XXXSP, M37225ECSP P00-P05 P06, P30, P31, P33, P50, Input Input Output
Input/Output ports
P52-P55 Serial Multi-master I2C-BUS interface converter output circuit Timers correction function Subroutine nesting Interrupt
Clock generating circuit
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Table Performance Overview (Continued) Parameter Number display characters structure Kinds characters Kinds character sizes Character font coloring Display position Functions characters lines dots kinds kinds screen kinds (per character unit) Horizontal levels, Vertical levels typ. oscillation frequency f(XIN) MHz, fOSC MHz) typ. oscillation frequency f(XIN) MHz) 1.65 maximum CMOS silicon gate process 42-pin plastic molded SDIP
function
Power source voltage Power dissipation stop mode Operating temperature range Device structure Package
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
DESCRIPTION
Table Description VCC, CNVSS
Name Power source CNVSS Reset input
Input/ Output
Functions Apply voltage (typical) VCC, VSS. This connected VSS.
RESET
Input
enter reset state, reset input must kept more (under normal conditions). more time needed quartz-crystal oscillator stabilize, this condition should maintained required time. This chip internal clock generating circuit. control generating frequency, external ceramic resonator quartz-crystal oscillator connected between pins XOUT. external clock used, clock source should connected XOUT should left open. Port 8-bit port with direction register allowing each individually programmed input output. reset, this port input mode. output structure N-channel open-drain output. (See note Pins P00-P05 also used output pins PWM0-PWM5 respectively. output structure N-channel open-drain output. Pins also used external interrupt input pins INT2 INT1 respectively. also used analog input A-D4. Port 8-bit port basically same functions port output structure CMOS output. (See note Pins also used output OUT2. output structure CMOS output. Pins P11-P14 used SCL1, SCL2, SDA1 SDA2 respectively, when multi-master I2C-BUS interface used. output structure N-channel open-drain output. Pins P10, P15-P17 also used analog input A-D8, A-D1-A-D3 respectively. also used external interrupt input INT3. Pins also used 14-bit output DA2. output structure CMOS output. Port 8-bit port basically same functions port P21/SOUT(/SIN), output structure CMOS output. (See note also used serial synchronous clock input/output SCLK. output structure N-channel open-drain output. also used serial data input/output output structure N-channel open-drain output. also used serial data input SIN. Pins also used timer external clock input pins TIM3 TIM2 respectively. Ports P30-P32 3-bit port basically same functions port (see note Either CMOS output N-channel open-drain output structure selected ports output structure port N-channel open-drain output structure.(See notes Pins P30-P32 also used analog input pins A-D5-A-D7 respectively. also used 14-bit output DA1. output structure CMOS output. reset, output undefined. Pins 2-bit input port. also used clock input OSC1. also used clock output OSC2. output structure CMOS output.
XOUT
Clock input Clock output
Input Output
P00/PWM0- port P05/PWM5, P06/INT2/A-D4, P07/INT1 output External interrupt input Analog input P10/OUT2/A-D8, port P11/SCL1, P12/SCL2, output P13/SDA1, Multi-master P14/SDA2, I2C-BUS interface P15/INT3/A-D1, Analog input P16/A-D2, External interrupt P17/DA2/A-D3 input output P20/SCLK, P22/SIN, P23/TIM3, P24/TIM2, P25-P27 port Serial synchronous clock input/output port Serial data input/output Serial data input External clock input timer P30/A-D5, P31/A-D6, P32/A-D7, DA1/P35 port
Output Input Input Output Input Input Output Input Input
Analog input output OSC1/P33, Input port OSC2/P34, Clock input Clock output
Input Output Input Input Output
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Table Description (continued) Name Input/ Output Input Input Input Output Output Ports 2-bit input port. This horizontal synchronizing signal input OSD. This vertical synchronizing signal input OSD. Ports P52-P55 4-bit output port. output structure CMOS output. Pins P52-P55 also used output pins OUT1 respectively. output structure CMOS output. reset, output LOW. Functions
HSYNC/P50, Input port VSYNC/P51 R/P52, G/P53, B/P54, OUT1/P55 HSYNC input VSYNC input Output port output
Notes Port port direction register which used program each input ("0") output ("1"). pins programmed direction register output pins. When pins programmed "0," they input pins. When pins programmed output pins, output data written into port latch then output. When data read from output pins, output level read data port latch read. This allows previously-output value read correctly even output voltage risen, example, because light emitting diode directly driven. input pins floating state, values pins read. When data written into input pin, written only into port latch, while remains floating state. switch output structures, following bits. port direction register port direction register port output mode control register When "0," CMOS output; when "1," N-channel open-drain output.
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Ports P00-P05
N-channel open-drain output
Direction register
Ports P00-P05
Data Port latch
Note Each port also used follows 0-P05 PWM0-PWM5
Ports P30,
Direction register
CMOS output Ports P30, P31, Notes Each port also used follows OUT2/AD8 SCL1 TIM3 SCL2 TIM2 SDA1 A-D5 SDA2 A-D6 INT3/A-D1 A-D2 DA2/A-D3 SCLK SOUT/(SIN) Either CMOS output N-channel opendrain output structure selected ports P30, (when selecting N-channel open-drain, same with N-channel open-drain output below).
Data
Port latch
Ports P06, P07,
N-channel open-drain output
Direction register
Ports P06, P07,
Data Port latch
Note Each port also used follows INT2/A-D4 INT1
Fig. Block Diagram
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
P52-P55
Data Internal circuit
Port latch
CMOS output Ports P52-P55 Note Each also used follows OUT1
P50,
Data Internal circuit
Schmidt input Ports P50, Note Each also used follows HSYNC VSYNC
P33,
Input
Data
Ports P33, Note Each also used follows OSC1 OSC2
Fig. Block Diagram
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses standard Family instruction set. Refer table Family addressing modes machine instructions SERIES <Software> User's Manual details instruction set. Machine-resident Family instructions follows: FST, instruction cannot used. MUL, DIV, instructions used.
8.1.1 Mode Register
mode register contains stack page selection internal system clock selection bit. mode register allocated address 00FB16.
Mode Register
mode register (CM) [Address 00FB16] Name
Functions Single-chip mode available
After reset
Processor mode bits (CM0, CM1)
Stack page selection (CM2) (See note) these bits "1." these bits "0."
page page
Note: This after reset release.
Fig. 8.1.1 Mode Register
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
MEMORY 8.2.1 Special Function Register (SFR) Area
special function register (SFR) area zero page contains control registers such ports timers.
8.2.2
used data storage stack area subroutine calls interrupts.
8.2.3
used storing user programs well interrupt vector area.
8.2.4
display used specifying character codes colors display.
8.2.5
display used storing character data.
8.2.6 Interrupt Vector Area
interrupt vector area contains reset interrupt vectors.
8.2.7 Zero Page
bytes from addresses 000016 00FF16 called zero page area. internal special function registers (SFR) allocated this area. zero page addressing mode used specify memory register addresses zero page area. Access this area with only bytes possible zero page addressing mode.
8.2.8 Special Page
bytes from addresses FF0016 FFFF16 called special page area. special page addressing mode used specify memory addresses special page area. Access this area with only bytes possible special page addressing mode.
8.2.9 Correction Vector
This used program jump destination addresses correction.
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
sM37225M6/M8-XXXSP
000016
00BF16 00C016
1000016
1140016
Zero page used
area 00FF16 010016 01FF16
021716 021D
(1024 bytes)
used page register used page register used
(15K bytes)
13BFF16
used
1540016
154FF16
used
1560016
024016
024F16
02C016
156FF16
used
1580016
158FF16
correction function
used
02E016
030016
Vector address 02C016 Vector address 02E016 Vector address 030016
15A0016
15AFF16
used
15C0016
15CFF16
used
04FF16
15E0016
used
byres) (See note)
080016 087716
15EFF16
used
1600016
160FF16
used
1620016
162FF16
used
1640016
164FF16
used
1660016
166FF16
used
1680016
168FF16
used
16A0016
16AFF16
used
16C0016
16CFF16
used
16E0016
used
16EFF16
used
1700016
170FF16
used
1720016
172FF16
used
1740016
174FF16
used
1760016
176FF16
used
1780016 178FF16
used
17A0016 17AFF16
M37225M8XXXSP (32K bytes)
M37225M6XXXSP (24K bytes)
800016 A00016
used
FF0016 FFDE16 FFFF16 Interrupt vector area
Special page
1FFFF16
Note: Refer Table 8.10.3 RAM.
Fig. 8.2.1 Memory (M37225M6/M8-XXXSP)
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
sM37225MA/MC-XXXSP, M37225ECSP
000016
1000016
1140016
00BF16 00C016
used
Zero page
area
00FF16 010016 01FF16
021716 021D 024016
024F16
02C016
correction function
(15K bytes)
13BFF16
used
1540016
used page register used page register used
154FF16
used
(2048 bytes)
1560016
156FF16
used
1580016
158FF16
used Vector address 02C016 Vector address 02E016 Vector address 030016
02E016
030016
15A0016
15AFF16
used
15C0016
15CFF16
used
bytes) (See note)
07FF16 080016
087716
used
15E0016
15EFF16
used
1600016
090016 09FF16
160FF16
used
1620016
162FF16
used
1640016
164FF16
used
1660016
166FF16
used
1680016
168FF16
used
16A0016
16AFF16
used
16C0016
16CFF16
used used
16E0016
16EFF16
used
1700016
170FF16
used
1720016
172FF16
used
1740016
174FF16
used
1760016
176FF16
used
1780016 178FF16
used
17A0016 17AFF16
M37225MC-XXXSP M37225ECSP (48K bytes) 400016
600016
used
M37225MA-XXXSP (40K bytes)
FF0016 FFDE16 FFFF16
Interrupt vector area
Special page
1FFFF16
Note: Refer Table 8.10.3
Fig. 8.2.2 Memory (M37225MA/MC-XXXSP, M37225ECSP)
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
area (addresses C016 DF16)
allocation State immediately after reset
Name
Function
immediately after reset immediately after reset Indeterminate immediately after reset
function
this write "1") this write "0") Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register
Port (P0) Port direction register (D0) Port (P1) Port direction register (D1) Port (P2) Port direction register (D2) Port (P3) Port direction register (D3) Port output mode control register (P3S) Port (P5) port control register (PF) Test register Interrupt input polarity register (IP) DA1-H register (DA1-H) DA1-L register (DA1-L) PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) output control register (PW) output control register (PN) data shift register (S0) address register (S0D) status register (S1) control register (S1D) clock control register (S2) Serial mode register (SM) Serial register (SIO) conversion register (AD) control register (ADCON)
P34IN P33IN P31S P30S P35D P32D P31D P30D
allocation
State immediately after reset
P35S
OUT2
POL3 POL2 POL1
OCG1OCG0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
BSEL1 BSEL0 10BIT FAST MODE CCR4 CCR3 CCR2 CCR1 CCR0
ADVREF ADSTR ADIN2 ADIN1 ADIN0
0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0816
Fig. 8.2.3 Memory Special Function Register (SFR)
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
area (addresses E016 FF16)
allocation State immediately after reset
Name
Function
immediately after reset immediately after reset Indeterminate immediately after reset
function
this write "1") this write "0") Address Register
allocation
BHP5 BHP4 BHP3 BHP2 BHP1 BHP0 B1VP7 B1VP6 B1VP5 B1VP4 B1VP3 B1VP2 B1VP1 B1VP0 B2VP7 B2VP6 B2VP5 B2VP4 B2VP3 B2VP2 B2VP1 B2VP0 SHP7 SHP6 SHP5 SHP4 SHP3 SHP2 SHP1 SHP0 SVP7 SVP6 SVP5 SVP4 SVP3 SVP2 SVP1 SVP0 CO16 CO15 CO14 CO13 CO12 CO11 CO10 CO26 CO25 CO24 CO23 CO22 CO21 CO20 CO36 CO35 CO34 CO33 CO32 CO31 CO30 CO46 CO45 CO44 CO43 CO42 CO41 CO40
State immediately after reset
E016 Block register (BHP) E116 Block register (B1VP) E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16
Block register (B2VP) SPRITE control register (SC) SPRITE register (SHP) SPRITE register (SVP) Color register (CO1) Color register (CO2) Color register (CO3) Color register (CO4) control register (OC) polarity control register (OPC) Color register (CO5) Color register (CO6) Color register (CO7) Color register (CO8) Timer (T1) Timer (T2) Timer (T3) Timer (T4) Timer mode register (TM1) Timer mode register (TM2) PWM5 register (PWM5) Test register Test register Block control register (B1C) Block control register (B2C) mode register (CM) Interrupt request register (IREQ1) Interrupt request register (IREQ2) Interrupt control register (ICON1) Interrupt control register (ICON2)
OPC7 OPC6 OPC5 OPC4 OPC3 OPC2 OPC1 OPC0 CO56 CO55 CO54 CO53 CO52 CO51 CO50 CO66 CO65 CO64 CO63 CO62 CO61 CO60 CO76 CO75 CO74 CO73 CO72 CO71 CO70 CO86 CO85 CO84 CO83 CO82 CO81 CO80
TM15 TM14 TM13 TM12 TM11 TM10 TM25 TM24 TM23 TM22 TM21 TM20
0016 0016
B1C4 B1C3 B1C2 B1C1 B1C0 B2C4 B2C3 B2C2 B2C1 B2C0
IT3R IICR VSCR OSDR TM4R TM3R TM2R TM1R
IT2R IT1R
IT3E IICE VSCE OSDE TM4E TM3E TM2E TM1E
IT2E IT1E
0016 0016 0016 0016 0016 FF16 0716 FF16 0716 0016 0016 3C16 0016 0016 0016 0016
Fig. 8.2.4 Memory Special Function Register (SFR)
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
page register area (addresses 21016 21F16, 24016 24F16)
allocation State immediately after reset
Name
Function
immediately after reset immediately after reset Indeterminate immediately after reset
function
this write "1") this write "0") Address 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 21C16 21D16 21E16 21F16 24016 24116 24216 24316 24416 24516 24616 24716 24816 24916 24A16 24B16 24C16 24D16 24E16 24F16 Register allocation
State immediately after reset
correction address (high-order) correction address (low-order) correction address (high-order) correction address (low-order) correction enable register (RCR) correction address (high-order) correction address (low-order)
RCR2 RCR1RCR0
Left border control register (LBR) Right border control register (RBR)
LBR6 LBR5 LBR4 LBR3 LBR2 LBR1 LBR0 RBR6 RBR5 RBR4 RBR3 RBR2 RBR1 RBR0
border control register (TBR) TBR7 TBR6 TBR5 TBR4 TBR3 TBR2 TBR1 TBR0 Bottom border control register (BBR) BBR7 BBR6 BBR5 BBR4 BBR3 BBR2 BBR1 BBR0 0016 Test register
DA2-H register (DA2H) DA2-L register (DA2L)
0016 0016 0016 0016 0016 0016 0016 0016 0016 0016
Fig. 8.2.5 Memory Page Register Area
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
allocation
State immediately after reset
Name
Function
immediately after reset
immediately after reset
Indeterminate immediately after reset
function
this write "1") this write "0")
Register
Processor status register (PS) Program counter (PCH) Program counter (PCL)
allocation
State immediately after reset
Contents address FFFF16 Contents address FFFE16
Fig. 8.2.6 Internal State Processor Status Register Program Counter Reset
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
INTERRUPTS
Interrupts caused different sources consisting external, internal, software, reset. Interrupts vectored interrupts with priorities shown Table 8.3.1. Reset also included table because operation similar interrupt. When interrupt accepted, contents program counter processor status register automatically stored into stack. interrupt disable flag corresponding interrupt request "0." jump destination address stored vector address enters program counter. Other interrupts disabled when interrupt disable flag "1." interrupts except instruction interrupt have interrupt request interrupt enable bit. interrupt request bits interrupt request registers interrupt enable bits interrupt control registers Figures 8.3.2 8.3.6 show interrupt-related registers. Interrupts other than instruction interrupt reset accepted when interrupt enable "1," interrupt request "1," interrupt disable flag "0." interrupt request program, "1." interrupt enable program. Reset treated non-maskable interrupt with highest priority. Figure 8.3.1 shows interrupt control.
8.3.1 Interrupt Causes VSYNC, OSD, SPRITE Interrupts
VSYNC interrupt interrupt request synchronized with vertical sync signal. interrupt occurs after character block display completed. SPRITE interrupt occurs completion SPRITE display.
INT1 INT3 External Interrupts
INT1 INT3 interrupts external interrupt inputs, system detects that level changes from HIGH from HIGH LOW, generates interrupt request. input active edge selected bits interrupt input polarity register (address 00CD16) when this "0," change from HIGH detected; when "1," change from HIGH detected. Note that both bits cleared reset.
Timers Interrupts
interrupt generated overflow timers
Table 8.3.1 Interrupt Vector Addresses Priority Priority Interrupt Source Reset interrupt INT2 external interrupt INT1 external interrupt SPRITE interrupt Timer interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer interrupt Timer interrupt Timer interrupt Serial interrupt Multi-master I2C-BUS interface interrupt INT3 external interrupt conversion interrupt instruction interrupt Vector Addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF716, FFF616 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFE316, FFE216 FFDF16, FFDE16 Remarks Non-maskable Active edge selectable Active edge selectable
Active edge selectable Non-maskable
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Serial Interrupt
This interrupt request from clock synchronous serial function.
f(XIN)/4096 Interrupt
(XIN)/4096 interrupt occurs regularly with f(XIN)/4096 period. mode register "0."
Interrupt request Interrupt enable
Multi-master I2C-BUS Interface Interrupt
This interrupt request related multi-master I2C-BUS interface.
Interrupt disable flag
instruction Reset
Interrupt request
Conversion Interrupt
conversion interrupt occurs completion conversion.
Instruction Interrupt
This software interrupt least significant priority. does have corresponding interrupt enable bit, affected interrupt disable flag (non-maskable).
Fig. 8.3.1 Interrupt Control
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Interrupt Request Register
Interrupt request register (IREQ1) [Address 00FC16] Name Timer interrupt request (TM1R) Functions After reset interrupt request issued Interrupt request issued Timer interrupt interrupt request issued request (TM2R) Interrupt request issued Timer interrupt interrupt request issued request (TM3R) Interrupt request issued Timer interrupt interrupt request issued request (TM4R) Interrupt request issued interrupt request interrupt request issued Interrupt request issued (OSDR) VSYNC interrupt interrupt request issued request (VSCR) Interrupt request issued Multi-master I2C-BUS interface interrupt request issued interrupt request (IICR) Interrupt request issued INT3 external interrupt interrupt request issued request (IT3R) Interrupt request issued
software, cannot set.
Fig. 8.3.2 Interrupt Request Register
Interrupt Request Register
Interrupt request register (IREQ2) [Address 00FD16] Name Functions After reset INT1 external interrupt interrupt request issued Interrupt request issued request (IT1R) INT2 external interrupt interrupt request issued Interrupt request issued request (IT2R) Serial interrupt interrupt request issued request (S1R) Interrupt request issued SPRITE interrupt interrupt request issued request (SPR) Interrupt request issued f(XIN)/4096 interrupt interrupt request issued request (MSR) Interrupt request issued Nothing assigned. This write disable bit. When this read out, value "0." conversion interrupt interrupt request issued request (ADR) Interrupt request issued this "0."
software, cannot set.
Fig. 8.3.3 Interrupt Request Register
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Interrupt Control Register
Interrupt control register (ICON1) [Address 00FE16] Name Functions Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled After reset
Timer interrupt enable (TM1E) Timer interrupt enable (TM2E) Timer interrupt enable (TM3E) Timer interrupt enable (TM4E) interrupt enable (OSDE) VSYNC interrupt enable (VSCE) Multi-master I2C-BUS interface interrupt enable (IICE) INT3 external interrupt enable (IT3E)
Fig. 8.3.4 Interrupt Control Register
Interrupt Control Register
Interrupt control register (ICON2) [Address 00FF16] Name Functions Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled After reset
INT1 external interrupt enable (IT1E) INT2 external interrupt enable (IT2E) Serial interrupt enable (S1E) SPRITE interrupt enable (SPE) f(XIN)/4096 interrupt enable (MSE) this "0."
conversion interrupt Interrupt disabled enable (ADE) Interrupt enabled Nothing assigned. This write disable bit. When this read out, value "0."
Fig. 8.3.5 Interrupt Control Register
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Interrupt Input Polarity Register
Interrupt input polarity register (IP) [Address 00CD16] Name Function Function clock supplied connecting across pins OSC1 OSC2. However, corresponding bi-scan mode. Since main clock used clock OSD, oscillation frequency limited. Because this, character size width (horizonal) direction also limited. this case, pins OSC1 OSC2 also used input ports respectively. After reset
clock selection bits (OCG0, OCG1)
oscillation frequency f(XIN)
clock supplied connecting across pins OSC1 OSC2. bi-scan mode, sure this. clock supplied connecting following across pins OSC1 OSC2. However, corresponding bi-scan mode. ceramic resonator only feedback resistor quartz-crystal oscillator only feedback resistor
this "0." INT1 polarity switch (POL1) INT2 polarity switch (POL2) INT3 polarity switch (POL3) Positive polarity Negative polarity Positive polarity Negative polarity Positive polarity Negative polarity
these bits "0."
Fig. 8.3.6 Interrupt Input Polarity Register
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
TIMERS
This microcomputer timers: timers timers 8-bit timers with 8-bit timer latch. timer block diagram shown Figure 8.4.3. timers count down their divide ratio 1/(n+1), where value timer latch. writing count value corresponding timer latch (addresses 00F016 00F316 timers value also timer, simultaneously. count value decremented timer interrupt request timer overflow next count pulse, after count value reaches "0016." reset, timers connected hardware "FF16" automatically timer "0716" timer f(XIN)/16 selected timer count source. internal reset released timer overflow this state internal clock connected. execution instruction, timers connected hardware "FF16" automatically timer "0716" timer However, f(XIN)/16 selected timer count source. both timer mode register (address 00F516) address 00C716 before execution instruction (f(XIN)/16 selected timer count source). internal state released timer overflow this state internal clock connected. result above procedure, program start under stable clock. However, when setting timer mode register (address 00F416), timers above value, state executing instruction. This allows program time return from state. timer-related registers shown Figures 8.4.1 8.4.2.
8.4.1 Timer
Timer select following count sources: f(XIN)/16 f(XIN)/4096 f(XCIN)/4096 count source timer selected setting timer mode register (address 00F416). Timer interrupt request occurs timer overflow.
8.4.2 Timer
Timer select following count sources: f(XIN)/16 Timer overflow signal External clock from TIM2 count source timer selected setting bits timer mode register (address 00F416). When timer overflow signal count source timer timer functions 8-bit prescaler. Timer interrupt request occurs timer overflow.
8.4.3 Timer
Timer select following count sources: f(XIN)/16 External clock from HSYNC External clock from TIM3 count source timer selected setting bits timer mode register (address 00F516). Timer interrupt request occurs timer overflow.
8.4.4 Timer
Timer select following count sources: f(XIN)/16 f(XIN)/2 Timer overflow signal count source timer selected setting bits timer mode register (address 00F516). When timer overflow signal count source timer timer functions 8-bit prescaler. Timer interrupt request occurs timer overflow.
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Timer Mode Register
Timer mode register (TM1) [Address 00F416] Name Timer count source selection (TM10) Timer count source selection (TM11) Functions f(XIN)/16 f(XIN)/4096 Interrupt clock source External clock from TIM2 Count start Count stop Count start Count stop After reset
Timer count stop (TM12) Timer count stop (TM13)
Timer internal count source f(XIN)/16 Timer overflow selection (TM14) execution instruction> Timers auto disable (TM15) Auto enabled Auto disabled
Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.4.1 Timer Mode Register
Timer Mode Register
Timer mode register (TM2) [Address 00F516] Name Timer count source selection (TM20) Timer internal interrupt count source selection (TM21) Functions f(XIN)/16 External clock source Timer overflow signal f(XIN)/16 Count start Count stop Count start Count stop Internal clock source f(XIN)/2 After reset
Timer count stop (TM22) Timer count stop (TM23) Timer count source selection (TM24)
Timer external count TIM3 input source selection (TM25) HSYNC input
Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.4.2 Timer Mode Register
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Data
1/4096
Timer latch
TM10 TM12
Timer TM14
Timer interrupt request
Timer latch TIM2 TM11 TM13 FF16 TIM3 TM25 Timer latch Timer TM20 TM22 0716 Timer latch Timer TM24 TM23 Timer interrupt request Timer interrupt request instruction TM15 Timer Timer interrupt request
HSYNC
Reset
Selection gate Connected black side reset TM21 Timer mode register Timer mode register
Notes HIGH pulse width timer external clock inputs TIM2 TIM3 needs machine cycles more. When external clock source selected, timers counted rising edge input signal. stop mode wait mode, external clock inputs TIM2 TIM3 cannot used.
Fig. 8.4.3 Timer Block Diagram
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
SERIAL
This microcomputer built-in serial which either transmit receive 8-bit data serially clock synchronous mode. serial block diagram shown Figure 8.5.1. synchronous clock (SCLK), data output (SOUT) also function port data input (SIN) also functions port serial mode register (address 00DC16) selects whether synchronous clock supplied internally externally (from SCLK pin). When internal clock selected, bits select whether f(XIN) f(XCIN) divided serial I/O, corresponding port direction register (address 00C516) "0."
operation serial described below. operation serial differs depending clock source; external clock internal clock.
Data Frequency divider
1/16 1/32 1/64
Synchronous circuit latch SCLK latch SOUT
Selection gate Connected black side reset Serial mode register
Serial counter
Serial interrupt request
(See note)
Serial shift register (Address 00DD16)
Note When data serial register (address 00DD16), register functions serial shift register.
Fig. 8.5.1 Serial Block Diagram
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Internal clock serial counter during write cycle into serial register (address 00DD16), transfer clock goes HIGH forcibly. each falling edge transfer clock after write cycle, serial data output from SOUT pin. Transfer direction selected serial mode register. each rising edge transfer clock, data input from data serial register shifted bit. After transfer clock counted times, serial counter becomes transfer clock stops HIGH. this time interrupt request "1."
External clock external clock selected clock source, interrupt request after transfer clock been counted counts. However, transfer operation does stop, clock should controlled externally. external clock less with duty cycle 50%. serial timing shown Figure 8.5.2. When using external clock transfer, external clock must held HIGH initializing serial counter. When switching between internal clock external clock, switch during transfer. Also, sure initialize serial counter after switching.
Notes programming, note that serial counter writing serial register with managing instructions, such CLB. When external clock used synchronous clock, write transmit data serial register when transfer clock input level HIGH.
Synchronous clock
Transfer clock Serial register write signal (Note) Serial output SOUT Serial input
Interrupt request Note When internal clock selected, SOUT high-impedance after transfer completed.
Fig. 8.5.2 Serial Timing (for first)
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Serial Mode Register
Serial mode register (SM) [Address 00DC16] Name Functions f(XIN)/4 f(XIN)/16 f(XIN)/32 f(XIN)/64 External clock Internal clock P20, SCLK, SOUT After reset
Internal synchronous clock selection bits (SM0, SM1)
Synchronous clock selection (SM2) Serial port selection (SM3)
this "0." Transfer direction selection (SM5) Serial input selection (SM6) first first Input signal from pin. Input signal from SOUT pin.
Nothing assigned. This write disable bit. When this read out, value "0."
Fig. 8.5.3 Serial Mode Register
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.5.1 Serial Common Transmission/Reception mode
writing serial mode register, signals SOUT switched internally able transmit receive serial data. Figure 8.5.4 shows signals serial common transmission/reception mode.
Note: When receiving serial data after writing "FF16" serial register.
SCLK
Clock
SOUT Serial shift register
Serial mode register
Fig. 8.5.4 Signals Serial Common Transmission/Reception Mode
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
MULTI-MASTER I2C-BUS INTERFACE
multi-master I2C-BUS interface serial communications circuit, conforming Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection synchronous functions, useful multi-master serial communications. Figure 8.6.1 shows block diagram multi-master I2C-BUS interface Table 8.6.1 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists address register, data shift register, clock control register, control register, status register other control circuits.
Table 8.6.1 Multi-master I2C-BUS Interface Functions Item Function conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 MHz)
Format
Communication mode
clock frequency
System clock f(XIN)/2
Note responsible third party's infringement patent rights other rights attributable control function (bits control register address 00DA16) connections between I2C-BUS interface ports (SCL1, SCL2, SDA1, SDA2).
address register (S0D)
Interrupt generating circuit Interrupt request signal (IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
Address comparator Serial data
(SDA)
Noise elimination circuit
Data control circuit
data shift register
circuit
Internal data
status register (S1)
circuit
Serial clock
(SCL)
Noise elimination circuit
Clock control circuit
FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE
BSEL1 BSEL0 10BIT
clock control register (S2) Clock division
control register (S1D) System clock counter
Fig. 8.6.1 Block Diagram Multi-master I2C-BUS Interface
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.6.1 Data Shift Register
data shift register address 00D716) 8-bit shift register store receive data write transmit data. When transmit data written into this register, transferred outside from synchronization with clock, each time one-bit data output, data this register shifted left. When data received, input this register from synchronization with clock, each time one-bit data input, data this register shifted left. data shift register write enable status only when control register (address 00DA16) "1." counter reset write instruction data shift register. When both status register (address 00D916) "1," output write instruction data shift register. Reading data from data shift register always enabled regardless value.
Note: write data into data shift register after setting (slave mode), keep interval machine cycles more.
Address Register
address register (S0D) [Address 00D816]
Name
Read/write (RBW)
Functions
<Only 10-bit addressing slave) mode> last significant address data compared. Wait first byte slave address after START condition (read state) Wait first byte slave address after RESTART condition (write state) both modes> address data compared.
After reset
Slave address (SAD0 SAD6)
Fig. 8.6.2 Data Shift Register
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.6.2 Address Register
address register (address 00D816) consists 7-bit slave address read/write bit. addressing mode, slave address written this register compared with address data received immediately after START condition detected.
read/write (RBW)
used when comparing addresses, 7-bit addressing mode. 10-bit addressing mode, first address data received compared with contents (SAD6 SAD0 RBW) address register. cleared automatically when stop condition detected.
Bits slave address (SAD0-SAD6)
These bits store slave addresses. Regardless 7-bit addressing mode 10-bit addressing mode, address data transmitted from master compared with contents these bits.
Address Register
address register (S0D) [Address 00D816]
Name
Read/write (RBW)
Functions
<Only 10-bit addressing slave) mode> last significant address data compared. Wait first byte slave address after START condition (read state) Wait first byte slave address after RESTART condition (write state) both modes> address data compared.
After reset
Slave address (SAD0 SAD6)
Fig. 8.6.3 Address Register
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.6.3 Clock Control Register
clock control register (address 00DB16) used control, mode frequency.
clock (ACK)
This specifies mode acknowledgment which acknowledgment response data transmission. When this "0," clock mode set. this case, clock occurs after data transmission. When "1," clock mode master generates clock upon completion each 1-byte data transmission.The device transmitting address data control data releases occurrence clock (make HIGH) receives generated data receiving device.
Note: write data into clock control register during transmission. data written during transmission, clock generator reset, that data cannot transmitted normally.
Bits frequency control bits (CCR0-CCR4)
These bits control frequency.
mode specification (FAST MODE)
This specifies mode. When this "0," standard clock mode set. When "1," high-speed clock mode set.
(ACK BIT)
This sets status when clock generated. When this "0," return mode goes occurrence clock. When "1," non-return mode set. held HIGH status occurrence clock. However, when slave address matches address data reception address data "0," automatically made (ACK returned). there mismatch between slave address address data, automatically made HIGH (ACK returned). clock: Clock acknowledgement
Clock Control Register
clock control register (S2) [Address 00DB16]
Name
Functions
After reset
frequency control bits Setup value Standard clock High speed (CCR0 CCR4) CCR4-CCR0 mode clock mode
Setup disabled Setup disabled Setup disabled Setup disabled 83.3 17.2 16.6 16.1 (See note) 34.5 33.3 32.3
500/CCR value 1000/CCR value
MHz, unit kHz) mode specification (FAST MODE) (ACK BIT) clock (ACK) Standard clock mode High-speed clock mode returned. returned. clock clock
Note: high-speed clock mode, duty below period period other cases, duty below. period period
Fig. 8.6.4 Address Register
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.6.4 Control Register
control register (address 00DA16) controls data communication format.
data format selection (ALS)
This decides whether recognize slave addresses. When this "0," addressing format selected, that address data recognized. When match found between slave address address data result comparison when general call (refer "8.6.5 Status Register," received, transmission processing performed. When this "1," free data format selected, that slave addresses recognized.
Bits counter (BC0-BC2)
These bits decide number bits next 1-byte data transmitted. interrupt request signal occurs immediately after number bits specified with these bits transmitted. When START condition received, these bits become "0002" address data always transmitted received bits.
interface enable (ESO)
This enables usage multimaster interface. When this "0," disable status provided, become high-impedance. When "1," interface enabled. When "0," following performed. "1," (they bits status register address 00D916 Writing data data shift register (address 00D716) disabled.
addressing format selection (10BIT SAD)
This selects slave address specification format. When this "0," 7-bit addressing format selected. this case, only high-order bits (slave address) address register (address 00D816) compared with address data. When this "1," 10-bit addressing format selected, bits address register compared with address data.
Bits connection control bits between C-BUS interface ports (BSEL0, BSEL1)
These bits controls connection between ports ports (refer Figure 8.6.5).
BSEL0 P11/SCL1 Multi-master I2C-BUS interface BSEL1 P12/SCL2 BSEL0 P13/SDA1 BSEL1 P14/SDA2
Fig. 8.6.5 Connection Port Control BSEL0 BSEL1
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Control Register
control register (S1D) [Address 00DA16]
Name
counter (Number transmit/recieve bits) (BC0 BC2)
Functions
After reset
I2C-BUS interface enable (ESO) Data format selection bit(ALS) Addressing format selection (10BIT SAD)
Disabled Enabled Addressing format Free data format 7-bit addressing format 10-bit addressing format Connection port (See note) None SCL1, SDA1 SCL2, SDA2 SCL1, SDA1, SCL2, SDA2
Connection control bits between I2C-BUS interface ports (BSEL0, BSEL1)
Note: When using ports P11-P14 I2C-BUS interface, output structure changes automatically from CMOS output N-channel open-drain output.
Fig. 8.6.6 Control Register
Rev.
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8.6.5 Status Register
status register (address 00D916) controls I2C-BUS interface status. low-order bits read-only bits highorder bits read written
I2C-BUS interface interrupt request (PIN)
This generates interrupt request signal. Each time 1-byte data transmitted, state changes from "0." same time, interrupt request signal sent CPU. synchronization with falling edge last clock (including clock) internal clock interrupt request signal occurs synchronization with falling edge bit. When detecting STOP condition slave, multi-master I2C-BUS interface interrupt request (IR) (interrupt request) regardless falling bit. When "0," kept state clock generation disabled. Figure 8.6.8 shows interrupt request signal generating timing chart. following conditions. Writing Executing write instruction data shift register (address 00D716). When reset
Note: takes BCLK cycles more until become after write instructions executed these registers.
last receive (LRB)
This stores last value received data also used receive confirmation. returned when clock occurs, "0." returned, this "1." Except mode, last value received data input. state this changed from executing write instruction data shift register (address 00D716).
general call detecting flag (AD0)
This when general call whose address data received slave mode. general call master device, every slave device receives control data after general call. detecting STOP condition START condition. General call: master transmits general call address "0016" slaves.
slave address comparison flag (AAS)
This flag indicates comparison result address data. slave receive mode, when 7-bit addressing format selected, this following conditions. address data immediately after occurrence START condition matches slave address stored high-order bits address register (address 00D816). general call received. slave reception mode, when 10-bit addressing format selected, this with following condition. When address data compared with address register bits consists slave address RBW), first bytes match. state this changed from executing write instruction data shift register (address 00D716).
conditions which shown below: Immediately after completion 1-byte data transmission (including when arbitration lost detected) Immediately after completion 1-byte data reception slave reception mode, with immediately after completion slave address general call address reception slave reception mode, with immediately after completion address data reception
busy flag (BB)
This indicates status system. When this "0," this system busy START condition generated. When this "1," this system busy occurrence START condition disabled START condition duplication prevention function (See note). This flag written software only master transmission mode. other modes, this detecting START condition detecting STOP condition. When control register (address 00DA16) reset, flag kept state.
arbitration lost detecting flag (AL)
master transmission mode, when device other than microcomputer sets "L,", arbitration judged have been lost, that this "1." same time, "0," that immediately after transmission byte whose arbitration lost completed, "0." When arbitration lost during slave address transmission, reception mode set. Consequently, becomes possible receive recognize slave address transmitted another master device. Arbitration lost: status which communication master disabled.
communication mode specification (transfer direction specification bit: TRX)
This decides direction transfer data communication. When this "0," reception mode selected data transmitting device received. When "1," transmission mode selected address data control data output into synchronization with clock generated SCL. When control register (address 00DA16) slave reception mode selected, (transmit) least significant (R/W bit) address data trans_ mitted master "1." When "0," cleared (receive). cleared following conditions. When arbitration lost detected. When STOP condition detected. When occurence START condition disabled START condition duplication prevention function (Note). With when START condition detected. With when non-return detected. reset
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Communication mode specification (master/slave specification bit: MST)
This used master/slave specification data communication. When this "0," slave specified, that START condition STOP condition generated master received, data communication performed synchronization with clock generated master. When this "1," master specified START condition STOP condition generated, also clocks required data communication generated SCL. cleared following conditions. Immediately after completion 1-byte data transmission when arbitration lost detected When STOP condition detected. When occurence START condition disabled START condition duplication preventing function (Note). reset
Note: START condition duplication prevention function disables START condition generation, reset counter reset, output, when following condition satisfied: START condition another master device.
Status Register
status register (S1) [Address 00D916]
Name
Last receive (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request (PIN) busy flag (BB)
Functions
Last Last (See note)
After reset
Indeterminate
general call detected General call detected (See note) Address mismatch Address match detected Detected (See note)
(See note) Interrupt request issued interrupt request issued free busy Slave recieve mode Slave transmit mode Master recieve mode Master transmit mode
Communication mode specification bits (TRX, MST)
Note These bits flags read out, cannnot written.
Fig. 8.6.7 Status Register
IICIRQ
Fig. 8.6.8 Interrupt Request Signal Generation Timing
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.6.6 START Condition Generation Method
When control register (address 00DA16) "1," execute write instruction status register (address 00D916) MST, bits "1." START condition will then generated. After that, counter becomes "0002" byte output. START condition generation timing timing different standard clock mode highspeed clock mode. Refer Figure 8.6.9 START condition generation timing diagram, Table 8.6.2 START condition/ STOP condition generation timing table.
status register write signal flag Setup time Setup time Hold time time flag
Fig. 8.6.9 START Condition Generation Timing Diagram
8.6.7 STOP Condition Generation Method
When control register (address 00DA16) "1," execute write instruction status register (address 00D916) setting "0". STOP condition will then generated. STOP condition generation timing flag reset timing different standard clock mode high-speed clock mode. Refer Figure 8.6.10 STOP condition generation timing diagram, Table 8.6.2 START condition/STOP condition generation timing table.
status register write signal flag Setup time Hold time Reset time flag
Fig. 8.6.10 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Timing Table Item Standard Clock Mode Setup time cycles) (START condition) Setup time 4.25 cycles) (STOP condition) cycles) Hold time Set/reset time cycles) flag High-speed Clock Mode cycles) 1.75 cycles) cycles) cycles)
Note: Absolute time MHz. value parentheses denotes number cycles.
Rev.
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M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.6.8 START/STOP Condition Detect Conditions
START/STOP condition detect conditions shown Figure 8.6.11 Table 8.6.3. Only when conditions Table 8.6.3 satisfied, START/STOP condition detected.
Note: When STOP condition detected slave mode (MST interrupt request signal "IICIRQ" generated CPU.
8.6.9 Address Data Communication
There address data communication formats, namely, 7-bit addressing format 10-bit addressing format. respective address communication formats described below.
7-bit addressing format
meet 7-bit addressing format, 10BIT control register (address 00DA16) "0." first 7-bit address data transmitted from master compared with high-order 7-bit slave address stored address register (address 00D816). time this comparison, address comparison address register (address 00D816) made. data transmission format when 7-bit addressing format selected, refer Figure 8.6.12, (2).
release time (START condition) (STOP condition) Setup time Setup time Hold time
10-bit addressing format
Hold time meet 10-bit addressing format, 10BIT control register (address 00DA16) "1." address comparison made between first-byte address data transmitted from master 7-bit slave address stored address register (address 00D816). time this comparison, address comparison between address register (address 00D816) which last address data transmitted from master made. 10-bit addressing mode, which last address data only specifies direction communication control data also processed address data bit. When first-byte address data matches slave address, status register (address 00D916) "1." After second-byte address data stored into data shift register (address 00D716), make address comparison between second-byte data slave address software. When address data bytes matches slave address, address register (address 00D816) software. This processing match 7-bit slave address data, which received after RESTART condition detected, with value address register (address 00D816). data transmission format when 10-bit addressing format selected, refer Figure 8.6.12, (4).
Fig. 8.6.11 START Condition/STOP Condition Detect Timing Diagram
Table 8.6.3 START Condition/STOP Condition Detect Conditions Standard Clock Mode cycles) release time 3.25 cycles) Setup time 3.25 cycles) Hold time High-speed Clock Mode cycles) release time cycles) Setup time cycles) Hold time
Note: Absolute time MHz. value parentheses denotes number cycles.
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.6.10 Example Master Transmission
example master transmission standard clock mode, frequency return mode shown below. slave address high-order bits address register (address 00D816) bit. return mode setting "8516" clock control register (address 00DB16). "1016" status register (address 00D916) hold HIGH. communication enable status setting "4816" control register (address 00DA16). address data destination transmission highorder bits data shift register (address 00D716) least significant bit. "F016" status register (address 00D916) generate START condition. this time, byte clock automatically occurs. transmit data data shift register (address 00D716). this time, clock automatically occurs. When transmitting control data more than byte, repeat step "D016" status register (address 00D916). After this, returned transmission ends, STOP condition will generated.
8.6.11 Example Slave Reception
example slave reception high-speed clock mode, frequency kHz, non-return mode, using addressing format, shown below. slave address high-order bits address register (address 00D816) bit. clock mode setting "2516" clock control register (address 00DB16). "1016" status register (address 00D916) hold HIGH. communication enable status setting "4816" control register (address 00DA16). When START condition received, address comparison made. transmitted address are"0" (general call): status register (address 00D916) "1"and interrupt request signal occurs. transmitted addresses match address status register (address 00D916) interrupt request signal occurs. cases other than above: status register (address 00D916) interrupt request signal occurs. dummy data data shift register (address 00D716). When receiving control data more than byte, repeat step When STOP condition detected, communication ends.
Rev.
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M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Slave address
Data
Data
bits bits bits master-transmitter transmits data slave-receiver
Slave address
Data
Data
bits bits bits master-receiver receives data from slave-transmitter Slave address bits Slave address byte
Data
Data
bits bits bits bits master-transmitter transmits data slave-receiver with 10-bit address Slave address bits Slave address byte Slave address bits
Data
Data bits
bits bits bits bits master-receiver receives data from slave-transmitter with 10-bit address START condition Restart condition STOP condition Read/Write From master slave From slave master
Fig. 8.6.12 Address Data Communication Format
8.6.12 Precautions when using multi-master I2C-BUS interface Read-modify-write instruction
precautions when raead-modify-write instruction such SEB, etc. executed each register multi-master I2C-BUS interface described below. data shift register (S0) When executing read-modify-write instruction this register during transfer, data become value intended. address register (S0D) When read-modify-write instruction executed this register detecting STOP condition, data become value intended. because hardware changes read/write (RBW) above timing. status register (S1) execute read-modify-write instruction this register because bits this register changed hardware. control register (S1D) When read-modify-write instruction executed this register detecting START condition completing byte transfer, data become value intended. Because hardware changes counter (BC0-BC2) above timing. clock control register (S2) read-modify-write instruction executed this register.
START condition generating procedure using multi-master
Procedure example (The necessary conditions generating procedure described following
5,S1,BUSBUSY BUSFREE: #$F0, BUSBUSY:
(Taking slave address value) (Interrupt disabled) flag confirming branch process) (Writing slave address value) (Trigger START condition generating) (Interrupt enabled)
(Interrupt enabled)
"STA," "STX" "STY" zero page addressing instruction writing slave address value data shift register. "LDM" instruction setting trigger START condition generating. Write slave address value above trigger START condition generating above continuously shown above procedure example. Disable interrupts during following three process steps: flag confirming Writing slave address value Trigger START condition generating When condition flag busy, enable interrupts immediately.
Rev.
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M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
RESTART condition generating procedure
Procedure example (The necessary conditions generating procedure described following Execute following procedure when "0." #$00, #$F0, Select slave receive mode when "0." write bit. Neither specified writing bit. becomes released. released writing slave address value data shift register. "STA," "STX" "STY" zero page addressing instruction writing. "LDM" instruction setting trigger RESTART condition generating. Write slave address value above trigger RESTART condition generating above continuously shown above procedure example. Disable interrupts during following process steps: Writing slave address value Trigger RESTART condition generating
STOP condition generating procedure
Procedure example (The necessary conditions generating procedure described following
(Select slave receive mode) (Taking slave address value) (Interrupt disabled) (Writing slave address value) (Trigger RESTART condition generating) (Interrupt enabled)
#$C0, #$D0,
(Interrupt disabled) (Select master transmit mode) (Set NOP) (Trigger STOP condition generating) (Interrupt enabled)
Write when master transmit mode select. Execute "NOP" instruction after setting master transmit mode. Also, trigger STOP condition generating within cycles after selecting master trasmit mode. Disable interrupts during following process steps: Select master transmit mode Trigger STOP condition generating
Writing status register
execute instruction from instruction bits from simultaneously. because enter state that released released after about machine cycle. execute instruction bits from simultaneously when "1." because become same above.
Process after STOP condition generating
write data data shift register status register until busy flag becomes after generating STOP condition master mode. because STOP condition waveform might normally generated. Reading above registers have problem.
Rev.
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M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
OUTPUT FUNCTION
This microcomputer equipped with 14-bit PWMs (DA1, DA2) 8-bit PWMs (PWM0-PWM5). have 14-bit resolution with minimum resolution width 0.25 repeat period 4096 (for f(XIN) MHz). PWM0-PWM5 have same circuit structure 8-bit resolution with minimum resolution width repeat period 1024 (for f(XIN) MHz). Figure 8.7.1 shows block diagram. timing generating circuit applies individual control signals DA1, PWM0-PWM5 using f(XIN) divided reference signal.
shown Figure 8.7.2 (b). kinds output (HIGH area: 0/256 255/256) selected changing contents register. length entirely HIGH output cannot output, i.e. 256/256.
8.7.4 Operating 14-bit
DA1, with 8-bit PWM, output control register (address 00D516) reset, already automatically), that count source supplied. Next, select output polarity output control register (address 00D616). Then, 14-bit outputs from output setting output control register reset, this already automatically) select output. with DA1, output control register (address 00D516) reset, already automatically), that count source supplied. Next, select output polarity output control register (address 00D616). Then, 14-bit outputs from output setting output control register reset, this already automatically) select output. output example 14-bit shown Figure 8.7.3. 14-bit divides data latch into low-order bits high-order bits. fundamental waveform determined with high-order 8-bit data "DH." HIGH area with length (HIGH area fundamental waveform) output every short area minimum resolution width ns). HIGH level area increase interval (tm) determined with low-order 6-bit data "DL." HIGH smaller intervals "tm" shown Table longer than that other smaller intervals repeat period 64t. Thus, rectangular waveform with different HIGH width output from pins Accordingly, output changes unit pulse width changing contents DAi-H DAi-L registers length entirely HIGH cannot output, 256/256.
8.7.1 Data Setting
When outputting DA1, first high-order bits DA1-H register (address 00CE16), then low-order bits DA1-L register (address 00CF16). When outputting DA1, first highorder bits DA2-H register (address 024E16), then loworder bits DA2-L register (address 024F16). When outputting PWM0-PWM5, 8-bit output data PWMi register means addresses 00D016 00D416, 00F616).
8.7.2 Transferring Data from Registers Circuit
Data transfer from 8-bit register 8-bit circuit executed writing data register. signal output from 8-bit output corresponds contents this register. Also, data transfer from register (addresses 00CE16 00CF16) 14-bit circuit executed writing data DA1-L register (address 00CF16). Reading from DA1-H register (address 00CE16) means reading this transferred data. Data transfer from register (addresses 024E16 024F16) 14bit circuit executed writing data DA2-L register (address 024F16). Reading from DA2-H register (address 024E16) means reading this transferred data. Accordingly, possible confirm data being output from output reading register.
8.7.5 Output after Reset
reset, output ports P00-P05 high-impedance state, contents register circuit undefined. Note that after reset, output undefined until setting register. Table 8.7.1 Relation Between Low-order 6-bit Data Highlevel Area Increase Interval Low-order bits Data Area Longer than That Other
8.7.3 Operating 8-bit
following explains operation. First, output control register (address 00D516) reset, already automatically), that count source supplied. PWM0-PWM5 also used pins P00-P05, respectively. PWM0-PWM5, corresponding bits ports direction register (output mode). select each output polarity output control register (address 00D616). Then, bits output control register (PWM output). waveform output from output pins setting these registers. Figure 8.7.2 shows 8-bit timing. cycle composed (28) segments. kinds pulses, relative weight each (bits output inside circuit during cycle. Refer Figure 8.7.2 (a). 8-bit outputs waveform which logical (OR) pulses corresponding contents bits 8-bit register. Several examples
000000 000001 000010 000100 001000 010000 100000
Nothing
Rev.
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M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Data
DA1-H register (Address 00CE16) latch bits)
DA1-L register (See note) (Address 00CF16)
14-bit circuit
DA2-H register (Address 024E16 latch bits)
DA2-L register (See note) (Address 024F16)
14-bit circuit timing generating circuit
register (Address 00D0
8-bit circuit
PWM0
PWM1
Selection gate: Connected black side reset. Pass gate Inside with others. same contents
PWM1 register (Address 00D116) PWM2 register (Address 00D216) PWM3 register (Address 00D316) PWM4 register (Address 00D416) PWM5 register (Address 00F616)
PWM2
PWM5 PWM4 PWM3
mode register [address 00D516] mode register [address 00D616] Port direction register [address 00C116] Port register [address 00C016] Port register [address 00C216] Port register [address 00C416]
Note: DAi-L register also used low-order bits latch
Fig. 8.7.1 Block Diagram
Rev.
3579
Fig. 8.7.2 Timing
Pulses showing weight each
0016
0116
1816 (24)
FF16 (255)
output 1024 f(XIN)
Example 8-bit
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Rev.
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M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
"2C16" DAi-H register.
"2816" DAi-L register.
[DAi-H register] writing DAi-L [DAi latch]
[DAi-L register]
writing DAi-L
These bits decide HIGH level area fundamental waveform.
HIGH level area fundamental waveform
These bits decide smaller interval "tm" which HIGH leval area [HIGH level area fundamental waveform
Minimum resolution width 0.25
High-order 8-bit value latch
Fundamental waveform
Waveform smaller interval "tm" specified low-order bits 0.25 µs44 0.25 µs45 0.25 14-bit output 8-bit counter
14-bit output 8-bit counter
Fundamental waveform smaller interval "tm" which specified low-order bits changed. 0.25 µs44 0.25
14-bit output Low-order 6-bit output latch Repeat period 4096
Note: indicates
Fig. 8.7.3 14-bit Timing (f(XIN) MHz)
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Output Control Register
output control register (PW) [Address 00D5 Name Functions Count source supply DA1, DA2, count source selection (PW0) Count source stop output output/P35 output selection (PW1) P00/PWM0 output selection (PW2) P01/PWM1 output selection (PW3) P02/PWM2 output selection (PW4) P03/PWM3 output selection (PW5) P04/PWM4 output selection (PW6) P05/PWM5 output selection (PW7) output PWM0 output output PWM1 output output PWM2 output output PWM3 output output PWM4 output output PWM5 output After reset
Fig. 8.7.4 Output Control Register
Output Control Register
output control register (PN) [Address 00D6 Name these bits "0." output polarity selection (PN3) output polarity selection (PN4) output polarity selection (PN5) P17/DA2 output selection (PN5) these bits "0." Functions After reset Positive polarity Negative polarity Positive polarity Negative polarity Output Output HIGH
Fig. 8.7.5 Output Control Register
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
CONVERTER 8.8.1 Conversion Register (AD)
conversion reigister read-only register that stores result conversion. This register should read during conversion.
8.8.3 Comparison Voltage Generator (Resistor Ladder)
voltage generator divides voltage between 256, outputs divided voltages comparator reference voltage Vref.
8.8.2 Control Register (ADCON)
control register controls conversion. Bits this register select analog input pins. When these pins used anlog input pins, they used ordinary pins. conversion completion bit, conversion started writing this bit. value this remains during conversion, then changes when conversion completed. controls connection between resistor ladder VCC. When using converter, resistor ladder from internal setting this "0," accordingly providing lowpower dissipation.
8.8.4 Channel Selector
channel selector connects analog input pin, selected bits control register, comparator.
8.8.5 Comparator Control Circuit
conversion result analog input voltage reference voltage "Vref" stored conversion register. conversion completion conversion interrupt request completion conversion.
Data
control register (address 00DF16)
control circuit A-D1 A-D2 A-D3 A-D4 A-D5 A-D6 A-D7 A-D8 Comparator conversion register (address 00DE16)
conversion interrupt request
Channel selector
Switch tree
Resistor ladder
Fig. 8.8.1 Converter Block Diagram
Rev.
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M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Control Register
control register (ADCON) [Address 00DF16]
Name
Analog input selection bits (ADIN0 ADIN2)
Functions
A-D1 A-D2 A-D3 A-D4 A-D5 A-D6 A-D7 A-D8
After reset
conversion completion (ADSTR) connection selection (ADVREF) this "0."
Conversion progress Convertion completed
Indeterm inate
Nothing assigned. This write disable bit. When this read out, value indeterminate. this "0."
Fig. 8.8.2 Control Register
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.8.6 Conversion Method
conversion interrupt request (even when conversion started, conversion interrupt reguest automatically). When using conversion interrupt, enable interrupts setting conversion interrupt enable setting interrupt disable flag "0." connection selection connect resistor ladder. Select analog input pins analog input selection control register. conversion completion "0." This write operation starts conversion. read conversion register during conversion. Verify completion conversion state ("1") conversion completion bit, state ("1") conversion interrupt reguest bit, occurrence conversion interrupt. Read conversion register obtain conversion results.
Note When ladder resistor disconnect from VCC, connection selection between steps
8.8.7 Internal Operation
When conversion starts, following operations automatically performed. conversion register "0016." most significant conversion register becomes comparison voltage "Vref" input comparator. this point, Vref compared with analog input voltage "VIN determined comparison results follows. When Vref holds When Vref becomes With above operations, analog value converted into digital value. conversion terminates maximum machine cycles (8.5 f(XIN) MHz) after starts, conversion result stored conversion register. conversion interrupt request occurs same time conversion completion, conversion interrupt request becomes "1." conversion completion also becomes "1."
Table 8.8.1 Expression Vref VREF conversion register contents (decimal notation)
Note: VREF indicates reference voltage Vcc).
Vref VREF 0.5)
Contents conversion register conversion start
Reference voltage (Vref)
VREF VREF VREF
VREF VREF VREF VREF VREF VREF
comparison start comparison start comparison start
comparison start
VREF VREF VREF VREF VREF
conversion completion (8th comparison completion)
Digital value corresponding analog input voltage.
Value determined result
Fig. 8.8.3 Changes Conversion Register Comparison Voltage during Conversion
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.8.8 Definition Conversion Accuracy
definition conversion accuracy described below (refer Figure 8.8.4).
EDifferential non-linearity error deviation input voltage required change output data "1," from corresponding ideal conversion characteristics between VREF. (Vn+1 1LSB 1LSB
Relative Accuracy
transition error (V0T) deviation input voltage which conversion output data changes from "1," from corresponding ideal conversion characteristics between VREF. VREF/256) 1LSB [LSB] Differential non-linearity error [LSB]
Absolute Accuracy
EAbsolute accuracy error deviation actual conversion characteristics, from ideal conversion characteristics between VREF. 1LSBA 1/2) Absolute accuracy error 1LSBA [LSB]
Full-scale transition error (VFST) deviation input voltage which conversion output data changes from "255" "254," from corresponding ideal conversion characteristics between VREF. VFST (VREF VREF/256) V254 1LSB [LSB]
Note: analog input voltage "Vn" which conversion output data changes from 254) follows (refer Figure 8.8.4)
Non-linearity error deviation actual conversion characteristics, from ideal conversion characteristics between V254. (1LSB 1LSB
1LSB with respect relative accuracy
V254 VREF
Non-linearity error
[LSB]
1LSBA with respect absolute accuracy
Output code 0916 0816 Absolute accuracy 0716 0616 0516 0416 0316 2LSB 0216 0116 0016 Analog input voltage (mV)
Fig. 8.8.4 Definition Conversion Accuracy
2LSB Ideal conversion characteristics Limitless resolution conversion characteristics
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
CORRECTION FUNCTION
This correct program data ROM. addresses corrected, program correction stored correction vector address. correction vectors vectors. Vector address 02C016 Vector address 02E016 Vector address 030016 address data corrected into correction address register. When value counter matches data address correction vector address, main program branches correction program stored memory correction. return from correction program main program, code operand instruction (total bytes) necessary correction program. correction function controlled correction enable register.
Notes instruction correction address. instruction (total bytes) return from correction program main program. same correction address vectors
correction address (high-order) 021716 correction address (low-order) 021816
correction address (high-order) 021916 correction address (low-order) 021A16
correction address (high-order) 021C16 correction address (low-order) 021D16
Fig. 8.9.1 Correction Address Registers
Correction Enable Register
correction enable register (RCR) [Address 021B16]
Name
Vector enable (RCR0) Vector enable (RCR1) Vector enable (RCR2) these bits "0."
Functions
Disabled Enabled Disabled Enabled Disabled Enabled
After reset
Fig. 8.9.2 Correction Enable Register
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.10 FUNCTIONS
This function display following types: "Block display characters lines) "SPRITE display" (display only character) "Raster patterning display" (display character entire screen side side) "Raster flat display" (coloring entire screen) above displays overlapped same time. priority SPRITE display Block display Raster flat display
Block display Raster patterning display Raster flat display
Note that raster patterning display SPRITE display cannot used simultaneously. Figure 8.10.2 shows block diagram circuit, Figure 8.10.3 shows configuration character display area, Figure 8.10.4 shows control register.
spla Type
(See note) Priorit
errupt eques
Function
SPRITE display (see note) Block display mode bordered Shadow bordered
SPRITE interrupt
Middle BUTTON mode bordered Shadow bordered Raster patterning display (See note)
interrupt
Bottom
Middle Bottom
Raster flat display
Note: Raster patterning display SPRITE display cannot used simultaneously.
Fig. 8.10.1 Display Types Function
Rev.
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M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Clock OSC1 HSYNC VSYNC
Main clock
Display ocsillation circuit
Control registers control circuit port control register Interrupt input polarity register Block register Block register SPRITE control register SPRITE register SPRITE register Color register control register polarity register Block control register Left border register Right border register border register Bottom border register (Address 00CB16) (Address 00CD16) (Address 00E016) (Addresses 00E116, 00E216) (Address 00E316) (Address 00E416) (Address 00E516) (Addresses 00E616 00E916, 00EC16 00EF16) (Address 00EA16) (Address 00EB16) (Addresses 00F916, 00FA16) (Address 024016) (Address 024116) (Address 024516) (Address 024616)
bits characters lines
dots dots characters
Shift register Output circuit
OUT1
OUT2
Data
Fig. 8.10.2 Block Diagram Circuit
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
SPRITE Display Block Display (OSD Mode)
dots
Block Display (BUTTON Mode)
dots
dots
dots
BUTTON display area (displayed only BUTTON mode)
Fig. 8.10.3 Configuration Character Display Area
Control Register
control register (OC) [Address 00EA16] Name control (OC0) (See note Border type selection (OC1) Functions All-blocks display All-blocks display bordered Shadow bordered (See note (See notes Standard Standard 1TOSC Standard 2TOSC Standard 3TOSC
After reset
Window horizontal position minute adjustment (OC2, OC3)
Window control (OC4)
Window Window
Scan mode selection Normal scan mode (OC5) Bi-scan mode (See note Raster color OUT1 control (OC6) Raster color OUT2 control (OC7) output Output output Output
Notes Even this switched during display, display screen remains unchanged until rising (falling) next VSYNC. Shadow border output right bottom side font. TOSC oscillation cycle These bits vallid both left border right border (for detail, refer "(8) Window Function.") When setting bi-scan mode, connect between pins OSC1 OSC2. Fig. 8.10.4 Control Register
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Clock
clock display used OSD, possible select following types. Main clock from pins XOUT Clock from oscillator supplied from pins OSC1 OSC2 Clock from ceramic resonator quartz-crystal oscillator from pins OSC1 OSC2 clock display used selected bits interrupt input polarity register (address 00CD16). besides, when selecting main clock, oscillation frequency MHz.
Interrupt Input Polarity Register
Interrupt input polarity register (IP) [Address 00CD16] Name Function Function clock supplied connecting across pins OSC1 OSC2. However, corresponding bi-scan mode. Since main clock used clock OSD, oscillation frequency limited. Because this, character size width (horizonal) direction also limited. this case, pins OSC1 OSC2 also used input ports respectively. After reset
clock selection bits (OCG0, OCG1)
oscillation frequency f(XIN)
clock supplied connecting across pins OSC1 OSC2. bi-scan mode, sure this. clock supplied connecting following across pins OSC1 OSC2. However, corresponding bi-scan mode. ceramic resonator only feedback resistor quartz-crystal oscillator only feedback resistor
this "0." INT1 polarity switch (POL1) INT2 polarity switch (POL2) INT3 polarity switch (POL3) Positive polarity Negative polarity Positive polarity Negative polarity Positive polarity Negative polarity
these bits "0."
Fig. 8.10.5 Interrupt Input Polarity Register
Rev.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Scan mode
This microcomputer bi-scan mode corresponding HSYNC double-speed frequency. bi-scan mode, vertical start display position vertical size times compared with normal scan mode. scan mode selected control register (refer Figure 8.10.3). Table 8.10.1 Setting Scan Mode Scan Mode Parameter Control Register Vertical Display Start Position Vertical Size Normal Scan Value vertical position register 1TOSC 2TOSC 3TOSC Bi-Scan Value vertical position register 1TOSC 2TOSC 3TOSC
Notes TOSC oscillation cycle HSYNC
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
input/output control
output pins OUT1 OUT2 also function ports P52, P53, P54, P55, respectively. Switch either output function port function port control register (address 00CB16). input polarity HSYNC, VSYNC output polarity signals OUT1 OUT2 specified with polarity register (address 00EB16). specify positive polarity;
specify negative polarity. Figure 8.10.6 shows polarity register Figure 8.10.7 shows port control register.
Polarity Register
polarity register (OPC) [Address 00EB16] Name HSYNC input polarity switch (OPC0) VSYNC input polarity switch (OPC1) Functions Positive polarity input Negative polarity input Positive polarity input Negative polarity input
R/G/B output polarity switch Positive polarity output Negative polarity output (OPC2) OUT1 output polarity switch (OPC3) OUT2 output polarity switch (OPC4) Raster color control (OPC5) Raster color control (OPC6) Raster color control (OPC7) Positive polarity output Negative polarity output Positive polarity output Negative polarity output output Output output Output output Output
Fig. 8.10.6 Polarity Register
Port Control Register
port control register [Address 00CB16]
Name
Functions
After reset
these bits Port output signal selection (P52SEL) Port output signal selection (P53SEL) Port output signal selection (P54SEL) Port output signal selection (P55SEL) Port output signal selection (OUT2SEL) this signal output Port output signal output Port output signal output Port output OUT1 signal output Port output Port signal output OUT2 output
Fig. 8.10.7 Port Control Register
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.10.1 Block Display
There display modes they selected block unit. display modes selected bits block control register features each mode described below. There extended display mode. This mode allows multiple lines lines more) displayed screen interrupting display each time line displayed rewriting data block which display terminated software. Table 8.10.2 Features Each Display Style Block Display
Display style Display mode Parameter Number display characters structure Kinds characters Kinds character sizes size Attribute Character font coloring Character background coloring output Raster coloring Other functions Display position Display expansion (multiline display) Notes TOSC oscillation cycle HSYNC SPRITE display effected window function. dots mode (On-screen display mode) characters lines dots Character display area: dots dots dots dots) kinds kinds 1TOSC 2TOSC 3TOSC (per block unit) (See notes Border (per block unit) Border (per block unit) BUTTON display (per character unit) Block shadow display (per character unit) screen: kinds (per character unit) screen: kinds (per character unit) Possible (per screen unit) Corresponding bi-scan Window function (See note Horizontal: levels, Vertical: levels Possible Block display BUTTON mode (BUTTON display mode)
Block Control Register
Block control register (BiC) [Addresses 00F916, 00FA16] Functions After reset Display mode Indeterminate Display mode border) BUTTON mode border) mode (border) BUTTON mode (border) Indeterminate size selection size (BiC3, BiC4) 1TOSC 2TOSC 3TOSC Nothing assigned. These bits write disable bits. When these bits read out, values "0." Name Display mode selection bits (BiC0 BiC2)
Notes TOSC oscillation cycle HSYNC
Fig. 8.10.8 Block Control Register
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Display position
display positions characters specified block. There blocks, blocks characters displayed each block (refer "(3) Memory OSD"). display position each block both horizontal vertical directions software. display start position horizontal direction blocks common 64-step display positions units 4TOSC (TOSC oscillation cycle). display start position vertical direction each block 255-step display positions units HSYNC cycle). Blocks displayed conformance with following rules: When display position block overlapped with block (Figure 8.10.9 (b)), block displayed front. When another block display position appears while block displayed (Figure 8.10.9 (c)), block with larger value vertical display start position displayed. display position SPRITE display, necessary independently, possible display positions independently. Refer "8.10.2 SPRITE Display."
B1VP Block B2VP Block
Example when each block separated
B1VP B2VP Block (Block displayed) Example when block overlaps with block
B1VP B2VP
Block Block
Example when block overlaps process block
Notes B1VP B2VP indicates vertical display start position display blocks indicates horizontal display start position display blocks
Fig. 8.10.9 Display Position
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
vertical display start position determined counting horizontal sync signal (HSYNC). this time, when VSYNC HSYNC positive polarity (negative polarity), starts count rising edge (falling edge) HSYNC signal from after fixed cycle rising edge (falling edge) VSYNC signal. interval from rising edge (falling edge) VSYNC signal rising edge (falling edge) HSYNC signal needs enough time machine cycles more) avoiding jitter. polarity HSYNC VSYNC signals select with polarity register (address 00EB16).
machine cycles more
VSYNC signal input 0.25 0.50 [µs] f(XIN) 8MHz) VSYNC control signal microcomputer Period counting HSYNC signal HSYNC signal input machine cycles more (See note
count When bits polarity control register (address 00EB16) (negative polarity) Notes vertical position determined counting falling edge HSYNC signal after rising edge VSYNC control signal microcomputer. generate falling edge HSYNC signal near rising edge VSYNC control signal microcomputer avoid jitter. pulse width VSYNC HSYNC needs machine cycles more.
Fig. 8.10.10 Supplement Explanation Display Position
vertical display start position each block steps (where each step HSYNC cycle)) values "0116" "FF16" block register (addresses 00E116 00E216). When setting block register "0116," display started count value HSYNC signal. vertical display start position here indicates position character display area OSD/ BUTTON mode. block register shown Figures 8.10.11.
Block Register
Block register (BiVP) [Addresses 00E116 00E216] Name Functions Control bits Vertical display start positions Hdef vertical display setting value, Hdef: 17H, HSYNC) start positions (BiVP0 BiVP7) (See note Note: values except "0016" BiVP. After reset Indeterminate
Fig. 8.10.11 Block Register
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
VSYNC
HSYNC (When setting "0116" block register, vertical display start position each mode)
screen
Hdef
Vertical display start position
Hdef
:Value block register (decimal) :17H
mode
BUTTON mode
When bits polarity register (address 00EB16) (negative polarity)
Fig. 8.10.12 Notes Vertical Display Start Position
horizontal display start position common blocks, steps (where step 4TOSC TOSC being oscillation cycle) values "0016" "3F16" block register (address 00E016). block register shown Figure 8.10.13.
Block Register
Horizontal position register (HP) [Address 00E016] Name Functions After reset
Control bits horizontal Horizontal display start positions Tdef1 4TOSC display start positions setting value, Tdef1: 31TOSC, (BHP0 BHP5) TOSC: oscillation cycle) (See note Nothing assigned. These bits write disable bits. Note: setting value synchronizes with VSYNC.
Fig. 8.10.13 Block Register
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
When setting block register "0016," needs 31TOSC Tdef1) from rising edge (negative polarity) HSYNC signal horizontal display start position. horizontal display start position here indicates left position character's BUTTON display area BUTTON mode. When also changing character size, horizontal display start position same. mode, display position shifted BUTTON display area (for dots) from that same character size BUTTON mode.
Horizontal display start position HSYNC Tdef1 4TOSC
BUTTON mode (1TOSC
BUTTON mode (2TOSC Value block register (decimal) TOSC oscillation cycle Tdef1 31TOSC
BUTTON mode (3TOSC
mode
Width BUTTON display area dots)
Fig. 8.10.14 Notes Horizontal Display Start Position
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
size
size selected block unit. size vertical direction determined dividing HSYNC vertical size control circuit. size horizontal determined dividing following clock horizontal size control circuit clock gained dividing clock source (OSC1, main clock from XIN) pre-divide circuit. size specified bits block control register.
Refer Figure 8.10.8 (the block control register). block diagram size control circuit shown Figure 8.10.15.
OSC1 Synchronous circuit
OCG0 OCG1
Clock cycle 1TOSC Horizontal size control circuit
Main clock
HSYNC
Vertical size control circuit
control circuit
Fig. 8.10.15 Block Diagram Size Control Circuit
1TOSC
2TOSC
3TOSC Scanning line F1(F2) Scanning line F2(F1)
Fig. 8.10.16 Definition Sizes
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Memory
There types memory (addresses 1140016 13BFF16 1540016 17AFF16) used specify character data (addresses 080016 0877) used specify characters, colors, attribute. following describes each type memory.
(addresses 1140016 13BFF16, 1540016 17AFF16) pattern data characters stored character font area ROM. specify kinds character font, necessary write character code (based address) into RAM. modes selected control register each screen. character font data storing address shown Figure 8.10.17.
address character font data
address Line number Character code Font AD16 AD15 AD14 AD13 AD12 AD11 AD10
Font
Character code (highorder
Line number
Character code (low-order bits)
Line number "0A16" "1D16" Character code "00016" "17F16" ("07F16", "08016" "17F16 cannot used.) Font Left area Right area
Line number
Left area
Right area
data 000016 7FF016 7FF816 601C16 600C16 600C16 600C16 600C16 601C16 7FF816 7FF016 630016 638016 61C016 60E016 607016 603816 601C16 600C16 000016
Character font
Fig. 8.10.17 Character Font Data Storing Address
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Note: 120-byte addresses corresponding character code "07F16," "08016" "17F16" test data storing area. "FF16" area. stores test data this area different data from "FF16" stored actual products.) <The test data storing area> 1100016 10016 FE16 1100016 10016 0116 1500016 10016 FE16 1500016 10016 0116 Address area
addresses 114FE16 1150116 addresses 116FE16 1170116 addresses 138FE16 1390116 addresses 13AFE16 13B0116 addresses 154FE16 154FF16 addresses 156FE16 156FF16 addresses 178FE16 178FF16 addresses 17AFE16 17AFF16
(addresses 080016 087716) character allocated addresses 080016 084716, 085016 085716, 086016 086716, 087016 087716, divided into display character code specification part 087016 087716, color/attribute specification part each block. Tables 8.10.3 shows contents RAM. example, display character position (the left edge) block write character code address 080016, write color/attribute code 081016. structure shown Figure 8.10.18.
Table 8.10.3 Contents Display Position (from left) Block character character character 16th character 17st character 24nd character character character character 16th character 17st character 24nd character
Character Code Specification 080016 080116 080216 080F16 084016 084716 082016 082116 082216 082F16 086016 086716
Color/Attribute Code Specification 081016 081116 081216 081F16 085016 085716 083016 083116 083216 083F16 087016 087716
Block
Block
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Blocks
OUT2 control Attribute code (See note
Mode
Color code
Character code (See note
BUTTON Mode
Mode name Character code Character code Character code Function
name Character code
Function
Color code
Color code
Attribute code OUT2 control
Color register Color register Color register Color register Color register Color register Color register Color register used
Color register Color register Color register Color register Color register Color register Color register Color register
BUTTON/block shadow display BUTTON display BUTTON display Block shadow display OUT2 control OUT2 blank output OUT2 blank output
OUT2 blank output OUT2 blank output
Notes Attribute code valid only BUTTON mode. character codes "07F16," "08016," "17F16." also, character codes "18016" "1FF16" (these codes included area).
Fig. 8.10.18 Structure
Rev.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Character color
Character colors specified RAM. Color data color register (CO1 CO8: addresses 00E616 00E916, 00EC16 00EF16) advance, kinds color register specified color codes.
OUT1, OUT2 signals
OUT1 signal used erase back ground image. output waveform OUT1 signal controlled combining following bits; display mode selection bits (bits block control register), border type selection (bit control register), OUT1 output control (bit color register Figure 8.10.20 8.10.21 shows output example OUT1. OUT2 signal used change luminance background image. output waveform OUT2 signal blank output controlled character unit RAM.
Character background color
Character background specified color register same character color.
Note character background displayed following part: (character display area) (character font) (border) (BUTTON display area) Accordingly, character background color color signal these sections cannot mixed.
Color Register
Color register (CO1 CO8) (i=1 [Addresses 00E616 00E916, 00EC16 00EF16]
Name signal output selection (COi0) signal output selection (COi1) signal output selection (COi2)
Functions output Output output Output output Output
After
Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
signal output (background) output selection (COi3) Output signal output (background) output selection (COi4) Output signal output (background) output Output selection (COi5) OUT1 output control (COi6) Character output Blank output
Nothing assined. This write disable bit. When this read out, value "0."
Fig. 8.10.19 Color register
Rev.
color register output OUT1 output Display example
FONT (See note FONT
Display mode output (background output)
output
(Not bordered)
FONT AREA FONT AREA
FONT
(See note
FONT BORDER
output
(Bordered)
FONT
AREA- FONT BORDER
=AREA
GREEN FONT= font pattern output
BLUE
AREA character display area mode
mode character display area (AREA) BUTTON mode character display area
BLACK OUT1)
Fig. 8.10.20 Output Example OUT1 (Character Color: Green, Character Background Color: Blue) Mode)
WHITE
BORDER border pattern output around FONT BUTTON buttun display output around AREA
Notes when positive polarity selected. Examples bordered display shown.
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Rev.
Rev.
color register output OUT1 output Display example
FONT BUTTON
Display mode
FONT BUTTON BUTTON
output (background output)
(Not bordered)
FONT BUTTON AREA BUTTON FONT AREA BUTTON
FONT BUTTON BUTTON
FONT BORDER BUTTON
(Bordered)
FONT BUTTON
AREA BUTTON FONT -BORDER
AREA BUTTON
GREEN FONT= font pattern output
BLUE
AREA character display area mode
mode character display area (AREA) BUTTON mode character display area
BLACK OUT1)
WHITE
BORDER border pattern output around FONT BUTTON buttun display output around AREA
Fig. 8.10.21 Output Example OUT1 (Character Color: Green, Character Background Color: Blue) BUTTON Mode)
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
Notes when positive polarity selected. Examples bordered display shown. Examples BUTTON display shown.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M37225M6/M8/MA/MC-XXXSP M37225ECSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Attribute (block display)
attributes (border, BUTTON display, block shadow display) controlled character font. display mode specified bloc
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