Cautions Keep safety first your circuit designs! Renesas Technolo
|
|
|
Top Searches for this datasheet
Cautions
Keep safety first your circuit designs! Renesas Technology Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) nonflammable material (iii) prevention against malfunction mishap. Notes regarding these materials These materials intended reference assist customers selection Renesas Technology Corporation product best suited customer's application; they convey license under intellectual property rights, other rights, belonging Renesas Technology Corporation third party. Renesas Technology Corporation assumes responsibility damage, infringement third-party's rights, originating product data, diagrams, charts, programs, algorithms, circuit application examples contained these materials. information contained these materials, including product data, diagrams, charts, programs algorithms represents information products time publication these materials, subject change Renesas Technology Corporation without notice product improvements other reasons. therefore recommended that customers contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor latest product information before purchasing product listed herein. information described here contain technical inaccuracies typographical errors. Renesas Technology Corporation assumes responsibility damage, liability, other loss rising from these inaccuracies errors. Please also attention information published Renesas Technology Corporation various means, including Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). When using information contained these materials, including product data, diagrams, charts, programs, algorithms, please sure evaluate information total system before making final decision applicability information products. Renesas Technology Corporation assumes responsibility damage, liability other loss resulting from information contained herein. Renesas Technology Corporation semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor when considering product contained herein specific purposes, such apparatus systems transportation, vehicular, medical, aerospace, nuclear, undersea repeater use. prior written approval Renesas Technology Corporation necessary reprint reproduce whole part these materials. these products technologies subject Japanese export control restrictions, they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations Japan and/or country destination prohibited. Please contact Renesas Technology Corporation further details these materials products contained therein.
Hitachi 16-Bit Microcomputer
H8/3008
Hardware Manual
ADE-602-221B Rev. 5/31/02 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
H8/3008 high-performance single-chip microcomputer that incorporates internal 32-bit H8/300H also equipped with peripheral functions necessary configuring user system. H8/3008 built with variety peripheral functions such ROM, RAM, 16-bit timer, 8-bit timer, programmable timing pattern controller (TPC), watchdog timer (WDT), serial communication interface (SCI), converter, converter ports. Target Readers: This manual designed people design application systems using H/3008. this manual, basic knowledge electric circuits, logic circuits microcomputers required. Purpose: This manual provides information hardware functions electrical characteristics H8/3008. H8/300H Series Programming Manual contains detailed information executable instructions. Please read Programming Manual together with this manual. Book: understand general functions Read manual from beginning. manual explains CPU, system control functions, peripheral functions electrical characteristics that order. understanding functions Refer separate H8/300H Series Programming Manual. detailed functions registers with known names Refer Appendix "Internal Registers" summary addresses, description initialization. Explanatory Note: sequence: upper left, lower right List Related Documents: latest documents available site. Please make sure that have latest version. User manual H8/3008
Name Document H8/3008 Hardware Manual H8/300H Series Programming Manual Document This manual ADE-602-053
User manual development tools
Name Document C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual Hitachi Embedded Workshop User's Manual H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging Interface User's Manual Document ADE-702-247 ADE-702-037 ADE-702-201 ADE-702-231
Application note
Name Document H8/300H Application Note H8/300H On-Chip Supporting Modules Application Note H8/300H Technical Document ADE-502-033 ADE-502-035 ADE-502-038
List Items Revised Added This Version
Section 1.3.1 Arrangement 1.3.2 Functions 1.3.3 Assignments Each Mode 14.1.1 Features 17.2.1 Connecting Crystal Resonator 17.2.2 External Clock Input Page Item Description Table Comparison Amended table H8/3008 Arrangements Table Functions number table amended
Table Assignments (vCL)*3 added mode Each Mode (FP-100B, through mode TFP-100B) High-speed conversion Table 17.2 Crystal Resonator Parameters Table 17.3 Clock Timing (Preliminary) Amended Conversion time Amended table Amended amended external clock input high pulse width minimum values from amended external clock rise lower time maximum values from Incorrect recommended setting time amended Deleted word preliminary Table 19.1 Absolute Maximum Ratings Amended values power supply voltage analog power supply voltage versions Amended table note Amended conditions Amended condition amended clock cycle time clock pulse high width minimum values, well clock rise fall time maximum values, condition column
18.4.3 Selection Waiting Time Exit from Software Standby Mode Section Electrical Characteristics 19.1 Absolute Maximum Ratings
Table 18.3 Clock Frequency Waiting Time Clock Settle
19.2 Characteristics
Table 19.2 Characteristics Table 19.3 Permissible Output Currents Table 19.4 Clock Timing
19.3 Characteristics
Section 19.3 Characteristics
Page
Item Table 19.5 Control Signal Timing
Description Amended condition amended setup time NMI, setup time minimum values, well RESO output delay time maximum value, condition column Amended condition amended minimum maximum values condition column Amended condition amended output data delay time timer output delay time maximum values condition column Input clock rise time input clock fall time values conditions table amended
461,
Table 19.6 Timing
Table 19.7 Timing OnChip Supporting Modules
19.4 Conversion Characteristics
465,
Table 19.8 Conversion Characteristics
Amended condition amended conversion time (single mode) minimum values, maximum values, units Permissible signal-source impedance, nonlinearity error, offset error, full-scale error, absolute accuracy max. values condition amended. Permissible signal-source impedance entries deleted
19.5 Conversion Characteristics Differences between H8/3067 H8/3062 Series, H8/3048 Series, H8/3006 H8/3007, H8/3008
Table 19.9 Conversion Characteristics
Amended condition B-mask version notation added flash memory functions description H8/3067 Series, H8/3062 Series
Comparison Functions 100-Pin Package Products (FP-100B, TFP100B)
Table Arrangement Each Product (FP-100B, TFP100B)
Note description amended B-mask version
Contents
Section Overview.
Overview. Block Diagram. Description 1.3.1 Arrangement 1.3.2 Functions. 1.3.3 Assignments Each Mode.
Section
Overview. 2.1.1 Features 2.1.2 Differences from H8/300 CPU. Operating Modes Address Space. Register Configuration 2.4.1 Overview 2.4.2 General Registers. 2.4.3 Control Registers. 2.4.4 Initial Register Values Data Formats. 2.5.1 General Register Data Formats 2.5.2 Memory Data Formats. Instruction Set. 2.6.1 Instruction Overview. 2.6.2 Instructions Addressing Modes 2.6.3 Tables Instructions Classified Function. 2.6.4 Basic Instruction Formats. 2.6.5 Notes Manipulation Instructions. Addressing Modes Effective Address Calculation 2.7.1 Addressing Modes. 2.7.2 Effective Address Calculation. Processing States. 2.8.1 Overview 2.8.2 Program Execution State 2.8.3 Exception-Handling State 2.8.4 Exception Handling Operation 2.8.5 Bus-Released State 2.8.6 Reset State 2.8.7 Power-Down State.
Basic Operational Timing. 2.9.1 Overview 2.9.2 On-Chip Memory Access Timing 2.9.3 On-Chip Supporting Module Access Timing. 2.9.4 Access External Address Space
Section Operating Modes
Overview. 3.1.1 Operating Mode Selection. 3.1.2 Register Configuration Mode Control Register (MDCR) System Control Register (SYSCR). Operating Mode Descriptions. 3.4.1 Mode 3.4.2 Mode 3.4.3 Mode 3.4.4 Mode 3.4.5 Modes Functions Each Operating Mode. Memory Each Operating Mode. 3.6.1 Reserved Areas.
Section Exception Handling
Overview. 4.1.1 Exception Handling Types Priority 4.1.2 Exception Handling Operation 4.1.3 Exception Vector Table. Reset 4.2.1 Overview 4.2.2 Reset Sequence. 4.2.3 Interrupts after Reset Interrupts. Trap Instruction Stack Status after Exception Handling Notes Stack Usage.
Section Interrupt Controller
Overview. 5.1.1 Features 5.1.2 Block Diagram. 5.1.3 Configuration 5.1.4 Register Configuration Register Descriptions.
5.2.1 System Control Register (SYSCR) 5.2.2 Interrupt Priority Registers (IPRA, IPRB) 5.2.3 Status Register (ISR) 5.2.4 Enable Register (IER) 5.2.5 Sense Control Register (ISCR). Interrupt Sources. 5.3.1 External Interrupts. 5.3.2 Internal Interrupts 5.3.3 Interrupt Exception Handling Vector Table Interrupt Operation 5.4.1 Interrupt Handling Process 5.4.2 Interrupt Exception Handling Sequence 5.4.3 Interrupt Response Time Usage Notes 5.5.1 Contention between Interrupt Interrupt-Disabling Instruction. 5.5.2 Instructions that Inhibit Interrupts. 5.5.3 Interrupts during EEPMOV Instruction Execution
Section Controller
Overview. 6.1.1 Features 6.1.2 Block Diagram. 6.1.3 Configuration 6.1.4 Register Configuration Register Descriptions. 6.2.1 Width Control Register (ABWCR) 6.2.2 Access State Control Register (ASTCR). 6.2.3 Wait Control Registers (WCRH, WCRL). 6.2.4 Release Control Register (BRCR) 6.2.5 Control Register (BCR) 6.2.6 Chip Select Control Register (CSCR). 6.2.7 Address Control Register (ADRCR). Operation 6.3.1 Area Division. 6.3.2 Specifications 6.3.3 Memory Interfaces. 6.3.4 Chip Select Signals. 6.3.5 Address Output Method Basic Interface. 6.4.1 Overview 6.4.2 Data Size Data Alignment 6.4.3 Valid Strobes 6.4.4 Memory Areas.
6.4.5 Basic Control Signal Timing. 6.4.6 Wait Control Idle Cycle. 6.5.1 Operation 6.5.2 States Idle Cycle Arbiter 6.6.1 Operation Register Input Timing 6.7.1 Register Write Timing. 6.7.2 BREQ Input Timing.
Section Ports
Overview. Port 7.2.1 Overview 7.2.2 Register Descriptions. Port 7.3.1 Overview 7.3.2 Register Descriptions. Port 7.4.1 Overview 7.4.2 Register Description Port 7.5.1 Overview 7.5.2 Register Descriptions. Port 7.6.1 Overview 7.6.2 Register Descriptions. Port 7.7.1 Overview 7.7.2 Register Descriptions. Port 7.8.1 Overview 7.8.2 Register Descriptions.
Section 16-Bit Timer
Overview. 8.1.1 Features 8.1.2 Block Diagrams. 8.1.3 Configuration 8.1.4 Register Configuration Register Descriptions. 8.2.1 Timer Start Register (TSTR).
8.2.2 Timer Synchro Register (TSNC). 8.2.3 Timer Mode Register (TMDR) 8.2.4 Timer Interrupt Status Register (TISRA) 8.2.5 Timer Interrupt Status Register (TISRB). 8.2.6 Timer Interrupt Status Register (TISRC). 8.2.7 Timer Counters (16TCNT). 8.2.8 General Registers (GRA, GRB) 8.2.9 Timer Control Registers (16TCR). 8.2.10 Timer Control Register (TIOR) 8.2.11 Timer Output Level Setting Register (TOLR). Interface 8.3.1 16-Bit Accessible Registers. 8.3.2 8-Bit Accessible Registers. Operation 8.4.1 Overview 8.4.2 Basic Functions 8.4.3 Synchronization. 8.4.4 Mode 8.4.5 Phase Counting Mode 8.4.6 16-Bit Timer Output Timing Interrupts. 8.5.1 Setting Status Flags. 8.5.2 Timing Clearing Status Flags 8.5.3 Interrupt Sources Usage Notes
Section 8-Bit Timers.
Overview. 9.1.1 Features 9.1.2 Block Diagram. 9.1.3 Configuration 9.1.4 Register Configuration Register Descriptions. 9.2.1 Timer Counters (8TCNT). 9.2.2 Time Constant Registers (TCORA) 9.2.3 Time Constant Registers (TCORB). 9.2.4 Timer Control Register (8TCR) 9.2.5 Timer Control/Status Registers (8TCSR) Interface 9.3.1 8-Bit Registers. Operation 9.4.1 8TCNT Count Timing. 9.4.2 Compare Match Timing
9.4.3 Input Capture Signal Timing. 9.4.4 Timing Status Flag Setting. 9.4.5 Operation with Cascaded Connection 9.4.6 Input Capture Setting. Interrupt 9.5.1 Interrupt Sources 9.5.2 Converter Activation 8-Bit Timer Application Example Usage Notes 9.7.1 Contention between 8TCNT Write Clear. 9.7.2 Contention between 8TCNT Write Increment 9.7.3 Contention between TCOR Write Compare Match 9.7.4 Contention between TCOR Read Input Capture 9.7.5 Contention between Counter Clearing Input Capture Counter Increment. 9.7.6 Contention between TCOR Write Input Capture 9.7.7 Contention between 8TCNT Byte Write Increment 16-Bit Count Mode (Cascaded Connection) 9.7.8 Contention between Compare Matches 9.7.9 8TCNT Operation Internal Clock Source Switchover
Section Programmable Timing Pattern Controller (TPC).
10.1 Overview. 10.1.1 Features 10.1.2 Block Diagram. 10.1.3 Configuration 10.1.4 Register Configuration 10.2 Register Descriptions. 10.2.1 Port Data Direction Register (PADDR) 10.2.2 Port Data Register (PADR) 10.2.3 Port Data Direction Register (PBDDR). 10.2.4 Port Data Register (PBDR). 10.2.5 Next Data Register (NDRA) 10.2.6 Next Data Register (NDRB) 10.2.7 Next Data Enable Register (NDERA). 10.2.8 Next Data Enable Register (NDERB) 10.2.9 Output Control Register (TPCR) 10.2.10 Output Mode Register (TPMR) 10.3 Operation 10.3.1 Overview 10.3.2 Output Timing 10.3.3 Normal Output 10.3.4 Non-Overlapping Output
10.3.5 Output Triggering Input Capture 10.4 Usage Notes 10.4.1 Operation Output Pins 10.4.2 Note Non-Overlapping Output.
Section Watchdog Timer
11.1 Overview. 11.1.1 Features 11.1.2 Block Diagram. 11.1.3 Configuration 11.1.4 Register Configuration 11.2 Register Descriptions. 11.2.1 Timer Counter (TCNT) 11.2.2 Timer Control/Status Register (TCSR) 11.2.3 Reset Control/Status Register (RSTCSR) 11.2.4 Notes Register Access 11.3 Operation 11.3.1 Watchdog Timer Operation. 11.3.2 Interval Timer Operation. 11.3.3 Timing Setting Overflow Flag (OVF) 11.3.4 Timing Setting Watchdog Timer Reset (WRST) 11.4 Interrupts. 11.5 Usage Notes
Section Serial Communication Interface
12.1 Overview. 12.1.1 Features 12.1.2 Block Diagram. 12.1.3 Configuration 12.1.4 Register Configuration 12.2 Register Descriptions. 12.2.1 Receive Shift Register (RSR). 12.2.2 Receive Data Register (RDR) 12.2.3 Transmit Shift Register (TSR). 12.2.4 Transmit Data Register (TDR) 12.2.5 Serial Mode Register (SMR). 12.2.6 Serial Control Register (SCR). 12.2.7 Serial Status Register (SSR). 12.2.8 Rate Register (BRR). 12.3 Operation 12.3.1 Overview 12.3.2 Operation Asynchronous Mode. 12.3.3 Multiprocessor Communication
12.3.4 Synchronous Operation 12.4 Interrupts 12.5 Usage Notes 12.5.1 Notes
Section Smart Card Interface
13.1 Overview. 13.1.1 Features 13.1.2 Block Diagram. 13.1.3 Configuration 13.1.4 Register Configuration 13.2 Register Descriptions. 13.2.1 Smart Card Mode Register (SCMR) 13.2.2 Serial Status Register (SSR). 13.2.3 Serial Mode Register (SMR). 13.2.4 Serial Control Register (SCR). 13.3 Operation 13.3.1 Overview 13.3.2 Connections. 13.3.3 Data Format. 13.3.4 Register Settings. 13.3.5 Clock 13.3.6 Transmitting Receiving Data. 13.4 Usage Notes
Section Converter
14.1 Overview. 14.1.1 Features 14.1.2 Block Diagram. 14.1.3 Configuration 14.1.4 Register Configuration 14.2 Register Descriptions. 14.2.1 Data Registers (ADDRA ADDRD). 14.2.2 Control/Status Register (ADCSR). 14.2.3 Control Register (ADCR). 14.3 Interface 14.4 Operation 14.4.1 Single Mode (SCAN 14.4.2 Scan Mode (SCAN 14.4.3 Input Sampling Conversion Time. 14.4.4 External Trigger Input Timing 14.5 Interrupts. 14.6 Usage Notes
viii
Section Converter
15.1 Overview. 15.1.1 Features 15.1.2 Block Diagram. 15.1.3 Configuration 15.1.4 Register Configuration 15.2 Register Descriptions. 15.2.1 Data Registers (DADR0, DADR1). 15.2.2 Control Register (DACR). 15.2.3 Standby Control Register (DASTCR) 15.3 Operation 15.4 Output Control
Section
16.1 Overview. 16.1.1 Block Diagram. 16.1.2 Register Configuration 16.2 System Control Register (SYSCR). 16.3 Operation
Section Clock Pulse Generator
17.1 Overview. 17.1.1 Block Diagram 17.2 Oscillator Circuit 17.2.1 Connecting Crystal Resonator 17.2.2 External Clock Input 17.3 Duty Adjustment Circuit. 17.4 Prescalers 17.5 Frequency Divider 17.5.1 Register Configuration 17.5.2 Division Control Register (DIVCR) 17.5.3 Usage Notes.
Section Power-Down State.
18.1 Overview. 18.2 Register Configuration 18.2.1 System Control Register (SYSCR) 18.2.2 Module Standby Control Register (MSTCRH). 18.2.3 Module Standby Control Register (MSTCRL). 18.3 Sleep Mode. 18.3.1 Transition Sleep Mode 18.3.2 Exit from Sleep Mode 18.4 Software Standby Mode
18.4.1 Transition Software Standby Mode. 18.4.2 Exit from Software Standby Mode. 18.4.3 Selection Waiting Time Exit from Software Standby Mode. 18.4.4 Sample Application Software Standby Mode. 18.4.5 Note 18.5 Hardware Standby Mode 18.5.1 Transition Hardware Standby Mode 18.5.2 Exit from Hardware Standby Mode 18.5.3 Timing Hardware Standby Mode 18.6 Module Standby Function. 18.6.1 Module Standby Timing. 18.6.2 Read/Write Module Standby. 18.6.3 Usage Notes. 18.7 System Clock Output Disabling Function
Section Electrical Characteristics
19.1 19.2 19.3 19.4 19.5 19.6 Absolute Maximum Ratings. Characteristics Characteristics Conversion Characteristics Conversion Characteristics Operational Timing. 19.6.1 Clock Timing. 19.6.2 Control Signal Timing. 19.6.3 Timing 19.6.4 Port Timing 19.6.5 Timer Input/Output Timing. 19.6.6 Input/Output Timing
Appendix Instruction
Instruction List. Operation Code Maps. Number States Required Execution.
Appendix Internal Registers.
Address List Functions.
Appendix Port Block Diagrams
Port Block Diagram. Port Block Diagrams Port Block Diagrams Port Block Diagrams
Port Block Diagrams Port Block Diagrams. Port Block Diagrams.
Appendix States
Port States Each Mode States Reset.
Appendix Appendix
Timing Transition Recovery from Hardware Standby Mode Product Code Lineup
Appendix Package Dimensions Appendix Comparison H8/300H Series Product Specifications
Differences between H8/3067 H8/3062 Series, H8/3048 Series, H8/3006 H8/3007, H8/3008. Comparison Functions 100-Pin Package Products (FP-100B, TFP-100B)
Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 2.10 Figure 2.11 Figure 2.12 Figure 2.13 Figure 2.14 Figure 2.15 Figure 2.16 Figure 2.17 Figure 2.18 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Block Diagram. Arrangement H8/3008 (FP-100B TFP-100B Package, View) Operating Modes Memory Map. Registers Usage General Registers Stack General Register Data Formats General Register Data Formats Memory Data Formats. Instruction Formats Memory-Indirect Branch Address Specification. Processing States Classification Exception Sources. State Transitions Stack Structure after Exception Handling On-Chip Memory Access Cycle States during On-Chip Memory Access (Address Update Mode Access Cycle On-Chip Supporting Modules. States during Access On-Chip Supporting Modules. Memory H8/3008 Each Operating Mode Exception Sources Reset Sequence (Modes Reset Sequence (Modes Interrupt Sources Number Interrupts Stack after Completion Exception Handling. Operation when Value Odd. Interrupt Controller Block Diagram Block Diagram Interrupts IRQ5 IRQ0 Timing Setting IRQnF Process Interrupt Acceptance when Interrupt Masking State Transitions (Example) Process Interrupt Acceptance when Interrupt Exception Handling Sequence Contention between Interrupt Interrupt-Disabling Instruction. Block Diagram Controller Access Area Each Operating Mode. Memory 16-Mbyte Mode. Signal Output Timing Sample Address Output Each Address Update Mode (Basic Interface, 3-State Space) Example Consecutive External Space Accesses Address Update Mode
Figure Figure Figure Figure 6.10 Figure 6.11 Figure 6.12 Figure 6.13 Figure 6.14 Figure 6.15 Figure 6.16 Figure 6.17 Figure 6.18 Figure 6.19 Figure 6.20 Figure 6.21 Figure 6.22 Figure 6.23 Figure 6.24 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 8.10 Figure 8.11 Figure 8.12
Access Sizes Data Alignment Control (8-Bit Access Area). Access Sizes Data Alignment Control (16-Bit Access Area). Control Signal Timing 8-Bit, Three-State-Access Area. Control Signal Timing 8-Bit, Two-State-Access Area. Control Signal Timing 16-Bit, Three-State-Access Area (Byte Access Even Address) Control Signal Timing 16-Bit, Three-State-Access Area (Byte Access Address) Control Signal Timing 16-Bit, Three-State-Access Area (Word Access). Control Signal Timing 16-Bit, Two-State-Access Area (Byte Access Even Address) Control Signal Timing 16-Bit, Two-State-Access Area (Byte Access Address) Control Signal Timing 16-Bit, Two-State-Access Area (Word Access). Example Wait State Insertion Timing. Example Idle Cycle Operation (ICIS1 Example Idle Cycle Operation (ICIS0 Example Idle Cycle Operation Example External Master Operation ASTCR Write Timing Write Timing. BRCR Write Timing Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration. Port Configuration. 16-bit timer Block Diagram (Overall). Block Diagram Channels Block Diagram Channel 16TCNT Access Operation [CPU 16TCNT (Word)]. Access Timer Counter (CPU Reads 16TCNT, Word) Access Timer Counter (CPU Writes 16TCNTH, Upper Byte). Access Timer Counter (CPU Writes 16TCNTL, Lower Byte) Access Timer Counter (CPU Reads 16TCNTH, Upper Byte) Access Timer Counter (CPU Reads 16TCNTL, Lower Byte) 16TCR Access (CPU Writes 16TCR). 16TCR Access (CPU Reads 16TCR) Counter Setup Procedure (Example).
xiii
Figure 8.13 Figure 8.14 Figure 8.15 Figure 8.16 Figure 8.17 Figure 8.18 Figure 8.19 Figure 8.20 Figure 8.21 Figure 8.22 Figure 8.23 Figure 8.24 Figure 8.25 Figure 8.26 Figure 8.27 Figure 8.28 Figure 8.29 Figure 8.30 Figure 8.31 Figure 8.32 Figure 8.33 Figure 8.34 Figure 8.35 Figure 8.36 Figure 8.37 Figure 8.38 Figure 8.39 Figure 8.40 Figure 8.41 Figure 8.42 Figure 8.43 Figure 8.44 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 9.10
Free-Running Counter Operation Periodic Counter Operation. Count Timing Internal Clock Sources Count Timing External Clock Sources (when Both Edges Detected) Setup Procedure Waveform Output Compare Match (Example) Output (TOA Toggle Output (TOA Output Compare Output Timing Setup Procedure Input Capture (Example) Input Capture (Example) Input Capture Signal Timing. Setup Procedure Synchronization (Example) Synchronization (Example). Setup Procedure Mode (Example) Mode (Example Mode (Example Setup Procedure Phase Counting Mode (Example). Operation Phase Counting Mode (Example). Phase Difference, Overlap, Pulse Width Phase Counting Mode Timing Setting 16-Bit Timer Output Level Writing TOLR Timing Setting IMFA IMFB Compare Match. Timing Setting IMFA IMFB Input Capture Timing Setting Timing Clearing Status Flags Contention between 16TCNT Write Clear. Contention between 16TCNT Word Write Increment Contention between 16TCNT Byte Write Increment. Contention between General Register Write Compare Match Contention between 16TCNT Write Overflow Contention between General Register Read Input Capture. Contention between Counter Clearing Input Capture Counter Increment. Contention between General Register Write Input Capture. Block Diagram 8-Bit Timer Unit (Two Channels: Group 8TCNT Access Operation (CPU Writes 8TCNT, Word) 8TCNT Access Operation (CPU Reads 8TCNT, Word). 8TCNT0 Access Operation (CPU Writes 8TCNT0, Upper Byte) 8TCNT1 Access Operation (CPU Writes 8TCNT1, Lower Byte) 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte) 8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte). Count Timing Internal Clock Input Count Timing External Clock Input (Both-Edge Detection). Timing Timer Output
Figure 9.11 Figure 9.12 Figure 9.13 Figure 9.14 Figure 9.15 Figure 9.16 Figure 9.17 Figure 9.18 Figure 9.19 Figure 9.20 Figure 9.21 Figure 9.22
Timing Clear Compare Match Timing Clear Input Capture Timing Input Capture Input Signal Flag Setting Timing when Compare Match Occurs. CMFB Flag Setting Timing when Input Capture Occurs Timing Setting Example Pulse Output. Contention between 8TCNT Write Clear. Contention between 8TCNT Write Increment Contention between TCOR Write Compare Match Contention between TCOR Read Input Capture Contention between Counter Clearing Input Capture Counter Increment. Figure 9.23 Contention between TCOR Write Input Capture Figure 9.24 Contention between 8TCNT Byte Write Increment 16-Bit Count Mode Figure 10.1 Block Diagram Figure 10.2 Output Operation. Figure 10.3 Timing Transfer Next Data Register Contents Output (Example) Figure 10.4 Setup Procedure Normal Output (Example) Figure 10.5 Normal Output Example (Five-Phase Pulse Output) Figure 10.6 Setup Procedure Non-Overlapping Output (Example) Figure 10.7 Non-Overlapping Output Example (Four-Phase Complementary Non-Overlapping Pulse Output) Figure 10.8 Output Triggering Input Capture (Example) Figure 10.9 Non-Overlapping Output Figure 10.10 Non-Overlapping Operation Write Timing. Figure 11.1 Block Diagram Figure 11.2 Format Data Written TCNT TCSR Figure 11.3 Format Data Written RSTCSR Figure 11.4 Operation Watchdog Timer Mode Figure 11.5 Interval Timer Operation. Figure 11.6 Timing Setting Figure 11.7 Timing Setting WRST Internal Reset Figure 11.8 Contention between TCNT Write Count Figure 12.1 Block Diagram Figure 12.2 Data Format Asynchronous Communication (Example: 8-Bit Data with Parity Stop Bits) Figure 12.3 Phase Relationship between Output Clock Serial Data (Asynchronous Mode). Figure 12.4 Sample Flowchart Initialization Figure 12.5 Sample Flowchart Transmitting Serial Data Figure 12.6 Example Transmit Operation Asynchronous Mode (8-Bit Data with Parity Stop Bit)
Figure 12.7 Figure 12.8 Figure 12.9 Figure 12.10 Figure 12.11 Figure 12.12 Figure 12.13 Figure 12.14 Figure 12.15 Figure 12.16 Figure 12.17 Figure 12.18 Figure 12.19 Figure 12.20 Figure 12.21 Figure 12.22 Figure 12.23 Figure 12.24 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Figure 13.7 Figure 13.8 Figure 13.9 Figure 13.10 Figure 13.11 Figure 13.12 Figure 13.13 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6
Sample Flowchart Receiving Serial Data Example Receive Operation (8-Bit Data with Parity Stop Bit) Example Communication among Processors using Multiprocessor Format (Sending Data H'AA Receiving Processor Sample Flowchart Transmitting Multiprocessor Serial Data Example Transmit Operation (8-Bit Data with Multiprocessor Stop Bit). Sample Flowchart Receiving Multiprocessor Serial Data. Example Receive Operation (8-Bit Data with Multiprocessor Stop Bit). Data Format Synchronous Communication Sample Flowchart Initialization Sample Flowchart Serial Transmitting Example Transmit Operation. Sample Flowchart Serial Receiving. Example Receive Operation Sample Flowchart Simultaneous Serial Transmitting Receiving Receive Data Sampling Timing Asynchronous Mode Example Synchronous Transmission Operation when Switching from Function Port Function. Operation when Switching from Function Port Function (Example Preventing Low-Level Output). Block Diagram Smart Card Interface Smart Card Interface Connection Diagram Smart Card Interface Data Format. Timing TEND Flag Setting. Sample Transmission Processing Flowchart. Relation Between Transmit Operation Internal Registers Timing TEND Flag Setting. Sample Reception Processing Flowchart Timing Fixing Cock Output. Procedure Stopping Restarting Clock Receive Data Sampling Timing Smart Card Interface Mode Retransmission Receive Mode. Retransmission Transmit Mode Converter Block Diagram Data Register Access Operation (Reading H'AA40). Example Converter Operation (Single Mode, Channel Selected) Example Converter Operation (Scan Mode, Channels Selected). Conversion Timing External Trigger Input Timing
Figure 14.7 Figure 14.8 Figure 14.9 Figure 14.10 Figure 14.11 Figure 15.1 Figure 15.2 Figure 16.1 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Figure 17.6 Figure 17.7 Figure 18.1 Figure 18.2 Figure 18.3 Figure 19.1 Figure 19.2 Figure 19.3 Figure 19.4 Figure 19.5 Figure 19.6 Figure 19.7 Figure 19.8 Figure 19.9 Figure 19.10 Figure 19.11 Figure 19.12 Figure 19.13 Figure 19.14 Figure 19.15 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Example Analog Input Protection Circuit. Analog Input Equivalent Circuit Converter Accuracy Definitions Converter Accuracy Definitions Analog Input Circuit (Example). Converter Block Diagram Example Converter Operation. Block Diagram Block Diagram Clock Pulse Generator. Connection Crystal Resonator (Example). Crystal Resonator Equivalent Circuit. Oscillator Circuit Block Board Design Precautions. External Clock Input (Examples) External Clock Input Timing. External Clock Output Settling Delay Timing Timing Software Standby Mode (Example) Hardware Standby Mode Timing Starting Stopping System Clock Output Darlington Pair Drive Circuit (Example) Output Load Circuit Oscillator Settling Timing. Reset Input Timing Reset Output Timing Interrupt Input Timing. Basic Cycle: Two-State Access Basic Cycle: Three-State Access Basic Cycle: Three-State Access with Wait State Bus-Release Mode Timing Port Input/Output Timing. Timer Input/Output Timing. Timer External Clock Input Timing Input Clock Timing Input/Output Timing Synchronous Mode Port Block Diagram. Port Block Diagram (Pin P60). Port Block Diagram (Pin P61). Port Block Diagram (Pin P62). Port Block Diagram (Pin P67). Port Block Diagram (Pins P75). Port Block Diagram (Pins P77). Port Block Diagram (Pin P80). Port Block Diagram (Pins P82). Port Block Diagram (Pin P83).
xvii
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Port Block Diagram (Pin P84). Port Block Diagram (Pin P90). Port Block Diagram (Pin P91). Port Block Diagram (Pin P92). Port Block Diagram (Pin P93). Port Block Diagram (Pin P94). Port Block Diagram (Pin P95). Port Block Diagram (Pins PA1). Port Block Diagram (Pins PA3). Port Block Diagram (Pins Port Block Diagram (Pins PB2). Port Block Diagram (Pins PB3). Port Block Diagram (Pin Port Block Diagram (Pin Port Block Diagram (Pin Port Block Diagram (Pin Reset during Memory Access (Modes Reset during Memory Access (Modes Package Dimensions (FP-100B) Package Dimensions (TFP-100B)
xviii
Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.14 Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Features Comparison H8/3008 Arrangements. Functions Assignments Each Mode (FP-100B, TFP-100B) Instruction Classification Instructions Addressing Modes. Data Transfer Instructions Arithmetic Operation Instructions Logic Operation Instructions Shift Instructions. Manipulation Instructions Branching Instructions. System Control Instructions. Block Transfer Instruction. Addressing Modes Absolute Address Access Ranges. Effective Address Calculation Exception Handling Types Priority. Operating Mode Selection Registers. Functions Each Mode Exception Types Priority. Exception Vector Table Interrupt Pins Interrupt Controller Registers Interrupt Sources, Vector Addresses, Priority. Settings Interrupt Handling Interrupt Response Time. Controller Pins Controller Registers Specifications Each Area (Basic Interface) Data Buses Used Valid Strobes. States Idle Cycle Port Functions Port Registers Input Pull-Up Transistor States (Port Port Registers Port Functions Modes Port Data Register. Port Registers Port Functions Modes Port Registers
Table 7.10 Port Functions. Table 7.11 Port Registers. Table 7.12 Port Functions (Modes Table 7.13 Port Functions (Modes Table 7.14 Port Functions (Modes Table 7.15 Port Registers Table 7.16 Port Functions (Modes Table 16-bit timer Functions. Table 16-bit timer Pins. Table 16-bit timer Registers. Table Output Pins Registers Table Up/Down Counting Conditions Table 16-bit timer Interrupt Sources. Table 16-bit timer Operating Modes (Channel Table 16-bit timer Operating Modes (Channel Table 16-bit timer Operating Modes (Channel Table 8-Bit Timer Pins. Table 8-Bit Timer Registers. Table Operation Channels when 8TCSR1 Register Table Operation Channels when 8TCSR3 Register Table Types 8-Bit Timer Interrupt Sources Priority Order Table 8-Bit Timer Interrupt Sources. Table Timer Output Priority Order Table Internal Clock Switchover 8TCNT Operation Table 10.1 Pins Table 10.2 Registers Table 10.3 Operating Conditions. Table 11.1 Table 11.2 Registers. Table 11.3 Read Addresses TCNT, TCSR, RSTCSR Table 12.1 Pins Table 12.2 Registers Table 12.3 Examples Rates Settings Asynchronous Mode Table 12.4 Examples Rates Settings Synchronous Mode Table 12.5 Maximum Rates Various Frequencies (Asynchronous Mode) Table 12.6 Maximum Rates with External Clock Input (Asynchronous Mode) Table 12.7 Maximum Rates with External Clock Input (Synchronous Mode) Table 12.8 Settings Serial Communication Formats Table 12.9 Settings Clock Source Selection Table 12.10 Serial Communication Formats (Asynchronous Mode) Table 12.11 Receive Error Conditions. Table 12.12 Interrupt Sources. Table 12.13 Status Flags Transfer Receive Data.
Table 13.1 Smart Card Interface Pins Table 13.2 Smart Card Interface Registers Table 13.3 Smart Card Interface Register Settings. Table 13.4 n-Values CKS1 CKS0 Settings. Table 13.5 Rates (bits/s) Various Settings (When Table 13.6 Settings Typical Rates (bits/s) (When Table 13.7 Maximum Rates Various Frequencies (Smart Card Interface Mode). Table 13.8 Smart Card Interface Mode Operating States Interrupt Sources. Table 14.1 Converter Pins. Table 14.2 Converter Registers. Table 14.3 Analog Input Channels Data Registers (ADDRA ADDRD) Table 14.4 Conversion Time (Single Mode) Table 14.5 Analog Input Ratings. Table 15.1 Converter Pins. Table 15.2 Converter Registers. Table 16.1 H8/3008 On-Chip Specifications. Table 16.2 System Control Register Table 17.1 Damping Resistance Value. Table 17.1 External Capacitance Values Table 17.2 Crystal Resonator Parameters Table 17.3 Clock Timing (Preliminary). Table 17.4 Frequency Division Register Table 18.1 Power-Down State Module Standby Function Table 18.2 Control Register. Table 18.3 Clock Frequency Waiting Time Clock Settle Table 18.4 State Various Operating States. Table 19.1 Absolute Maximum Ratings Table 19.2 Characteristics Table 19.2 Characteristics Table 19.3 Permissible Output Currents Table 19.4 Clock Timing Table 19.5 Control Signal Timing Table 19.6 Timing Table 19.7 Timing On-Chip Supporting Modules. Table 19.8 Conversion Characteristics Table 19.9 Conversion Characteristics Table Instruction Table Operation Code Table Operation Code Table Operation Code Table Number States Cycle. Table Number Cycles Instruction. Table Port States
Table Table
H8/3008 Product Code Lineup Arrangement Each Product (FP-100B, TFP-100B)
xxii
Section Overview
Overview
H8/3008 microcontroller (MCU) that integrates system supporting functions together with H8/300H core having original Hitachi architecture. H8/300H 32-bit internal architecture with sixteen 16-bit general registers, concise, optimized instruction designed speed. address 16-Mbyte linear address space. instruction upward-compatible object-code level with H8/300 CPU, enabling easy porting software from H8/300 Series. on-chip system supporting functions include RAM, 16-bit timer, 8-bit timer, programmable timing pattern controller (TPC), watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports, other facilities. operating modes offer choice width address space size. modes (modes include four expanded modes. Table summarizes features H8/3008.
Table
Feature
Features
Description Upward-compatible with H8/300 object-code level General-register machine Sixteen 16-bit general registers (also usable sixteen 8-bit registers plus eight 16-bit registers, eight 32-bit registers)
High-speed operation Maximum clock rate: Add/subtract: Multiply/divide:
16-Mbyte address space Instruction features 8/16/32-bit data transfer, arithmetic, logic instructions Signed unsigned multiply instructions bits bits, bits bits) Signed unsigned divide instructions bits bits, bits bits) accumulator function
manipulation instructions with register-indirect specification positions Memory H8/3008 Interrupt controller controller RAM: kbytes Seven external interrupt pins: NMI, IRQ0 IRQ5 internal interrupts Three selectable interrupt priority levels Address space partitioned into eight areas, with independent specifications each area Chip select output available areas 8-bit access 16-bit access selectable each area Two-state three-state access selectable each area Selection wait modes Number program wait states selectable each area arbitration function address update modes
Feature 16-bit timer, channels
Description Three 16-bit timer channels, capable processing pulse outputs pulse inputs 16-bit timer counter (channels multiplexed output compare/input capture pins (channels Operation synchronized (channels mode available (channels Phase counting mode available (channel 8-bit up-counter (external event count capability) time constant registers channels connected Maximum 16-bit pulse output, using 16-bit timer time base four 4-bit pulse output groups 16-bit group, 8-bit groups) Non-overlap mode available Internal reset signal generated overflow Reset signal output externally Usable interval timer Selection asynchronous synchronous mode Full duplex: transmit receive simultaneously On-chip baud-rate generator Smart card interface functions added Resolution: bits Eight channels, with selection single scan mode Variable analog conversion voltage range Sample-and-hold function conversion started external trigger 8-bit timer comparematch Resolution: bits channels outputs sustained software standby mode input/output pins input-only pins
8-bit timer, channels
Programmable timing pattern controller (TPC) Watchdog timer (WDT), channel Serial communication interface (SCI), channels
converter
converter
ports
Feature
Description Address Space Mbyte Mbyte Mbytes Mbytes Address Pins Initial Width bits bits bits bits Max. Width bits bits bits bits
Operating modes operating modes Mode Mode Mode Mode Mode Power-down state Other features Product lineup Product Type H8/3008 Model operation HD6413008F HD6413008TE operation HD6413008VF HD6413008VTE
On-chip disabled modes Sleep mode Software standby mode Hardware standby mode Module standby function Programmable system clock frequency division On-chip clock pulse generator Package (Hitachi Package Code) 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin TQFP (TFP-100B)
Block Diagram
Figure shows internal block diagram.
VCL*
Port Address
Port Port Port controller Port Port Port VREF DA1/AN7/P77 DA0/AN6/P76 AN5/P75 AN4/P74 AN3/P73 AN2/P72 AN1/P71 AN0/P70
EXTAL XTAL STBY RESO /P67 Port BACK/P62 BREQ/P61 WAIT/P60 CS0/P84 CS2/IRQ2/P82 CS3/IRQ1/P81 IRQ0/P80 Port ADTRG/CS1/IRQ3/P83 Interrupt controller Clock pulse generator
Data (upper) Data (lower)
H8/300H Watchdog timer (WDT)
16-bit timer unit Serial communication interface (SCI) channels
8-bit timer unit
/SCK /IRQ /SCK /IRQ /RxD1 /RxD0 /TxD /TxD
Programmable timing pattern controller (TPC)
converter converter
Port CS5/TMO2/TP10/PB2 CS6/TMIO1/TP9/PB1 A20/TIOCB2/TP7/PA7 A21/TIOCA2/TP6/PA6 A22/TIOCB1/TP5/PA5 CS7/TMO0/TP8/PB0 TP15/PB7
Port A23/TIOCA1/TP4/PA4 TCLKD/TIOCB0/TP3/PA3 TCLKC/TIOCA0/TP2/PA2 TCLKB/TP1/PA1 TCLKA/TP0/PA0 AVCC AVSS
TP14/PB6
Note: operation models have pin, require connection external capacitor.
CS4/TMIO3/TP11/PB3
TP13/PB5
TP12/PB4
Figure Block Diagram
1.3.1
Description
Arrangement
arrangement H8/3008 shown figures 1.3. Differences H8/3008 arrangements shown table 1.2. Except differences shown table 1.2, arrangements same. Table Comparison H8/3008 Arrangements
H8/3064 F-ZTAT B-Mask Version Number
H8/3026 F-ZTAT
H8/3062 F-ZTAT A-Mask Version
H8/3024 F-ZTAT
H8/3008 ROMless
Operation Model
Package
FP-100B (TFP-100B)
RESO
RESO
/BREQ
/BACK
EXTAL
STBY
P67/
XTAL
/WAIT
VREF /AN0 /AN1 /AN2 /AN3 /AN4 /AN5 /AN6 /AN7 IRQ0 /P80 /IRQ1/P81 CS2/IRQ2/P82 ADTRG/CS1/IRQ3/P83 CS0/P84 TCLKA/TP0/PA0 TCLKB/TP1/PA1 TCLKC/TIOCA0/TP2/PA2 TCLKD/TIOCB0/TP3/PA3 A23/TIOCA1/TP4/PA4 A22/TIOCB1/TP5/PA5 A21/TIOCA2/TP6/PA6 A20/TIOCB2/TP7/PA7
D7/P47
view (FP-100B, TFP-100B)
TxD0 /P90
TxD1 /P91
RxD0 /P92
RxD1 /P93
IRQ4 /SCK0 /P94
IRQ5 /SCK1 /P95
/P40
/P41
/P42
VCC/VCL* CS7/TMO0/TP8/PB0
/TMIO 1/TP9/PB1
/TMO2/TP10/PB2
/TMIO 3/TP11/PB3
TP12/PB4
TP13/PB5
TP14/PB6
TP15/PB7
/P43
/P44
/P45
/P46
Note: operation models, operation models. external capacitor must connected pin.
Figure Arrangement H8/3008 (FP-100B TFP-100B Package, View)
RESO
1.3.2
Functions
Table summarizes functions. operation models have pin, require connection external capacitor. Table Functions
Type Power Symbol FP-100B TFP-100B Input Input Name Function Power: connection power supply. Connect pins system power supply. Ground: connection ground Connect pins system power supply. Connect external capacitor between this connect
Internal step-down Clock
Output
XTAL
Input
connection crystal resonator. examples crystal resonator external clock input, section Clock Pulse Generator. connection crystal resonator input external clock signal. examples crystal resonator external clock input, section Clock Pulse Generator. System clock: Supplies system clock external devices. Mode mode setting operating mode, follows. Inputs these pins must changed during operation. Operating Mode Setting prohibited Mode Mode Mode Mode Setting prohibited Setting prohibited Setting prohibited
EXTAL
Input
Operating mode control
Output Input
Type System control Symbol RESO STBY BREQ BACK Interrupts IRQ5 IRQ0 Address Data control FP-100B TFP-100B 100, Input Output Input Input Output Input Input Output Name Function Reset input: When driven low, this resets chip. This must driven power-up. Reset output: Outputs reset signal generated watchdog timer external devices Standby: When driven low, this forces transition hardware standby mode request: Used external master request right request acknowledge: Indicates that been granted external master Nonmaskable interrupt: Requests nonmaskable interrupt Interrupt request Maskable interrupt request pins Address bus: Outputs address signals
Input/ output Output Output Output Output
Data bus: Bidirectional data Chip select: Select signals areas Address strobe: Goes indicate valid address output address Read: Goes indicate reading from external address space High write: Goes indicate writing external address space; indicates valid data upper data (D15 D8). write: Goes indicate writing external address space; indicates valid data lower data D0). Wait: Requests insertion wait states cycles during access external address space
Output
WAIT
Input
Type 16-bit timer Symbol TCLKD TCLKA TIOCA2 TIOCA0 TIOCB2 TIOCB0 8-bit timer TMO0, TMO2 TMIO1, TMIO3 TCLKD TCLKA Programmable timing pattern controller (TPC) Serial communication interface (SCI) TxD1, TxD0 RxD1, RxD0 converter ADTRG converter Analog power supply AVCC FP-100B TFP-100B Input Input/ output Name Function Clock input External clock inputs Input capture/output compare GRA2 GRA0 output compare input capture, output Input capture/output compare GRB2 GRB0 output compare input capture Compare match output: Compare match output pins Input capture input/compare match output: Input capture input compare match output pins Counter external clock input: These pins input external clock counters. output Pulse output
100, Input/ output Output Input/ output Input Output
Output Input Input/ output Input Input Output Input
Transmit data (channels data output Receive data (channels data input Serial clock (channels clock input/output Analog Analog input pins conversion external trigger input: External trigger input starting conversion Analog output: Analog output from converter Power supply converters. Connect system power supply when using converters. Ground converters. Connect system ground Reference voltage input converters. Connect system power supply when using converters.
AVSS VREF
Input Input
Type ports Symbol FP-100B TFP-100B Input/ output Input/ output Input Input/ output Input/ output Input/ output Input/ output Name Function Port Eight input/output pins. direction each selected port data direction register (P4DDR). Port Eight input/output pins. direction each selected port data direction register (P6DDR). Port Eight input pins Port Five input/output pins. direction each selected port data direction register (P8DDR). Port input/output pins. direction each selected port data direction register (P9DDR). Port Eight input/output pins. direction each selected port data direction register (PADDR). Port Eight input/output pins. direction each selected port data direction register (PBDDR).
P67,
Note: operation models. This operation models.
1.3.3
Assignments Each Mode
Table lists assignments each mode. Table
FP-100B TFP-100B Mode CL)*
Assignments Each Mode (FP-100B, TFP-100B)
Name Mode CL)*
Mode CL)*
Mode CL)*3 0/TP8/TMO0/CS7 1/TP9/TMIO1/CS6 2/TP10/TMO2/CS5 3/TP11/TMIO3/CS4 4/TP12 5/TP13 6/TP14 7/TP15 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK 0/IRQ4 P95/SCK 1/IRQ5 P40/D0*2 P41/D1*2 P42/D2*2 P43/D3*2
0/TP8/TMO0/CS7 1/TP9/TMIO1/CS6 2/TP10/TMO2/CS5 3/TP11/TMIO3/CS4 4/TP12 5/TP13 6/TP14 7/TP15 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK 0/IRQ4 P95/SCK 1/IRQ5 P40/D0*
0/TP8/TMO0/CS7 1/TP9/TMIO1/CS6 2/TP10/TMO2/CS5 3/TP11/TMIO3/CS4 4/TP12 5/TP13 6/TP14 7/TP15 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK 0/IRQ4 P95/SCK 1/IRQ5 P40/D0*
0/TP8/TMO0/CS7 1/TP9/TMIO1/CS6 2/TP10/TMO2/CS5 3/TP11/TMIO3/CS4 4/TP12 5/TP13 6/TP14 7/TP15 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK 0/IRQ4 P95/SCK 1/IRQ5 P40/D0*
P41/D1*1 P42/D2*1 P43/D3* P44/D4*
P41/D1*2 P42/D2*2 P43/D3* P44/D4*
P41/D1*1 P42/D2*1 P43/D3* P44/D4*
P44/D4*2 P45/D5*2 P46/D6*2 P47/D7*2
P45/D5*1 P46/D6*
P45/D5*2 P46/D6*
P45/D5*1 P46/D6*
P47/D7*1
P47/D7*2
P47/D7*1
FP-100B TFP-100B Mode P60/WAIT P61/BREQ P62/BACK STBY Mode P60/WAIT P61/BREQ P62/BACK STBY
Name Mode P60/WAIT P61/BREQ P62/BACK STBY Mode P60/WAIT P61/BREQ P62/BACK STBY
FP-100B TFP-100B Mode EXTAL XTAL VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 P80/IRQ0 P81/IRQ1/CS3 P82/IRQ2/CS2 Mode EXTAL XTAL VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 P80/IRQ0 P81/IRQ1/CS3 P82/IRQ2/CS2
Name Mode EXTAL XTAL VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 P80/IRQ0 P81/IRQ1/CS3 P82/IRQ2/CS2 Mode EXTAL XTAL VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 P80/IRQ0 P81/IRQ1/CS3 P82/IRQ2/CS2
P83/IRQ3/CS1/ADTRG P83/IRQ3/CS1/ADTRG P83/IRQ3/CS1/ADTRG P83/IRQ3/CS1/ADTRG P84/CS0 0/TP0/TCLKA 1/TP1/TCLKB 2/TP2/TIOCA TCLKC 3/TP3/TIOCB TCLKD P84/CS0 0/TP0/TCLKA 1/TP1/TCLKB 2/TP2/TIOCA TCLKC 3/TP3/TIOCB TCLKD P84/CS0 0/TP0/TCLKA 1/TP1/TCLKB 2/TP2/TIOCA TCLKC 3/TP3/TIOCB TCLKD P84/CS0 0/TP0/TCLKA 1/TP1/TCLKB 2/TP2/TIOCA TCLKC 3/TP3/TIOCB TCLKD
FP-100B TFP-100B Mode 4/TP4/TIOCA 5/TP5/TIOCB 6/TP6/TIOCA 7/TP7/TIOCB Mode 4/TP4/TIOCA 5/TP5/TIOCB 6/TP6/TIOCA 7/TP7/TIOCB
Name Mode 4/TP4/TIOCA 5/TP5/TIOCB 6/TP6/TIOCA Mode 4/TP4/TIOCA 5/TP5/TIOCB 6/TP6/TIOCA
Notes: modes functions pins P40/D0 7/D7 selected after reset, they changed software. modes functions pins P40/D0 7/D7 selected after reset, they changed software. This functions operation models, operation models.
Section
Overview
H8/300H high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 CPU. H8/300H sixteen 16-bit general registers, address 16-Mbyte linear address space, ideal realtime control. 2.1.1 Features
H8/300H following features. Upward compatibility with H8/300 execute H8/300 Series object programs General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16, ERn) @(d:24, ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8, @(d:16, PC)] Memory indirect [@@aa:8] 16-Mbyte linear address space High-speed operation frequently-used instructions execute four states Maximum clock frequency: 8/16/32-bit register-register add/subtract: ns@25 8-bit register-register multiply: ns@25 8-bit register-register divide: ns@25 16-bit register-register multiply: ns@25 16-bit register-register divide: ns@25
operating modes Normal mode Advanced mode Low-power mode Transition power-down state SLEEP instruction 2.1.2 Differences from H8/300
comparison H8/300 CPU, H8/300H following enhancements. More general registers Eight 16-bit registers have been added. Expanded address space Advanced mode supports maximum 16-Mbyte address space. Normal mode supports same 64-kbyte address space H8/300 CPU. Enhanced addressing addressing modes have been enhanced make effective 16-Mbyte address space. Enhanced instructions Data transfer, arithmetic, logic instructions operate 32-bit data. Signed multiply/divide instructions other instructions have been added.
Operating Modes
H8/300H operating modes: normal advanced. Normal mode supports maximum 64-kbyte address space. Advanced mode supports Mbytes.
Maximum kbytes, program data areas combined
Normal mode
operating modes Maximum Mbytes, program data areas combined
Advanced mode
Figure Operating Modes
Address Space
Figure shows simple memory H8/3008. H8/300H address linear address space with maximum size kbytes normal mode, Mbytes advanced mode. further details section 3.6, Memory Each Operating Mode. 1-Mbyte operating modes 20-bit addressing. upper bits effective addresses ignored.
H'0000 H'FFFF
H'00000
H'000000
H'FFFFF
H'FFFFFF 1-Mbyte mode Normal mode 16-Mbyte mode Advanced mode
Figure Memory
2.4.1
Register Configuration
Overview
H8/300H internal registers shown figure 2.3. There types registers: general registers control registers.
General Registers (ERn) Control Registers (CR) Legend: Stack pointer Program counter CCR: Condition code register Interrupt mask User interrupt mask Half-carry flag User Negative flag Zero flag Overflow flag Carry flag (SP)
Figure Registers
2.4.2
General Registers
H8/300H eight 32-bit general registers. These general registers functionally alike used without distinction between data registers address registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. Figure illustrates usage general registers. usage each register selected independently.
Address registers 32-bit registers
16-bit registers registers (extended registers)
8-bit registers
registers registers
registers
registers
Figure Usage General Registers General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Free area (ER7) Stack area
Figure Stack 2.4.3 Control Registers
control registers 24-bit program counter (PC) 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word), least significant ignored. When instruction fetched, least significant regarded Condition Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. 7-Interrupt Mask (I): Masks interrupts other than when accepted regardless setting. start exception-handling sequence. 6-User Interrupt Mask (UI): written read software using LDC, STC, ANDC, ORC, XORC instructions. This also used interrupt mask bit. details section Interrupt Controller. 5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise. 4-User (U): written read software using LDC, STC, ANDC, ORC, XORC instructions. 3-Negative Flag (N): Stores value most significant data, regarded sign bit. 2-Zero Flag (Z): indicate zero data, cleared indicate non-zero data.
1-Overflow Flag (V): when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): when carry generated execution operation, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions carry flag also used accumulator manipulation instructions. Some instructions leave flag bits unchanged. Operations performed LDC, STC, ANDC, ORC, XORC instructions. flags used conditional branch (Bcc) instructions. action each instruction flag bits, appendix A.1, Instruction List. bits, section Interrupt Controller. 2.4.4 Initial Register Values
reset exception handling, initialized value loaded from vector table, other bits general registers initialized. particular, initial value stack pointer (ER7) also undefined. stack pointer (ER7) must therefore initialized MOV.L instruction executed immediately after reset.
Data Formats
H8/300H process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data. 2.5.1 General Register Data Formats
Figures show data formats general registers.
General Register
Data Type
Data Format Don't care
1-bit data
1-bit data
Don't care
4-bit data
Upper digit Lower digit
Don't care
4-bit data
Don't care
Upper digit Lower digit
Byte data
Don't care
Byte data
Don't care
Legend: RnH: General register RnL: General register
Figure General Register Data Formats
Data Type
General Register
Data Format
Word data
Word data
Longword data Legend: ERn: General register General register General register MSB: Most significant LSB: Least significant
Figure General Register Data Formats 2.5.2 Memory Data Formats
Figure shows data formats memory. H8/300H access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches.
Data Type
Address
Data Format
1-bit data Byte data Word data Address Address Address Address Address Longword data Address Address Address
Figure Memory Data Formats When (SP) used address register access stack, operand size should word size longword size.
2.6.1
Instruction
Instruction Overview
H8/300H types instructions, which classified table 2.1. Table
Function Data transfer Arithmetic operations Logic operations Shift operations manipulation Branch System control Block data transfer
Instruction Classification
Instruction MOV, PUSH* POP* MOVTPE* MOVFPE*
Types
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc* JMP, BSR, JSR, TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV Total types
Notes: POP.W identical MOV.W @SP+, PUSH.W identical MOV.W @-SP. POP.L identical MOV.L @SP+, PUSH.L identical MOV.L @-SP. available H8/3008. generic branching instruction.
2.6.2
Instructions Addressing Modes
Table indicates instructions available H8/300H CPU. Table Instructions Addressing Modes
Addressing Modes (d:16, ERn) (d:24, ERn) (d:8, (d:16,
Function Data transfer
Instruction POP, PUSH MOVFPE, MOVTPE
@ERn
@ERn+/ @-ERn
aa:8
aa:16
aa:24
aa:8
Arithmetic operations
ADD, ADDX, SUBX ADDS, SUBS INC, DAA, MULXU, MULXS, DIVXU, DIVXS EXTU, EXTS
Logic operations
AND,
Shift instructions manipulation Branch Bcc, JMP, System control TRAPA SLEEP ANDC, ORC, XORC Block data transfer
2.6.3
Tables Instructions Classified Function
Tables 2.10 summarize instructions each functional category. operation notation used these tables defined next. Operation Notation
(EAd) (EAs) #IMM disp :3/:8/:16/:24 General register (destination)* General register (source)* General register* General register (32-bit register address register)* Destination operand Source operand Condition code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division logical logical Exclusive logical Move (logical complement) 16-, 24-bit length
Note: General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit data address registers (ER0 ER7).
Table
Data Transfer Instructions
Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register.
Instruction Size* B/W/L
MOVFPE
(EAs) Cannot used H8/3008. (EAs) Cannot used H8/3008. @SP+ Pops general register from stack. POP.W identical MOV.W @SP+, Similarly, POP.L identical MOV.L @SP+, ERn.
MOVTPE
PUSH
@-SP Pushes general register onto stack. PUSH.W identical MOV.W @-SP. Similarly, PUSH.L identical MOV.L ERn, @-SP.
Note: Size refers operand size. Byte Word Longword
Table
Arithmetic Operation Instructions
Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from data general register. SUBX instruction.)
Instruction Size* ADD,SUB B/W/L
ADDX, SUBX
#IMM Performs addition subtraction with carry borrow data general registers, immediate data data general register.
INC,
B/W/L
Increments decrements general register (Byte operands incremented decremented only.)
ADDS, SUBS DAA,
Adds subtracts value from data 32-bit register. decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4-bit data.
MULXU
Performs unsigned multiplication data general registers: either bits bits bits bits bits bits.
MULXS
Performs signed multiplication data general registers: either bits bits bits bits bits bits.
Instruction Size* DIVXU
Function Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder
DIVXS
Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder, bits bits 16-bit quotient 16-bit remainder
B/W/L
#IMM Compares data general register with data another general register with immediate data, sets according result.
B/W/L
Takes two's complement (arithmetic complement) data general register.
EXTS
(sign extension) Extends byte data lower bits 16-bit register word data, extends word data lower bits 32-bit register longword data, extending sign bit.
EXTU
(zero extension) Extends byte data lower bits 16-bit register word data, extends word data lower bits 32-bit register longword data, padding with zeros.
Note: Size refers operand size. Byte Word Longword
Table
Logic Operation Instructions
Function #IMM Performs logical operation general register another general register immediate data.
Instruction Size* B/W/L
B/W/L
#IMM Performs logical operation general register another general register immediate data.
B/W/L
#IMM Performs logical exclusive operation general register another general register immediate data.
B/W/L
Takes one's complement (logical complement) general register contents.
Note: Size refers operand size. Byte Word Longword
Table
Shift Instructions
Function (shift) Performs arithmetic shift general register contents. B/W/L (shift) Performs logical shift general register contents. B/W/L (rotate) Rotates general register contents. B/W/L (rotate) Rotates general register contents, including carry bit.
Instruction Size* SHAL, SHAR SHLL, SHLR ROTL, ROTR ROTXL, ROTXR B/W/L
Note: Size refers operand size. Byte Word Longword
Table
Manipulation Instructions
Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower bits general register.
Instruction Size* BSET
BCLR
(<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower bits general register.
BNOT
(<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower bits general register.
BTST
(<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower bits general register.
BAND
(<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>)] ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
BIAND
Instruction Size*
Function (<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>)] carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>)] Exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers specified general register memory operand carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers inverse carry flag value specified general register memory operand. number specified 3-bit immediate data.
BIOR
BXOR
BIXOR
BILD
BIST
Note: Size refers operand size. Byte
Table
Branching Instructions
Function Branches specified address address specified condition met. branching conditions listed below. Mnemonic (BT) (BF) (BHS) (BLO) Description Always (true) Never (false) High same Condition Always Never CZ=0 CZ=1
Instruction Size
Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal NV=0 NV=1
Branches unconditionally specified address Branches subroutine specified address Branches subroutine specified address Returns from subroutine
Table
System Control Instructions
Function Starts trap-instruction exception handling Returns from exception-handling routine Causes transition power-down state (EAs) Moves source operand contents condition code register. condition code register size byte, transfer from memory, data read word access.
Instruction Size* TRAPA SLEEP
(EAd) Transfers contents destination location. condition code register size byte, transfer memory, data written word access.
ANDC
#IMM Logically ANDs condition code register with immediate data. #IMM Logically condition code register with immediate data. #IMM Logically exclusive-ORs condition code register with immediate data. Only increments program counter.
XORC
Note: Size refers operand size. Byte Word
Table 2.10 Block Transfer Instruction
Instruction EEPMOV.B Size Function then repeat @ER5+ @ER6+, until else next; then repeat @ER5+ @ER6+, until else next; Block transfer instruction. This instruction transfers number data bytes specified starting from address indicated ER5, location starting address indicated ER6. transfer, next instruction executed.
EEPMOV.W
2.6.4 Basic Instruction Formats H8/300H instructions consist 2-byte (word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Operation Field: Indicates function instruction, addressing mode, operation carried operand. operation field always includes first bits instruction. Some instructions have operation fields. Register Field: Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension: Eight, bits specifying immediate data, absolute address, displacement. 24-bit address displacement treated 32-bit data which first bits (H'00). Condition Field: Specifies branching condition instructions. Figure shows examples instruction formats.
Operation field only Operation field register fields ADD.B etc. NOP, RTS, etc.
Operation field, register fields, effective address extension (disp) Operation field, effective address extension, condition field (disp) MOV.B @(d:16, Rn),
Figure Instruction Formats 2.6.5 Notes Manipulation Instructions
BSET, BCLR, BNOT, BST, BIST instructions read byte data, modify byte, then write byte back. Care required when these instructions used access registers with write-only bits, access ports.
Step Read Modify Write Description Read data byte specified address Modify data byte Write modified data byte back specified address
Example BCLR executed clear port data direction register (P4DDR) under following conditions. Input pins Output pins intended purpose this BCLR instruction switch from output input.
Before Execution BCLR Instruction
Input/output Input Input Output Output Output Output Output Output
Execution BCLR Instruction BCLR P4DDR Execute BCLR instruction
After Execution BCLR Instruction
Input/output Output Output Output Output Output Output Output Input
Explanation: execute BCLR instruction, begins reading P4DDR. Since P4DDR write-only register, read H'FF, even though true value H'3F. Next clears read data, changing value H'FE. Finally, writes this value (H'FE) back P4DDR complete BCLR instruction. result, P40DDR cleared making input pin. addition, P47DDR P46DDR making output pins. BCLR instruction used clear flags on-chip registers case status register (ISR), example, flag must read condition clearing when using BCLR instruction, known that flag been interrupt-handling routine, instance, necessary read flag ahead time.
2.7.1
Addressing Modes Effective Address Calculation
Addressing Modes
H8/300H supports eight addressing modes listed table 2.11. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except programcounter relative memory indirect. manipulation instructions register direct, register indirect, absolute (@aa:8) addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table 2.11 Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @ERn @(d:16, ERn)/@(d:24, ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8, PC)/@(d:16, @@aa:8
Register Direct-Rn: register field instruction code specifies 16-, 32-bit register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32-bit registers. Register Indirect-@ERn: register field instruction code specifies address register (ERn), lower bits which contain address operand. Register Indirect with Displacement-@(d:16, ERn) @(d:24, ERn): 16-bit 24-bit displacement contained instruction code added contents address register (ERn) specified register field instruction, lower bits specify address memory operand. 16-bit displacement sign-extended when added.
Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn: Register indirect with post-increment-@ERn+ register field instruction code specifies address register (ERn) lower bits which contain address memory operand. After operand accessed, added address register contents bits) stored address register. value added byte access, word access, longword access. word longword access, register value should even. Register indirect with pre-decrement-@-ERn value subtracted from address register (ERn) specified register field instruction code, lower bits result become address memory operand. result also stored address register. value subtracted byte access, word access, longword access. word longword access, resulting register value should even. Absolute Address-@aa:8, @aa:16, @aa:24: instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24). 8-bit absolute address, upper bits assumed (H'FFFF). 16-bit absolute address upper bits sign extension. 24-bit absolute address access entire address space. Table 2.12 indicates accessible address ranges. Table 2.12 Absolute Address Access Ranges
Absolute Address bits (@aa:8) bits (@aa:16) 1-Mbyte Modes H'FFF00 H'FFFFF (1048320 1048575) H'00000 H'07FFF, H'F8000 H'FFFFF 32767, 1015808 1048575) H'00000 H'FFFFF 1048575) 16-Mbyte Modes H'FFFF00 H'FFFFFF (16776960 16777215) H'000000 H'007FFF, H'FF8000 H'FFFFFF 32767, 16744448 16777215) H'000000 H'FFFFFF 16777215)
bits (@aa:24)
Immediate-#xx:8, #xx:16, #xx:32: instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. instruction codes ADDS, SUBS, INC, instructions contain immediate data implicitly. instruction codes some manipulation instructions contain 3-bit immediate data specifying number. TRAPA instruction code contains 2-bit immediate data specifying vector address. Program-Counter Relative-@(d:8, @(d:16, PC): This mode used instructions. 8-bit 16-bit displacement contained instruction code sign42
extended bits added 24-bit contents generate 24-bit branch address. value which displacement added address first byte next instruction, possible branching range -126 +128 bytes (-63 words) -32766 +32768 bytes (-16383 +16384 words) from branch instruction. resulting value should even number. Memory Indirect-@@aa:8: This mode used instructions. instruction code contains 8-bit absolute address specifying memory operand. This memory operand contains branch address. memory operand accessed longword access. first byte memory operand ignored, generating 24-bit branch address. figure 2.10. upper bits 8-bit absolute address assumed (H'0000), address range (H'000000 H'0000FF). Note that first part this range also exception vector area. further details section Interrupt Controller.
Specified @aa:8
Reserved
Branch address
Figure 2.10 Memory-Indirect Branch Address Specification When word-size longword-size memory operand specified, when branch address specified, specified memory address odd, least significant regarded accessed data instruction code therefore begins preceding address. section 2.5.2, Memory Data Formats. 2.7.2 Effective Address Calculation
Table 2.13 explains effective address calculated each addressing mode. 1-Mbyte operating modes upper bits calculated address ignored order generate 20-bit effective address.
Effective Address Calculation Operand general register contents General register contents General register contents Effective Address Sign extension disp General register contents General register contents byte operand, word operand, longword operand
Addressing Mode Instruction Format
Register direct (Rn)
Register indirect (@ERn)
Register indirect with displacement @(d:16, ERn)/@(d:24, ERn)
Table 2.13 Effective Address Calculation
Register indirect with post-increment pre-decrement
Register indirect with post-increment @ERn+
Register indirect with pre-decrement @-ERn
H'FFFF
Addressing Mode Instruction Format Effective Address Calculation
Effective Address
Absolute address @aa:8
Sign extension
@aa:16
@aa:24
Immediate #xx:8, #xx:16, #xx:32
Operand immediate data
Program-counter relative @(d:8, @(d:16,
contents
Sign extension
disp
disp
Effective Address Calculation Effective Address H'0000 Memory contents H'00 H'0000 Memory contents
Addressing Mode Instruction Format
Memory indirect @@aa:8
Normal mode
Advanced mode
Legend: disp: IMM: abs:
Register field Operation field Displacement Immediate data Absolute address
2.8.1
Processing States
Overview
H8/300H five processing states: program execution state, exception-handling state, power-down state, reset state, bus-released state. power-down state includes sleep mode, software standby mode, hardware standby mode. Figure 2.11 classifies processing states. Figure 2.13 indicates state transitions.
Processing states
Program execution state executes program instructions sequence Exception-handling state transient state which executes hardware sequence (saving CCR, fetching vector, etc.) response reset, interrupt, other exception
Bus-released state external been released response request signal from master other than Reset state on-chip supporting modules initialized halted
Power-down state halted conserve power
Sleep mode
Software standby mode
Hardware standby mode
Figure 2.11 Processing States 2.8.2 Program Execution State
this state executes program instructions normal sequence.
2.8.3
Exception-Handling State
exception-handling state transient state that occurs when alters normal program flow reset, interrupt, trap instruction. fetches starting address from exception vector table branches that address. interrupt trap exception handling references stack pointer (ER7) saves program counter condition code register. Types Exception Handling Their Priority: Exception handling performed resets, interrupts, trap instructions. Table 2.14 indicates types exception handling their priority. Trap instruction exceptions accepted times program execution state. Table 2.14 Exception Handling Types Priority
Priority High Type Exception Detection Timing Reset Interrupt Synchronized with clock instruction execution exception handling* Start Exception Handling Exception handling starts immediately when changes from high When interrupt requested, exception handling starts current instruction current exception-handling sequence
Trap instruction
When TRAPA instruction Exception handling starts when trap executed (TRAPA) instruction executed
Note: Interrupts detected ANDC, ORC, XORC, instructions, immediately after reset exception handling.
Figure 2.12 classifies exception sources. further details about exception sources, vector numbers, vector addresses, section Exception Handling, section Interrupt Controller.
Reset External interrupts Exception sources Interrupt Internal interrupts (from on-chip supporting modules) Trap instruction
Figure 2.12 Classification Exception Sources
request release Program execution state release request Exception handling source Bus-released state exception handling Exception-handling state
SLEEP instruction with SSBY Sleep mode
Interrupt source NMI, interrupt
SLEEP instruction with SSBY
Software standby mode
"High" STBY="High", ="Low"
Reset state
Hardware standby mode Power-down state
Notes: From state except hardware standby mode, transition reset state occurs whenever goes low. From state, transition hardware standby mode occurs when STBY goes low.
Figure 2.13 State Transitions 2.8.4 Exception Handling Operation
Reset Exception Handling: Reset exception handling highest priority. reset state entered when signal goes low. Reset exception handling starts after that, when changes from high. When reset exception handling starts fetches start address from exception vector table starts program execution from that address. interrupts, including NMI, disabled during reset exception-handling sequence immediately after ends. Interrupt Exception Handling Trap Instruction Exception Handling: When these exception-handling sequences begin, references stack pointer (ER7) pushes program counter condition code register stack. Next, system control register (SYSCR) sets condition code register cleared sets both condition code register Then fetches start address from exception vector table execution branches that address.
Figure 2.14 shows stack after exception-handling sequence.
SP-4 SP-3 SP-2 SP-1 (ER7) Stack area
(ER7) SP+1 SP+2 SP+3 SP+4
Even address
Before exception handling starts Legend: CCR: Condition code register Stack pointer
Pushed stack
After exception handling ends
Notes: address first instruction executed after return from exception-handling routine. Registers must saved restored word access longword access, starting even address.
Figure 2.14 Stack Structure after Exception Handling 2.8.5 Bus-Released State
this state released master other than CPU, response request. masters other than external master. While released, halts except internal operations. Interrupt requests accepted. details section 6.6, Arbiter. 2.8.6 Reset State
When input goes current processing stops enters reset state. condition code register reset. interrupts masked reset state. Reset exception handling starts when signal changes from high. reset state also entered watchdog timer overflow. details section Watchdog Timer.
2.8.7
Power-Down State
power-down state stops operating conserve power. There three modes: sleep mode, software standby mode, hardware standby mode. Sleep Mode: transition sleep mode made SLEEP instruction executed while SSBY cleared system control register (SYSCR). operations stop immediately after execution SLEEP instruction, contents registers retained. Software Standby Mode: transition software standby mode made SLEEP instruction executed while SSBY SYSCR. clock halt on-chip supporting modules stop operating. on-chip supporting modules reset, long specified voltage supplied contents registers on-chip retained. ports also remain their existing states. Hardware Standby Mode: transition hardware standby mode made when STBY input goes low. software standby mode, clocks halt on-chip supporting modules reset, long specified voltage supplied, on-chip contents retained. further information section Power-Down State.
2.9.1
Basic Operational Timing
Overview
H8/300H operates according system clock interval from rise system clock next rise referred "state." memory cycle cycle consists three states. uses different methods access on-chip memory, on-chip supporting modules, external address space. Access external address space controlled controller. 2.9.2 On-Chip Memory Access Timing
On-chip memory accessed states. data bits wide, permitting both byte word access. Figure 2.15 shows on-chip memory access cycle. Figure 2.16 indicates states. H8/3008 function changing method outputting addresses from address pins. details section 6.3.5, Address Output Method.
cycle state Internal address Internal read signal Internal data (read access) Internal write signal Internal data (write access) Write data Read data Address state
Figure 2.15 On-Chip Memory Access Cycle
Address Address
High High impedance
Figure 2.16 States during On-Chip Memory Access (Address Update Mode 2.9.3 On-Chip Supporting Module Access Timing
on-chip supporting modules accessed three states. data bits wide, depending internal register being accessed. Figure 2.17 shows on-chip supporting module access timing. Figure 2.18 indicates states.
cycle state Address Internal read signal Internal data Address state state
Read access
Read data
Internal write signal Write access Internal data Write data
Figure 2.17 Access Cycle On-Chip Supporting Modules
Address Address
High High impedance
Figure 2.18 States during Access On-Chip Supporting Modules 2.9.4 Access External Address Space
external address space divided into eight areas (areas Bus-controller settings determine whether each area accessed 8-bit 16-bit data bus, whether accessed three states. details section Controller.
Section Operating Modes
3.1.1
Overview
Operating Mode Selection
H8/3008 four operating modes (modes that selected mode pins (MD2 MD0) indicated table 3.1. input these pins determines size address space initial mode. Table Operating Mode Selection
Description Mode Pins Operating Mode Mode Mode Mode Mode Address Space Setting prohibited Expanded mode Expanded mode Expanded mode Expanded mode Setting prohibited Setting prohibited Setting prohibited Initial Mode*1 Setting prohibited bits bits bits bits Setting prohibited Setting prohibited Setting prohibited On-Chip Setting prohibited Disabled Disabled Disabled Disabled Setting prohibited Setting prohibited Setting prohibited On-Chip Setting prohibited Enabled* Enabled* Enabled* Enabled* Setting prohibited Setting prohibited Setting prohibited
Notes: modes 8-bit 16-bit data selected per-area basis settings made area width control register (ABWCR). details section Controller. RAME SYSCR cleared these addresses become external addresses.
address space size there three choices: Mbyte Mbyte. external data either bits wide depending ABWCR settings. 8-bit mode used only 8-bit access selected areas. details section Controller.
Modes externally expanded modes that enable access external memory peripheral devices disable access on-chip ROM. Modes support maximum address space Mbyte. Modes support maximum address space Mbytes. H8/3008 used only modes inputs mode pins must select these four modes. inputs mode pins must changed during operation. reset state before changing inputs these pins. 3.1.2 Register Configuration
H8/3008 mode control register (MDCR) that indicates inputs mode pins (MD2 MD0), system control register (SYSCR). Table summarizes these registers. Table
Address* H'EE011 H'EE012
Registers
Name Mode control register System control register Abbreviation MDCR SYSCR Initial Value Undetermined H'09
Note: Lower bits address advanced mode.
Mode Control Register (MDCR)
MDCR 8-bit read-only register that indicates current operating mode H8/3008.
Initial value Read/Write Reserved bits MDS2 MDS1 MDS0
Mode select Bits indicating current operating mode
Note: Determined pins
Bits 6-Reserved: These bits modified always read Bits 3-Reserved: These bits modified always read Bits 0-Mode Select (MDS2 MDS0): These bits indicate logic levels pins (the current operating mode). MDS2 MDS0 correspond MD0. MDS2
MDS0 read-only bits. mode MD0) levels latched into these bits when MDCR read.
System Control Register (SYSCR)
SYSCR 8-bit register that controls operation H8/3008.
Initial value Read/Write SSBY STS2 STS1 STS0 NMIEG SSOE RAME enable Enables disables on-chip Software standby output port enable Selects output state address control signals software standby mode edge select Selects valid edge input User enable Selects whether user interrupt mask Standby timer select These bits select waiting time recovery from software standby mode Software standby Enables transition software standby mode
7-Software Standby (SSBY): Enables transition software standby mode. (For further information about software standby mode section Power-Down State.) When software standby mode exited external interrupt, transition made normal operation, this remains clear this bit, write
SSBY Description SLEEP instruction causes transition sleep mode SLEEP instruction causes transition software standby mode (Initial value)
Bits 4-Standby Timer Select (STS2 STS0): These bits select length time on-chip supporting modules wait internal clock oscillator settle when software standby mode exited external interrupt. When using crystal oscillator, these bits that waiting time will least system clock rate. further information about waiting time selection, section 18.4.3, Selection Waiting Time Exit from Software Standby Mode.
STS2 STS1 STS0 Description Waiting time 8,192 states Waiting time 16,384 states Waiting time 32,768 states Waiting time 65,536 states Waiting time 131,072 states Waiting time 262,144 states Waiting time 1,024 states Illegal setting (Initial value)
3-User Enable (UE): Selects whether condition code register user interrupt mask bit.
Description used interrupt mask used user (Initial value)
2-NMI Edge Select (NMIEG): Selects valid edge input.
NMIEG Description interrupt requested falling edge interrupt requested rising edge (Initial value)
1-Software Standby Output Port Enable (SSOE): Specifies whether address control signals (CS0 CS7, HWR, LWR) kept outputs fixed high, placed high-impedance state software standby mode.
SSOE Description software standby mode, address control signals highimpedance (Initial value) software standby mode, address retains output state control signals fixed high
0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized rising edge signal. initialized software standby mode.
RAME Description On-chip disabled On-chip enabled (Initial value)
3.4.1
Operating Mode Descriptions
Mode
Ports function address pins permitting access maximum 1-Mbyte address space. initial mode after reset bits, with 8-bit access areas. least area designated 16-bit access ABWCR, mode switches bits. 3.4.2 Mode
Ports function address pins permitting access maximum 1-Mbyte address space. initial mode after reset bits, with 16-bit access areas. areas designated 8-bit access ABWCR, mode switches bits. 3.4.3 Mode
Ports part port function address pins permitting access maximum 16-Mbyte address space. initial mode after reset bits, with 8-bit access areas. least area designated 16-bit access ABWCR, mode switches bits. valid when written bits release control register (BRCR). this mode always used address output.)
3.4.4
Mode
Ports part port function address pins permitting access maximum 16-Mbyte address space. initial mode after reset bits, with 16-bit access areas. areas designated 8-bit access ABWCR, mode switches bits. valid when written bits BRCR. this mode always used address output.) 3.4.5 Modes
These modes cannot used H8/3008. settings must made these modes.
Functions Each Operating Mode
functions ports port vary depending operating mode. Table indicates their functions each operating mode. Table
Port Port Port Port Port Port Port
Functions Each Mode
Mode P40*1 Mode D0*1 Mode P40*1 PA4,
Mode D0*1 PA4,
Notes: Initial state. mode switched settings ABWCR. These pins function 8-bit mode, 16-bit mode. Initial state. always address output pin. switched over output writing bits BRCR.
Memory Each Operating Mode
Figures show memory maps H8/3008. expanded modes, address space divided into eight areas. initial mode differs between modes also between modes address locations on-chip on-chip registers differ between 1-Mbyte modes (modes 16-Mbyte modes (modes address range specifiable 16-bit absolute addressing modes (@aa:8 @aa:16) also differs. 3.6.1 Reserved Areas
H8/3008 memory includes reserved areas which access (reading writing) prohibited. Normal operation cannot guaranteed following reserved areas accessed. Reserved Area Internal Register Space: H8/3008 internal register space includes reserved area which access prohibited. details Appendix Internal Registers.
Modes (1-Mbyte expanded modes with on-chip disabled) Memory-indirect branch addresses H'00000 Vector area
Modes (16-Mbyte expanded modes with on-chip disabled) Vector area Memory-indirect branch addresses Area H'1FFFFF H'200000 Area H'3FFFFF H'400000 Area H'5FFFFF H'600000 H'7FFFFF H'800000 Area H'9FFFFF H'A00000 Area 16-bit absolute addresses H'BFFFFF H'C00000 Area H'DFFFFF H'E00000 H'FEE000 H'FEE0FF H'FF8000 H'FFEF1F H'FFEF20 H'FFFF00 H'FFFF1F H'FFFF20 H'FFFFE9 H'FFFFEA H'FFFFFF 8-bit absolute addresses On-chip RAM*
External address space
H'000000 16-bit absolute addresses
H'000FF
H'0000FF
H'07FFF
H'007FFF
H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External H'7FFFF address space H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 H'EE0FF H'F8000 H'FEF1F H'FEF20 H'FFF00 H'FFF1F H'FFF20 H'FFFE9 H'FFFEA H'FFFFF Internal registers
External address space
Area Area Area Area Area Area Area Area
External Area address space
On-chip RAM*
Internal registers External address space
8-bit absolute addresses
Area Internal registers
Internal registers External address space
Note: External addresses accessed disabling on-chip RAM.
Figure Memory H8/3008 Each Operating Mode
16-bit absolute addresses
16-bit absolute addresses
Section Exception Handling
4.1.1
Overview
Exception Handling Types Priority
table indicates, exception handling caused reset, interrupt, trap instruction. Exception handling prioritized shown table 4.1. more exceptions occur simultaneously, they accepted processed priority order. Trap instruction exceptions accepted times program execution state. Table Exception Types Priority
Start Exception Handling Starts immediately after low-to-high transition Interrupt requests handled when execution current instruction handling current exception completed
Priority Exception Type High Reset Interrupt
Trap instruction (TRAPA) Started execution trap instruction (TRAPA)
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions interrupts handled follows. program counter (PC) condition code register (CCR) pushed onto stack. interrupt mask vector address corresponding exception source generated, program execution starts from that address. Note: reset exception, steps above carried out.
4.1.3
Exception Vector Table
exception sources classified shown figure 4.1. Different vectors assigned different exception sources. Table lists exception sources their vector addresses.
Reset External interrupts: NMI, IRQ5 Exception sources Interrupts Internal interrupts: interrupts from on-chip supporting modules
Trap instruction
Figure Exception Sources
Table
Exception Vector Table
Vector Address*1
Exception Source Reset Reserved system
Vector Number
Advanced Mode H'0000 H'0003 H'0004 H'0007 H'0008 H'000B H'000C H'000F H'0010 H'0013 H'0014 H'0017 H'0018 H'001B H'001C H'001F H'0020 H'0023 H'0024 H'0027 H'0028 H'002B H'002C H'002F H'0030 H'0033 H'0034 H'0037 H'0038 H'003B H'003C H'003F H'0040 H'0043 H'0044 H'0047 H'0048 H'004B H'004C H'004F H'0050 H'0053 H'00FC H'00FF
Normal Mode H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B H'000C H'000D H'000E H'000F H'0010 H'0011 H'0012 H'0013 H'0014 H'0015 H'0016 H'0017 H'0018 H'0019 H'001A H'001B H'001C H'001D H'001E H'001F H'0020 H'0021 H'0022 H'0023 H'0024 H'0025 H'0026 H'0027 H'0028 H'0029 H'007E H'007F
External interrupt (NMI) Trap instruction sources)
External interrupt IRQ0 External interrupt IRQ1 External interrupt IRQ2 External interrupt IRQ3 External interrupt IRQ4 External interrupt IRQ5 Reserved system
Internal interrupts*2
Notes: Lower bits address. internal interrupt vectors, section 5.3.3, Interrupt Vector Table.
4.2.1
Reset
Overview
reset highest-priority exception. When goes low, processing halts chip enters reset state. reset initializes internal state registers on-chip supporting modules. Reset exception handling begins when changes from high. chip also reset overflow watchdog timer. details section Watchdog Timer. 4.2.2 Reset Sequence
chip enters reset state when goes low. ensure that chip reset, hold least power-up. reset chip during operation, hold least system clock cycles. versions with on-chip flash memory, must held least system clock cycles. appendix D.2, States Reset, states pins reset state. When goes high after being held necessary time, chip starts reset exception handling follows. internal state registers on-chip supporting modules initialized, CCR. contents reset vector address (H'0000 H'0003 advanced mode, H'0000 H'0001 normal mode) read, program execution starts from address indicated vector address. Figure shows reset sequence modes Figure shows reset sequence modes
Vector fetch
Internal processing
Prefetch first program instruction
Address
High (10)
Figure Reset Sequence (Modes
(1), (3), (5), (2), (4), (6), (10)
Address reset exception handling vector: H'000000, H'000001, H'000002, H'000003 Start address (contents reset exception handling vector address) Start address First instruction program
Note: After reset, wait-state controller inserts three wait states every cycle.
Vector fetch
Internal processing
Prefetch first program instruction
Address
High
(1), (2),
Address reset exception handling vector: H'000000, H'000002 Start address (contents reset exception handling vector address) Start address First instruction program
Note: After reset, wait-state controller inserts three wait states every cycle.
Figure Reset Sequence (Modes 4.2.3 Interrupts after Reset
interrupt accepted after reset before stack pointer (SP) initialized, will saved correctly, leading program crash. prevent this, interrupt requests, including NMI, disabled immediately after reset exception handling. first instruction program always executed immediately after reset state ends. This instruction should initialize stack pointer (example: MOV.L #xx:32, SP).
Interrupts
Interrupt exception handling requested seven external sources (NMI, IRQ0 IRQ5), internal sources on-chip supporting modules. Figure classifies interrupt sources indicates number interrupts each type. on-chip supporting modules that request interrupts watchdog timer (WDT), 16-bit timer, 8-bit timer, serial communication interface (SCI), converter. Each interrupt source separate vector address. highest-priority interrupt always accepted. Interrupts controlled interrupt controller. interrupt controller assign interrupts other than priority levels, arbitrate between simultaneous interrupts. Interrupt priorities assigned interrupt priority registers (IPRA IPRB) interrupt controller. details interrupts section Interrupt Controller.
External interrupts Interrupts
Internal interrupts
WDT* 16-bit timer 8-bit timer converter
Notes: Numbers parentheses number interrupt sources. When watchdog timer used interval timer, generates interrupt request every counter overflow.
Figure Interrupt Sources Number Interrupts
Trap Instruction
Trap instruction exception handling starts when TRAPA instruction executed. system control register (SYSCR), exception handling sequence sets CCR. bits both CCR. TRAPA instruction fetches start address from vector table entry corresponding vector number from which specified instruction code.
Stack Status after Exception Handling
Figure shows stack after completion trap instruction exception handling interrupt exception handling.
SP-4 SP-3 SP-2 SP-1 (ER7)
Stack area
(ER7) SP+1 SP+2 SP+3 SP+4
Even address
Before exception handling Pushed stack Normal mode
After exception handling
SP-4 SP-3 SP-2 SP-1 (ER7)
Stack area
(ER7) SP+1 SP+2 SP+3 SP+4
Even address
Before exception handling Pushed stack Advanced mode Legend PCE: Bits program counter (PC) PCH: Bits program counter (PC) PCL: Bits program counter (PC) CCR: Condition code register Stack pointer
After exception handling
Notes: Ignored return. indicates address first instruction that will executed after return. Registers must saved word longword size even addresses.
Figure Stack after Completion Exception Handling
Notes Stack Usage
When accessing word data longword data, H8/3008 regards lowest address stack should always accessed word access longword access, value stack pointer (SP:ER7) should always kept even. following instructions save registers: PUSH.W PUSH.L MOV.W @-SP) MOV.L ERn, @-SP)
following instructions restore registers: POP.W POP.L MOV.W @SP+, MOV.L @SP+, ERn)
Setting value lead malfunction. Figure shows example what happens when value odd.
H'FFFEFA H'FFFEFB
H'FFFEFC H'FFFEFD H'FFFEFE
H'FFFEFF
TRAPA instruction executed
MOV. R1L, @-ER7
H'FFFEFF Legend CCR: Condition code register Program counter R1L: General register Stack pointer
Data saved above
contents lost
Note: diagram illustrates modes
Figure Operation when Value
Section Interrupt Controller
5.1.1
Overview
Features
interrupt controller following features: Interrupt priority registers (IPRs) setting interrupt priorities Interrupts other than assigned priority levels module-by-module basis interrupt priority registers (IPRA IPRB). Three-level enabling/disabling bits CPU's condition code register (CCR) system control register (SYSCR) Seven external interrupt pins highest priority always accepted; either rising falling edge selected. each IRQ5 IRQ0, sensing falling edge level sensing selected independently.
5.1.2
Block Diagram
Figure shows block diagram interrupt controller.
ISCR input input TEIE input section Priority decision logic IPRA, IPRB
Interrupt request Vector number
Interrupt controller Legend: ISCR: IER: ISR: IPRA: IPRB: SYSCR: SYSCR sense control register enable register status register Interrupt priority register Interrupt priority register System control register
Figure Interrupt Controller Block Diagram
5.1.3
Configuration
Table lists interrupt pins. Table
Name Nonmaskable interrupt External interrupt request
Interrupt Pins
Abbreviation IRQ5 IRQ0 Function
Input Nonmaskable interrupt, rising edge falling edge selectable Input Maskable interrupts, falling edge level sensing selectable
5.1.4
Register Configuration
Table lists registers interrupt controller. Table
Address* H'EE012 H'EE014 H'EE015 H'EE016 H'EE018 H'EE019
Interrupt Controller Registers
Name System control register sense control register enable register status register Interrupt priority register Interrupt priority register Abbreviation SYSCR ISCR IPRA IPRB R/(W)*
Initial Value H'09 H'00 H'00 H'00 H'00 H'00
Notes: Lower bits address advanced mode. Only written, clear flags.
5.2.1
Register Descriptions
System Control Register (SYSCR)
SYSCR 8-bit readable/writable register that controls software standby mode, selects action CCR, selects edge, enables disables on-chip RAM. Only bits described here. other bits, section 3.3, System Control Register (SYSCR).
SYSCR initialized H'09 reset hardware standby mode. initialized software standby mode.
Initial value Read/Write SSBY STS2 STS1 STS0 NMIEG SSOE RAME
enable Software standby output port enable Standby timer select Software standby edge select Selects input edge User enable Selects whether user interrupt mask
3-User Enable (UE): Selects whether user interrupt mask bit.
Description used interrupt mask used user (Initial value)
2-NMI Edge Select (NMIEG): Selects input edge.
NMIEG Description Interrupt requested falling edge input Interrupt requested rising edge input (Initial value)
5.2.2
Interrupt Priority Registers (IPRA, IPRB)
IPRA IPRB 8-bit readable/writable registers that control interrupt priority.
Interrupt Priority Register (IPRA): IPRA 8-bit readable/writable register which interrupt priority levels set.
Initial value Read/Write IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0
Priority level Selects priority level 16-bit timer channel interrupt requests Priority level Selects priority level 16-bit timer channel interrupt requests Priority level Selects priority level 16-bit timer channel interrupt requests Priority level Selects priority level WDT, converter interrupt requests Priority level Selects priority level IRQ4 interrupt requests Priority level Selects priority level interrupt requests Priority level Selects priority level IRQ1 interrupt requests Priority level Selects priority level interrupt requests
IPRA initialized H'00 reset hardware standby mode.
7-Priority Level (IPRA7): Selects priority level interrupt requests.
IPRA7 Description IRQ0 interrupt requests have priority level (low priority) IRQ0 interrupt requests have priority level (high priority) (Initial value)
6-Priority Level (IPRA6): Selects priority level interrupt requests.
IPRA6 Description IRQ1 interrupt requests have priority level (low priority) IRQ1 interrupt requests have priority level (high priority) (Initial value)
5-Priority Level (IPRA5): Selects priority level interrupt requests.
IPRA5 Description IRQ2 IRQ3 interrupt requests have priority level (low priority) IRQ2 IRQ3 interrupt requests have priority level (high priority) (Initial value)
4-Priority Level (IPRA4): Selects priority level interrupt requests.
IPRA4 Description IRQ4 IRQ5 interrupt requests have priority level (low priority) IRQ4 IRQ5 interrupt requests have priority level (high priority) (Initial value)
3-Priority Level (IPRA3): Selects priority level WDT, converter interrupt requests.
IPRA3 Description WDT, converter interrupt requests have priority level (low priority) (Initial value) WDT, converter interrupt requests have priority level (high priority)
2-Priority Level (IPRA2): Selects priority level 16-bit timer channel interrupt requests.
IPRA2 Description 16-bit timer channel interrupt requests have priority level (low priority) (Initial value) 16-bit timer channel interrupt requests have priority level (high priority)
1-Priority Level (IPRA1): Selects priority level 16-bit timer channel interrupt requests.
IPRA1 Description 16-bit timer channel interrupt requests have priority level (low priority) (Initial value) 16-bit timer channel interrupt requests have priority level (high priority)
0-Priority Level (IPRA0): Selects priority level 16-bit timer channel interrupt requests.
IPRA0 Description 16-bit timer channel interrupt requests have priority level (low priority) (Initial value) 16-bit timer channel interrupt requests have priority level (high priority)
Interrupt Priority Register (IPRB): IPRB 8-bit readable/writable register which interrupt priority levels set.
Initial value Read/Write IPRB7 IPRB6 IPRB3 IPRB2
Reserved Priority level Selects priority level channel interrupt requests Priority level Selects priority level channel interrupt requests Reserved bits Priority level Selects priority level 8-bit timer channel interrupt requests Priority level Selects priority level 8-bit timer channel interrupt requests
IPRB initialized H'00 reset hardware standby mode. 7-Priority Level (IPRB7): Selects priority level 8-bit timer channel interrupt requests.
IPRB7 Description 8-bit timer channel interrupt requests have priority level (low priority) (Initial value) 8-bit timer channel interrupt requests have priority level (high priority)
6-Priority Level (IPRB6): Selects priority level 8-bit timer channel interrupt requests.
IPRB6 Description 8-bit timer channel interrupt requests have priority level (low priority) (Initial value) 8-bit timer channel interrupt requests have priority level (high priority)
Bits 4-Reserved: These bits written read, they affect interrupt priority. 3-Priority Level (IPRB3): Selects priority level channel
Other recent searches
YA862C08R - YA862C08R YA862C08R Datasheet
XNN1LUYR86M - XNN1LUYR86M XNN1LUYR86M Datasheet
SM1105 - SM1105 SM1105 Datasheet
PS7141-1B - PS7141-1B PS7141-1B Datasheet
PS7141L-1B - PS7141L-1B PS7141L-1B Datasheet
MHW2805 - MHW2805 MHW2805 Datasheet
MHW2805-1 - MHW2805-1 MHW2805-1 Datasheet
MHW2805-2 - MHW2805-2 MHW2805-2 Datasheet
ISL6327 - ISL6327 ISL6327 Datasheet
I2716 - I2716 I2716 Datasheet
GPLB32A2 - GPLB32A2 GPLB32A2 Datasheet
ROSC32K - ROSC32K ROSC32K Datasheet
AN1948 - AN1948 AN1948 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
