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revision list viewed directly clicking title page. revision list summarizes locations revisions additions. Details should always checked referring relevant text.
H8/3006, H8/3007
HD6413006, HD6413007
Hardware Manual
ADE-602-145C Rev. 3/4/03 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
H8/3006 H8/3007 series high-performance microcontrollers that integrate system supporting functions together with H8/300H core. H8/300H 32-bit internal architecture with sixteen 16-bit general registers, concise, optimized instruction designed speed. address 16-Mbyte linear address space. on-chip supporting functions include RAM, 16-bit timers, 8-bit timers, programmable timing pattern controller (TPC), watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports, controller (DMAC). address space divided into eight areas. data width access cycle length selected independently each area, simplifying connection different types memory. Four operating modes (modes provided, offering choice data width initial value address space. With these features, H8/3006 H8/3007 offers easy implementation compact, highperformance systems. This manual describes H8/3006 H8/3007 Series hardware. details instruction set, refer H8/300H Series Programming Manual.
List Items Revised Added This Version
Page Item Overview Table Feature Watchdog timer (WDT) 2.6.1 Instruction Overview Table Manipulation Instructions 2.6.5 Notes Manipulation Instruction Explanation Table 2-13 Effective Address Calculation Description Specification description amended Number instruction types amended Function description added Description added Addressing Mode Instruction Format column amended Table amended Description added Description added Description added Figure amended cycle amended
Table Operating Mode Selection 3.1.1 Operating Mode Selection 4.2.2 Reset Sequence 5.1.1 Features Figure 6.15 Example Wait State Insertion Timing Figure 6.42 Example Idle Cycle Operation (ICIS0 Idle cycle inserted 7.4.2 Mode Table Register Functions Mode
Description added Description added Description added Description added Description added Description added Note added Description amended Description amended Reference changed Description added Description amended
7.4.3 Idle Mode Table Register Functions Idle Mode 7.4.4 Repeat Mode Table Register Functions Repeat Mode 7.4.8 DMAC Cycle 8.3.2 Register Configuration Port Data Direction Register (P6DDR) 8.3.2 Register Configuration Port Data Register (P6DR) 8.5.1 Overview Figure Port Configuration
8.5.2 Register Configuration Port Data Direction Register (P8DDR)
Page
Item 8.5.2 Register Configuration Port Data Register (P8DR) 8.6.2 Register Configuration Port Data Direction Register (P9DDR) 8.7.2 Register Configuration Port Data Direction Register (PADDR) Figure Port Configuration 8.8.2 Register Configuration Port Data Direction Register (PBDDR) Section 16-Bit Timers
Description Description amended Description amended Description amended Description added Description amended Register names changed TCNT 16TCNT 16TCR Register names changed TCNT 8TCNT 8TCR TCSR 8TCSR 8TCSR2 initial value changed Description amended Description added Note added Description added 20.00 value added 20.00 value added 20.00 value added Restart procedure amended Figure amended Text note amended Register names amended
Section 8-Bit Timers
Table 10.2 8-Bit Timer Register 10.2.4 Timer Control Register (8TCR) Bits 10.2.5 Timer Control/Status Registers (8TCSR) Table 12.2 Registers Figure 13.5 Sample Flowchart Transmitting Serial Data Table 14.5 Rates (bit/s) Various Settings (When Table 14.6 Settings Typical Rates (bits/s) (When Table 14.7 Maximum Rate Various Frequencies (Smart Card Interface Mode)
640,
Figure 14.10 Procedure Stopping Restarting Clock Figure 18.7 External Clock Output Setting Delay Timing 18.5.3 Usage Notes Addresses
Page
Item Functions P8DDR-Port Data Direction Register Functions TSTR-Timer Start Register Functions TSNC-Timer Syncro Register Functions TMDR-Timer Mode Register Functions TISRA-Timer Interrupt Status Register Function TISRB-Timer Interrupt Status Register Functions TISRC-Timer Interrupt Status Register Functions 16TCR0-Timer Control Register Functions 16TCNT0H/L-Timer Counter 0H/L Functions 16TCR1-Timer Control Register Function 16TCNT1H/L-Timer Counter 1H/L
Description Note deleted Description amended Description amended Description amended Description amended Description amended Description amended Register name changed Register name changed Register name changed Register name changed Register name changed Register name changed Register names changed, description amended Register names changed, description amended Register names changed, description amended Register names changed
Functions 16TCR2-Timer Control Register Functions 16TCNT2H/L-Timer Counter 2H/L Functions 8TCR0-Timer Control Register 8TCR1-Timer Control Register Functions 8TCSR0-Timer Control/Status Register Functions 8TCSR1-Timer Control/Status Register Functions 8TCNT0-Timer Counter 8TCNT1-Timer Counter Functions 8TCR2-Timer Control Register 8TCR3-Timer Control Register
Register names changed, description amended
Page
Item Functions 8TCSR2-Timer Control/Status Register 8TCSR3-Timer Control/Status Register Functions 8TCNT2-Timer Counter 8TCNT3-Timer Counter Functions P6DR-Port Data Register Figure Port Block Diagram Figure C.2(a) Figure C.2(c) Port Block Diagram Figure C.4(a) Figure C.4(d) Port Block Diagram Figure C.5(a) Figure C.5(f) Port Block Diagram Figure C.6(a) Figure C.6(c) Port Block Diagram Figure C.7(a) Figure C.7(f) Port Block Diagram
Description Register names changed, description amended Register name changed
Description amended Figure amended Figure amended Figure amended Figure amended Figure amended Figure amended
Contents
Section Overview.
Overview. Internal Block Diagram Description 1.3.1 Arrangement 1.3.2 Functions. 1.3.3 Assignments Each Mode.
Section
Overview. 2.1.1 Features 2.1.2 Differences from H8/300 CPU. Operating Modes Address Space. Register Configuration 2.4.1 Overview 2.4.2 General Registers. 2.4.3 Control Registers. 2.4.4 Initial Register Values Data Formats. 2.5.1 General Register Data Formats 2.5.2 Memory Data Formats. Instruction Set. 2.6.1 Instruction Overview. 2.6.2 Instructions Addressing Modes 2.6.3 Tables Instructions Classified Function. 2.6.4 Basic Instruction Formats. 2.6.5 Notes Manipulation Instructions. Addressing Modes Effective Address Calculation 2.7.1 Addressing Modes. 2.7.2 Effective Address Calculation. Processing States 2.8.1 Overview 2.8.2 Program Execution State 2.8.3 Exception-Handling State 2.8.4 Exception-Handling Sequences. 2.8.5 Bus-Released State 2.8.6 Reset State 2.8.7 Power-Down State.
Basic Operational Timing. 2.9.1 Overview 2.9.2 On-Chip Memory Access Timing 2.9.3 On-Chip Supporting Module Access Timing. 2.9.4 Access External Address Space.
Section Operating Modes
Overview. 3.1.1 Operating Mode Selection. 3.1.2 Register Configration Mode Control Register (MDCR) System Control Register (SYSCR). Operating Mode Descriptions. 3.4.1 Mode 3.4.2 Mode 3.4.3 Mode 3.4.4 Mode Functions Each Operating Mode. Memory Each Operating Mode. 3.6.1 Note Reserved Areas
Section Exception Handling
Overview. 4.1.1 Exception Handling Types Priority 4.1.2 Exception Handling Operation 4.1.3 Exception Vector Table. Reset 4.2.1 Overview 4.2.2 Reset Sequence. 4.2.3 Interrupts after Reset Interrupts. Trap Instruction Stack Status after Exception Handling Notes Stack Usage.
Section Interrupt Controller
Overview. 5.1.1 Features 5.1.2 Block Diagram. 5.1.3 Configuration 5.1.4 Register Configuration Register Descriptions. 5.2.1 System Control Register (SYSCR)
5.2.2 Interrupt Priority Registers (IPRA, IPRB) 5.2.3 Status Register (ISR) 5.2.4 Enable Register (IER) 5.2.5 Sense Control Register (ISCR). Interrupt Sources. 5.3.1 External Interrupts. 5.3.2 Internal Interrupts 5.3.3 Interrupt Vector Table Interrupt Operation 5.4.1 Interrupt Handling Process 5.4.2 Interrupt Sequence. 5.4.3 Interrupt Response Time Usage Notes 5.5.1 Contention between Interrupt Interrupt-Disabling Instruction. 5.5.2 Instructions that Inhibit Interrupts. 5.5.3 Interrupts during EEPMOV Instruction Execution
Section Controller
Overview. 6.1.1 Features 6.1.2 Block Diagram. 6.1.3 Configuration 6.1.4 Register Configuration Register Descriptions. 6.2.1 Width Control Register (ABWCR) 6.2.2 Access State Control Register (ASTCR). 6.2.3 Wait Control Registers (WCRH, WCRL). 6.2.4 Release Control Register (BRCR) 6.2.5 Control Register (BCR) 6.2.6 Chip Select Control Register (CSCR). 6.2.7 DRAM Control Register (DRCRA) 6.2.8 DRAM Control Register (DRCRB). 6.2.9 Refresh Timer Control/Status Register (RTMCSR) 6.2.10 Refresh Timer Counter (RTCNT) 6.2.11 Refresh Time Constant Register (RTCOR). Operation 6.3.1 Area Division. 6.3.2 Specifications 6.3.3 Memory Interfaces. 6.3.4 Chip Select Signals. Basic Interface. 6.4.1 Overview 6.4.2 Data Size Data Alignment
6.4.3 Valid Strobes 6.4.4 Memory Areas. 6.4.5 Basic Control Signal Timing. 6.4.6 Wait Control DRAM Interface. 6.5.1 Overview 6.5.2 DRAM Space Output Settings 6.5.3 Address Multiplexing 6.5.4 Data 6.5.5 Pins Used DRAM Interface 6.5.6 Basic Timing 6.5.7 Precharge State Control. 6.5.8 Wait Control 6.5.9 Byte Access Control Output Pin. 6.5.10 Burst Operation 6.5.11 Refresh Control 6.5.12 Examples Use. 6.5.13 Usage Notes. Interval Timer. 6.6.1 Operation Interrupt Sources. Burst Interface 6.8.1 Overview 6.8.2 Basic Timing 6.8.3 Wait Control Idle Cycle. 6.9.1 Operation 6.9.2 States Idle Cycle 6.10 Arbiter 6.10.1 Operation 6.11 Register Input Timing 6.11.1 Register Write Timing. 6.11.2 BREQ Input Timing.
Section Controller
Overview. 7.1.1 Features 7.1.2 Block Diagram. 7.1.3 Functional Overview 7.1.4 Configuration 7.1.5 Register Configuration Register Descriptions (Short Address Mode) 7.2.1 Memory Address Registers (MAR).
7.2.2 Address Registers (IOAR) 7.2.3 Execute Transfer Count Registers (ETCR) 7.2.4 Data Transfer Control Registers (DTCR) Register Descriptions (Full Address Mode) 7.3.1 Memory Address Registers (MAR). 7.3.2 Address Registers (IOAR) 7.3.3 Execute Transfer Count Registers (ETCR) 7.3.4 Data Transfer Control Registers (DTCR) Operation 7.4.1 Overview 7.4.2 Mode 7.4.3 Idle Mode. 7.4.4 Repeat Mode 7.4.5 Normal Mode. 7.4.6 Block Transfer Mode. 7.4.7 DMAC Activation 7.4.8 DMAC Cycle 7.4.9 Multiple-Channel Operation 7.4.10 External Requests, DRAM Interface, DMAC. 7.4.11 Interrupts DMAC. 7.4.12 Aborting DMAC Transfer 7.4.13 Exiting Full Address Mode 7.4.14 DMAC States Reset State, Standby Modes, Sleep Mode. Interrupts. Usage Notes 7.6.1 Note Word Data Transfer 7.6.2 DMAC Self-Access. 7.6.3 Longword Access Memory Address Registers 7.6.4 Note Full Address Mode Setup 7.6.5 Note Activating DMAC Internal Interrupts 7.6.6 Interrupts Block Transfer Mode. 7.6.7 Memory Address Register Values 7.6.8 Cycle when Transfer Aborted. 7.6.9 Transfer Requests Converter
Section Ports
Overview. Port 8.2.1 Overview 8.2.2 Register Configuration Port 8.3.1 Overview 8.3.2 Register Configuration
Port 8.4.1 Overview 8.4.2 Register Configuration Port 8.5.1 Overview 8.5.2 Register Configuration Port 8.6.1 Overview 8.6.2 Register Configuration Port 8.7.1 Overview 8.7.2 Register Configuration Port 8.8.1 Overview 8.8.2 Register Configuration
Section 16-Bit Timer
Overview. 9.1.1 Features 9.1.2 Block Diagrams. 9.1.3 Configuration 9.1.4 Register Configuration Register Descriptions. 9.2.1 Timer Start Register (TSTR). 9.2.2 Timer Synchro Register (TSNC). 9.2.3 Timer Mode Register (TMDR) 9.2.4 Timer Interrupt Status Register (TISRA) 9.2.5 Timer Interrupt Status Register (TISRB). 9.2.6 Timer Interrupt Status Register (TISRC) 9.2.7 Timer Counters (16TCNT). 9.2.8 General Registers (GRA, GRB) 9.2.9 Timer Control Registers (16TCR). 9.2.10 Timer Control Register (TIOR) 9.2.11 Timer Output Level Setting Register (TOLR). Interface 9.3.1 16-Bit Accessible Registers. 9.3.2 8-Bit Accessible Registers. Operation 9.4.1 Overview 9.4.2 Basic Functions 9.4.3 Synchronization. 9.4.4 Mode 9.4.5 Phase Counting Mode
9.4.6 Setting Initial Value 16-Bit Timer Output Interrupts. 9.5.1 Setting Status Flags. 9.5.2 Timing Clearing Status Flags 9.5.3 Interrupt Sources Controller Activation. Usage Notes
Section 8-Bit Timers
10.1 Overview. 10.1.1 Features 10.1.2 Block Diagram. 10.1.3 Configuration 10.1.4 Register Configuration 10.2 Register Descriptions. 10.2.1 Timer Counters (8TCNT). 10.2.2 Time Constant Registers (TCORA) 10.2.3 Time Constant Registers (TCORB). 10.2.4 Timer Control Register (8TCR) 10.2.5 Timer Control/Status Registers (8TCSR) 10.3 Interface 10.3.1 8-Bit Registers. 10.4 Operation 10.4.1 8TCNT Count Timing. 10.4.2 Compare Match Timing 10.4.3 Input Capture Signal Timing. 10.4.4 Timing Status Flag Setting. 10.4.5 Operation with Cascaded Connection 10.4.6 Input Capture Setting. 10.5 Interrupt 10.5.1 Interrupt Source. 10.5.2 Converter Activation 10.6 8-Bit Timer Application Example 10.7 Usage Notes 10.7.1 Contention between 8TCNT Write Clear. 10.7.2 Contention between 8TCNT Write Increment 10.7.3 Contention between TCOR Write Compare Match 10.7.4 Contention between TCOR Read Input Capture 10.7.5 Contention between Counter Clearing Input Capture Counter Increment 10.7.6 Contention between TCOR Write Input Capture 10.7.7 Contention between 8TCNT Byte Write Increment 16-Bit Count Mode (Cascaded Connection). 10.7.8 Contention between Compare Matches 10.7.9 8TCNT Operation Internal Clock Source Switchover
Section Programmable Timing Pattern Controller (TPC).
11.1 Overview. 11.1.1 Features 11.1.2 Block Diagram. 11.1.3 Configuration 11.1.4 Register Configuration 11.2 Register Descriptions. 11.2.1 Port Data Direction Register (PADDR) 11.2.2 Port Data Register (PADR) 11.2.3 Port Data Direction Register (PBDDR). 11.2.4 Port Data Register (PBDR). 11.2.5 Next Data Register (NDRA) 11.2.6 Next Data Register (NDRB) 11.2.7 Next Data Enable Register (NDERA). 11.2.8 Next Data Enable Register (NDERB) 11.2.9 Output Control Register (TPCR) 11.2.10 Output Mode Register (TPMR) 11.3 Operation 11.3.1 Overview 11.3.2 Output Timing 11.3.3 Normal Output 11.3.4 Non-Overlapping Output 11.3.5 Output Triggering Input Capture 11.4 Usage Notes 11.4.1 Operation Output Pins. 11.4.2 Note Non-Overlapping Output.
Section Watchdog Timer
12.1 Overview. 12.1.1 Features 12.1.2 Block Diagram. 12.1.3 Configuration 12.1.4 Register Configuration 12.2 Register Descriptions. 12.2.1 Timer Counter (TCNT) 12.2.2 Timer Control/Status Register (TCSR) 12.2.3 Reset Control/Status Register (RSTCSR) 12.2.4 Notes Register Access 12.3 Operation 12.3.1 Watchdog Timer Operation. 12.3.2 Interval Timer Operation. 12.3.3 Timing Setting Overflow Flag (OVF) 12.3.4 Timing Setting Watchdog Timer Reset (WRST)
viii
12.4 Interrupts. 12.5 Usage Notes
Section Serial Communication Interface
13.1 Overview. 13.1.1 Features 13.1.2 Block Diagram. 13.1.3 Configuration 13.1.4 Register Configuration 13.2 Register Descriptions. 13.2.1 Receive Shift Register (RSR). 13.2.2 Receive Data Register (RDR) 13.2.3 Transmit Shift Register (TSR). 13.2.4 Transmit Data Register (TDR) 13.2.5 Serial Mode Register (SMR). 13.2.6 Serial Control Register (SCR). 13.2.7 Serial Status Register (SSR). 13.2.8 Rate Register (BRR). 13.3 Operation 13.3.1 Overview 13.3.2 Operation Asynchronous Mode. 13.3.3 Multiprocessor Communication 13.3.4 Synchronous Operation 13.4 Interrupts 13.5 Usage Notes 13.5.1 Notes
Section Smart Card Interface
14.1 Overview. 14.1.1 Features 14.1.2 Block Diagram. 14.1.3 Configuration 14.1.4 Register Configuration 14.2 Register Descriptions. 14.2.1 Smart Card Mode Register (SCMR) 14.2.2 Serial Status Register (SSR). 14.2.3 Serial Mode Register (SMR). 14.2.4 Serial Control Register (SCR). 14.3 Operation 14.3.1 Overview 14.3.2 Connections. 14.3.3 Data Format. 14.3.4 Register Settings.
14.3.5 Clock 14.3.6 Transmitting Receiving Data. 14.4 Usage Notes
Section Converter
15.1 Overview. 15.1.1 Features 15.1.2 Block Diagram. 15.1.3 Configuration 15.1.4 Register Configuration 15.2 Register Descriptions. 15.2.1 Data Registers (ADDRA ADDRD). 15.2.2 Control/Status Register (ADCSR). 15.2.3 Control Register (ADCR). 15.3 Interface 15.4 Operation 15.4.1 Single Mode (SCAN 15.4.2 Scan Mode (SCAN 15.4.3 Input Sampling Conversion Time. 15.4.4 External Trigger Input Timing 15.5 Interrupts. 15.6 Usage Notes
Section Converter
16.1 Overview. 16.1.1 Features 16.1.2 Block Diagram. 16.1.3 Configuration 16.1.4 Register Configuration 16.2 Register Descriptions. 16.2.1 Data Registers (DADR0/1). 16.2.2 Control Register (DACR). 16.2.3 Standby Control Register (DASTCR). 16.3 Operation 16.4 Output Control
Section
17.1 Overview. 17.1.1 Block Diagram. 17.1.2 Register Configuration 17.2 System Control Register (SYSCR). 17.3 Operation
Section Clock Pulse Generator
18.1 Overview. 18.1.1 Block Diagram. 18.2 Oscillator Circuit 18.2.1 Connecting Crystal Resonator 18.2.2 External Clock Input 18.3 Duty Adjustment Circuit. 18.4 Prescalers 18.5 Frequency Divider 18.5.1 Register Configuration 18.5.2 Division Control Register (DIVCR) 18.5.3 Usage Notes.
Section Power-Down State.
19.1 Overview. 19.2 Register Configuration 19.2.1 System Control Register (SYSCR) 19.2.2 Module Standby Control RegisterH (MSTCRH) 19.2.3 Module Standby Control Register (MSTCRL). 19.3 Sleep Mode. 19.3.1 Transition Sleep Mode 19.3.2 Exit from Sleep Mode 19.4 Software Standby Mode 19.4.1 Transition Software Standby Mode. 19.4.2 Exit from Software Standby Mode. 19.4.3 Selection Waiting Time Exit from Software Standby Mode. 19.4.4 Sample Application Software Standby Mode. 19.4.5 Note 19.5 Hardware Standby Mode 19.5.1 Transition Hardware Standby Mode 19.5.2 Exit from Hardware Standby Mode 19.5.3 Timing Hardware Standby Mode 19.6 Module Standby Function. 19.6.1 Module Standby Timing. 19.6.2 Read/Write Module Standby. 19.6.3 Usage Notes. 19.7 System Clock Output Disabling Function
Section Electrical Characteristics
20.1 Absolute Maximum Ratings. 20.2 Electrical Characteristics 20.2.1 Characteristics.
20.2.2 Characteristics. 20.2.3 Conversion Characteristics 20.2.4 Conversion Characteristics 20.3 Operational Timing. 20.3.1 Clock Timing. 20.3.2 Control Signal Timing. 20.3.3 Timing 20.3.4 DRAM Interface Timing. 20.3.5 Port Timing 20.3.6 Timer Input/Output Timing. 20.3.7 Input/Output Timing 20.3.8 DMAC Timing
Appendix Instruction
Instruction List. Operation Code Number States Required Execution.
Appendix Internal Registers.
Addresses. Functions.
Appendix Port Block Diagrams
Port Block Diagram. Port Block Diagrams Port Block Diagrams Port Block Diagrams Port Block Diagrams Port Block Diagrams. Port Block Diagrams.
Appendix States.
Port States Each Mode States Reset.
Appendix Timing Transition Recovery from Hardware Standby Mode Appendix List Product Codes Appendix Package Dimensions
Appendix Comparison H8/300H Series Product Specifications.
Differences between H8/3067 H8/3062 Series, H8/3048 Series, H8/3007 H8/3006, H8/3002. Comparison Functions 100-Pin Package Products (FP-100B, TFP-100B)
xiii
Section Overview
Overview
H8/3006 H8/3007 series microcontrollers (MCUs) that integrate system supporting functions together with H8/300H core having original Hitachi architecture. H8/300H 32-bit internal architecture with sixteen 16-bit general registers, concise, optimized instruction designed speed. address 16-Mbyte linear address space. instruction upward-compatible object-code level with H8/300 CPU, enabling easy porting software from H8/300 Series. on-chip system supporting functions include RAM, 16-bit timer, 8-bit timer, programmable timing pattern controller (TPC), watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports, direct memory access controller (DMAC), other facilities. Four operating modes offer choice width address space size. Table summarizes features H8/3006 H8/3007. Table
Feature
Features
Description Upward-compatible with H8/300 object-code level General-register machine Sixteen 16-bit general registers (also usable sixteen 8-bit registers plus eight 16-bit registers, eight 32-bit registers) Maximum clock rate: Add/subtract: Multiply/divide:
High-speed operation
16-Mbyte address space Instruction features 8/16/32-bit data transfer, arithmetic, logic instructions Signed unsigned multiply instructions bits bits, bits bits) Signed unsigned divide instructions bits bits, bits bits) accumulator function manipulation instructions with register-indirect specification positions
Feature Memory
Description H8/3007 RAM: kbytes RAM: kbytes Seven external interrupt pins: NMI, IRQ0 IRQ5 internal interrupts Three selectable interrupt priority levels Address space partitioned into eight areas, with independent specifications each area Chip select output available areas 8-bit access 16-bit access selectable each area Two-state three-state access selectable each area Selection wait modes Number program wait states selectable each area Direct connection burst Direct connection 8-Mbyte DRAM DRAM interface used interval timer) arbitration function H8/3006
Interrupt controller controller
controller (DMAC)
Short address mode Maximum four channels available Selection mode, idle mode, repeat mode activated compare match/input capture interrupts from 16-bit timer channels conversion-end interrupts from converter, transmit-data-empty receive-data-full interrupts from SCI, external requests Maximum channels available Selection normal mode block transfer mode activated compare match/input capture interrupts from 16-bit timer channels conversion-end interrupts from converter, external requests, auto-request
Full address mode
Feature 16-bit timer, channels
Description Three 16-bit timer channels, capable processing pulse outputs pulse inputs 16-bit timer counter (channels multiplexed output compare/input capture pins (channels Operation synchronized (channels mode available (channels Phase counting mode available (channel DMAC activated compare match/input capture interrupts (channels 8-bit up-counter (external event count capability) time constant registers channels connected Maximum 16-bit pulse output, using 16-bit timer time base four 4-bit pulse output groups 16-bit group, 8-bit groups) Non-overlap mode available Output data transferred DMAC Internal reset signal generated overflow Reset signal output externally Usable interval timer Selection asynchronous synchronous mode Full duplex: transmit receive simultaneously On-chip baud-rate generator Smart card interface functions added Resolution: bits Eight channels, with selection single scan mode Variable analog conversion voltage range Sample-and-hold function conversion started external trigger 8-bit timer comparematch DMAC activated conversion interrupt Resolution: bits channels outputs sustained software standby mode input/output pins input-only pins
8-bit timer, channels
Programmable timing pattern controller (TPC)
Watchdog timer (WDT), channel Serial communication interface (SCI), channels converter
converter
ports
Feature Operating modes
Description Four operating modes Mode Mode Mode Mode Mode Address Space Address Pins Initial Width Max. Width Mbyte Mbyte Mbytes Mbytes bits bits bits bits bits bits bits bits
Power-down state
Sleep mode Software standby mode Hardware standby mode Module standby function Programmable system clock frequency division On-chip clock pulse generator Model HD6413007F HD6413007TE HD6413007FP HD6413007VF (Low voltage) HD6413007VTE HD6413007VFP HD6413006F HD6413006TE HD6413006FP HD6413006VF (Low voltage) HD6413006VTE HD6413006VFP Package 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100A) 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100A) 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100A) 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100A)
Other features Product lineup
Product Name H8/3007
H8/3006
Internal Block Diagram
Figure shows internal block diagram.
Data Address EXTAL XTAL STBY RESO /P67
Port Clock pulse generator
Port
Data (upper) Data (lower)
Address Port
H8/300H
Interrupt controller controller (DMAC)
BACK/P62 BREQ/P61 WAIT/P60
controller
CS0/P84 CS2/IRQ2/P82 CS3/IRQ1/P81 RFSH/IRQ0/P80
Port
ADTRG/CS1/IRQ3/P83
Watchdog timer (WDT) 16-bit timer unit Serial communication interface (SCI) channels /SCK /IRQ Programmable timing pattern controller (TPC) converter converter /SCK /IRQ /RxD1 /RxD0 /TxD /TxD
8-bit timer unit
Port
CS4/DREQ1/TMIO3/TP11/PB3 CS6/DREQ0/TMIO1/TP9/PB1 CS5/TMO2/TP10/PB2 CS7/TMO0/TP8/PB0 SCK2/LCAS/TP13/PB5 A20/TIOCB2/TP7/PA7 A21/TIOCA2/TP6/PA6 A22/TIOCB1/TP5/PA5 UCAS/TP12/PB4 RxD2/TP15/PB7 TxD2/TP14/PB6
Port
VREF AVCC TEND1/TCLKB/TP1/PA1 TCLKD/TIOCB0/TP3/PA3 TCLKC/TIOCA0/TP2/PA2 TEND0/TCLKA/TP0/PA0 A23/TIOCA1/TP4/PA4 AVSS DA1/AN7/P77 DA0/AN6/P76 AN5/P75
Port
AN4/P74 AN3/P73 AN2/P72 AN1/P71 AN0/P70
Figure Block Diagram
1.3.1
Description
Arrangement
arrangement H8/3006, H8/3007 FP-100B TFP-100B packages shown figure 1-2, that FP-100A package figure 1-3.
/BREQ /BACK /WAIT
EXTAL
STBY
P67/
XTAL
AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P80/IRQ0/RFSH P81/IRQ1/CS3 P82/IRQ2/CS2 P83/IRQ3/CS1/ADTRG P84/CS0 PA0/TP0/TCLKA/TEND0 PA1/TP1/TCLKB/TEND1 PA2/TP2/TIOCA0/TCLKC PA3/TP3/TIOCB0/TCLKD PA4/TP4/TIOCA1/A23 PA5/TP5/TIOCB1/A22 PA6/TP6/TIOCA2/A21 PA7/TP7/TIOCB2/A20
INDEX view (FP-100B, TFP-100B)
D7/P47
TxD0 /P90
TxD1 /P91
RxD0 /P92
RxD1 /P93
IRQ4 /SCK0 /P94
IRQ5 /SCK1 /P95
/P40
/P41
/P42
CS7/TMO0/TP8/PB0
CS6/DREQ0/TMIO1/TP9/PB1
CS5/TMO2/TP10/PB2
CS4/DREQ1/TMIO3/TP11/PB3
UCAS/TP12/PB4
SCK2/LCAS/TP13/PB5
TxD2/TP14/PB6
RxD2/TP15/PB7
/P43
RESO
/P44
/P45
Figure Arrangement (FP-100B TFP-100B, View)
/P46
P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P80/IRQ0/RFSH P81/IRQ1/CS3 P82/IRQ2/CS2 P83/IRQ3/CS1/ADTRG P84/CS0 PA0/TP0/TCLKA/TEND0 PA1/TP1/TCLKB/TEND1 PA2/TP2/TIOCA0/TCLKC PA3/TP3/TIOCB0/TCLKD PA4/TP4/TIOCA1/A23 PA5/TP5/TIOCB1/A22
Figure
view (FP-100A)
Arrangement (FP-100A, View)
A21/TIOCA2 /TP6 /PA6 A20/TIOCB2 /TP7 /PA7 /TMO0 /TP8 /PB0 /DREQ0 /TMIO1 /TP9 /PB1 /TMO /TP10 /PB2 /DREQ /TMIO /TP11/PB3 UCAS/TP12 /PB4 SCK2 /LCAS/TP13 /PB5 /TP14 /PB6 /TP15 RESO TxD0 /P90 TxD1 /P91 /SCK /P94 /SCK /P95 /P41 /P42 /P43 D4/P44 D5/P45 D6/P46 D7/P47
P70/AN0 VREF AVCC XTAL EXTAL STBY P67/ P62/BACK P61/BREQ P60/WAIT
1.3.2
Functions
Table summarizes functions. Table Functions
Type Power Symbol FP-100B TFP-100B FP-100A Input Name Function Power: connection power supply. Connect pins system power supply. Ground: connection ground Connect pins system power supply. connection crystal resonator. examples crystal resonator external clock input, section Clock Pulse Generator. connection crystal resonator input external clock signal. examples crystal resonator external clock input, section Clock Pulse Generator.
Input
Clock
XTAL
Input
EXTAL
Input
Operating mode control
Output System clock: Supplies system clock external devices. Mode mode setting operating mode, follows. Inputs these pins must changed during operation. Operating Mode Mode Mode Mode Mode
Input
Type System control Symbol RESO FP-100B TFP-100B FP-100A Input Name Function Reset input: When driven low, this resets chip
Output Reset output: Outputs reset signal generated watchdog timer external devices Input Input Standby: When driven low, this forces transition hardware standby mode request: Used external master request right
STBY BREQ BACK
Output request acknowledge: Indicates that been granted external master Input Nonmaskable interrupt: Requests nonmaskable interrupt Interrupt request Maskable interrupt request pins
Interrupts IRQ5 IRQ0 Address
Input
100, Output Address bus: Outputs address signals Input/ Data bus: Bidirectional data output Output Chip select: Select signals areas Output Address strobe: Goes indicate valid address output address Output Read: Goes indicate reading from external address space Output High write: Goes indicate writing external address space; indicates valid data upper data D8). Output write: Goes indicate writing external address space; indicates valid data lower data D0). Input Wait: Requests insertion wait states cycles during access external address space
Data control
WAIT
Type DRAM interface Symbol RFSH UCAS LCAS controller (DMAC) DREQ1, DREQ0 TEND1, TEND0 FP-100B TFP-100B FP-100A Name Function
Output Refresh: Indicates refresh cycle Output address strobe RAS: address strobe signal DRAM Output Write enable Write enable signal DRAM Output Upper column address strobe UCAS: Column address strobe signal DRAM Output Lower column address strobe LCAS: Column address strobe signal DRAM Input request DMAC activation requests
to95
Output Transfer These signals indicate that DMAC ended data transfer Input Clock input External clock inputs
16-bit timer
TCLKD TCLKA
TIOCA2 Input/ Input capture/output compare TIOCA0 output GRA2 GRA0 output compare input capture, output TIOCB2 100, TIOCB0 8-bit timer TMO0, TMO2 TMIO1, TMIO3 100, Input/ Input capture/output compare output GRB2 GRB0 output compare input capture, output Output Compare match output: Compare match output pins Input/ Input capture input/compare match output: output Input capture input compare match output pins Counter external clock input: These pins input external clock counters.
TCLKD TCLKA
Input
Type Symbol FP-100B TFP-100B FP-100A Name Function
Program- mable timing pattern controller (TPC) Serial communication interface (SCI) TxD2 TxD0 RxD2 RxD0
Output output Pulse output
Output Transmit data (channels data output Input Receive data (channels data input
Input/ Serial clock (channels clock output input/output Input Input Analog Analog input pins conversion external trigger input: External trigger input starting conversion
converter ADTRG
converter AVCC converters AVSS VREF
Output Analog output: Analog output from converter Input Power supply converters. Connect system power supply when using converters. Ground converters. Connect system ground Reference voltage input converters. Connect system power supply when using converters.
Input Input
Type ports Symbol FP-100B TFP-100B FP-100A Name Function
P67,
Input/ Port Eight input/output pins. direction output each selected port data direction register (P4DDR). Input/ Port Four input/output pins. direction output each selected port data direction register (P6DDR). Input Port Eight input pins
Input/ Port Five input/output pins. direction output each selected port data direction register (P8DDR). Input/ Port input/output pins. direction output each selected port data direction register (P9DDR). Input/ Port Eight input/output pins. direction output each selected port data direction register (PADDR). Input/ Port Eight input/output pins. direction output each selected port data direction register (PBDDR).
1.3.3 Assignments Each Mode Table lists assignments each mode. Table Assignments Each Mode (FP-100B TFP-100B, FP-100A)
Name Mode PB0/TP8/TMO0/ PB1/TP9/TMIO1/ DREQ0/CS PB2/TP10 /TMO2/ Mode PB0/TP8/TMO0/ PB1/TP9/TMIO1/ DREQ0/CS PB2/TP10 /TMO2/ Mode PB0/TP8/TMO0/ PB1/TP9/TMIO1/ DREQ0/CS PB2/TP10 /TMO2/ Mode PB0/TP8/TMO0/ PB1/TP9/TMIO1/ DREQ0/CS PB2/TP10 /TMO2/
FP-100B TFP-100B FP-100A
PB3/TP11 /TMIO3/ PB3/TP11 /TMIO3/ PB3/TP11 /TMIO3/ PB3/TP11 /TMIO3/ DREQ1/CS DREQ1/CS DREQ1/CS DREQ1/CS PB4/TP12 /UCAS PB4/TP12 /UCAS PB4/TP12 /UCAS PB4/TP12 /UCAS
PB5/TP13 /LCAS/ PB5/TP13 /LCAS/ PB5/TP13 /LCAS/ PB5/TP13 /LCAS/ PB6/TP14 /TxD2 PB7/TP15 /RxD2 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 /IRQ4 /SCK0 P95/IRQ5 /SCK1 P40/D0*
PB6/TP14 /TxD2 PB7/TP15 /RxD2 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 /IRQ4 /SCK0 P95/IRQ5 /SCK1 P40/D0*
PB6/TP14 /TxD2 PB7/TP15 /RxD2 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 /IRQ4 /SCK0 P95/IRQ5 /SCK1 P40/D0*
PB6/TP14 /TxD2 PB7/TP15 /RxD2 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 /IRQ4 /SCK0 P95/IRQ5 /SCK1 P40/D0* P41/D1* P42/D2* P43/D3* P44/D4*
P41/D1* P42/D2* P43/D3* P44/D4*
P41/D1* P42/D2* P43/D3* P44/D4*
P41/D1* P42/D2* P43/D3* P44/D4*
FP-100B TFP-100B FP-100A Mode P45/D5*
Name Mode P45/D5*
Mode P45/D5*
Mode P45/D5* P46/D6* P47/D7*
P46/D6* P47/D7*
P46/D6* P47/D7*
P46/D6* P47/D7*
FP-100B TFP-100B FP-100A Mode P60/WAIT P61/BREQ P62/BACK P67/ STBY EXTAL XTAL AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 Mode P60/WAIT P61/BREQ P62/BACK P67/ STBY EXTAL XTAL AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1
Name Mode P60/WAIT P61/BREQ P62/BACK P67/ STBY EXTAL XTAL AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 Mode P60/WAIT P61/BREQ P62/BACK P67/ STBY EXTAL XTAL AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1
FP-100B TFP-100B FP-100A Mode AVSS P80/IRQ0/RFSH P81/IRQ1/CS P82/IRQ2/CS P83/IRQ3/CS ADTRG P84/CS Mode AVSS
Name Mode AVSS P80/IRQ0/RFSH P81/IRQ1/CS P82/IRQ2/CS P83/IRQ3/CS ADTRG P84/CS Mode AVSS P80/IRQ0/RFSH P81/IRQ1/CS P82/IRQ2/CS P83/IRQ3/CS ADTRG P84/CS
P80/IRQ0/RFSH P81/IRQ1/CS P82/IRQ2/CS P83/IRQ3/CS ADTRG P84/CS
PA0/TP0/TCLKA/ PA0/TP0/TCLKA/ PA0/TP0/TCLKA/ PA0/TP0/TCLKA/ TEND0 TEND0 TEND0 TEND0 PA1/TP1/TCLKB/ PA1/TP1/TCLKB/ PA1/TP1/TCLKB/ PA1/TP1/TCLKB/ TEND1 TEND1 TEND1 TEND1 PA2/TP2/TIOCA0/ PA2/TP2/TIOCA0/ PA2/TP2/TIOCA0/ PA2/TP2/TIOCA0/ TCLKC TCLKC TCLKC TCLKC PA3/TP3/TIOCB0/ PA3/TP3/TIOCB0/ PA3/TP3/TIOCB0/ PA3/TP3/TIOCB0/ TCLKD TCLKD TCLKD TCLKD PA4/TP4/TIOCA1 PA4/TP4/TIOCA1 PA4/TP4/TIOCA1/ PA4/TP4/TIOCA1/ PA5/TP5/TIOCB1 PA5/TP5/TIOCB1 PA5/TP5/TIOCB1/ PA5/TP5/TIOCB1/ PA6/TP6/TIOCA2 PA6/TP6/TIOCA2 PA6/TP6/TIOCA2/ PA6/TP6/TIOCA2/ PA7/TP7/TIOCB2 PA7/TP7/TIOCB2
Notes: modes functions pins P40/D0 7/D7 selected after reset, they changed software. modes functions pins P40/D0 7/D7 selected after reset, they changed software.
Section
Overview
H8/300H high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 CPU. H8/300H sixteen 16-bit general registers, address 16-Mbyte linear address space, ideal realtime control. 2.1.1 Features
H8/300H following features. Upward compatibility with H8/300 execute H8/300 Series object programs General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) Sixty-two basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16, ERn) @(d:24, ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8, @(d:16, PC)] Memory indirect [@@aa:8] 16-Mbyte linear address space
High-speed operation frequently-used instructions execute four states Maximum clock frequency: 8/16/32-bit register-register add/subtract: 8-bit register-register multiply: 8-bit register-register divide: 16-bit register-register multiply: 16-bit register-register divide: operating modes Normal mode (not available H8/3006 H8/3007) Advanced mode Low-power mode Transition power-down state SLEEP instruction 2.1.2 Differences from H8/300
comparison H8/300 CPU, H8/300H following enhancements. More general registers Eight 16-bit registers have been added. Expanded address space Advanced mode supports maximum 16-Mbyte address space. Normal mode supports same 64-kbyte address space H8/300 CPU. Enhanced addressing addressing modes have been enhanced make effective 16-Mbyte address space. Enhanced instructions Data transfer, arithmetic, logic instructions operate 32-bit data. Signed multiply/divide instructions other instructions have been added.
Operating Modes
H8/300H operating modes: normal advanced. Normal mode supports maximum 64-kbyte address space. Advanced mode supports Mbytes.
Maximum kbytes, program data areas combined
Normal mode*
operating modes Maximum Mbytes, program data areas combined
Advanced mode
Note: Normal mode available H8/3006 H8/3007.
Figure Operating Modes
Address Space
Figure shows simple memory H8/3006 H8/3007. H8/300H address linear address space with maximum size kbytes normal mode, Mbytes advanced mode. further details section 3.6, Memory Each Operating Mode. 1-Mbyte operating modes 20-bit addressing. upper bits effective addresses ignored.
H'0000 H'FFFF
H'00000
H'000000
H'FFFFF
H'FFFFFF 1-Mbyte mode Normal mode* 16-Mbyte mode Advanced mode
Note: Normal mode available H8/3006 H8/3007.
Figure Memory
2.4.1
Register Configuration
Overview
H8/300H internal registers shown figure 2-3. There types registers: general registers control registers.
General Registers (ERn) Control Registers (CR) Legend Stack pointer Program counter CCR: Condition code register Interrupt mask User interrupt mask Half-carry flag User Negative flag Zero flag Overflow flag Carry flag (SP)
Figure Registers
2.4.2
General Registers
H8/300H eight 32-bit general registers. These general registers functionally alike used without distinction between data registers address registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. Figure illustrates usage general registers. usage each register selected independently.
Address registers 32-bit registers
16-bit registers registers (extended registers)
8-bit registers
registers registers
registers
registers
Figure Usage General Registers
General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Free area (ER7) Stack area
Figure Stack 2.4.3 Control Registers
control registers 24-bit program counter (PC) 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word) multiple bytes, least significant ignored. When instruction fetched, least significant regarded Condition Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. 7-Interrupt Mask (I): Masks interrupts other than when accepted regardless setting. start exception-handling sequence. 6-User Interrupt Mask (UI): written read software using LDC, STC, ANDC, ORC, XORC instructions. This also used interrupt mask bit. details section Interrupt Controller.
5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise. 4-User (U): written read software using LDC, STC, ANDC, ORC, XORC instructions. 3-Negative Flag (N): Stores value most significant data, regarded sign bit. 2-Zero Flag (Z): indicate zero data, cleared indicate non-zero data. 1-Overflow Flag (V): when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): when carry generated execution operation, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions carry flag also used accumulator manipulation instructions. Some instructions leave flag bits unchanged. Operations performed LDC, STC, ANDC, ORC, XORC instructions. flags used conditional branch (Bcc) instructions. action each instruction flag bits, appendix A.1, Instruction List. bits, section Interrupt Controller. 2.4.4 Initial Register Values
reset exception handling, initialized value loaded from vector table, other bits general registers initialized. particular, initial value stack pointer (ER7) also undefined. stack pointer (ER7) must therefore initialized MOV.L instruction executed immediately after reset.
Data Formats
H8/300H process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data. 2.5.1 General Register Data Formats
Figures show data formats general registers.
General Register
Data Type
Data Format Don't care
1-bit data
1-bit data
Don't care
4-bit data
Upper digit Lower digit
Don't care
4-bit data
Don't care
Upper digit Lower digit
Byte data
Don't care
Byte data
Don't care
Legend RnH: General register RnL: General register
Figure General Register Data Formats
Data Type
General Register
Data Format
Word data
Word data
Longword data Legend ERn: General register General register General register MSB: Most significant LSB: Least significant
Figure General Register Data Formats 2.5.2 Memory Data Formats
Figure shows data formats memory. H8/300H access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches.
Data Type
Address
Data Format
1-bit data Byte data Word data Address Address Address Address Address Longword data Address Address Address
Figure Memory Data Formats When (SP) used address register access stack, operand size should word size longword size.
2.6.1
Instruction
Instruction Overview
H8/300H types instructions, which classified table 2-1. Table
Function Data transfer Arithmetic operations Logic operations Shift operations manipulation Branch System control Block data transfer
Instruction Classification
Instruction MOV, PUSH* POP* MOVTPE* MOVFPE*
Types
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc* JMP, BSR, JSR, TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV Total types
Notes: POP.W identical MOV.W @SP+, PUSH.W identical MOV.W @-SP. POP.L identical MOV.L @SP+, PUSH.L identical MOV.L @-SP. available H8/3006 H8/3007. generic branching instruction.
2.6.2
Instructions Addressing Modes
Table indicates instructions available H8/300H CPU. Table Instructions Addressing Modes
Addressing Modes (d:16, ERn) (d:24, ERn) (d:8, (d:16,
Function Data transfer
Instruction POP, PUSH MOVFPE, MOVTPE
@ERn
@ERn+/ @-ERn
aa:8
aa:16
aa:24
aa:8
Arithmetic operations
ADD, ADDX, SUBX ADDS, SUBS INC, DAA, MULXU, MULXS, DIVXU, DIVXS EXTU, EXTS
Logic operations
AND,
Shift instructions manipulation Branch Bcc, JMP, System control TRAPA SLEEP ANDC, ORC, XORC Block data transfer
2.6.3
Tables Instructions Classified Function
Tables 2-10 summarize instructions each functional category. operation notation used these tables defined next. Operation Notation
(EAd) (EAs) #IMM disp :3/:8/:16/:24 Note: General register (destination)* General register (source)* General register* General register (32-bit register address register) Destination operand Source operand Condition code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division logical logical Exclusive logical Move (logical complement) 16-, 24-bit length
General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit data address registers (ER0 ER7).
Table
Data Transfer Instructions
Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register.
Instruction Size* B/W/L
MOVFPE
(EAs) Cannot used this LSI. (EAs) Cannot used this LSI. @SP+ Pops general register from stack. POP.W identical MOV.W @SP+, Similarly, POP.L identical MOV.L @SP+, ERn.
MOVTPE
PUSH
@-SP Pushes general register onto stack. PUSH.W identical MOV.W @-SP. Similarly, PUSH.L identical MOV.L ERn, @-SP.
Note: Size refers operand size. Byte Word Longword
Table
Arithmetic Operation Instructions
Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from data general register. SUBX instruction.)
Instruction Size* ADD,SUB B/W/L
ADDX, SUBX
#IMM Performs addition subtraction with carry borrow data general registers, immediate data data general register.
INC,
B/W/L
Increments decrements general register (Byte operands incremented decremented only.)
ADDS, SUBS DAA,
Adds subtracts value from data 32-bit register. decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4-bit data.
MULXU
Performs unsigned multiplication data general registers: either bits bits bits bits bits bits.
MULXS
Performs signed multiplication data general registers: either bits bits bits bits bits bits.
Instruction Size* DIVXU
Function Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder
DIVXS
Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder, bits bits 16-bit quotient 16-bit remainder
B/W/L
#IMM Compares data general register with data another general register with immediate data, sets according result.
B/W/L
Takes two's complement (arithmetic complement) data general register.
EXTS
(sign extension) Extends byte data lower bits 16-bit register word data, extends word data lower bits 32-bit register longword data, extending sign bit.
EXTU
(zero extension) Extends byte data lower bits 16-bit register word data, extends word data lower bits 32-bit register longword data, padding with zeros.
Note: Size refers operand size. Byte Word Longword
Table
Logic Operation Instructions
Function #IMM Performs logical operation general register another general register immediate data.
Instruction Size* B/W/L
B/W/L
#IMM Performs logical operation general register another general register immediate data.
B/W/L
#IMM Performs logical exclusive operation general register another general register immediate data.
B/W/L
Takes one's complement (logical complement) general register contents.
Note: Size refers operand size. Byte Word Longword
Table
Shift Instructions
Function (shift) Performs arithmetic shift general register contents. B/W/L (shift) Performs logical shift general register contents. B/W/L (rotate) Rotates general register contents. B/W/L (rotate) Rotates general register contents, including carry bit.
Instruction Size* SHAL, SHAR SHLL, SHLR ROTL, ROTR ROTXL, ROTXR B/W/L
Note: Size refers operand size. Byte Word Longword
Table
Manipulation Instructions
Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower bits general register.
Instruction Size* BSET
BCLR
(<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower bits general register.
BNOT
(<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower bits general register.
BTST
(<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower bits general register.
BAND
(<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
BIAND
(<bit-No.> <EAd>)] ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
Instruction Size*
Function (<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
BIOR
(<bit-No.> <EAd>)] carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
BXOR
(<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
BIXOR
(<bit-No.> <EAd>)] Exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
(<bit-No.> <EAd>) Transfers specified general register memory operand carry flag. number specified 3-bit immediate data.
BILD
(<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag. number specified 3-bit immediate data.
(<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand. number specified 3-bit immediate data.
BIST
(<bit-No.> <EAd>) Transfers inverse carry flag value specified general register memory operand. number specified 3-bit immediate data.
Note: Size refers operand size. Byte
Table
Branching Instructions
Function Branches specified address address specified condition met. branching conditions listed below. Mnemonic (BT) (BF) (BHS) (BLO) Description Always (true) Never (false) High same Condition Always Never CZ=0 CZ=1
Instruction Size
Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal NV=0 NV=1
Branches unconditionally specified address Branches subroutine specified address Branches subroutine specified address Returns from subroutine
Table
System Control Instructions
Function Starts trap-instruction exception handling Returns from exception-handling routine Causes transition power-down state (EAs) Moves source operand contents condition code register. condition code register size byte, transfer from memory, data read word access.
Instruction Size* TRAPA SLEEP
(EAd) Transfers contents destination location. condition code register size byte, transfer memory, data written word access.
ANDC
#IMM Logically ANDs condition code register with immediate data. #IMM Logically condition code register with immediate data. #IMM Logically exclusive-ORs condition code register with immediate data. Only increments program counter.
XORC
Note: Size refers operand size. Byte Word
Table 2-10 Block Transfer Instruction
Instruction EEPMOV.B Size Function then repeat @ER5+ @ER6+, until else next; then repeat @ER5+ @ER6+, until else next; Block transfer instruction. This instruction transfers number data bytes specified starting from address indicated ER5, location starting address indicated ER6. transfer, next instruction executed.
EEPMOV.W
2.6.4 Basic Instruction Formats H8/300H instructions consist 2-byte (1-word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Operation Field: Indicates function instruction, addressing mode, operation carried operand. operation field always includes first bits instruction. Some instructions have operation fields. Register Field: Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension: Eight, bits specifying immediate data, absolute address, displacement. 24-bit address displacement treated 32-bit data which first bits (H'00). Condition Field: Specifies branching condition instructions. Figure shows examples instruction formats.
Operation field only Operation field register fields ADD.B etc. NOP, RTS, etc.
Operation field, register fields, effective address extension (disp) Operation field, effective address extension, condition field (disp) MOV.B @(d:16, Rn),
Figure Instruction Formats 2.6.5 Notes Manipulation Instructions
BSET, BCLR, BNOT, BST, BIST instructions read byte data, modify byte, then write byte back. Care required when these instructions used access registers with write-only bits, access ports.
Step Read Modify Write Description Read data byte specified address Modify data byte Write modified data byte back specified address
Example BCLR executed clear port data direction register (P4DDR) under following conditions. Input pins Output pins
intended purpose this BCLR instruction switch from output input.
Before Execution BCLR Instruction
Input/output Input Input Output Output Output Output Output Output
Execution BCLR Instruction BCLR @P4DDR ;Clear data direction register
After Execution BCLR Instruction
Input/output Output Output Output Output Output Output Output Input
Explanation: execute BCLR instruction, begins reading P4DDR. Since P4DDR write-only register, read H'FF, even though true value H'3F. Next clears read data, changing value H'FE. Finally, writes this value (H'FE) back P4DDR complete BCLR instruction. result, P40DDR cleared making input pin. addition, P47DDR P46DDR making output pins. BCLR instruction used clear flags on-chip registers case status register (ISR), example, flag must read condition clearing when using BCLR instruction, known that flag been interrupt-handling routine, instance, necessary read flag ahead time.
2.7.1
Addressing Modes Effective Address Calculation
Addressing Modes
H8/300H supports eight addressing modes listed table 2-11. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except programcounter relative memory indirect. manipulation instructions register direct, register indirect, absolute (@aa:8) addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table 2-11 Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @ERn @(d:16, ERn)/@(d:24, ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8, PC)/@(d:16, @@aa:8
Register Direct-Rn: register field instruction code specifies 16-, 32-bit register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32-bit registers. Register Indirect-@ERn: register field instruction code specifies address register (ERn), lower bits which contain address operand. Register Indirect with Displacement-@(d:16, ERn) @(d:24, ERn): 16-bit 24-bit displacement contained instruction code added contents address register (ERn) specified register field instruction, lower bits specify address memory operand. 16-bit displacement sign-extended when added.
Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn: Register indirect with post-increment-@ERn+ register field instruction code specifies address register (ERn) lower bits which contain address memory operand. After operand accessed, added address register contents bits) stored address register. value added byte access, word access, longword access. word longword access, register value should even. Register indirect with pre-decrement-@-ERn value subtracted from address register (ERn) specified register field instruction code, lower bits result become address memory operand. result also stored address register. value subtracted byte access, word access, longword access. word longword access, resulting register value should even. Absolute Address-@aa:8, @aa:16, @aa:24: instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24). 8-bit absolute address, upper bits assumed (H'FFFF). 16-bit absolute address upper bits sign extension. 24-bit absolute address access entire address space. Table 2-12 indicates accessible address ranges. Table 2-12 Absolute Address Access Ranges
Absolute Address bits (@aa:8) bits (@aa:16) 1-Mbyte Modes H'FFF00 H'FFFFF (1048320 1048575) H'00000 H'07FFF, H'F8000 H'FFFFF 32767, 1015808 1048575) H'00000 H'FFFFF 1048575) 16-Mbyte Modes H'FFFF00 H'FFFFFF (16776960 16777215) H'000000 H'007FFF, H'FF8000 H'FFFFFF 32767, 16744448 16777215) H'000000 H'FFFFFF 16777215)
bits (@aa:24)
Immediate-#xx:8, #xx:16, #xx:32: instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. instruction codes ADDS, SUBS, INC, instructions contain immediate data implicitly. instruction codes some manipulation instructions contain 3-bit immediate data specifying number. TRAPA instruction code contains 2-bit immediate data specifying vector address.
Program-Counter Relative-@(d:8, @(d:16, PC): This mode used instructions. 8-bit 16-bit displacement contained instruction code signextended bits added 24-bit contents generate 24-bit branch address. value which displacement added address first byte next instruction, possible branching range -126 +128 bytes (-63 words) -32766 +32768 bytes (-16383 +16384 words) from branch instruction. resulting value should even number. Memory Indirect-@@aa:8: This mode used instructions. instruction code contains 8-bit absolute address specifying memory operand. This memory operand contains branch address. memory operand accessed longword access. first byte memory operand ignored, generating 24-bit branch address. figure 2-10. upper bits 8-bit absolute address assumed (H'0000), address range (H'000000 H'0000FF). Note that first part this range also exception vector area. further details section Interrupt Controller.
Specified @aa:8
Reserved
Branch address
Figure 2-10 Memory-Indirect Branch Address Specification When word-size longword-size memory operand specified, when branch address specified, specified memory address odd, least significant regarded accessed data instruction code therefore begins preceding address. section 2.5.2, Memory Data Formats. 2.7.2 Effective Address Calculation
Table 2-13 explains effective address calculated each addressing mode. 1-Mbyte operating modes upper bits calculated address ignored order generate 20-bit effective address.
Table 2-13 Effective Address Calculation
Addressing Mode Instruction Format Effective Address Calculation Register direct (Rn) Register indirect (@ERn) General register contents Register indirect with displacement @(d:16, ERn)/@(d:24, ERn) General register contents disp Effective Address Operand general register contents
Sign extension
Register indirect with post-increment @ERn+
Register indirect with post-increment pre-decrement General register contents
General register contents byte operand, word operand, longword operand
Register indirect with pre-decrement @-ERn
Effective Address Calculation H'FFFF Effective Address Operand immediate data
Sign extension
Addressing Mode Instruction Format
Absolute address @aa:8
@aa:16
@aa:24
Immediate #xx:8, #xx:16, #xx:32
Program-counter relative @(d:8, @(d:16,
contents
Sign extension
disp
disp
Addressing Mode Instruction Format Effective Address Calculation
Effective Address
Memory indirect @@aa:8
Normal mode H'0000 Memory contents H'00
Advanced mode H'0000 Memory contents
Legend disp: IMM: abs: Register field Operation field Displacement Immediate data Absolute address
2.8.1
Processing States
Overview
H8/300H five processing states: program execution state, exception-handling state, power-down state, reset state, bus-released state. power-down state includes sleep mode, software standby mode, hardware standby mode. Figure 2-11 classifies processing states. Figure 2-13 indicates state transitions.
Processing states
Program execution state executes program instructions sequence Exception-handling state transient state which executes hardware sequence (saving CCR, fetching vector, etc.) response reset, interrupt, other exception
Bus-released state external been released response request signal from master other than Reset state on-chip supporting modules initialized halted
Power-down state halted conserve power
Sleep mode
Software standby mode
Hardware standby mode
Figure 2-11 Processing States
2.8.2
Program Execution State
this state executes program instructions normal sequence. 2.8.3 Exception-Handling State
exception-handling state transient state that occurs when alters normal program flow reset, interrupt, trap instruction. fetches starting address from exception vector table branches that address. interrupt trap exception handling references stack pointer (ER7) saves program counter condition code register. Types Exception Handling Their Priority: Exception handling performed resets, interrupts, trap instructions. Table 2-14 indicates types exception handling their priority. Trap instruction exceptions accepted times program execution state. Table 2-14 Exception Handling Types Priority
Priority High Type Exception Detection Timing Reset Interrupt Synchronized with clock instruction execution exception handling* Start Exception Handling Exception handling starts immediately when changes from high When interrupt requested, exception handling starts current instruction current exception-handling sequence
Trap instruction
When TRAPA instruction Exception handling starts when trap executed (TRAPA) instruction executed
Note: Interrupts detected ANDC, ORC, XORC, instructions, immediately after reset exception handling.
Figure 2-12 classifies exception sources. further details about exception sources, vector numbers, vector addresses, section Exception Handling, section Interrupt Controller.
Reset External interrupts Exception sources Interrupt Internal interrupts (from on-chip supporting modules) Trap instruction
Figure 2-12 Classification Exception Sources
request release Program execution state release request Exception handling source Bus-released state exception handling Exception-handling state
SLEEP instruction with SSBY Sleep mode
Interrupt source NMI, interrupt
SLEEP instruction with SSBY
Software standby mode
High STBY High,
Reset state
Hardware standby mode Power-down state
Notes: From state except hardware standby mode, transition reset state occurs whenever goes low. From state, transition hardware standby mode occurs when STBY goes low.
Figure 2-13 State Transitions
2.8.4
Exception-Handling Sequences
Reset Exception Handling: Reset exception handling highest priority. reset state entered when signal goes low. Reset exception handling starts after that, when changes from high. When reset exception handling starts fetches start address from exception vector table starts program execution from that address. interrupts, including NMI, disabled during reset exception-handling sequence immediately after ends. Interrupt Exception Handling Trap Instruction Exception Handling: When these exception-handling sequences begin, references stack pointer (ER7) pushes program counter condition code register stack. Next, system control register (SYSCR) sets condition code register cleared sets both condition code register Then fetches start address from exception vector table execution branches that address. Figure 2-14 shows stack after exception-handling sequence.
SP-4 SP-3 SP-2 SP-1 (ER7) Stack area
(ER7) SP+1 SP+2 SP+3 SP+4
Even address
Before exception handling starts Legend CCR: Condition code register Stack pointer
Pushed stack
After exception handling ends
Notes: address first instruction executed after return from exception-handling routine. Registers must saved restored word access longword access, starting even address.
Figure 2-14 Stack Structure after Exception Handling
2.8.5
Bus-Released State
this state released master other than CPU, response request. masters other than controller, DRAM interface, external master. While released, halts except internal operations. Interrupt requests accepted. details section 6.10, Arbiter. 2.8.6 Reset State
When input goes current processing stops enters reset state. condition code register reset. interrupts masked reset state. Reset exception handling starts when signal changes from high. reset state also entered watchdog timer overflow. details section Watchdog Timer. 2.8.7 Power-Down State
power-down state stops operating conserve power. There three modes: sleep mode, software standby mode, hardware standby mode. Sleep Mode: transition sleep mode made SLEEP instruction executed while SSBY cleared system control register (SYSCR). operations stop immediately after execution SLEEP instruction, contents registers retained. Software Standby Mode: transition software standby mode made SLEEP instruction executed while SSBY SYSCR. clock halt on-chip supporting modules stop operating. on-chip supporting modules reset, long specified voltage supplied contents registers on-chip retained. ports also remain their existing states. Hardware Standby Mode: transition hardware standby mode made when STBY input goes low. software standby mode, clocks halt on-chip supporting modules reset, long specified voltage supplied, on-chip contents retained. further information section Power-Down State.
2.9.1
Basic Operational Timing
Overview
H8/300H operates according system clock interval from rise system clock next rise referred "state." memory cycle cycle consists three states. uses different methods access on-chip memory, on-chip supporting modules, external address space. Access external address space controlled controller. 2.9.2 On-Chip Memory Access Timing
On-chip memory accessed states. data bits wide, permitting both byte word access. Figure 2-15 shows on-chip memory access cycle. Figure 2-16 indicates states.
cycle state Internal address Internal read signal Internal data (read access) Internal write signal Internal data (write access) Write data Read data Address state
Figure 2-15 On-Chip Memory Access Cycle
Address Address
High High impedance
Figure 2-16 States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing
on-chip supporting modules accessed three states. data bits wide, depending internal register being accessed. Figure 2-17 shows on-chip supporting module access timing. Figure 2-18 indicates states.
cycle state Address Internal read signal Internal data Address state state
Read access
Read data
Internal write signal Write access Internal data Write data
Figure 2-17 Access Cycle On-Chip Supporting Modules
Address
Address
High High impedance
Figure 2-18 States during Access On-Chip Supporting Modules 2.9.4 Access External Address Space
external address space divided into eight areas (areas Bus-controller settings determine whether each area accessed 8-bit 16-bit bus, whether accessed three states. details section Controller.
Section Operating Modes
3.1.1
Overview
Operating Mode Selection
H8/3006 H8/3007 have four operating modes (modes that selected mode pins (MD2 MD0) indicated table 3-1. input these pins determines size address space initial mode. Table Operating Mode Selection
Description Operating Mode Mode Mode Mode Mode Mode Pins Address Space Setting prohibited Mbyte Mbyte Mbytes Mbytes Initial Mode*1 Setting prohibited bits bits bits bits On-Chip Setting prohibited Enabled* Enabled* Enabled* Enabled*
Notes: modes 8-bit 16-bit data selected per-area basis settings made area width control register (ABWCR). details section Controller. RAME SYSCR cleared these addresses become external addresses.
address space size there choices: Mbyte, Mbyte.The external data either bits wide depending ABWCR settings. 8-bit access selected areas, 8bit mode used. details section Controller. Modes support maximum address space Mbyte. Modes support maximum address space Mbytes. H8/3006 H8/3007 used only modes inputs mode pins must select these four modes. inputs mode pins must changed during operation. When changing mode, chip must placed reset state before mode inputs changed.
3.1.2
Register Configuration
H8/3006 H8/3007 have mode control register (MDCR) that indicates inputs mode pins (MD2 MD0), system control register (SYSCR). Table summarizes these registers. Table
Address* H'EE011 H'EE012 Note:
Registers
Name Mode control register System control register Abbreviation MDCR SYSCR Initial Value Undetermined H'09
Lower bits address advanced mode.
Mode Control Register (MDCR)
MDCR 8-bit read-only register that indicates current operating mode H8/3006 H8/3007.
Initial value Read/Write Reserved bits MDS2 MDS1 MDS0
Mode select Bits indicating current operating mode
Note: Determined pins
Bits 6-Reserved: These bits modified always read Bits 3-Reserved: These bits modified always read Bits 0-Mode Select (MDS2 MDS0): These bits indicate logic levels pins (the current operating mode). MDS2 MDS0 correspond MD0. MDS2 MDS0 read-only bits. mode MD0) levels latched into these bits when MDCR read.
System Control Register (SYSCR)
SYSCR 8-bit register that controls operation H8/3006 H8/3007.
Initial value Read/Write SSBY STS2 STS1 STS0 NMIEG SSOE RAME enable Enables disables on-chip Software standby output port enable Selects output state address control signals software standby mode edge select Selects valid edge input User enable Selects whether user interrupt mask Standby timer select These bits select waiting time recovery from software standby mode Software standby Enables transition software standby mode
7-Software Standby (SSBY): Enables transition software standby mode. (For further information about software standby mode section Power-Down State.) When software standby mode exited external interrupt transition made normal operation, this remains clear this bit, write
SSBY Description SLEEP instruction causes transition sleep mode SLEEP instruction causes transition software standby mode (Initial value)
Bits 4-Standby Timer Select (STS2 STS0): These bits select length time on-chip supporting modules wait internal clock oscillator settle when software standby mode exited external interrupt. When using crystal oscillator, these bits that waiting time will least system clock rate. further information about waiting time selection, section 19.4.3, Selection Waiting Time Exit from Software Standby Mode.
STS2 STS1 STS0 Description Waiting time 8,192 states Waiting time 16,384 states Waiting time 32,768 states Waiting time 65,536 states Waiting time 131,072 states Waiting time 262,144 states Waiting time 1,024 states Illegal setting (Initial value)
3-User Enable (UE): Selects whether condition code register user interrupt mask bit.
Description used interrupt mask used user (Initial value)
2-NMI Edge Select (NMIEG): Selects valid edge input.
NMIEG Description interrupt requested falling edge interrupt requested rising edge (Initial value)
1-Software Standby Output Port Enable (SSOE): Specifies whether address control signals (CS0 CS7, HWR, LWR, UCAS, LCAS, RFSH) kept outputs fixed high, placed high-impedance state software standby mode.
SSOE Description software standby mode, address control signals highimpedance (Initial value) software standby mode, address retains output state control signals fixed high
0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized rising edge signal. initialized software standby mode.
RAME Description On-chip disabled On-chip enabled (Initial value)
3.4.1
Operating Mode Descriptions
Mode
maximum 1-Mbyte address space accessed. initial mode after reset bits, with 8-bit access areas. least area designated 16-bit access ABWCR, mode switches bits. 3.4.2 Mode
maximum 1-Mbyte address space accessed. initial mode after reset bits, with 16-bit access areas. areas designated 8-bit access ABWCR, mode switches bits. 3.4.3 Mode
Part port function address pins A20, permitting access maximum 16-Mbyte address space. initial mode after reset bits, with 8-bit access areas. least area designated 16-bit access ABWCR, mode switches bits. valid when written bits release control register (BRCR). this mode always used address output.) 3.4.4 Mode
Part port function address pins A20, permitting access maximum 16-Mbyte address space. initial mode after reset bits, with 16-bit access areas. areas designated 8-bit access ABWCR, mode switches bits. valid when written bits BRCR. this mode always used address output.)
Functions Each Operating Mode
functions port port vary depending operating mode. Table indicates their functions each operating mode. Table Functions Each Mode
Port Port Port Mode
Mode
Mode
Mode
Notes: Initial state. mode switched settings ABWCR. These pins function 8-bit mode, 16-bit mode. Initial state. always address output pin. switched over output writing bits BRCR.
Memory Each Operating Mode
Figure 3-1, show memory maps H8/3006 H8/3007. address space divided into eight areas. initial mode differs between modes also between modes address locations on-chip internal registers differ between 1-Mbyte modes (modes 16-Mbyte modes (modes address range specifiable 16-bit absolute addressing modes (@aa:8 @aa:16) also differs. 3.6.1 Note Reserved Areas
memory H8/3006 H8/3007 includes reserved areas which read/write access prohibited. Note that normal operation guaranteed following reserved areas accessed. internal register space H8/3006 H8/3007 includes reserved area which access prohibited. details, Appendix Internal Registers.
Modes Mbyte) Memory-indirect branch addresses H'00000 Vector area H'000FF H'000000 16-bit absolute addresses
Modes Mbytes) Memory-indirect branch addresses Area H'1FFFFF H'200000 Area H'3FFFFF H'400000 Area H'5FFFFF H'600000 H'7FFFFF H'800000 H'9FFFFF H'A00000 Area 8-bit absolute addresses 16-bit absolute addresses H'BFFFFF H'C00000 Area H'DFFFFF H'E00000 H'FEE000 H'FEE0FF H'FF8000 H'FFEF1F H'FFEF20 H'FFFF00 H'FFFF1F H'FFFF20 H'FFFFE9 H'FFFFEA H'FFFFFF 8-bit absolute addresses On-chip RAM*
External address space
Vector area H'0000FF
H'07FFF
H'007FFF
H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 H'EE0FF H'F8000 H'FEF1F H'FEF20 H'FFF00 H'FFF1F H'FFF20 H'FFFE9 H'FFFEA H'FFFFF Internal registers External address space Internal registers
External address space
Area Area Area Area Area Area Area Area External address space
Area
Area
On-chip RAM*
Area Internal registers
Internal registers External address space
Note: External addresses accessed disabling on-chip RAM.
Figure H8/3007 Memory Each Operating Mode
16-bit absolute addresses
16-bit absolute addresses
Modes Mbyte) Memory-indirect branch addresses H'00000 Vector area H'000FF H'000000 16-bit absolute addresses
Modes Mbytes) Memory-indirect branch addresses Area H'1FFFFF H'200000 Area H'3FFFFF H'400000 Area H'5FFFFF H'600000 H'7FFFFF H'800000 H'9FFFFF H'A00000 Area 16-bit absolute addresses H'BFFFFF H'C00000 Area H'DFFFFF H'E00000 H'FEE000 H'FEE0FF H'FF8000
External address space
Vector area H'0000FF
H'07FFF
H'007FFF
H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 H'EE0FF H'F8000 Internal registers
External address space
Area Area Area Area Area Area Area Area External address space
Area
Area
On-chip RAM* Internal registers External address space
H'FFF1F H'FFF20 H'FFFE9 H'FFFEA H'FFFFF
8-bit absolute addresses
H'FF71F H'FF720 H'FFF00
Area Internal registers
H'FFFF1F H'FFFF20 H'FFFFE9 H'FFFFEA
On-chip RAM* Internal registers External address space
H'FFFFFF Note: External addresses accessed disabling on-chip RAM.
Figure H8/3006 Memory Each Operating Mode
16-bit absolute addresses
8-bit absolute addresses
H'FFF71F H'FFF720 H'FFFF00
16-bit absolute addresses
Section Exception Handling
4.1.1
Overview
Exception Handling Types Priority
table indicates, exception handling caused reset, interrupt, trap instruction. Exception handling prioritized shown table 4-1. more exceptions occur simultaneously, they accepted processed priority order. Trap instruction exceptions accepted times program execution state. Table Exception Types Priority
Start Exception Handling Starts immediately after low-to-high transition Interrupt requests handled when execution current instruction handling current exception completed
Priority Exception Type High Reset Interrupt
Trap instruction (TRAPA) Started execution trap instruction (TRAPA)
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions interrupts handled follows. program counter (PC) condition code register (CCR) pushed onto stack. interrupt mask vector address corresponding exception source generated, program execution starts from that address. Note: reset exception, steps above carried out.
4.1.3
Exception Vector Table
exception sources classified shown figure 4-1. Different vectors assigned different exception sources. Table lists exception sources their vector addresses.
Reset External interrupts: NMI, IRQ5 Exception sources Interrupts Internal interrupts: interrupts from on-chip supporting modules
Trap instruction
Figure Exception Sources
Table
Exception Vector Table
Vector Address*1
Exception Source Reset Reserved system
Vector Number
Advanced Mode H'0000 H'0003 H'0004 H'0007 H'0008 H'000B H'000C H'000F H'0010 H'0013 H'0014 H'0017 H'0018 H'001B H'001C H'001F H'0020 H'0023 H'0024 H'0027 H'0028 H'002B H'002C H'002F H'0030 H'0033 H'0034 H'0037 H'0038 H'003B H'003C H'003F H'0040 H'0043 H'0044 H'0047 H'0048 H'004B H'004C H'004F H'0050 H'0053 H'00FC H'00FF
Normal Mode*3 H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B H'000C H'000D H'000E H'000F H'0010 H'0011 H'0012 H'0013 H'0014 H'0015 H'0016 H'0017 H'0018 H'0019 H'001A H'001B H'001C H'001D H'001E H'001F H'0020 H'0021 H'0022 H'0023 H'0024 H'0025 H'0026 H'0027 H'0028 H'0029 H'007E H'007F
External interrupt (NMI) Trap instruction sources)
External interrupt IRQ0 External interrupt IRQ1 External interrupt IRQ2 External interrupt IRQ3 External interrupt IRQ4 External interrupt IRQ5 Reserved system
Internal interrupts*2
Notes: Lower bits address. internal interrupt vectors, section 5.3.3, Interrupt Vector Table. Normal mode available H8/3006 H8/3007.
Reset
4.2.1 Overview reset highest-priority exception. When goes low, processing halts chip enters reset state. reset initializes internal state registers on-chip supporting modules. Reset exception handling begins when changes from high. chip also reset overflow watchdog timer. details section Watchdog Timer. 4.2.2 Reset Sequence chip enters reset state when goes low. ensure that chip properly reset, hold last power-up. reset chip during operation, hold least system clock cycles. appendix D.2, States Reset, states pins reset state. When goes high after being held necessary time, chip starts reset exception handling follows. internal state registers on-chip supporting modules initialized, CCR. contents reset vector address (H'0000 H'0003) read, program execution starts from address indicated vector address. Figure shows reset sequence modes Figure shows reset sequence modes
Vector fetch
Internal processing
Prefetch first program instruction
Address
High
Figure Reset Sequence (Modes
(10)
(1), (3), (5), (2), (4), (6), (10)
Address reset vector: H'000000, H'000001, H'000002, H'000003 Start address (contents reset exception handling vector address) Start address First instruction program
Note: After reset, wait-state controller inserts three wait states every cycle.
Vector fetch
Internal processing
Prefetch first program instruction
Address
High
(1), (2),
Address reset vector: H'000000, H'000002 Start address (contents reset exception handling vector address) Start address First instruction program
Note: After reset, wait-state controller inserts three wait states every cycle.
Figure Reset Sequence (Modes 4.2.3 Interrupts after Reset
interrupt accepted after reset before stack pointer (SP) initialized, will saved correctly, leading program crash. prevent this, interrupt requests, including NMI, disabled immediately after reset. first instruction program always executed immediately after reset state ends. This instruction should initialize stack pointer (example: MOV.L #xx:32, SP).
Interrupts
Interrupt exception handling requested seven external sources (NMI, IRQ0 IRQ5), internal sources on-chip supporting modules. Figure classifies interrupt sources indicates number interrupts each type. on-chip supporting modules that request interrupts watchdog timer (WDT), DRAM interface, 16-bit timer, 8-bit timer, controller (DMAC), serial communication interface (SCI), converter. Each interrupt source separate vector address. highest-priority interrupt always accepted. Interrupts controlled interrupt controller. interrupt controller assign interrupts other than priority levels, arbitrate between simultaneous interrupts. Interrupt priorities assigned interrupt priority registers (IPRA IPRB) interrupt controller. details interrupts section Interrupt Controller.
DRAM interface*2 16-bit timer 8-bit timer DMAC (12) converter
External interrupts Interrupts
Internal interrupts
Notes: Numbers parentheses number interrupt sources. When watchdog timer used interval timer, generates interrupt request every counter overflow. When DRAM interface used interval timer, generates interrupt request compare match.
Figure Interrupt Sources Number Interrupts
Trap Instruction
Trap instruction exception handling starts when TRAPA instruction executed. system control register (SYSCR), exception handling sequence sets CCR. bits both TRAPA instruction fetches start address from vector table entry corresponding vector number from which specified instruction code.
Stack Status after Exception Handling
Figure shows stack after completion trap instruction exception handling interrupt exception handling.
SP-4 SP-3 SP-2 SP-1 (ER7)
Stack area
(ER7) SP+1 SP+2 SP+3 SP+4
Even address
Before exception handling Pushed stack Legend PCE: Bits program counter (PC) PCH: Bits program counter (PC) PCL: Bits program counter (PC) CCR: Condition code register Stack pointer
After exception handling
Notes: indicates address first instruction that will executed after return. Registers must saved word longword size even addresses.
Figure Stack after Completion Exception Handling
Notes Stack Usage
When accessing word data longword data, H8/3006 H8/3007 regards lowest address stack should always accessed word access longword access, value stack pointer (SP: ER7) should always kept even. following instructions save registers: PUSH.W PUSH.L (MOV.W @-SP) (MOV.L ERn, @-SP)
following instructions restore registers: POP.W POP.L
(MOV.W @SP+, (MOV.L @SP+, ERn)
Setting value lead malfunction. Figure shows example what happens when value odd.
H'FFFEFA H'FFFEFB
H'FFFEFC H'FFFEFD
H'FFFEFF
TRAPA instruction executed
MOV. R1L, @-ER7
H'FFFEFF Legend CCR: Condition code register Program counter R1L: General register Stack pointer
Data saved above
contents lost
Note: diagram illustrates modes
Figure Operation when Value
Section Interrupt Controller
5.1.1
Overview
Features
interrupt controller following features: Interrupt priority registers (IPRs) setting interrupt priorities Interrupts other than assigned priority levels module-by-module basis interrupt priority registers (IPRA IPRB). Three-level enable/disable state setting possible means bits CPU's condition code register (CCR) system control register (SYSCR) Seven external interrupt pins highest priority always accepted; either rising falling edge selected. each IRQ0 IRQ5, sensing falling edge level sensing selected independently.
5.1.2
Block Diagram
Figure shows block diagram interrupt controller.
ISCR input input TEIE input section Priority decision logic IPRA, IPRB
Interrupt request Vector number
Interrupt controller SYSCR Legend ISCR: IER: ISR: IPRA: IPRB: SYSCR: sense control register enable register status register Interrupt priority register Interrupt priority register System control register
Figure Interrupt Controller Block Diagram
5.1.3
Configuration
Table lists interrupt pins. Table
Name Nonmaskable interrupt External interrupt request
Interrupt Pins
Abbreviation IRQ5 IRQ0 Function
Input Nonmaskable interrupt, rising edge falling edge selectable Input Maskable interrupts, falling edge level sensing selectable
5.1.4
Register Configuration
Table lists registers interrupt controller. Table
Address* H'EE012 H'EE014 H'EE015 H'EE016 H'EE018 H'EE019
Interrupt Controller Registers
Name System control register sense control register enable register status register Interrupt priority register Interrupt priority register Abbreviation SYSCR ISCR IPRA IPRB R/(W)*
Initial Value H'09 H'00 H'00 H'00 H'00 H'00
Notes: Lower bits address advanced mode. Only written, clear flags.
5.2.1
Register Descriptions
System Control Register (SYSCR)
SYSCR 8-bit readable/writable register that controls software standby mode, selects action CCR, selects edge, enables disables on-chip RAM. Only bits described here. other bits, section 3.3, System Control Register (SYSCR). SYSCR initialized H'09 reset hardware standby mode. initialized software standby mode.
Initial value Read/Write SSBY STS2 STS1 STS0 NMIEG SSOE RAME
enable Software standby output port enable Standby timer select Software standby edge select Selects input edge User enable Selects whether user interrupt mask
3-User Enable (UE): Selects whether user interrupt mask bit.
Description used interrupt mask used user (Initial value)
2-NMI Edge Select (NMIEG): Selects input edge.
NMIEG Description Interrupt requested falling edge input Interrupt requested rising edge input (Initial value)
5.2.2
Interrupt Priority Registers (IPRA, IPRB)
IPRA IPRB 8-bit readable/writable registers that control interrupt priority.
Interrupt Priority Register (IPRA): IPRA 8-bit readable/writable register which interrupt priority levels set.
Initial value Read/Write IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0
Priority level Selects priority level 16-bit timer channel interrupt requests Priority level Selects priority level 16-bit timer channel interrupt requests Priority level Selects priority level 16-bit timer channel interrupt requests Priority level Selects priority level WDT, DRAM interface, converter interrupt requests Priority level Selects priority level IRQ4 interrupt requests Priority level Selects priority level interrupt requests Priority level Selects priority level IRQ1 interrupt requests Priority level Selects priority level interrupt requests
IPRA initialized H'00 reset hardware standby mode.
7-Priority Level (IPRA7): Selects priority level interrupt requests.
IPRA7 Description IRQ0 interrupt requests have priority level (low priority) IRQ0 interrupt requests have priority level (high priority) (Initial value)
6-Priority Level (IPRA6): Selects priority level interrupt requests.
IPRA6 Description IRQ1 interrupt requests have priority level (low priority) IRQ1 interrupt requests have priority level (high priority) (Initial value)
5-Priority Level (IPRA5): Selects priority level interrupt requests.
IPRA5 Description IRQ2 IRQ3 interrupt requests have priority level (low priority) IRQ2 IRQ3 interrupt requests have priority level (high priority) (Initial value)
4-Priority Level (IPRA4): Selects priority level interrupt requests.
IPRA4 Description IRQ4 IRQ5 interrupt requests have priority level (low priority) IRQ4 IRQ5 interrupt requests have priority level (high priority) (Initial value)
3-Priority Level (IPRA3): Selects priority level WDT, DRAM interface, converter interrupt requests.
IPRA3 Description WDT, DRAM interface, converter interrupt requests have priority level (low priority) (Initial value) WDT, DRAM interface, converter interrupt requests have priority level (high priority)
2-Priority Level (IPRA2): Selects priority level 16-bit timer channel interrupt requests.
IPRA2 Description 16-bit timer channel interrupt requests have priority level (low priority) (Initial value) 16-bit timer channel interrupt requests have priority level (high priority)
1-Priority Level (IPRA1): Selects priority level 16-bit timer channel interrupt requests.
IPRA1 Description 16-bit timer channel interrupt requests have priority level (low priority) (Initial value) 16-bit timer channel interrupt requests have priority level (high priority)
0-Priority Level (IPRA0): Selects priority level 16-bit timer channel interrupt requests.
IPRA0 Description 16-bit timer channel interrupt requests have priority level (low priority) (Initial value) 16-bit timer channel interrupt requests have priority level (high priority)
Interrupt Priority Register (IPRB): IPRB 8-bit readable/writable register which interrupt priority levels set.
Initial value Read/Write IPRB7 IPRB6 IPRB5 IPRB3 IPRB2 IPRB1
Reserved Priority level Selects priority level channel interrupt requests Priority level Selects priority level channel interrupt requests Priority level Selects priority level channel interrupt requests Reserved
Priority level Selects priority level DMAC interrupt requests (channels Priority level Selects priority level 8-bit timer channel interrupt requests Priority level Selects priority level 8-bit timer channel interrupt requests
IPRB initialized H'00 reset hardware standby mode.
7-Priority Level (IPRB7): Selects priority level 8-bit timer channel interrupt requests.
IPRB7 Description 8-bit timer channel interrupt requests have priority level (low priority)(Initial value) 8-bit timer channel interrupt requests have priority level (high priority)
6-Priority Level (IPRB6): Selects priority level 8-bit timer channel interrupt requests.
IPRB6 Description 8-bit timer channel interrupt requests have priority level (low priority)(Initial value) 8-bit timer channel interrupt requests have priority level (high priority)
5-Priority Level (IPRB5): Selects priority level DMAC interrupt requests (channels
IPRB5 Description DMAC interrupt requests (channels have priority level (low priority) (Initial value)
DMAC interrupt requests (channels have priority level (high priority)
4-Reserved: This written read, does affect interrupt priority.
3-Priority Level (IPRB3): Selects priority level channel interrupt requests.
IPRB3 Description SCI0 interrupt requests have priority level (low priority) SCI0 interrupt requests have priority level (high priority) (Initial value)
2-Priority Level (IPRB2): Selects priority level channel interrupt requests.
IPRB2 Description SCI1 interrupt requests have priority level (low priority) SCI1 interrupt requests have priority level (high priority) (Initial value)
1-Priority Level (IPRB1): Selects priority level channel interrupt requests.
IPRB1 Description channel interrupt requests have priority level (low priority) channel interrupt requests have priority level (high priority) (Initial value)
0-Reserved: This written read, does affect interrupt priority.
5.2.3
Status Register (ISR)
8-bit readable/writable register that indicates status IRQ0 IRQ5 interrupt requests.
Initial value Read/Write IRQ5F R/(W)* IRQ4F R/(W)* IRQ3F R/(W)* IRQ2F R/(W)* IRQ1F R/(W)* IRQ0F R/(W)*
Reserved bits
IRQ0 flags These bits indicate interrupt request status
Note: Only written, clear flags.
initialized H'00 reset hardware standby mode. Bits 6-Reserved: These bits modified always read Bits 0-IRQ5 IRQ0 Flags (IRQ5F IRQ0F): These bits indicate status IRQ5 IRQ0 interrupt requests.
Bits IRQ5F IRQ0F Description [Clearing conditions] Note: (Initial value)
written IRQnF after reading IRQnF flag when IRQnF IRQnSC IRQn input high, interrupt exception handling carried out. IRQnSC IRQn interrupt exception handling carried out. IRQnSC IRQn input low. IRQnSC IRQn input changes from high low.
[Setting conditions]
5.2.4
Enable Register (IER)
8-bit readable/writable register that enables disables IRQ0 IRQ5 interrupt requests.
Initial value Read/Write IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
Reserved bits
IRQ0 enable These bits enable disable interrupts
initialized H'00 reset hardware standby mode. Bits 6-Reserved: These bits written read, they enable disable interrupts. Bits 0-IRQ5 IRQ0 Enable (IRQ5E IRQ0E): These bits enable disable IRQ5 IRQ0 interrupts.
Bits IRQ5E IRQ0E Description IRQ5 interrupts disabled IRQ5 interrupts enabled (Initial value)
5.2.5
Sense Control Register (ISCR)
ISCR 8-bit readable/writable register that selects level sensing falling-edge sensing inputs pins IRQ5 IRQ0.
Initial value Read/Write
IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
Reserved bits
IRQ0 sense control These bits select level sensing falling-edge sensing interrupts
ISCR initialized H'00 reset hardware standby mode. Bits 6-Reserved: These bits written read, they select level falling-edge sensing. Bits 0-IRQ5 IRQ0 Sense Control (IRQ5SC IRQ0SC): These bits select whether interrupts IRQ5 IRQ0 requested level sensing pins IRQ5 IRQ0, falling-edge sensing.
Bits IRQ5SC IRQ0SC Description Interrupts requested when IRQ5 IRQ0 inputs Interrupts requested falling-edge input IRQ5 IRQ0 (Initial value)
Interrupt Sources
interrupt sources include external interrupts (NMI, IRQ0 IRQ5) internal interrupts. 5.3.1 External Interrupts
There seven external interrupts: NMI, IRQ0 IRQ5. these, NMI, IRQ0, IRQ1, IRQ2 used exit software standby mode. NMI: highest-priority interrupt always accepted, regardless states bits CCR. NMIEG SYSCR selects whether interrupt requested rising falling edge input pin. interrupt exception handling vector number IRQ0 IRQ5 Interrupts: These interrupts requested input signals pins IRQ0 IRQ5. IRQ0 IRQ5 interrupts have following features. ISCR settings select whether interrupt requested level input pins IRQ0 IRQ5, falling edge. settings enable disable IRQ0 IRQ5 interrupts. Interrupt priority levels assigned four bits IPRA (IPRA7 IPRA4). status IRQ0 IRQ5 interrupt requests indicated ISR. flags cleared software. Figure shows block diagram interrupts IRQ0 IRQ5.
IRQnSC IRQnF Edge/level sense circuit IRQn input Clear signal Note: IRQn interrupt request IRQnE
Figure Block Diagram Interrupts IRQ5
Figure shows timing setting interrupt flags (IRQnF).
IRQn input IRQnF
Note:
Figure Timing Setting IRQnF Interrupts IRQ5 have vector numbers These interrupts detected regardless whether corresponding input output. When using external interrupt input, clear chip select output, refresh output, input/output, external trigger input. 5.3.2 Internal Interrupts
Thirty-Six internal interrupts requested from on-chip supporting modules. Each on-chip supporting module status flags indicating interrupt status, enable bits enabling disabling interrupts. Interrupt priority levels assigned IPRA IPRB. 16-bit timer, SCI, converter interrupt requests activate DMAC, which case interrupt request sent interrupt controller, bits disregarded. 5.3.3 Interrupt Vector Table
Table lists interrupt sources, their vector addresses, their default priority order. default priority order, smaller vector numbers have higher priority. priority interrupts other than changed IPRA IPRB. priority order after reset default order shown table 5-3.
Table
Interrupt Sources, Vector Addresses, Priority
Vector Address*
Interrupt Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved WOVI (interval timer) (compare match) Reserved (A/D end) IMIA0 (compare match/ input capture IMIB0 (compare match/ input capture OVI0 (overflow Reserved IMIA1 (compare match/ inputcapture IMIB1 (compare match/ input capture OVI1 (overflow Reserved
Origin External pins
Vector Number
Advanced Mode H'001C H'001F H'0030 H'0033 H'0034 H0037 H'0038 H'003B H'003C H'003F H'0040 H'0043 H'0044 H'0047 H'0048 H'004B H'004C H'004F H'0050 H'0053 H'0054 H'0057 H'0058 H'005B H'005E H'005F H'0060 H'0063
IPRA7 IPRA6 IPRA5 IPRA4
Priority High
Watchdog timer DRAM interface 16-bit timer channel
IPRA3
IPRA2
H'0064 H'0067
16-bit timer channel
H'0068 H'006B H'006C H'006F H'0070 H'0073 IPRA1
H'0074 H'0077
H'0078 H'007B H'007C H'007F
Vector Address* Interrupt Source IMIA2 (compare match/ input capture IMIB2 (compare match/ input capture OVI2 (overflow Reserved CMIA0 (compare match CMIB0 (compare match CMIA1/CMIB1 (compare match A1/B1) TOVI0/TOVI1 (overflow 0/1) CMIA2 (compare match CMIB2 (compare match CMIA3/CMIB3 (compare match A3/B3) TOVI2/TOVI3 (overflow 2/3) DEND0A DEND0B DEND1A DEND1B Reserved Origin 16-bit timer channel Vector Number Advanced Mode H'0080 H'0083 IPRA0 Priority High
H'0084 H'0087
8-bit timer channel
H'0088 H'008B H'008C H'008F H'0090 H'0093 IPRB7
H'0094 H'0097
H'0098 H'009B
8-bit timer channel
H'009C H'009F H'00A0 H'00A3 IPRB6
H'00A4 H'00A7
H'00A8 H'00AB
DMAC
H'00AC H'00AF H'00B0 H'00B3 H'00B4 H'00B7 H'00B8 H'00BB H'00BC H'00BF H'00C0 H'00C3 H'00C4 H'00C7 H'00C8 H'00CB H'00CC H'00CF IPRB5
Vector Address* Interrupt Source ERI0 (receive error RXI0 (receive data full TXI0 (transmit data empty TEI0 (transmit ERI1 (receive error RXI1 (receive data full TXI1 (transmit data empty TEI1 (transmit ERI2 (receive error RXI2 (receive data full TXI2 (transmit data empty TEI2 (transmit Note: Origin channel Vector Number channel channel Advanced Mode H'00D0 H'00D3 H'00D4 H'00D7 H'00D8 H'00DB H'00DC H'00DF H'00E0 H'00E3 H'00E4 H'00E7 H'00E8 H'00EB H'00EC H'00EF H'00F0 H'00F3 H'00F4 H'00F7 H'00F8 H'00FB H'00FC H'00FF IPRB1 IPRB2 IPRB3 Priority High
Lower bits address.
5.4.1
Interrupt Operation
Interrupt Handling Process
H8/3006 H8/3007 handles interrupts differently depending setting bit. When interrupts controlled bit. When interrupts controlled bits. Table indicates interrupts handled setting combinations bits. interrupts always accepted except reset hardware standby states. interrupts interrupts from on-chip supporting modules have their enable bits. Interrupt requests ignored when enable bits cleared Table
SYSCR
Settings Interrupt Handling
Description interrupts accepted. Interrupts with priority level have higher priority. interrupts accepted except NMI. interrupts accepted. Interrupts with priority level have higher priority. interrupts with priority level accepted.
interrupts accepted except NMI.
Interrupts IRQ0 IRQ5 interrupts from on-chip supporting modules masked CPU's CCR. Interrupts masked when unmasked when cleared Interrupts with priority level have higher priority. Figure flowchart showing interrupts accepted when
Program execution state
Interrupt requested? Priority level Pending
IRQ0
IRQ0
IRQ1
IRQ1
TEI2
TEI2
Save Read vector address Branch interrupt service routine
Figure Process Interrupt Acceptance when
interrupt condition occurs corresponding interrupt enable interrupt request sent interrupt controller. When interrupt controller receives more interrupt requests, selects highestpriority request, following interrupt priority settings, holds other requests pending. more interrupts with same setting requested simultaneously, interrupt controller follows priority order shown table 5-3. interrupt controller checks bit. cleared selected interrupt request accepted. only accepted; other interrupt requests held pending. When interrupt request accepted, interrupt exception handling starts after execution current instruction been completed. interrupt exception handling, saved stack area. value that saved indicates address first instruction that will executed after return from interrupt service routine. Next CCR, masking interrupts except NMI. vector address accepted interrupt generated, interrupt service routine starts executing from address indicated contents vector address. bits CPU's bits enable three-level masking IRQ0 IRQ5 interrupts interrupts from on-chip supporting modules. Interrupt requests with priority level masked when unmasked when cleared Interrupt requests with priority level masked when bits both unmasked when either cleared example, interrupt enable bits interrupt requests IPRA H'20, IPRB H'00 (giving IRQ2 interrupt requests priority over other interrupts), interrupts masked follows: interrupts unmasked (priority order: IRQ2 IRQ3 >IRQ0 only NMI, IRQ2, IRQ3 unmasked. interrupts masked except NMI.
Figure shows transitions among above states.
interrupts unmasked Only NMI, unmasked
Exception handling,
Exception handling,
interrupts masked except
Figure Interrupt Masking State Transitions (Example) Figure flowchart showing interrupts accepted when interrupt condition occurs corresponding interrupt enable interrupt request sent interrupt controller. When interrupt controller receives more interrupt requests, selects highestpriority request, following interrupt priority settings, holds other requests pending. more interrupts with same setting requested simultaneously, interrupt controller follows priority order shown table 5-3. interrupt controller checks b
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