REJ03B0007-0200Z Rev.2.00 2003.04.15 4519 Group 4-bit single-chip

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REJ03B0007-0200Z Rev.2.00 2003.04.15 4519 Group 4-bit single-chip

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4519 Group
REJ03B0007-0200Z Rev.2.00 2003.04.15
4519 Group 4-bit single-chip microcomputer designed with CMOS technology. that 4500 series using simple, high-speed instruction set. computer equipped with serial I/O, four 8-bit timers (each timer reload register), 10-bit converter, interrupts, oscillation circuit switch function. various microcomputers 4519 Group include variations built-in memory size shown table below.
FEATURES
Minimum instruction execution time oscillation frequency, through-mode) Supply voltage Mask version Time PROM version depends operation source clock, oscillation frequency operation mode) Timers Timer 8-bit timer with reload register Timer 8-bit timer with reload register Timer 8-bit timer with reload register Timer 8-bit timer with reload registers Product M34519M6-XXXFP M34519M8-XXXFP M34519E8FP (Note)
Note: Shipped blank.
Interrupt sources Key-on wakeup function pins Serial bits converter 10-bit successive approximation method, Voltage drop detection circuit Reset occurrence Typ. Reset release Typ. Watchdog timer Clock generating circuit (ceramic resonator/RC oscillation/quartz-crystal oscillation/internal ring oscillator) drive directly enabled (port
APPLICATION
Electrical household appliance, consumer electronic products, office automation equipment, etc.
(PROM) size bits) 6144 words 8192 words 8192 words
size bits) words words words
Package 42P2R-A 42P2R-A 42P2R-A
type Mask Mask Time PROM
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PRELIMINARY
4519 Group
Notice: This final specification. Some parametric limits subject change.
CONFIGURATION
D6/CNTR0 D7/CNTR1 P20/SCK P21/SOUT P22/SIN RESET CNVSS XOUT
P43/AIN7 P42/AIN6 P41/AIN5 P40/AIN4 P63/AIN3 P62/AIN2 P61/AIN1 P60/AIN0 P31/INT1 P30/INT0 VDCE
OUTLINE 42P2R-A
M34519Mx-XXXFP M34519E8FP
configuration (top view) (4519 Group)
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Block diagram (4519 Group)
Rev.2.00
Port Port Port Port Port Port System clock generation circuit -XOUT (Ceramic/Quartz-crystal/RC) Built-in ring oscillator Voltage drop detection circuit
4519 Group
port
Port
Internal peripheral functions
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Timer
Timer bits) Timer bits) Timer bits) Timer bits)
Watchdog timer bits)
converter bits
Memory
6144, 8192 words bits
Serial bits
4500 series core
ALU(4 bits)
Register bits) Register bits) Register bits) Register bits) Stack register levels) Interrupt stack register level)
words bits
Port
PRELIMINARY
Notice: This final specification. Some parametric limits subject change.
PRELIMINARY
4519 Group
Notice: This final specification. Some parametric limits subject change.
PERFORMANCE OVERVIEW
Parameter Number basic instructions Minimum instruction execution time Memory sizes M34519M6 Function oscillation frequency, through-mode)
6144 words bits 8192 words bits words bits Input/Output Eight independent ports; Ports also used CNTR0 CNTR1, respectively. ports output structure switched software. 4-bit port; pull-up function, key-on wakeup function output structure switched software. P10-P13 4-bit port; pull-up function, key-on wakeup function output structure switched software. P20-P22 3-bit port; ports P20, also used SCK, SOUT SIN, respectively. P30-P33 4-bit port ports also used INT0 INT1, respectively. P40-P43 4-bit port ports P40-P43 also used AIN4-AIN7, respectively. P50-P53 4-bit port output structure switched software. P60-P63 4-bit port ports P60-P63 also used AIN0-AIN3, respectively. Timer Timers 8-bit timer with reload register also used event counter. Also, this equipped with period/pulse width measurement function. Timer 8-bit timer with reload register. Timer 8-bit timer with reload register also used event counter. Timer 8-bit timer with reload registers output function. converter 10-bit wide This equipped with 8-bit comparator function. Serial 8-bit Sources Interrupt (two external, four timer, A-D, serial I/O) Nesting level Subroutine nesting levels Device structure CMOS silicon gate Package 42-pin plastic molded SSOP (42P2R-A) Operating temperature range Supply voltage Mask version depends operation source clock, oscillation frequency operating mode.) Time PROM version depends operation source clock, oscillation frequency operating mode.) Active mode Power (VDD=5V, f(XIN)=6 MHz, f(STCK)=f(XIN), ring oscillator stop) dissipation (VDD=5V, f(XIN)=32 kHz, f(STCK)=f(XIN), ring oscillator stop) (typical value) (VDD=5V, ring oscillator used, f(STCK)=f(RING), f(XIN) stop) back-up mode room temperature, output transistors cut-off state) M34519M8/E8 M34519M6/M8/E8 D0-D7 (Input examined skip decision) P00-P03
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PRELIMINARY
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Notice: This final specification. Some parametric limits subject change.
CNVSS VDCE Name Power supply Ground CNVSS Voltage drop detection circuit enable Reset input/output Input/Output Input Function Connected plus power supply. Connected power supply. Connect CNVSS apply (0V) CNVSS certainly. This used operate/stop voltage drop detection circuit. When level input this pin, circuit starts operating. When level input this pin, circuit stops operating. N-channel open-drain system reset. When SRST instruction, watchdog timer voltage drop detection circuit cause system reset, RESET outputs level. pins main clock generating circuit. When using ceramic resonator, connect between pins XOUT. When using quartz-crystal oscillator, connect between pins XOUT. feedback resistor built-in between them. When using oscillation, connect resistor capacitor leave XOUT open. Each port independent 1-bit wide function. output structure switched N-channel open-drain CMOS software. input use, latch specified select N-channel open-drain. Ports also used CNTR0 CNTR1 pin, respectively. Port serves 4-bit port. output structure switched N-channel open-drain CMOS software. input use, latch specified select N-channel open-drain. Port key-on wakeup function pull-up function. Both functions switched software. Port serves 4-bit port. output structure switched N-channel open-drain CMOS software. input use, latch specified select N-channel open-drain. Port key-on wakeup function pull-up function. Both functions switched software. Port serves 3-bit port. output structure N-channel open-drain. input use, latch specified "1". Ports P20-P22 also used SCK, SOUT, SIN, respectively. Port serves 4-bit port. output structure N-channel open-drain. input use, latch specified "1". Ports also used INT0 INT1 pin, respectively. Port serves 4-bit port. output structure switched N-channel open-drain. input use, latch specified "1". Ports P40-P43 also used AIN4-AIN7, respectively. Port serves 4-bit port. output structure switched N-channel open-drain CMOS software. input use, latch specified select N-channel open-drain. Port serves 4-bit port. output structure switched N-channel open-drain. input use, latch specified "1". Ports P60-P63 also used AIN0-AIN3, respectively. CNTR0 function input clock timer event counter, output timer timer underflow signal divided CNTR1 function input clock timer event counter, output signal generated timer 4.CNTR0 CNTR1 also used Ports respectively. INT0 INT1 accept external interrupts. They have key-on wakeup function which switched software. INT0 INT1 also used Ports P31, respectively. converter analog input pins. AIN0-AIN7 also used ports P60-P63 P40- P43, respectively. Serial data transfer synchronous clock pin. also used port P20. Serial data output pin. SOUT also used port P21. Serial data input pin. also used port P22.
RESET
XOUT D0-D7
Main clock input Main clock output port Input examined skip decision. port
Input Output
P00-P03
P10-P13
port
P20-P23
port
P30-P33
port
P40-P43
port
P50-P53
port
P60-P63
port
CNTR0, CNTR1
Timer input/output
INT0, INT1
Interrupt input
Input
AIN0-AIN7 SOUT
Analog input Serial data Serial data output Serial clock input
Input Output Input
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Notice: This final specification. Some parametric limits subject change.
MULTIFUNCTION
Multifunction CNTR0 CNTR1 SOUT INT0 INT1 CNTR0 CNTR1 SOUT INT0 INT1 Multifunction Multifunction AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Multifunction
Notes Pins except above have just single function. input/output used even when INT0 INT1 selected. input ports P20-P22 used even when SIN, SOUT selected. input/output used even when CNTR0 (input) selected. input used even when CNTR0 (output) selected. input/output used even when CNTR1 (input) selected. input used even when CNTR1 (output) selected.
DEFINITION CLOCK CYCLE
Operation source clock operation source clock source clock operate this product. this product, following clocks used. Clock (f(XIN)) external ceramic resonator Clock (f(XIN)) external oscillation Clock (f(XIN)) external input Clock (f(RING)) ring oscillator which internal oscillator Clock (f(XIN)) external quartz-crystal oscillation Table Selection system clock Register System clock f(STCK) f(XIN) f(STCK) f(RING) f(STCK) f(XIN)/2 f(STCK) f(RING)/2 f(STCK) f(XIN)/4 f(STCK) f(RING)/4 f(STCK) f(XIN)/8 f(STCK) f(RING)/8 Note: f(RING)/8 selected after system released from reset. When ring oscillator clock selected main clock, ring oscillator operating state.
System clock (STCK) system clock basic clock controlling this product. system clock selected clock control register shown table below. Instruction clock (INSTCK) instruction clock basic clock controlling CPU. instruction clock (INSTCK) signal derived dividing system clock (STCK) instruction clock cycle generates machine cycle. Machine cycle machine cycle standard cycle required execute instruction. Operation mode through mode Ring through mode divided mode Ring divided mode divided mode Ring divided mode divided mode Ring divided mode
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Notice: This final specification. Some parametric limits subject change.
PORT FUNCTION
Port Port D0-D5 D6/CNTR0 D7/CNTR1 P00-P03 Input Output Output structure N-channel open-drain/ CMOS N-channel open-drain/ CMOS unit Control instructions OP0A IAP0 Control registers FR1, Remark Output structure selection function (programmable) Built-in programmable pull-up functions, key-on wakeup functions output structure selection functions Built-in programmable pull-up functions, key-on wakeup functions output structure selection functions
Port
Port
P10-P13
N-channel open-drain/ CMOS
OP1A IAP1
Port Port Port Port Port
P20/SCK, P21/SOUT P22/SIN P30/INT0, P31/INT1 P32, P40/AIN4-P43/AIN7 P50-P53 P60/AIN0-P63/AIN3
N-channel open-drain N-channel open-drain N-channel open-drain N-channel open-drain/ CMOS N-channel open-drain
OP2A IAP2 OP3A IAP3 OP4A IAP4 OP5A IAP5 OP6A IAP6
Output structure selection function (programmable)
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Notice: This final specification. Some parametric limits subject change.
CONNECTIONS UNUSED PINS
XOUT Open. Open. Connection Usage condition Internal oscillator selected. Internal oscillator selected. oscillator selected. External clock input selected main clock. N-channel open-drain selected output structure. CNTR0 input selected timer count source. N-channel open-drain selected output structure. CNTR1 input selected timer count source. N-channel open-drain selected output structure. key-on wakeup function selected. N-channel open-drain selected output structure. pull-up function selected. key-on wakeup function selected. key-on wakeup function selected. N-channel open-drain selected output structure. pull-up function selected. key-on wakeup function selected. selected. (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note
D0-D5 D6/CNTR0 D7/CNTR1 P00-P03
Open. Connect VSS. Open. Connect VSS. Open. Connect VSS. Open. Connect VSS.
P10-P13
Open. Connect VSS.
P20/SCK P21/SOUT P22/SIN P30/INT0 P31/INT1 P32, P40/AIN4-P43/AIN7 P50-P53 P60/AIN0-P63/AIN3
Open. Connect VSS. Open. Connect VSS. Open. Connect VSS. Open. Connect Vss. Open. Connect Vss. Open. Connect Vss. Open. Connect Vss. Open. Connect Vss. Open. Connect Vss.
selected. output latch. output latch.
N-channel open-drain selected output structure.
Notes After system released from reset, internal oscillation (ring oscillator) selected main clock (RG0=0, MR0=1). When CRCK instruction executed, oscillation circuit becomes valid. careful that swich system clock executed only CRCK instruction execution. order start oscillation, setting main clock f(XIN) oscillation valid (MR1=0) required. necessary, generate oscillation stabilizing wait time software.) Also, when main clock (f(XIN)) selected system clock, main clock f(XIN) oscillation (MR1=0) valid, select main clock f(XIN) (MR0=0). careful that switch system clock cannot executed same time when main clock oscillation started. order external clock input main clock, select ceramic resonance executing CMCK instruction beggining software, then main clock (f(XIN)) oscillation valid (MR1=0). Until main clock (f(XIN)) oscillation becomes valid (MR1=0) after ceramic resonance becomes valid, fixed "H". When external clock used, insert resistor series limits current. sure select output structure ports D0-D5 pull-up function 0-P03 P10-P13 with every port. corresponding bits registers each port. sure select output structure ports P00-P03 P10-P13 with every ports. only pins used, leave another open. key-on wakeup function selected with every bits. When only key-on wakeup function used, considering that value key-on wake-up control register unused 1-bit input (turn pull-up transistor open) input (connect VSS, open output latch "0"). key-on wakeup function selected with every bits. When key-on wakeup function used, turn pull-up transistor unused open. (Note when connecting VDD) Connect unused pins using thickest wire shortest distance against noise.
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Notice: This final specification. Some parametric limits subject change.
PORT BLOCK DIAGRAMS
Skip decision Register Decoder instruction (Note FR1i (Note instruction instruction D0-D3 (Note (Note
instruction
Skip decision Register Decoder instruction FR20 (Note instruction instruction (Note (Note
instruction
Skip decision Register Decoder instruction FR21 (Note instruction instruction (Note (Note
instruction
Notes This symbol represents parasitic diode port. Applied potential these ports must less. represents bits
Port block diagram
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Notice: This final specification. Some parametric limits subject change.
Register
Decoder instruction instruction
Skip decision
FR22
(Note D6/CNTR0 (Note
instruction instruction Timer underflow signal Timer underflow signal
Clock (input) timer event count period measurement signal input
Register
Decoder instruction instruction
Skip decision
FR23 PWMOD
(Note D7/CNTR1 (Note
instruction instruction
Clock (input) timer event count
Notes
This symbol represents parasitic diode port. Applied potential these ports must less.
Port block diagram
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Notice: This final specification. Some parametric limits subject change.
(Note IAP0 instruction Register FR00 OP0A instruction Key-on wakeup
Pull-up transistor
PU0j (Note
(Note P00, P01(Note (Note
Level detection circuit Edge detection circuit (Note IAP0 instruction Register
FR01 OP0A instruction Key-on wakeup
Pull-up transistor
PU0k (Note
(Note P02, P03(Note (Note
Level detection circuit Edge detection circuit (Note IAP1 instruction Register
FR02 OP1A instruction Key-on wakeup
Pull-up transistor
PU1j (Note
(Note P10, P11(Note (Note
Level detection circuit
(Note IAP1 instruction Register FR03 OP1A instruction Key-on wakeup
Pull-up transistor
PU1k (Note
(Note P12, P13(Note (Note
Level detection circuit
Notes This symbol represents parasitic diode port. Applied potential these ports must less. represents bits represents bits
Port block diagram
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Notice: This final specification. Some parametric limits subject change.
Register
IAP2 instruction (Note P20/SCK (Note
OP2A instruction
Synchronous clock (output) serial data transfer Synchronous clock (input) serial data transfer
Register
IAP2 instruction (Note P21/SOUT (Note
OP2A instruction
Serial data output
Register
IAP2 instruction (Note P22/SIN (Note
OP2A instruction
Serial data input
This symbol represents parasitic diode port. Notes Applied potential these ports must less.
Port block diagram
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Notice: This final specification. Some parametric limits subject change.
Register
IAP3 instruction (Note P30/INT0 (Note
OP3A instruction
(Note External interrupt circuit
External interrupt Key-on wakeup input Timer count start synchronous circuit input Period measurement circuit input
Register
IAP3 instruction (Note P31/INT1 (Note
OP3A instruction
(Note External interrupt circuit
External interrupt Key-on wakeup input Timer count start synchronous circuit input
Register
IAP3 instruction (Note (Note
OP3A instruction
Register
IAP3 instruction (Note (Note
OP3A instruction
Notes This symbol represents parasitic diode port. Applied potential these ports must less. details, refer external interrupt circuit structure.
Port block diagram
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Notice: This final specification. Some parametric limits subject change.
(Note Register IAP4 instruction (Note OP4A instruction Decoder Analog input P40/AIN4-P43/AIN7 (Note
(Note Register
IAP5 instruction
(Note FR3i (Note OP5A instruction P50-P53 (Note
Notes This symbol represents parasitic diode port. Applied potential these ports must less. represents bits
Port block diagram
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Notice: This final specification. Some parametric limits subject change.
(Note Register IAP6 instruction (Note (Note OP6A instruction Decoder Analog input P60/AIN0, P61/AIN1 (Note
(Note Register IAP6 instruction (Note OP6A instruction Decoder Analog input P62/AIN2, P63/AIN3 (Note
Notes This symbol represents parasitic diode port. Applied potential these ports must less. represents bits represents bits
Port block diagram
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Notice: This final specification. Some parametric limits subject change.
(Note P30/INT0
Falling
Rising
One-sided edge detection circuit
EXF0 Both edges detection circuit (Note Level detection circuit (Note Edge detection circuit
External interrupt
Timer count start synchronous circuit
Key-on wakeup
Skip decision (SNZI0 instruction)
(Note P31/INT1
Falling
Rising
One-sided edge detection circuit
EXF1 Both edges detection circuit (Note Level detection circuit (Note Edge detection circuit Skip decision (SNZI1 instruction)
External interrupt
Timer count start synchronous circuit
Key-on wakeup
This symbol represents parasitic diode port. Notes (I22) level detected (I22) level detected (I22) Falling edge detected (I22) Rising edge detected
Port block diagram
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Notice: This final specification. Some parametric limits subject change.
FUNCTION BLOCK OPERATIONS
(CY)
<Carry>
Arithmetic logic unit (ALU)
arithmetic logic unit performs 4-bit arithmetic such 4bit data addition, comparison, operation, operation, manipulation.
(M(DP)) Addition
Register carry flag
Register 4-bit register used arithmetic, transfer, exchange, operation. Carry flag 1-bit flag that when there carry with instruction (Figure unchanged with both instruction instruction. value stored carry flag with instruction (Figure Carry flag with instruction cleared with instruction.
<Result>
Fig. instruction execution example
<Set> instruction
<Clear> instruction
<Rotation> instruction
Registers
Register 4-bit register used temporary storage 4-bit data, 8-bit data transfer together with register Register 8-bit register. used 8-bit data transfer with register used high-order bits register low-order bits (Figure Register undefined after system released from reset returned from back-up. Accordingly, initial value.
Fig. instruction execution example
Register
instruction
Register
Register
Register 3-bit register. used store 7-bit address together with register used pointer within specified page when TABP BMLA instruction executed. Also, when TABP instruction executed, high-order bits reference data stored low-order bits register contents high-order register "0". (Figure Register undefined after system released from reset returned from back-up. Accordingly, initial value.
TEAB instruction Register TABE instruction Register Register
instruction
Fig. Registers register
TABP instruction Specifying address
DR1DR0
Low-order 4bits Register Middle-order bits Register High-order bits Register High-order register "0".
Immediate field value
contents contents register register
Fig. TABP instruction execution example
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Notice: This final specification. Some parametric limits subject change.
Stack registers (SKS) stack pointer (SP)
Stack registers (SKs) used temporarily store contents program counter (PC) just before branching until returning original routine when; branching interrupt service routine (referred interrupt service routine), performing subroutine call, executing table reference instruction (TABP Stack registers (SKs) eight identical registers, that subroutines nested levels. However, stack registers used respectively when using interrupt service routine when executing table reference instruction. Accordingly, careful over stack when performing these operations together. contents registers destroyed when levels exceeded. register nesting level pointed automatically 3-bit stack pointer (SP). contents stack pointer (SP) transferred register with TASP instruction. Figure shows stack registers (SKs) structure. Figure shows example operation subroutine call.
Program counter (PC) Executing instruction Executing instruction (SP) (SP) (SP) (SP) (SP) (SP) (SP) (SP)
Stack pointer (SP) points reset returning from back-up mode. points executing first instruction, contents program counter stored SK0. When instruction executed after eight stack registers used ((SP) (SP) contents destroyed.
Fig. Stack registers (SKs) structure
Interrupt stack register (SDP)
Interrupt stack register (SDP) 1-stage register. When interrupt occurs, this register (SDP) used temporarily store contents data pointer, carry flag, skip flag, register register just before interrupt until returning original routine. Unlike stack registers (SKs), this register (SDP) used when executing subroutine call instruction table reference instruction.
(SP) (SK0) 000116 (PC) SUB1
Main program Address 000016 000116 SUB1 000216
Subroutine
SUB1
Skip flag
Skip flag controls skip decision conditional skip instructions continuous described skip instructions. When interrupt occurs, contents skip flag stored automatically interrupt stack register (SDP) skip condition retained.
(PC) (SK0) (SP)
Note Returning instruction execution address with instruction, instruction becomes instruction.
Fig. Example operation subroutine call
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Notice: This final specification. Some parametric limits subject change.
Program counter (PC)
Program counter (PC) used specify address (page address). determines sequence which instructions stored read. binary counter that increments number instruction bytes each time instruction executed. However, value changes specified address when branch instructions, subroutine call instructions, return instructions, table reference instruction (TABP executed. Program counter consists (most significant which specifies page (bits which specifies address within page. After reaches last address (address 127) page, specifies address next page (Figure Make sure that does specify after last page built-in ROM.
Program counter
Specifying page
Specifying address
Fig. Program counter (PC) structure
Data pointer (DP)
Data pointer (DP)
Data pointer (DP) used specify address consists registers Register specifies file group, register specifies file, register specifies digit (Figure Register also used specify port position. When using port port position register certainly execute instruction (Figure Note Register data pointer undefined after system released from reset. Also, registers undefined back-up. After system returned from back-up, these registers.
Register
Specifying digit
Register
Specifying file
Register
Specifying file group
Fig. Data pointer (DP) structure
Specifying position
Port output latch
Register
Fig. instruction execution example
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Notice: This final specification. Some parametric limits subject change.
PROGRAM MEMORY (ROM)
program memory mask ROM. word composed bits. separated every words unit page (addresses 127). Table shows size pages. Figure shows M34519M8/E8. Table size pages Product M34519M6 M34519M8/E8 (PROM) size bits) 6144 words 8192 words Pages
000016 007F16 008016 00FF16 010016 017F16 018016
Page
Interrupt address page Subroutine special page
Page Page Page
part page (addresses 008016 00FF16) reserved interrupt addresses (Figure 11). When interrupt occurs, address (interrupt address) corresponding each interrupt program counter, instruction interrupt address executed. When using interrupt service routine, write instruction generating branch that routine interrupt address. Page (addresses 010016 017F16) special page subroutine calls. Subroutines written this page called from page with 1-word instruction (BM). Subroutines extending from page another page also called with instruction when starts page pattern (bits addresses used data areas with TABP instruction.
1FFF16
Page
Fig. M34519M8/E8
008016 008216 008416 008616 008816 008A16 008C16 008E16
External interrupt address External interrupt address Timer interrupt address Timer interrupt address Timer interrupt address Timer interrupt address interrupt address Serial interrupt address
00FF16
Fig. Page (addresses 008016 00FF16) structure
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Notice: This final specification. Some parametric limits subject change.
DATA MEMORY (RAM)
word composed bits, 1-bit manipulation (with instructions) enabled entire memory area. address specified data pointer. data pointer consists registers value data pointer certainly when executing instruction access (also, value after system returns from back-up). includes area LCD. When writing corresponding displayed segment, segment turned Table shows size. Figure shows map. Note Register data pointer undefined after system released from reset. Also, registers undefined back-up. After system returned from back-up, these registers.
Table size Product M34519M6 M34519M8/E8 size words bits (1536 bits)
words bits (1536 bits)
Register Register
words
M34519M8/E8
Z=0, Z=1,
Fig.
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Notice: This final specification. Some parametric limits subject change.
INTERRUPT FUNCTION
interrupt type vectored interrupt branching individual address (interrupt address) according each interrupt source. interrupt occurs when following conditions satisfied. interrupt activated condition satisfied (request flag "1") Interrupt enable enabled ("1") Interrupt enable flag enabled (INTE "1") Table shows interrupt sources. (Refer each interrupt request flag details activated conditions.)
Table Interrupt sources Priority Interrupt name level External interrupt External interrupt Timer interrupt Timer interrupt Timer interrupt Timer interrupt interrupt Serial interrupt
Activated condition Level change INT0 Level change INT1 Timer underflow Timer underflow Timer underflow Timer underflow Completion conversion Completion serial transmit/receive
Interrupt enable flag (INTE)
interrupt enable flag (INTE) controls whether every interrupt enable/disable. Interrupts enabled when INTE flag with instruction disabled when INTE flag cleared with instruction. When interrupt occurs, INTE flag automatically cleared "0," that other interrupts disabled until instruction executed.
Interrupt address Address page Address page Address page Address page Address page Address page Address page Address page
Interrupt enable
interrupt enable interrupt control registers select corresponding interrupt skip instruction. Table shows interrupt request flag, interrupt enable skip instruction. Table shows interrupt enable function.
Table Interrupt request flag, interrupt enable skip instruction Request flag EXF0 EXF1 External interrupt Timer interrupt Timer interrupt Timer interrupt Timer interrupt interrupt SIOF Serial interrupt Interrupt name External interrupt Skip instruction SNZ0 SNZ1 SNZT1 SNZT2 SNZT3 SNZT4 SNZAD SNZSI Enable
Interrupt request flag
When activated condition each interrupt satisfied, corresponding interrupt request flag "1." Each interrupt request flag cleared when either; interrupt occurs, next instruction skipped with skip instruction. Each interrupt request flag when activated condition satisfied even interrupt disabled INTE flag interrupt enable bit. Once set, interrupt request flag retains until clear condition satisfied. Accordingly, interrupt occurs when interrupt disable state released while interrupt request flag set. more than interrupt request flag when interrupt disable state released, interrupt priority level follows shown Table
Table Interrupt enable function Interrupt enable Occurrence interrupt Enabled Disabled
Skip instruction Invalid Valid
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Notice: This final specification. Some parametric limits subject change.
Internal state during interrupt
internal state microcomputer during interrupt follows (Figure 14). Program counter (PC) interrupt address program counter. address executed when returning main routine automatically stored stack register (SK). Interrupt enable flag (INTE) INTE flag cleared that interrupts disabled. Interrupt request flag Only request flag current interrupt source cleared "0." Data pointer, carry flag, skip flag, registers contents these registers flags stored automatically interrupt stack register (SDP).
Program counter (PC) Each interrupt address Stack register (SK) address main routine executed when returning Interrupt enable flag (INTE) (Interrupt disabled) Interrupt request flag (only flag current interrupt source) Data pointer, carry flag, registers skip flag Stored interrupt stack register (SDP) automatically Fig. Internal state when interrupt occurs
Interrupt processing
When interrupt occurs, program interrupt address executed after branching data store sequence stack register. Write branch instruction interrupt service routine interrupt address. instruction return from interrupt service routine. Interrupt enabled executing instruction performed after executing instruction (just after next instruction executed). Accordingly, when instruction executed just before instruction, interrupts enabled after returning main routine. (Refer Figure
Activated condition INT0 interrupt waveform input
Request flag Enable (state retained)
Enable flag
EXF0
Address page Address page
INT1 interrupt waveform input
EXF1
Main routine Interrupt service routine
Interrupt occurs
Timer underflow
Address page
Timer underflow Timer underflow
Address page
Address page Address page
Interrupt enabled
Timer underflow conversion completed
Address page
Serial transmit/ receive completed
SIOF
INTE
Address page
Interrupt enabled state Interrupt disabled state
Fig. Program example interrupt processing
Fig. Interrupt system diagram
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Notice: This final specification. Some parametric limits subject change.
Interrupt control registers
Interrupt control register Interrupt enable bits external timer timer assigned register contents this register through register with TV1A instruction. TAV1 instruction used transfer contents register register Interrupt control register timer timer serial interrupt enable assigned register contents this register through register with TV2A instruction. TAV2 instruction used transfer contents register register Table Interrupt control registers Interrupt control register Timer interrupt enable Timer interrupt enable External interrupt enable External interrupt enable reset 00002 back-up 00002 TAV1/TV1A
Interrupt disabled (SNZT2 instruction valid) Interrupt enabled (SNZT2 instruction invalid) Interrupt disabled (SNZT1 instruction valid) Interrupt enabled (SNZT1 instruction invalid) Interrupt disabled (SNZ1 instruction valid) Interrupt enabled (SNZ1 instruction invalid) Interrupt disabled (SNZ0 instruction valid) Interrupt enabled (SNZ0 instruction invalid) TAV2/TV2A
Interrupt control register Serial interrupt enable interrupt enable Timer interrupt enable Timer interrupt enable
reset 00002
back-up 00002
Interrupt disabled (SNZSI instruction valid) Interrupt enabled (SNZSI instruction invalid) Interrupt disabled (SNZAD instruction valid) Interrupt enabled (SNZAD instruction invalid) Interrupt disabled (SNZT4 instruction valid) Interrupt enabled (SNZT4 instruction invalid) Interrupt disabled (SNZT3 instruction valid) Interrupt enabled (SNZT3 instruction invalid)
Note: represents read enabled, represents write enabled.
Interrupt sequence
Interrupts only occur when respective INTE flag, interrupt enable bits 0-V13, V20-V2 interrupt request flag "1." interrupt actually occurs machine cycles after cycle which three conditions satisfied. interrupt occurs after machine cycles only when three interrupt conditions satisfied execution other than one-cycle instructions (Refer Figure 16).
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Interrupt disabled state Interrupt enabled state Retaining level system clock periods more necessary. Interrupt activated condition satisfied. Flag cleared machine cycles (Notes program starts from interrupt address.
4519 Group
Fig. Interrupt sequence
When interrupt request flag after interrupt enabled (Note
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machine cycle
System clock (STCK)
instruction execution cycle
Interrupt enable flag (INTE)
INT0,INT1
External interrupt
EXF0,EXF1
Timer Timer Timer Timer Serial interrupts
T1F,T2F,T3F,T4F, ADF,SIOF
PRELIMINARY
Notice: This final specification. Some parametric limits subject change.
Notes address stacked last cycle. This interval cycles depends executed instruction time when each interrupt activated condition satisfied.
PRELIMINARY
4519 Group
Notice: This final specification. Some parametric limits subject change.
EXTERNAL INTERRUPTS
4519 Group external interrupt external interrupt. external interrupt request occurs when valid waveform input interrupt input (edge detection). external interrupt controlled with interrupt control registers Table External interrupt activated conditions Name External interrupt Input P30/INT0 Activated condition When next waveform input P30/INT0 Falling waveform ("H""L") Rising waveform ("L""H") Both rising falling waveforms External interrupt P31/INT1 When next waveform input P31/INT1 Falling waveform ("H""L") Rising waveform ("L""H") Both rising falling waveforms Valid waveform selection
(Note P30/INT0
Falling
Rising
One-sided edge detection circuit
EXF0 Both edges detection circuit (Note Level detection circuit (Note Edge detection circuit
External interrupt
Timer count start synchronous circuit
Key-on wakeup
Skip decision (SNZI0 instruction)
(Note P31/INT1
Falling
Rising
One-sided edge detection circuit
EXF1 Both edges detection circuit (Note Level detection circuit (Note Edge detection circuit Skip decision (SNZI1 instruction)
External interrupt
Timer count start synchronous circuit
Key-on wakeup
This symbol represents parasitic diode port. Notes (I22) level detected (I22) level detected (I22) Falling edge detected (I22) Rising edge detected
Fig. External interrupt circuit structure
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Notice: This final specification. Some parametric limits subject change.
External interrupt request flag (EXF0)
External interrupt request flag (EXF0) when valid waveform input P30/INT0 pin. valid waveforms causing interrupt must retained their level clock cycles more system clock (Refer Figure 16). state EXF0 flag examined with skip instruction (SNZ0). interrupt control register select interrupt skip instruction. EXF0 flag cleared when interrupt occurs when next instruction skipped with skip instruction. External interrupt activated condition External interrupt activated condition satisfied when valid waveform input P30/INT0 pin. valid waveform selected from rising waveform, falling waveform both rising falling waveforms. example external interrupt follows. register INT0 input enabled state. Select valid waveform with bits register Clear EXF0 flag with SNZ0 instruction. instruction case when skip performed with SNZ0 instruction. both external interrupt enable INTE flag "1." external interrupt enabled. when valid waveform input P30/INT0 pin, EXF0 flag external interrupt occurs.
External interrupt request flag (EXF1)
External interrupt request flag (EXF1) when valid waveform input P31/INT1 pin. valid waveforms causing interrupt must retained their level clock cycles more system clock (Refer Figure 16). state EXF1 flag examined with skip instruction (SNZ1). interrupt control register select interrupt skip instruction. EXF1 flag cleared when interrupt occurs when next instruction skipped with skip instruction. External interrupt activated condition External interrupt activated condition satisfied when valid waveform input P31/INT1 pin. valid waveform selected from rising waveform, falling waveform both rising falling waveforms. example external interrupt follows. register INT1 input enabled state. Select valid waveform with bits register Clear EXF1 flag with SNZ1 instruction. instruction case when skip performed with SNZ1 instruction. both external interrupt enable (V11) INTE flag "1." external interrupt enabled. when valid waveform input P31/INT1 pin, EXF1 flag external interrupt occurs.
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4519 Group
Notice: This final specification. Some parametric limits subject change.
External interrupt control registers
Interrupt control register Register controls valid waveform external interrupt. contents this register through register with TI1A instruction. TAI1 instruction used transfer contents register register Table External interrupt control register Interrupt control register INT0 input control
Interrupt control register Register controls valid waveform external interrupt. contents this register through register with TI2A instruction. TAI2 instruction used transfer contents register register
reset 00002
back-up state retained
TAI1/TI1A
INT0 input disabled INT0 input enabled Falling waveform/"L" level ("L" level recognized with SNZI0 instruction) Rising waveform/"H" level ("H" level recognized with SNZI0 instruction) One-sided edge detected Both edges detected Timer count start synchronous circuit selected Timer count start synchronous circuit selected
Interrupt valid waveform INT0 pin/ return level selection
INT0 edge detection circuit control INT0 Timer count start synchronous circuit selection
Interrupt control register INT1 input control (Note
reset 00002
back-up state retained
TAI2/TI2A
INT1 input disabled INT1 input enabled Falling waveform/"L" level ("L" level recognized with SNZI1 instruction) Rising waveform/"H" level ("H" level recognized with SNZI1 instruction) One-sided edge detected Both edges detected Timer count start synchronous circuit selected Timer count start synchronous circuit selected
Interrupt valid waveform INT1 pin/ return level selection (Note
INT1 edge detection circuit control INT1 Timer count start synchronous circuit selection
Notes represents read enabled, represents write enabled. When contents I12, changed, external interrupt request flag (EXF0, EXF1) set.
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4519 Group
Notice: This final specification. Some parametric limits subject change.
Notes External interrupt
Note register When input INT0 controlled with register software, careful about following notes. Depending input state 0/INT0 pin, external interrupt request flag (EXF0) when register changed. order avoid occurrence unexpected interrupt, clear register (refer Figure then, change register addition, execute SNZ0 instruction clear EXF0 flag after executing least instruction (refer Figure Also, instruction case when skip performed with SNZ0 instruction (refer Figure
Note register When interrupt valid waveform /INT0 changed with register software, careful about following notes. Depending input state P30/INT0 pin, external interrupt request flag (EXF0) when register changed. order avoid occurrence unexpected interrupt, clear register (refer Figure then, change register addition, execute SNZ0 instruction clear EXF0 flag after executing least instruction (refer Figure 20). Also, instruction case when skip performed with SNZ0 instruction (refer Figure 20).
TV1A TI1A SNZ0
(02) SNZ0 instruction valid (12) Control INT0 input changed SNZ0 instruction executed (EXF0 flag cleared)
TV1A TI1A SNZ0
(02) SNZ0 instruction valid Interrupt valid waveform changed SNZ0 instruction executed (EXF0 flag cleared)
these bits used here. Fig. External interrupt program example-1 Note register When register cleared, back-up mode selected input INT0 disabled, careful about following notes. When input INT0 disabled (register "0"), key-on wakeup function invalid (register "0") before system enters back-up mode. (refer Figure 19).
these bits used here. Fig. External interrupt program example-3
TK2A EPOF
(02) Input INT0 key-on wakeup invalid
back-up
these bits used here. Fig. External interrupt program example-2
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4519 Group
Notice: This final specification. Some parametric limits subject change.
Notes External interrupt
Note register When input INT1 controlled with register software, careful about following notes. Depending input state P31/INT1 pin, external interrupt request flag (EXF1) when register changed. order avoid occurrence unexpected interrupt, clear register (refer Figure then, change register addition, execute SNZ1 instruction clear EXF1 flag after executing least instruction (refer Figure 21). Also, instruction case when skip performed with SNZ1 instruction (refer Figure 21).
Note register When interrupt valid waveform /INT1 changed with register software, careful about following notes. Depending input state P31/INT1 pin, external interrupt request flag (EXF1) when register changed. order avoid occurrence unexpected interrupt, clear register (refer Figure then, change register addition, execute SNZ1 instruction clear EXF1 flag after executing least instruction (refer Figure 23). Also, instruction case when skip performed with SNZ1 instruction (refer Figure 23).
TV1A TI2A SNZ1
(02) SNZ1 instruction valid (12) Control INT1 input changed SNZ1 instruction executed (EXF1 flag cleared)
TV1A TI2A SNZ1
(02) SNZ1 instruction valid Interrupt valid waveform changed SNZ1 instruction executed (EXF1 flag cleared)
these bits used here. Fig. External interrupt program example-1 Note register When register cleared, back-up mode selected input INT1 disabled, careful about following notes. When input INT1 disabled (register "0"), key-on wakeup function invalid (register "0") before system enters back-up mode. (refer Figure 22).
these bits used here. Fig. External interrupt program example-3
TK2A EPOF
(02) Input INT1 key-on wakeup invalid
back-up
these bits used here. Fig. External interrupt program example-2
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4519 Group
Notice: This final specification. Some parametric limits subject change.
TIMERS
4519 Group following timers. Programmable timer programmable timer reload register enables frequency dividing ratio set. decremented from setting value When underflows (count timer interrupt request flag "1," data loaded from reload register, count continues (auto-reload function).
Fixed dividing frequency timer fixed dividing frequency timer fixed frequency dividing ratio (n). interrupt request flag after every count count pulse.
Counter initial value Count starts Reload Reload
contents counter
underflow
underflow
0016 Time count Timer interrupt request flag interrupt occurs skip instruction executed.
Fig. Auto-reload function 4519 Group timer consists following circuits. Prescaler 8-bit programmable timer Timer 8-bit programmable timer Timer 8-bit programmable timer Timer 8-bit programmable timer Timer 8-bit programmable timer Watchdog timer 16-bit fixed dividing frequency timer (Timers have interrupt function, respectively) Prescaler timers controlled with timer control registers watchdog timer free counter which controlled with control register. Each function described below.
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Notice: This final specification. Some parametric limits subject change.
Table Function related timers Circuit Prescaler Timer Structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link INT0 input) (period/pulse width measurement function) Timer 8-bit programmable binary down counter System clock (STCK) Prescaler output (ORCLK) Timer underflow (T1UDF) output (PWMOUT) Timer 8-bit programmable binary down counter (link INT1 input) output (PWMOUT) Prescaler output (ORCLK) Timer underflow (T2UDF) CNTR1 input Timer 8-bit programmable binary down counter Watchdog timer input Prescaler output (ORCLK) 65534 Timer count source CNTR1 output Timer interrupt System reset (count twice) flag decision CNTR1 output control Timer interrupt Timer count source CNTR0 output Timer interrupt Count source Instruction clock (INSTCK) Instruction clock (INSTCK) Prescaler output (ORCLK) input CNTR0 input Frequency dividing ratio output signal Timer count sources Timer count source CNTR0 output Timer interrupt Control register
(PWM output function) Instruction clock (INSTCK) 16-bit fixed dividing frequency
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Notice: This final specification. Some parametric limits subject change.
Division circuit Divided Ring oscillator Ceramic resonance Multiplexer (CMCK, CRCK, CYCK) (Note Divided Divided
MR3, Internal clock generating circuit (divided
System clock (STCK)
Instruction clock (INSTCK)
oscillation Quartz-crystal oscillation
Prescaler
ORCLK
Reload register (TPSAB) (TABPS) (TPSAB) (TPSAB) (TABPS)
Register
Register
Port output
T1UDF T2UDF
W51,
Ring oscillator
1/16
D6/CNTR0
One-period generation circuit
P30/INT0
One-sided edge detection circuit
(Note
Both edges detection circuit
T1UDF
W11, (Note
INSTCK ORCLK
W21, (TAB2) (TAB1)
Timer Reload register
(T1AB) (TR1AB) (T1AB) (T1AB) (TAB1)
Timer interrupt
Register Register
STCK ORCLK T1UDF PWMOUT
Timer underflow signal T1UDF)
Timer
Timer interrupt
Reload register
(T2AB) (T2AB) (T2AB) (TAB2)
Register Register
TR1AB: This instruction used transfer contents register register only reload register PWMOUT: output signal (from timer output unit)
Timer underflow signal (T2UDF)
Data automatically from each reload register when timer underflows (auto-reload function).
Notes When CMCK instruction executed, ceramic resonance selected. When CRCK instruction executed, oscillation selected. When CYCK instruction executed, quartz-crystal oscillator selected. Timer count start synchronous circuit valid edge P30/INT0 selected bits (I11) (I12) register cannot used count source when (MR1) register f(XIN) oscillation stopped.
Fig. Timer structure
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Notice: This final specification. Some parametric limits subject change.
P31/INT1
One-sided edge detection circuit
Both edges detection circuit
(Note
T3UDF
W31, PWMOD (TAB3)
PWMOUT ORCLK T2UDF
D7/CNTR1
Timer Reload register
(T3AB) (TR3AB) (T3AB) (T3AB) (TAB3)
Timer interrupt
Register Register
Timer underflow signal (T3UDF)
Port output T3UDF
Register Register
(T4HAB)
(Note
ORCLK
Reload register Reload control circuit
(T4R4L)
PWMOUT Timer interrupt
Timer
interval expansion
Reload register
(T4AB) (TAB4) (T4AB) (T4AB) (TAB4)
Register Register Watchdog timer
INSTCK
(Note
WDF1 WRST instruction RESET signal
DWDT instruction (Note WRST instruction Watchdog reset signal
RESET signal
TR3AB: This instruction used transfer contents Notes cannot used count source when (MR1) register register only reload register register f(XIN) oscillation stopped. T4R4L: This instruction used transfer contents reload register timer Timer count start synchronous circuit valid edge INSTCK: Instruction clock (system clock divided P31/INT1 selected bits (I21) (I22) register ORCLK: Prescaler output (instruction clock divided 256)
Data automatically from each reload register when timer underflows (auto-reload function).
Flag WDF1 cleared next instruction skipped when WRST instruction executed while flag WDF1 "1". next instruction skipped even when WRST instruction executed while flag WDF1 "0". Flag cleared watchdog timer reset does occur when DWDT instruction WRST instruction executed continuously.
Fig. Timer structure
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Notice: This final specification. Some parametric limits subject change.
Table Timer related registers Timer control register Prescaler control reset Stop (state initialized) Operating TAW1/TW1A back-up TPAA
Timer control register Timer count source selection bits Timer count auto-stop circuit selection Timer control
reset 00002
back-up state retained
Timer count auto-stop circuit selected Timer count auto-stop circuit selected Stop (state retained) Operating Count source Instruction clock (INSTCK) Prescaler output (ORCLK) input CNTR0 input TAW2/TW2A
Timer control register Timer count source selection bits CNTR0 output signal selection Timer control
reset 00002
back-up state retained
Timer underflow signal divided output Timer underflow signal divided output Stop (state retained) Operating Count source System clock (STCK) Prescaler output (ORCLK) Timer underflow signal (T1UDF) signal (PWMOUT)
Timer control register Timer count source selection bits Timer count auto-stop circuit selection (Note Timer control
reset 00002
back-up state retained
TAW3/TW3A
Timer count auto-stop circuit selected Timer count auto-stop circuit selected Stop (state retained) Operating Count source signal (PWMOUT) Prescaler output (ORCLK) Timer underflow signal (T2UDF) CNTR1 input
Notes represents read enabled, represents write enabled. This function valid only when timer count start synchronous circuit selected (I10="1"). This function valid only when timer count start synchronous circuit selected (I20="1").
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Notice: This final specification. Some parametric limits subject change.
Timer control register D7/CNTR1 function selection signal interval expansion function control Timer control Timer count source selection
reset 00002
back-up 00002
TAW4/TW4A
(I/O) CNTR1 (input) CNTR1 (I/O) (input) signal interval expansion function invalid signal interval expansion function valid Stop (state retained) Operating input Prescaler output (ORCLK) divided
Timer control register Signal period measurement selection bits used Period measurement circuit control
reset 00002
back-up state retained
TAW5/TW5A
This function, read/write enabled. Stop Operating Count value Ring oscillator (f(RING/16)) CNTR0 input INT0 input available TAW6/TW6A
Timer control register CNTR1 input count edge selection CNTR0 input count edge selection CNTR1 output auto-control circuit selection D6/CNTR0 function selection
reset 00002
back-up state retained
Falling edge Rising edge Falling edge Rising edge CNTR1 output auto-control circuit selected CNTR1 output auto-control circuit selected (I/O) CNTR0 (input) CNTR0 (I/O) (input)
Note: represents read enabled, represents write enabled.
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4519 Group
Notice: This final specification. Some parametric limits subject change.
Timer control registers
Timer control register Register controls count operation prescaler. contents this register through register with TPAA instruction. Timer control register Register controls selection timer count auto-stop circuit, count operation count source timer contents this register through register with TW1A instruction. TAW1 instruction used transfer contents register register Timer control register Register controls selection CNTR0 output, count operation count source timer contents this register through register with TW2A instruction. TAW2 instruction used transfer contents register register Timer control register Register controls selection count operation count source timer count auto-stop circuit. contents this register through register with TW3A instruction. TAW3 instruction used transfer contents register register Timer control register Register controls D7/CNTR1 output, expansion interval output, count operation count source timer contents this register through register with TW4A instruction. TAW4 instruction used transfer contents register register Timer control register Register controls period measurement circuit target signal period measurement. contents this register through register with TW5A instruction. TAW5 instruction used transfer contents register register Timer control register Register controls count edges CNTR0 CNTR1 pin, selection CNTR1 output auto-control circuit CNTR0 function. contents this register through register with TW6A instruction. TAW6 instruction used transfer contents register register
Prescaler
Prescaler 8-bit binary down counter with prescaler reload register PRS. Data simultaneously prescaler reload register with TPSAB instruction. Data read from reload register with TABPS instruction. Stop counting then execute TPSAB TABPS instruction read prescaler data. Prescaler starts counting after following process; data prescaler, register "1." When value reload register prescaler divides count source signal 255). Count source prescaler instruction clock (INSTCK). Once count started, when prescaler underflows (the next count pulse input after contents prescaler becomes "0"), data loaded from reload register RPS, count continues (auto-reload function). output signal (ORCLK) prescaler used timer count sources.
Timer (interrupt function)
Timer 8-bit binary down counter with timer reload register (R1). Data simultaneously timer reload register (R1) with T1AB instruction. Data written reload register (R1) with TR1AB instruction. Data read from timer with TAB1 instruction. Stop counting then execute T1AB TAB1 instruction read timer data. When executing TR1AB instruction data reload register while timer operating, avoid timing when timer underflows. Timer starts counting after following process; data timer count source bits register register "1." When value reload register timer divides count source signal 255). Once count started, when timer underflows (the next count pulse input after contents timer becomes "0"), timer interrupt request flag (T1F) "1," data loaded from reload register count continues (auto-reload function). INT0 input used start trigger timer count operation setting register "1." Also, this time, auto-stop function timer underflow performed setting register "1." Timer underflow signal divided output from CNTR0 clearing register setting register "1". period measurement circuit starts operating setting register timer used count one-period target signal period measurement. this time, timer interrupt request flag (T1F) timer underflow signal, flag detecting completion period measurement.
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Notice: This final specification. Some parametric limits subject change.
Timer (interrupt function)
Timer 8-bit binary down counter with timer reload register (R2). Data simultaneously timer reload register (R2) with T2AB instruction. Data read from timer with TAB2 instruction. Stop counting then execute T2AB TAB2 instruction read timer data. Timer starts counting after following process; data timer select count source with bits register register "1." When value reload register timer divides count source signal 255). Once count started, when timer underflows (the next count pulse input after contents timer becomes "0"), timer interrupt request flag (T2F) "1," data loaded from reload register count continues (auto-reload function). Timer underflow signal divided output from CNTR0 setting register setting register "1".
Timer (interrupt function)
Timer 8-bit binary down counter with timer reload registers (R4L, R4H). Data simultaneously timer reload register with T4AB instruction. Data reload register with T4HAB instruction. contents reload register with T4AB instruction timer again with T4R4L instruction. Data read from timer with TAB4 instruction. Stop counting then execute T4AB TAB4 instruction read timer data. When executing T4HAB instruction data reload register while timer operating, avoid timing when timer underflows. Timer starts counting after following process; data timer count source register register "1." When value reload register timer divides count source signal 255). Once count started, when timer underflows (the next count pulse input after contents timer becomes "0"), timer interrupt request flag (T4F) "1," data loaded from reload register R4L, count continues (auto-reload function). signal generated timer output from CNTR1 setting timer control register "1". Timer control output CNTR1 with timer setting timer control register "1".
Timer (interrupt function)
Timer 8-bit binary down counter with timer reload register (R3). Data simultaneously timer reload register (R3) with T3AB instruction. Data written reload register (R3) with TR3AB instruction. Data read from timer with TAB3 instruction. Stop counting then execute T3AB TAB3 instruction read timer data. When executing TR3AB instruction data reload register while timer operating, avoid timing when timer underflows. Timer starts counting after following process; data timer count source bits register register "1." When value reload register timer divides count source signal 255). Once count started, when timer underflows (the next count pulse input after contents timer becomes "0"), timer interrupt request flag (T3F) "1," data loaded from reload register count continues (auto-reload function). INT1 input used start trigger timer count operation setting register "1." Also, this time, auto-stop function timer underflow performed setting register "1."
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Notice: This final specification. Some parametric limits subject change.
Period measurement function (Timer period measurement circuit)
Timer period measurement circuit which performs timer count operation synchronizing with cycle signal divided built-in ring oscillator, 6/CNTR0 input, P30/INT0 input (one cycle, "H", pulse width case P30/INT0 input). When target signal period measurement bits register period measurement circuit started setting register "1". Then, input count source timer register "1", timer starts operation. Timer starts operation synchronizing with falling edge target signal period measurement, stops count operation synchronizing with next falling edge (one-period generation circuit). When selecting 6/CNTR0 input target signal period measurement, period measurement synchronous edge changed into rising edge setting register "1". When selecting 0/INT0 input target signal period measurement, period measurement synchronous edge changed into rising edge setting register "1". timer interrupt request flag (T1F) after completing measurement operation. When period measurement circuit operating, timer interrupt request flag (T1F) timer underflow signal, turns into flag which detects completion period measurement. addition, timer underflow signal used timer count source. Once period measurement operation completed, even period measurement valid edge input next, timer stop state measurement data held. When period measurement circuit used again, stop period measurement circuit once setting register "0", change period measurement circuit into state operation setting register again. When period measurement circuit used, clear register "0", timer count start synchronous circuit "not selected". Start timer operation immediately after operation period measurement circuit started. When target edge measurement input until timer operation started from operation period measurement circuit started, count operation executed until timer operation becomes valid. Accordingly, careful count data. When data read from timer, stop timer clear register stop period measurement circuit, then execute data read instruction. Depending state timer timer interrupt request flag (T1F) when period measurement circuit stopped clearing register "0". order avoid occurrence unexpected interrupt, clear register (refer Figure then, stop register stop period measurement circuit.
addition, execute SNZT1 instruction clear flag after executing least instruction (refer Figure 27). Also, instruction case when skip performed with SNZT1 instruction (refer Figure 27).
TV1A TW5A SNZT1
(02) SNZT1 instruction valid (02) Period measurement circuit stop SNZT1 instruction executed (T1F flag cleared)
these bits used here. Fig. Period measurement circuit program example When period measurement circuit used, select sufficiently higher-speed frequency than signal measurement count source timer When target signal period measurement D6/CNTR0 input, select D6/CNTR0 input timer count source. (The input recommended timer count source time period measurement circuit use.)
Pulse width measurement function (timer period measurement circuit)
period measurement circuit measure pulse width (from rising falling) pulse width (from falling rising) P30/ INT0 input (pulse width measurement function) when following set; register "0", (target period measurement circuit: 30/INT0 input). register (INT0 edge detection circuit: both edges detection) measurement pulse width ("H" "L") decided period measurement circuit P30/INT0 input level start time timer operation. time start period measurement circuit timer operation, pulse width (from falling rising) when input level P30/INT0 pulse width (from rising falling) when level measured. When input P30/INT0 selected target measurement, register "1", input INT0 enabled.
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Notice: This final specification. Some parametric limits subject change.
Count start synchronization circuit (timer timer
Timer timer have count start synchronous circuit which synchronizes input INT0 INT1 pin, start timer count operation. Timer count start synchronous circuit function selected setting register control INT0 input performed. Timer count start synchronous circuit function selected setting register control INT1 input performed. When timer timer count start synchronous circuit used, count start synchronous circuit set, count source input each timer inputting valid waveform INT0 INT1 pin. valid waveform INT0 INT1 count start synchronous circuit same external interrupt activated condition. Once set, count start synchronous circuit cleared clearing reset. However, when count auto-stop circuit selected, count start synchronous circuit cleared (auto-stop) timer timer underflow.
(11) Timer input/output (D6/CNTR0 pin, D7/CNTR1 pin)
CNTR0 used input timer count source output timer timer underflow signal divided CNTR1 used input timer count source output signal generated timer D6/CNTR0 function selected register selection D7/CNTR1 output signal controlled register When CNTR0 input selected timer count source, timer counts rising falling waveform CNTR0 input. count edge selected register When CNTR1 input selected timer count source, timer counts rising falling waveform CNTR1 input. count edge selected register
(12) output function (D7/CNTR1, timer timer
When register "1", timer reloads data from reload register alternately each underflow. Timer generates signal (PWMOUT) interval reload register R4L, interval reload register R4H. signal (PWMOUT) output from CNTR1 pin. When register this time, interval (PWM signal interval) reload register counter timer extended half period count source. this case, when value reload register timer divides count source signal 255). When this function used, more reload register R4H. When register "1", signal output CNTR1 switched valid/invalid each timer underflow. However, when timer stopped (bit register cleared "0"), this function canceled. Even when register cleared interval signal, timer does stop until next timer underflow. When clearing register stop timer avoid timing when timer underflows.
(10) Count auto-stop circuit (timer timer
Timer count auto-stop circuit which used stop timer automatically timer underflow when count start synchronous circuit used. count auto-stop cicuit valid setting register "1". cleared timer underflow count source timer stopped. This function valid only when timer count start synchronous circuit selected. Timer count auto-stop circuit which used stop timer automatically timer underflow when count start synchronous circuit used. count auto-stop cicuit valid setting register "1". cleared timer underflow count source timer stopped. This function valid only when timer count start synchronous circuit selected.
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Notice: This final specification. Some parametric limits subject change.
(13) Timer interrupt request flags (T1F, T2F, T3F, T4F)
Each timer interrupt request flag when each timer underflows. state these flags examined with skip instructions (SNZT1, SNZT2, SNZT3, SNZT4). interrupt control register select interrupt skip instruction. interrupt request flag cleared when interrupt occurs when next instruction skipped with skip instruction. timer interrupt request flag (T1F) timer underflow signal, flag detecting completion period measurement.
Depending state timer timer interrupt request flag (T1F) when period measurement circuit stopped clearing register "0". order avoid occurrence unexpected interrupt, clear register (refer Figure then, stop register stop period measurement circuit. addition, execute SNZT1 instruction clear flag after executing least instruction (refer Figure 28). Also, instruction case when skip performed with SNZT1 instruction (refer Figure 28).
(14) Precautions
Note following timers. Prescaler Stop counting then execute TABPS instruction read from prescaler data. Stop counting then execute TPSAB instruction prescaler data. Timer count source Stop timer counting change count source. Reading count value Stop timer counting then execute data read instruction (TAB1, TAB2, TAB3, TAB4) read data. Writing timer Stop timer counting then execute data write instruction (T1AB, T2AB, T3AB, T4AB) write data. Writing reload register When writing data reload register reload register reload regiser while timer timer timer operating, avoid timing when timer timer timer underflows. Timer Avoid timing when timer underflows stop timer When interval extension function signal "valid", more reload register R4H. Period measurement function When period measurement circuit used, clear register "0", timer count start synchronous circuit "not selected". Start timer operation immediately after operation period measurement circuit started. When target edge measurement input until timer operation started from operation period measurement circuit started, count operation executed until timer operation becomes valid. Accordingly, careful count data. When data read from timer, stop timer clear register stop period measurement circuit, then execute data read instruction.
TV1A TW5A SNZT1
(02) SNZT1 instruction valid (02) Period measurement circuit stop SNZT1 instruction executed (T1F flag cleared)
these bits used here. Fig. Period measurement circuit program example While period measurement circuit operating, timer interrupt request flag (T1F) timer underflow signal, flag detecting completion period measurement. When period measurement circuit used, select sufficiently higher-speed frequency than signal measurement count source timer When target signal period measurement D6/CNTR0 input, select D6/CNTR0 input timer count source. (The input recommended timer count source time period measurement circuit use.) When input P30/INT0 selected measurement, register "1", input INT0 enabled.
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Notice: This final specification. Some parametric limits subject change.
CNTR1 output: invalid (W43 "0")
Timer count source 0316 (R4L) (R4L) (R4L) (R4L) (R4L) 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016
Timer count value (Reload register) Timer underflow signal signal (output invalid)
Timer start
signal fixed
CNTR1 output: valid (W43 "1") signal interval extension function: invalid (W42 "0")
Timer count source Timer count value (Reload register) Timer underflow signal signal clock Timer start period clock clock period clock 0316 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
CNTR1 output: valid (W43 "1") signal interval extension function: valid (W42 "1") (Note)
Timer count source Timer count value (Reload register) Timer underflow signal signal Timer start clock period clock clock period clock 0316 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216
Note: signal interval extension function: valid, "0116" more reload register R4H.
Fig. Timer operation (reload register R4L: "0316", R4H: "0216")
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Notice: This final specification. Some parametric limits subject change.
CNTR1 output auto-control circuit timer selected.
CNTR1 output: valid (W43 "1") CNTR1 output auto-control circuit selected (W61 "1") signal Timer underflow signal Timer start CNTR1 output CNTR1 output start
CNTR1 output auto-control function
signal Timer underflow signal Timer start Register
Timer stop
CNTR1 output CNTR1 output start CNTR1 output stop
When CNTR1 output auto-control function invalid while CNTR1 output invalid, CNTR1 output invalid state retained. When CNTR1 output auto-control function invalid while CNTR1 output valid, CNTR1 output valid state retained. When timer stopped, CNTR1 output auto-control function becomes invalid.
Fig. CNTR1 output auto-control function timer
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Notice: This final specification. Some parametric limits subject change.
Waveform extension function CNTR1 output interval: Invalid (W42 "0"), CNTR1 output: valid (W43 "1"), Count source: input selected (W40 "0"), Reload register R4L: "0316" Reload register R4H: "0216"
Timer count start timing
Machine cycle
Mi+1
Mi+2
System clock f(STCK)=f(XIN)/4 input (count source selected) Register Timer count value (Reload register) Timer underflow signal signal
TW4A instruction execution cycle (W41)
0316 (R4L)
0216 0116 0016 0216 0116 0016 0316 0216 0116 (R4H) (R4L)
Timer count start timing
Timer count stop timing
Machine cycle Mi+1 Mi+2
System clock f(STCK)=f(XIN)/4 input (count source selected) Register Timer count value (Reload register) Timer underflow signal signal
TW4A instruction execution cycle (W41)
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 (R4H) (R4L)
0216 (R4H)
(Note
Timer count stop timing
Notes order stop timer CNTR1 output valid (W43 "1"), avoid timing when timer underflows. these timings overlap, hazard occur CNTR1 output waveform. CNTR1 output valid, timer stops after interval signal reload register output.
Fig. Timer count start/stop timing
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Notice: This final specification. Some parametric limits subject change.
WATCHDOG TIMER
Watchdog timer provides method reset system when program run-away occurs. Watchdog timer consists timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), watchdog timer flags (WDF1, WDF2). timer downcounts instruction clocks count source from "FFFF16" after system released from reset. After count started, when timer underflow occurs (after count value timer reaches "000016," next count pulse input), WDF1 flag "1." WRST instruction never executed until timer underflow occurs (until timer counts 65534), WDF2 flag "1," RESET outputs level reset microcomputer. Execute WRST instruction each period 65534 machine cycle less software when using watchdog timer keep microcomputer operating normally. When flag after system released from reset, watchdog timer function valid. When DWDT instruction WRST instruction executed continuously, flag cleared watchdog timer function invalid. However, order flag again once cleared "0", execute system reset. WRST instruction skip function. When WRST instruction executed while WDF1 flag "1", WDF1 flag cleared next instruction skipped. When WRST instruction executed while WDF1 flag "0", next instruction skipped. skip function WRST instruction used even when watchdog timer function invalid.
FFFF1 Value 16-bit timer (WDT) 000016 WDF1 flag
65534 count (Note) WDF2 flag
RESET output Reset released WRST instruction executed (skip executed) System reset
After system released from reset after program started), timer starts count down. When timer underflow occurs, WDF1 flag "1." When WRST instruction executed, WDF1 flag cleared "0," next instruction skipped. When timer underflow occurs while WDF1 flag "1," WDF2 flag watchdog reset signal output. output transistor RESET turned "ON" watchdog reset signal system reset executed. Note: number count equal number cycle because count source watchdog timer instruction clock.
Fig. Watchdog timer function
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Notice: This final specification. Some parametric limits subject change.
When watchdog timer used, clear WDF1 flag period 65534 machine cycles less with WRST instruction. When watchdog timer used, execute DWDT instruction WRST instruction continuously (refer Figure 33). watchdog timer stopped with only DWDT instruction. contents WDF1 flag timer initialized back-up mode. When using watchdog timer back-up mode, initialize WDF1 flag with WRST instruction just before microcomputer enters back-up state (refer Figure 34). watchdog timer function valid after system returned from back-up. When using watchdog timer function, execute DWDT instruction WRST instruction continuously every system returned from back-up, stop watchdog timer function.
WRST
WDF1 flag cleared
DWDT WRST
Watchdog timer function enabled/disabled WDF1 flags cleared
Fig. Program example start/stop watchdog timer
WRST WDF1 flag cleared Interrupt disabled EPOF instruction enabled Oscillation stop
Fig. Program example enter mode when using watchdog timer
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Notice: This final specification. Some parametric limits subject change.
CONVERTER (Comparator)
4519 Group built-in conversion circuit that performs conversion 10-bit successive comparison method. Table shows characteristics this converter. This converter also used 8-bit comparator compare analog voltages input from analog input with preset values.
Table converter characteristics Characteristics Parameter Conversion format Successive comparison method Resolution bits Relative accuracy Linearity error: ±2LSB (2.7 5.5V) Non-linearity error: ±0.9LSB (2.2 5.5V) Conversion speed (f(X MHz, STCK f(XIN) through-mode), ADCK INSTCK/6) Analog input
Register
Register IAP4 (P40-P43) IAP6 (P60-P63) OP4A (P40-P43) OP6A (P60-P63) TAQ1 TQ1A TAQ2 TQ2A TAQ3 TQ3A TALA
Division circuit Divided
TABAD
TADAB
Q31,
Instruction clock Ring oscillator clock
Divided Divided Divided
conversion clock (ADCK)
8-channel multi-plexed analog switch
control circuit
P60/AIN0 P61/AIN1 P62/AIN2 P63/AIN3 P40/AIN4 P41/AIN5 P42/AIN6 P43/AIN7
interrupt
Comparator
operation signal
Successive comparison register (AD) (10)
converter
(Note
Comparator register
(Note
Notes This switch turned only when converter operating generates comparison voltage. Writing/reading data comparator register possible only comparator mode (Q13=1). value comparator register retained even when mode switched conversion mode (Q13=0) because separated from successive comparison register (AD). Also, resolution comparator mode bits because comparator register consists bits.
Fig. conversion circuit structure
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Notice: This final specification. Some parametric limits subject change.
Table control registers
control register operation mode selection reset 00002 conversion mode Comparator mode AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 back-up state retained TAQ1/TQ1A
Analog input pins
Analog input selection bits
control register P40/AIN4, P41/AIN5, P42/AIN6, P43/AIN7 function selection P62/AIN2, P63/AIN3 function selection P61/AIN1 function selection P60/AIN0 function selection
reset 00002
back-up state retained
TAQ2/TQ2A
P40, P41, P42, AIN4, AIN5, AIN6, AIN7 P62, AIN2, AIN3 AIN1 AIN0
control register converter operation clock division ratio selection bits used converter operation clock selection
reset 00002
back-up state retained
TAQ3/TQ3A
This function, read/write enabled. Instruction clock (INSTCK) Ring oscillator (f(RING)) Division ratio Frequency divided Frequency divided Frequency divided Frequency divided
Note: represents read enabled, represents write enabled.
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Notice: This final specification. Some parametric limits subject change.
control register
control register Register controls selection operation mode selection analog input pins. contents this register through register with TQ1A instruction. TAQ1 instruction used transfer contents register register control register Register controls selection /AIN4-P43 /AIN7, P60/ AIN0-P63/AIN3. contents this register through register with TQ2A instruction. TAQ2 instruction used transfer contents register register control register Register controls selection converter operation clock. contents this register through register with TQ3A instruction. TAQ3 instruction used transfer contents register register
conversion completion flag (ADF)
conversion completion flag (ADF) when conversion completes. state flag examined with skip instruction (SNZAD). interrupt control register select interrupt skip instruction. flag cleared when interrupt occurs when next instruction skipped with skip instruction.
conversion start instruction (ADST)
conversion starts when ADST instruction executed. conversion result automatically stored register
Operation description
conversion started with conversion start instruction (ADST). internal operation during conversion follows: When conversion starts, register cleared "00016." Next, topmost register "1," comparison voltage Vref compared with analog input voltage VIN. When comparison result Vref VIN, topmost register remains "1." When comparison result Vref VIN, cleared "0." 4519 Group repeats this operation lowermost register convert analog value digital value. conversion stops after machine cycles conversion clock when f(XIN) through mode, f(ADCK) f(INSTCK)/ from start, conversion result stored register interrupt activated condition satisfied flag soon conversion completes (Figure 36).
Operating conversion mode
conversion mode setting register "0."
Successive comparison register
Register stores conversion result analog input 10-bit digital data format. contents high-order bits this register stored register register with TABAD instruction. contents low-order bits this register stored into high-order bits register with TALA instruction. However, execute these instructions during conversion. When contents register logic value comparison voltage generated from built-in converter obtained with reference voltage following formula: Logic value comparison voltage Vref Vref
1024
value register 1023)
Table Change successive comparison register during conversion starting conversion comparison comparison comparison After 10th comparison completes comparison result comparison result comparison result Change successive comparison register
Comparison voltage (Vref) value
1024
conversion result
comparison result comparison result 10th comparison result
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Notice: This final specification. Some parametric limits subject change.
conversion timing chart
Figure shows conversion timing chart.
ADST instruction machine cycles 10/f(ADCK) conversion completion flag (ADF) operation signal
Fig. conversion timing chart
conversion
conversion explained using example which analog input from P60/AIN0 converted, highorder bits converted data stored address M(Z, middle-order bits address M(Z, low-order bits address M(Z, RAM. interrupt used this example. Instruction clock/6 selected converter operation clock. Select AIN0 function with register Select function conversion mode with register Also, instruction clock divided selected with register (refer Figure Execute ADST instruction start conversion. Examine state flag with SNZAD instruction determine conversion. Transfer low-order bits converted data high-order bits register (TALA instruction). Transfer contents register Transfer high-order bits converted data registers (TABAD instruction). Transfer contents register Transfer contents register register then, store into M(Z,
(Bit
(Bit
control register
function selected
(Bit
(Bit
control register
selected conversion mode
(Bit
(Bit
control register
Frequency divided Instruction clock arbitrary value.
Fig. Setting registers
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Notice: This final specification. Some parametric limits subject change.
Operation comparator mode
converter comparator mode setting register "1." Below, operation comparator mode described.
(12) Comparator operation start instruction (ADST instruction)
comparator mode, executing ADST starts comparator operating. comparator stops machine cycles conversion clock f(ADCK) clock after started f(XIN) through mode, f(ADCK) f(INSTCK)/6). When analog input voltage lower than comparison voltage, flag "1."
(10) Comparator register
comparator mode, built-in comparator connected 8-bit comparator register register setting comparison voltages. contents register stored high-order bits comparator register contents register stored low-order bits comparator register with TADAB instruction. When changing from conversion mode comparator mode, result conversion (register undefined. However, because comparator register separated from register value retained even when changing from comparator mode conversion mode. Note that comparator register written read only comparator mode. value comparator register logic value comparison voltage Vref generated built-in converter determined from following formula: Logic value comparison voltage Vref Vref
(13) Notes conversion
TALA instruction When TALA instruction executed, low-order bits register transferred high-order bits register simultaneously, low-order bits register "0." Operation mode converter change operating mode (both conversion mode comparator mode) converter with register while converter operating. Clear register change operating mode converter from comparator mode conversion mode. conversion completion flag (ADF) when operating mode converter changed from comparator mode conversion mode. Accordingly, value register execute SNZAD instruction clear flag.
value register 255)
(11) Comparison result store flag (ADF)
comparator mode, flag, which shows completion conversion, stores results comparing analog input voltage with comparison voltage. When analog input voltage lower than comparison voltage, flag "1." state flag examined with skip instruction (SNZAD). interrupt control register select interrupt skip instruction. flag cleared when interrupt occurs when next instruction skipped with skip instruction.
ADST instruction machine cycles 1/f(ADCK) Comparison result store flag(ADF) operation signal
Comparator operation completed. (The value determined)
Fig. Comparator operation timing chart
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Notice: This final specification. Some parametric limits subject change.
(14) Definition converter accuracy
conversion accuracy defined below (refer Figure 39). Relative accuracy Zero transition voltage (V0T) This means analog input voltage when actual conversion output data changes from "1." Full-scale transition voltage (VFST) This means analog input voltage when actual conversion output data changes from "1023" "1022." Linearity error This means deviation from line between VFST converted value between VFST. Differential non-linearity error This means deviation from input potential difference required change converter value between VFST relative accuracy. Absolute accuracy This means deviation from ideal characteristics between actual conversion characteristics.
Analog input voltage when output data changes from "n+1" 1022) 1LSB relative accuracy VFST-V0T 1022 1024
1LSB absolute accuracy
Output data
1023 1022
Full-scale transition voltage (VFST)
Differential non-linearity error [LSB] Linearity error [LSB]
Actual conversion characteristics 1LSB relative accuracy Vn+1-Vn Difference between ideal actual
Ideal line conversion between V0-V1022
Zero transition voltage (V0T)
Vn+1
V1022 Analog voltage
Fig. Definition conversion accuracy
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Notice: This final specification. Some parametric limits subject change.
SERIAL
4519 Group built-in clock synchronous serial which serially transmit receive 8-bit data. Serial consists serial register serial control register serial transmit/receive completion flag (SIOF) serial counter Registers used perform data transfer with internal CPU, serial pins used external data transfer. functions serial pins with register
Table Serial pins P20/SCK P21/SOUT P22/SIN function when selecting serial Clock (SCK) Serial data output (SOUT) Serial data input (SIN)
Note: Even when SCK, OUT, functions used, input P20, P21, valid.
INSTCK
J13J12
Synchronous circuit
Serial counter
SIOF
Serial interrupt
P20/SCK
instruction Internal reset signal
P21/SOUT
SOUT
P22/SIN
Serial register TABSI TSIAB TABSI
Register
Register
Fig. Serial structure Table Serial control register Serial control register reset 00002 back-up state retained TAJ1/TJ1A
Synchronous clock Instruction clock (INSTCK) divided Serial synchronous clock selection bits Instruction clock (INSTCK) divided Instruction clock (INSTCK) divided External clock (SCK input) Port function P20, P21,P22 selected/SCK, SOUT, selected Serial port function selection bits SCK, SOUT, selected/P20, P21, selected SCK, P21, selected/P20, SOUT, selected SCK, SOUT, selected/P20, P21,P22 selected
Note: represents read enabled, represents write enabled.
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Notice: This final specification. Some parametric limits subject change.
transmit (D7-D0: transfer data)
receive
SOUT
Serial register (SI)
SOUT
Serial register (SI)
Transfer data
Transfer start
Fig. Serial register state when transferring
Transfer complete
Serial register
Serial register 8-bit data transfer serial/parallel conversion register. Data register through registers with TSIAB instruction. contents register transmitted low-order bits register contents register transmitted high-order bits register During transmission, each data transmitted first from lowermost (bit register during reception, each data received first register starting from topmost (bit When register used work register without using serial I/O, select pin.
Serial start instruction (SST)
When instruction executed, SIOF flag cleared then serial transmission/reception started.
Serial control register
Register controls synchronous clock, P20/S /SOUT P22/SIN function. contents this register through register with TJ1A instruction. TAJ1 instruction used transfer contents register register
Serial transmit/receive completion flag (SIOF)
Serial transmit/receive completion flag (SIOF) when serial data transmission reception completes. state SIOF flag examined with skip instruction (SNZSI). interrupt control register select interrupt skip instruction. SIOF flag cleared when interrupt occurs when next instruction skipped with skip instruction.
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Notice: This final specification. Some parametric limits subject change.
serial
Figure shows serial connection example. Serial interrupt used this example. actual wiring, pull
wiring between each with resistor. Figure shows data transfer timing Table shows data transfer sequence.
Master (clock control)
Slave (external clock)
SOUT
SRDY signal
SOUT
(Bit
(Bit
(Bit Serial control register Serial port SCK,SOUT,SIN
Instruction clock/8 selected synchronous clock
(Bit Serial control register Serial port SCK,SOUT,SIN
External clock selected synchronous clock
(Bit
(Bit Interrupt control register Serial interrupt enable (SNZSI instruction valid)
(Bit
(Bit Interrupt control register Serial interrupt enable (SNZSI instruction valid)
arbitrary value.
Fig. Serial connection example
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Notice: This final specification. Some parametric limits subject change.
Master
SOUT instruction
Slave
instruction
SRDY signal SOUT
M0-M7: Contents master serial register S0-S7: Contents slave serial register Rising SCK: Serial input Falling SCK: Serial output
Fig. Timing serial data transfer
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Table Processing sequence data transfer from master slave Master (transmission) [Initial setting] Setting serial mode register interrupt control register shown Figure TJ1A TV2A instructions Setting port received reception enable signal (SRDY) input mode. (Port used this example) instruction [Transmission enable state] Storing transmission data serial register TSIAB instruction [Initial setting] Setting serial mode register interrupt control register shown Figure TJ1A TV2A instructions Setting port transmitted reception enable signal (SRDY) outputting level (reception impossible). (Port used this example) instruction *[Reception enable state] SIOF flag cleared "0." instruction level (reception possible) output from port instruction [Transmission] port level. instruction transfer starts. instruction transmission completes. SNZSI instruction (timing when continuously transferring) Check reception completes. SNZSI instruction level output from port instruction [Data processing] 1-byte data serially transferred this process. Subsequently, data transferred continuously repeating process from When external clock selected synchronous clock, clock controlled internally. Control clock externally because serial transfer performed long clock externally input. (Unlike internal clock, external clock stopped when serial transfer completed.) However, SIOF flag when clock counted times after executing instruction. sure initial level external clock "H." [Reception] Slave (reception)
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Notice: This final specification. Some parametric limits subject change.
RESET FUNCTION
System reset performed applying level RESET machine cycle more when following condition satisfied; value supply voltage minimum value more recommended operating conditions. Then when level applied RESET pin, software starts from address page
f(RING)
RESET Ring oscillator (internal oscillator)
counted times.
Program starts (address page
Note: number clock cycles depends internal state microcomputer when reset performed.
Fig. Reset release timing
Reset input
Ring oscillator (internal oscillator)
machine cycle more
counted times.
0.85VDD RESET 0.3VDD
Program starts (address page
(Note)
Note: Keep value supply voltage minimum value more recommended operating conditions.
Fig. RESET input waveform reset operation
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Notice: This final specification. Some parametric limits subject change.
Power-on reset
Reset automatically performed power (power-on reset) built-in power-on reset circuit. When built-in power-on reset circuit used, time supply voltage rise from until value supply voltage reaches minimum operating voltage must less.
rising time exceeds connect capacitor between RESET shortest distance, input level RESET until value supply voltage reaches minimum operating voltage.
less
(Note
Pull-up transistor
(Note (Note
Power-on reset circuit output
RESET
Internal reset signal Power-on reset circuit
(Note
Voltage drop detection circuit Watchdog reset signal
Internal reset signal
Reset state Power-on Reset released
Notes This symbol represents parasitic diode. Applied potential RESET must less. Keep value supply voltage minimum value more recommended operating conditions.
Fig. Structure reset peripherals,, power-on reset operation Table Port state reset Name D0-D5 D6/CNTR0 D7/CNTR1 P00-P03 P10-P13 P20/SCK, P21/SOUT, P22/SIN P30/INT0, P31/INT1, P32, P40/AIN4-P43/AIN7 P50-P53 P60/AIN0-P63/AIN3
Notes Output latch "1." Output structure N-channel open-drain. Pull-up transistor turned OFF.
Function D0-D5 P00-P03 P10-P13 P20-P22 P30-P33 P40-P43 P50-P53 P60-P63 High-impedance (Notes High-impedance (Notes High-impedance (Notes
State
High-impedance (Notes High-impedance (Notes High-impedance (Note High-impedance (Note High-impedance (Note High-impedance (Notes High-impedance (Note
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Notice: This final specification. Some parametric limits subject change.
Internal state reset
Figure show internal state reset (they same after system released from reset). contents timers, registers, flags except shown Figure undefined, initial value them.
Program counter (PC) Address page program counter. Interrupt enable flag (INTE) Power down flag External interrupt request flag (EXF0) External interrupt request flag (EXF1) Interrupt control register Interrupt control register Interrupt control register Interrupt control register Timer interrupt request flag (T1F) Timer interrupt request flag (T2F) Timer interrupt request flag (T3F) Timer interrupt request flag (T4F) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) Timer control register Timer control register Timer control register Timer control register Timer control register Timer control register Timer control register Clock control register Clock control register Serial transmit/receive completion flag (SIOF) Serial mode register Serial register conversion completion flag (ADF) control register control register control register Successive approximation register Comparator register Key-on wakeup control register Key-on wakeup control register Key-on wakeup control register Pull-up control register Pull-up control register
(Interrupt disabled)
(Interrupt disabled) (Interrupt disabled)
(Prescaler stopped) (Timer stopped) (Timer stopped) (Timer stopped) (Timer stopped) (Period measurement circuit stopped)
(Ring oscillator operating) (External clock selected, serial port selected)
represents undefined. Fig. Internal state reset
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Notice: This final specification. Some parametric limits subject change.
Port output structure control register Port output structure control register Port output structure control register Port output structure control register Carry flag (CY) Register Register Register Register Register Register Register Stack pointer (SP) Operation source clock Ring oscillator (operating) Ceramic resonator circuit Stop oscillation circuit Stop Quartz-crystal oscillation circuit Stop represents undefined.
Fig. Internal state reset
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Notice: This final specification. Some parametric limits subject change.
VOLTAGE DROP DETECTION CIRCUIT
built-in voltage drop detection circuit designed detect drop voltage reset microcomputer supply voltage drops below value.
VDCE
VRST VRST
Voltage drop detection circuit Reset signal
Voltage drop detection circuit
Fig. Voltage drop detection reset circuit
VRST (reset release voltage) VRST -(reset voltage)
Voltage drop detection circuit Reset signal Microcomupter starts operation after ring oscillator (internal oscillator) clock counted times. RESET
Note: Detection voltage hysteresis voltage drop detection circuit (Typ).
Fig. Voltage drop detection circuit operation waveform Table Voltage drop detection circuit operation state VDCE operating Invalid Valid back-up Invalid Valid
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Notice: This final specification. Some parametric limits subject change.
BACK-UP MODE
4519 Group back-up mode. When EPOF instructions executed continuously, system enters back-up state. instruction equal instruction when EPOF instruction executed before instruction. oscillation stops retaining RAM, function reset circuit states back-up mode, current dissipation reduced without losing contents RAM. Table shows function states retained back-up. Figure shows state transition.
Table Functions states retained back-up Function Program counter (PC), registers carry flag (CY), stack pointer (SP) (Note Contents Interrupt control registers Interrupt control registers Selection oscillation circuit Clock control register Timer function Timer function Timer function Timer function Watchdog timer function Timer control register Timer control registers Serial function Serial mode register conversion function control registers Voltage drop detection circuit Port level Key-on wakeup control register Pull-up control registers PU0, Port output direction registers External interrupt request flag (EXF0) External interrupt request flag (EXF1) Timer interrupt request flag (T1F) Timer interrupt request flag (T2F) Timer interrupt request flag (T3F) Timer interrupt request flag (T4F) conversion completion flag (ADF) Serial transmission/reception completion flag (SIOF) Interrupt enable flag (INTE) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) (Note (Note back-up (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note
Identification start condition
Warm start (return from back-up state) cold start (return from normal reset state) identified examining state back-up flag with SNZP instruction.
Warm start condition
When external wakeup signal input after system enters back-up state executing EPOF instructions continuously, starts executing program from address page this case, flag "1."
Cold start condition
starts executing program from address page when; reset pulse input RESET pin, reset watchdog timer performed, voltage drop detection circuit detects voltage drop, SRST instruction executed. this case, flag "0."
Notes 1:"O" represents that function retained, represents that function initialized. Registers flags other than above undefined back-up, initial value after returning. stack pointer (SP) points level stack register initialized back-up. state timer undefined. Initialize watchdog timer with WRST instruction, then execute instruction. valid/invalid voltage drop detection circuit controlled only VDCE pin.
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Notice: This final specification. Some parametric limits subject change.
Return signal
external wakeup signal used return from back-up mode because oscillation stopped. Table shows return condition each return source.
Related registers
Key-on wakeup control register Register controls ports key-on wakeup function. contents this register through register with TK0A instruction. addition, TAK0 instruction used transfer contents register register Key-on wakeup control register Register controls return condition valid waveform/ level selection port contents this register through register with TK1A instruction. addition, TAK1 instruction used transfer contents register register Key-on wakeup control register Register controls INT0 INT1 key-on wakeup functions return condition function. contents this register through register with TK2A instruction. addition, TAK2 instruction used transfer contents register register Table Return source return condition Return source Return condition
Pull-up control register Register controls ON/OFF port pull-up transistor. contents this register through register with TPU0A instruction. addition, TAPU0 instruction used transfer contents register register Pull-up control register Register controls ON/OFF port pull-up transistor. contents this register through register with TPU1A instruction. addition, TAPU1 instruction used transfer contents register register External interrupt control register Register controls valid waveform external interrupt, input control INT0 pin, return input level. contents this register through register with TI1A instruction. addition, TAI1 instruction used transfer contents register register External interrupt control register Register controls valid waveform external interrupt, input control INT1 pin, return input level. contents this register through register with TI2A instruction. addition, TAI2 instruction used transfer contents register register
Remarks
External wakeup signal
Ports 0-P0 Return external level level input, rising edge ("L""H") falling edge ("H""L").
key-on wakeup function selected with port units. Select return level ("L" level level), return condition (return level edge) with register according external state before going into back-up state. Ports 0-P1 Return external level key-on wakeup function selected with port units. port using key-on wakeup function level before going into put. back-up state. INT0 INT1 Return external level Select return level ("L" level level) with registers ac"L" level input, rising edge cording external state, return condition (return level edge) with register before going into back-up state. ("H""L"). external interrupt request flags (EXF0, EXF1) set.
Rev.2.00
2003.04.15 page
PRELIMINARY
4519 Group
Notice: This final specification. Some parametric limits subject change.
Operation state Reset (Note Operation source clock: f(RING) f(XIN): Stop MR11
(Note Key-on wakeup
back-up mode
instruction execution (Note
(Note MR10
Operation state Operation source clock: f(RING) f(XIN): Operating (Note MR00 MR01 instruction execution (Note
Operation state Operation source clock: f(XIN) f(RING): Operating RG00 RG01 instruction execution (Note
Operation state Operation source clock: f(XIN) f(RING): Stop instruction execution (Note f(RING): stop f(XIN): stop
Notes Microcomputer starts operation after counting f(RING) times. f(XIN) oscillation circuit (ceramic resonance, oscillation quartz-crystal oscillation) selected CMCK, CRCK CYCK instruction starts oscillatng (the start oscillation operation source clock switched these instructions). start/stop oscillation operation source switched register Surely, select f(XIN) oscillation circuit executing CMCK, CRCK CYCK instruction before clearing "0". cannot cleared when oscillation circuit selected. Generate wait time software until oscillation stabilized, then, switch system clock. Continuous execution EPOF instruction instruction required into back-up state. System returns state certainly when returning from back-up mode. However, selected contents (CMCK, CRCK, CYCK instruction execution state) f(XIN) oscillation circuit retained.
Fig. State transition
EPOF instruction instruction Reset input
Power down flag
Program start
Warm start
source
EPOF instruction instruction
Cold start
Clear source Reset input
Fig. source clear source flag Fig. Start condition identified example using SNZP instruction
Rev.2.00
2003.04.15 page
PRELIMINARY
4519 Group
Notice: This final specification. Some parametric limits subject change.
Table Key-on wakeup control register, pull-up control register Key-on wakeup control register Pins key-on wakeup control Pins key-on wakeup control Pins key-on wakeup control Pins key-on wakeup control Key-on wakeup control register Ports return condition selection Ports valid

REJ03B0007-0200Z Rev.2.00 2003.04.15 4519 Group 4-bit single-chip

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