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H8S/2345 Series
H8S/2345, H8S/2344, H8S/2343, H8S/2341, H8S/2340
H8S/2345 F-ZTATHardware Manual
ADE-602-129B Rev. 3/13/03 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
H8S/2345 Series series high-performance microcontrollers with 32-bit H8S/2000 core, on-chip supporting functions required system configuration. H8S/2000 execute basic instructions state, provided with sixteen 16-bit general registers with 32-bit internal configuration, concise optimized instruction set. handle Mbyte linear address space (architecturally Gbytes). Programs based high-level language also efficiently. address space divided into eight areas. data width access states selected each these areas, various kinds memory connected fast easily. On-chip memory consists large-capacity RAM. With regard on-chip ROM*1, single power supply flash memory (F-ZTATTM*2), PROM (ZTATTM*2), mask versions available, providing quick flexible response conditions from ramp-up through fullscale volume production, even applications with frequently changing specifications. On-chip supporting functions include 16-bit timer pulse unit (TPU), 8-bit timers, watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports. on-chip data transfer controller (DTC) also provided, enabling high-speed data transfer without intervention. H8S/2345 Series enables compact, high-performance systems implemented easily. This manual describes hardware H8S/2345 Series. Refer H8S/2600 Series H8S/2000 Series Programming Manual detailed description instruction set. Notes: H8S/2345, H8S/2344, H8S/2343, H8S/2341 have on-chip ROM. H8S/2340 does have on-chip ROM. F-ZTAT (Flexible-ZTAT) trademark Hitachi, Ltd. ZTAT trademark Hitachi, Ltd.
Revisions Additions this Edition
Page Item Table Overview (Operating modes) Note Table Overview (Packages), (Product lineup) Notes Figure Arrangement 3.3.7 Mode Table Correspondence between Interrupt Sources Settings Note Table Port Functions (Port 11.2.3 Reset Control/Status Register table 12.5 Usage Notes Switching from Function Port Function Section 17.8.1 Boot Mode On-Chip Area Divisions Boot Mode 17.8.1 Boot Mode Notes User Mode 17.8.1 Boot Mode Notes User Mode 17.9.4 Erase-Verify Mode Table 17.22 Characteristics Writer Mode [Amendment] Note mode programming setup time tMDS (min)= [Amendment] Cleared after elapse more [Amendments] Values following items: Output high-level voltage Output low-Level voltage Input leak current current Amendment values Revision [Amendment] Modes available ROMless version. Amended line with completion TFP100G development Amended line with completion TFP100G development [Amendment] Note: used ROMless version [Amendment] Reserved bits. Only should written these bits. Amended: Functions amended accordance with notes [Amendment] Cleared reading RSTCR when WOVF then writing WOVF Added Deleted Part denoted "Preliminary" Amendment values
Page
Item Figure 17.36 Figure 17.38 Mode programming setup time 17.15 Notes when Converting ZTAT Application Software MaskROM Versions Table 18.2 Damping Resistance Value Table 18.3 Crystal Resonator Parameters Table 18.4 External Clock Input Conditions 19.2.1 Standby Control Register (SBYCR) Bits (standby time when using external clock) 19.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Using External Clock
Revision [Amendment] (min) Added
Added added Added added [Amendment] applies only ZTAT, mask ROM, ROMless versions [Amendment] 16-state standby time cannot used F-ZTAT version; standby time 8192 states longer should used. [Amendment] 16-state standby time cannot used F-ZTAT version; standby time 8192 states longer should used. [Amendment] operating temperature range flash memory programming/erase operations +75°C (regular specifications), +85°C (wide-range specifications). [Amendments] Values following items: Current dissipation Analog power supply current Referencecurrent value Note4 [Deletion] Characteristics table conditions AVCC Vref AVCC AVSS
Table 20.1 Absolute Maximum Ratings
Table 20.2 Characteristics
Page
Item Table 20.3 Permissible Output Currents Table 20.4 Clock Timing Table 20.5 Control Signal Timing Table 20.6 Timing Table 20.7 Timing On-Chip Supporting Modules Table 20.8 Conversion Characteristics Table 20.9 Conversion Characteristics
Revision [Deleted] Conditions AVCC Vref AVCC AVSS
Table 20.10 Flash Memory Characteristics Table 20.11 Absolute Maximum Ratings
Totally amended [Amendment] Programming voltage applies ZTAT version only [Added] Test Conditions:V [Added] Test Conditions:V [Amendment] RESS timing [Amendment] descriptions Amended Amended Amended line with completion TFP100G development Amended line with completion TFP100G development
Table 20.12 Characteristics Table 20.12 Characteristics Figure 20.9 Reset Input Timing ADCR, Control Register H'FF99 Figure Port Block Diagram (Pins P11) Figure Port Block Diagram (Pins P13) Table H8S/2345 Series Product Code Lineup Figure TFP-100G Package Dimensions
Contents
Section
Overview.
Overview. Block Diagram Description. 1.3.1 Arrangement 1.3.2 Functions Each Operating Mode. 1.3.3 Functions
Section
Overview. 2.1.1 Features 2.1.2 Differences between H8S/2600 H8S/2000 CPU. 2.1.3 Differences from H8/300 2.1.4 Differences from H8/300H Operating Modes Address Space. Register Configuration 2.4.1 Overview 2.4.2 General Registers. 2.4.3 Control Registers 2.4.4 Initial Register Values Data Formats. 2.5.1 General Register Data Formats. 2.5.2 Memory Data Formats. Instruction 2.6.1 Overview. 2.6.2 Instructions Addressing Modes. 2.6.3 Table Instructions Classified Function. 2.6.4 Basic Instruction Formats Addressing Modes Effective Address Calculation. 2.7.1 Addressing Mode. 2.7.2 Effective Address Calculation Processing States. 2.8.1 Overview. 2.8.2 Reset State 2.8.3 Exception-Handling State 2.8.4 Program Execution State 2.8.5 Bus-Released State. 2.8.6 Power-Down State
Basic Timing. 2.9.1 Overview. 2.9.2 On-Chip Memory (ROM, RAM). 2.9.3 On-Chip Supporting Module Access Timing 2.9.4 External Address Space Access Timing
Section
Operating Modes Overview. 3.1.1 Operating Mode Selection (F-ZTATVersion) 3.1.2 Operating Mode Selection (ZTAT, Mask ROM, ROMless Versions) 3.1.3 Register Configuration. Register Descriptions 3.2.1 Mode Control Register (MDCR) 3.2.2 System Control Register (SYSCR). 3.2.3 System Control Register (SYSCR2) (F-ZTAT Version Only). Operating Mode Descriptions 3.3.1 Mode (ZTAT, Mask ROM, ROMless Versions Only) 3.3.2 Mode (ZTAT Mask Versions Only). 3.3.3 Mode (ZTAT Mask Versions Only). 3.3.4 Mode 3.3.5 Mode 3.3.6 Mode 3.3.7 Mode 3.3.8 Modes (F-ZTAT Version Only). 3.3.9 Mode (F-ZTAT Version Only). 3.3.10 Mode (F-ZTAT Version Only). 3.3.11 Modes (F-ZTAT Version Only). 3.3.12 Mode (F-ZTAT Version Only). 3.3.13 Mode (F-ZTAT Version Only). Functions Each Operating Mode Memory Each Operating Mode Exception Handling Overview. 4.1.1 Exception Handling Types Priority. 4.1.2 Exception Handling Operation. 4.1.3 Exception Vector Table Reset. 4.2.1 Overview. 4.2.2 Reset Types. 4.2.3 Reset Sequence 4.2.4 Interrupts after Reset. 4.2.5 State On-Chip Supporting Modules after Reset Release.
Section
Traces Interrupts Trap Instruction. Stack Status after Exception Handling Notes Stack.
Section
Interrupt Controller Overview. 5.1.1 Features 5.1.2 Block Diagram. 5.1.3 Configuration. 5.1.4 Register Configuration. Register Descriptions 5.2.1 System Control Register (SYSCR). 5.2.2 Interrupt Priority Registers (IPRA IPRK) 5.2.3 Enable Register (IER) 5.2.4 Sense Control Registers (ISCRH, ISCRL) 5.2.5 Status Register (ISR) Interrupt Sources. 5.3.1 External Interrupts 5.3.2 Internal Interrupts. 5.3.3 Interrupt Exception Handling Vector Table Interrupt Operation. 5.4.1 Interrupt Control Modes Interrupt Operation 5.4.2 Interrupt Control Mode 5.4.3 Interrupt Control Mode 5.4.4 Interrupt Exception Handling Sequence 5.4.5 Interrupt Response Times Usage Notes 5.5.1 Contention between Interrupt Generation Disabling 5.5.2 Instructions that Disable Interrupts. 5.5.3 Times when Interrupts Disabled 5.5.4 Interrupts during Execution EEPMOV Instruction Activation Interrupt. 5.6.1 Overview. 5.6.2 Block Diagram. 5.6.3 Operation Controller Overview. 6.1.1 Features 6.1.2 Block Diagram. 6.1.3 Configuration.
Section
6.1.4 Register Configuration. Register Descriptions 6.2.1 Width Control Register (ABWCR) 6.2.2 Access State Control Register (ASTCR). 6.2.3 Wait Control Registers (WCRH, WCRL) 6.2.4 Control Register (BCRH) 6.2.5 Control Register (BCRL) Overview Control 6.3.1 Area Partitioning. 6.3.2 Specifications 6.3.3 Memory Interfaces. 6.3.4 Advanced Mode. 6.3.5 Areas Normal Mode (ZTAT, Mask ROM, ROMless versions Only) 6.3.6 Chip Select Signals Basic Interface 6.4.1 Overview. 6.4.2 Data Size Data Alignment. 6.4.3 Valid Strobes 6.4.4 Basic Timing. 6.4.5 Wait Control. Burst Interface. 6.5.1 Overview. 6.5.2 Basic Timing. 6.5.3 Wait Control. Idle Cycle 6.6.1 Operation 6.6.2 States Idle Cycle Release. 6.7.1 Overview. 6.7.2 Operation 6.7.3 States External Released State 6.7.4 Transition Timing 6.7.5 Usage Note. Arbitration. 6.8.1 Overview. 6.8.2 Operation 6.8.3 Transfer Timing 6.8.4 External Release Usage Note Resets Controller.
Section
Data Transfer Controller Overview. 7.1.1 Features 7.1.2 Block Diagram. 7.1.3 Register Configuration. Register Descriptions 7.2.1 Mode Register (MRA) 7.2.2 Mode Register (MRB). 7.2.3 Source Address Register (SAR) 7.2.4 Destination Address Register (DAR) 7.2.5 Transfer Count Register (CRA) 7.2.6 Transfer Count Register (CRB). 7.2.7 Enable Registers (DTCER). 7.2.8 Vector Register (DTVECR) 7.2.9 Module Stop Control Register (MSTPCR). Operation. 7.3.1 Overview. 7.3.2 Activation Sources. 7.3.3 Vector Table 7.3.4 Location Register Information Address Space. 7.3.5 Normal Mode. 7.3.6 Repeat Mode 7.3.7 Block Transfer Mode. 7.3.8 Chain Transfer 7.3.9 Operation Timing. 7.3.10 Number Execution States 7.3.11 Procedures Using DTC. 7.3.12 Examples DTC. Interrupts Usage Notes
Section
Ports
Overview. Port 8.2.1 Overview. 8.2.2 Register Configuration. 8.2.3 Functions Port 8.3.1 Overview. 8.3.2 Register Configuration. 8.3.3 Functions Port 8.4.1 Overview.
8.4.2 Register Configuration. 8.4.3 Functions Port 8.5.1 Overview. 8.5.2 Register Configuration. 8.5.3 Functions Port 8.6.1 Overview. 8.6.2 Register Configuration. 8.6.3 Functions 8.6.4 Input Pull-Up Function. Port 8.7.1 Overview 8.7.2 Register Configuration. 8.7.3 Functions 8.7.4 Input Pull-Up Function. Port 8.8.1 Overview. 8.8.2 Register Configuration. 8.8.3 Functions 8.8.4 Input Pull-Up Function. Port 8.9.1 Overview. 8.9.2 Register Configuration. 8.9.3 Functions 8.9.4 Input Pull-Up Function. 8.10 Port 8.10.1 Overview. 8.10.2 Register Configuration. 8.10.3 Functions 8.10.4 Input Pull-Up Function 8.11 Port 8.11.1 Overview. 8.11.2 Register Configuration. 8.11.3 Functions 8.12 Port 8.12.1 Overview. 8.12.2 Register Configuration. 8.12.3 Functions
Section
16-Bit Timer Pulse Unit (TPU) Overview. 9.1.1 Features
9.1.2 Block Diagram. 9.1.3 Configuration. 9.1.4 Register Configuration. Register Descriptions 9.2.1 Timer Control Register (TCR). 9.2.2 Timer Mode Register (TMDR). 9.2.3 Timer Control Register (TIOR). 9.2.4 Timer Interrupt Enable Register (TIER). 9.2.5 Timer Status Register (TSR) 9.2.6 Timer Counter (TCNT). 9.2.7 Timer General Register (TGR) 9.2.8 Timer Start Register (TSTR) 9.2.9 Timer Synchro Register (TSYR) 9.2.10 Module Stop Control Register (MSTPCR). Interface Master. 9.3.1 16-Bit Registers 9.3.2 8-Bit Registers Operation. 9.4.1 Overview. 9.4.2 Basic Functions. 9.4.3 Synchronous Operation 9.4.4 Buffer Operation 9.4.5 Cascaded Operation 9.4.6 Modes 9.4.7 Phase Counting Mode Interrupts 9.5.1 Interrupt Sources Priorities 9.5.2 Activation 9.5.3 Converter Activation. Operation Timing 9.6.1 Input/Output Timing 9.6.2 Interrupt Signal Timing Usage Notes
Section 8-Bit Timers.
10.1 Overview. 10.1.1 Features 10.1.2 Block Diagram. 10.1.3 Configuration. 10.1.4 Register Configuration. 10.2 Register Descriptions 10.2.1 Timer Counters (TCNT0, TCNT1). 10.2.2 Time Constant Registers (TCORA0, TCORA1).
10.3
10.4
10.5 10.6
10.2.3 Time Constant Registers (TCORB0, TCORB1) 10.2.4 Time Control Registers (TCR0, TCR1) 10.2.5 Timer Control/Status Registers (TCSR0, TCSR1) 10.2.6 Module Stop Control Register (MSTPCR). Operation. 10.3.1 TCNT Incrementation Timing. 10.3.2 Compare Match Timing. 10.3.3 Timing External RESET TCNT 10.3.4 Timing Overflow Flag (OVF) Setting. 10.3.5 Operation with Cascaded Connection Interrupts 10.4.1 Interrupt Sources Activation 10.4.2 Converter Activation. Sample Application. Usage Notes 10.6.1 Contention between TCNT Write Clear 10.6.2 Contention between TCNT Write Increment. 10.6.3 Contention between TCOR Write Compare Match 10.6.4 Contention between Compare Matches 10.6.5 Switching Internal Clocks TCNT Operation 10.6.6 Usage Note.
Section Watchdog Timer.
11.1 Overview. 11.1.1 Features 11.1.2 Block Diagram. 11.1.3 Configuration. 11.1.4 Register Configuration. 11.2 Register Descriptions 11.2.1 Timer Counter (TCNT). 11.2.2 Timer Control/Status Register (TCSR) 11.2.3 Reset Control/Status Register (RSTCSR) 11.2.4 Notes Register Access. 11.3 Operation. 11.3.1 Watchdog Timer Operation 11.3.2 Interval Timer Operation 11.3.3 Timing Setting Overflow Flag (OVF). 11.3.4 Timing Setting Watchdog Timer Overflow Flag (WOVF). 11.4 Interrupts 11.5 Usage Notes 11.5.1 Contention between Timer Counter (TCNT) Write Increment. 11.5.2 Changing Value CKS2 CKS0 11.5.3 Switching between Watchdog Timer Mode Interval Timer Mode.
viii
11.5.4 System Reset WDTOVF Signal 11.5.5 Internal Reset Watchdog Timer Mode
Section Serial Communication Interface (SCI)
12.1 Overview. 12.1.1 Features 12.1.2 Block Diagram. 12.1.3 Configuration. 12.1.4 Register Configuration. 12.2 Register Descriptions 12.2.1 Receive Shift Register (RSR) 12.2.2 Receive Data Register (RDR). 12.2.3 Transmit Shift Register (TSR). 12.2.4 Transmit Data Register (TDR). 12.2.5 Serial Mode Register (SMR) 12.2.6 Serial Control Register (SCR) 12.2.7 Serial Status Register (SSR) 12.2.8 Rate Register (BRR) 12.2.9 Smart Card Mode Register (SCMR). 12.2.10 Module Stop Control Register (MSTPCR). 12.3 Operation. 12.3.1 Overview. 12.3.2 Operation Asynchronous Mode. 12.3.3 Multiprocessor Communication Function 12.3.4 Operation Clocked Synchronous Mode. 12.4 Interrupts 12.5 Usage Notes
Section Smart Card Interface
13.1 Overview. 13.1.1 Features 13.1.2 Block Diagram. 13.1.3 Configuration. 13.1.4 Register Configuration. 13.2 Register Descriptions 13.2.1 Smart Card Mode Register (SCMR). 13.2.2 Serial Status Register (SSR) 13.2.3 Serial Mode Register (SMR) 13.2.4 Serial Control Register (SCR) 13.3 Operation. 13.3.1 Overview. 13.3.2 Connections 13.3.3 Data Format
13.3.4 Register Settings 13.3.5 Clock 13.3.6 Data Transfer Operations. 13.3.7 Operation Mode 13.4 Usage Note
Section Converter.
14.1 Overview. 14.1.1 Features 14.1.2 Block Diagram. 14.1.3 Configuration. 14.1.4 Register Configuration. 14.2 Register Descriptions 14.2.1 Data Registers (ADDRA ADDRD). 14.2.2 Control/Status Register (ADCSR) 14.2.3 Control Register (ADCR) 14.2.4 Module Stop Control Register (MSTPCR). 14.3 Interface Master. 14.4 Operation. 14.4.1 Single Mode (SCAN 14.4.2 Scan Mode (SCAN 14.4.3 Input Sampling Conversion Time 14.4.4 External Trigger Input Timing. 14.5 Interrupts 14.6 Usage Notes
Section Converter.
15.1 Overview. 15.1.1 Features 15.1.2 Block Diagram. 15.1.3 Configuration. 15.1.4 Register Configuration. 15.2 Register Descriptions 15.2.1 Data Registers (DADR0, DADR1). 15.2.2 Control Register (DACR) 15.2.3 Module Stop Control Register (MSTPCR). 15.3 Operation. 15.4 Usage Notes
Section RAM.
16.1 Overview. 16.1.1 Block Diagram. 16.1.2 Register Configuration.
16.2 Register Descriptions 16.2.1 System Control Register (SYSCR). 16.3 Operation. 16.4 Usage Note
Section ROM.
17.1 Overview. 17.1.1 Block Diagram. 17.1.2 Register Configuration. 17.2 Register Descriptions 17.2.1 Mode Control Register (MDCR) 17.2.2 Control Register (BCRL) 17.3 Operation. 17.4 PROM Mode. 17.4.1 PROM Mode Setting 17.4.2 Socket Adapter Memory Map. 17.5 Programming. 17.5.1 Overview. 17.5.2 Programming Verification 17.5.3 Programming Precautions. 17.5.4 Reliability Programmed Data 17.6 Overview Flash Memory 17.6.1 Features 17.6.2 Block Diagram. 17.6.3 Flash Memory Operating Modes 17.6.4 Configuration. 17.6.5 Register Configuration. 17.7 Register Descriptions 17.7.1 Flash Memory Control Register (FLMCR1) 17.7.2 Flash Memory Control Register (FLMCR2) 17.7.3 Erase Block Registers (EBR1, EBR2) 17.7.4 System Control Register (SYSCR2). 17.7.5 Emulation Register (RAMER). 17.8 On-Board Programming Modes. 17.8.1 Boot Mode 17.8.2 User Program Mode. 17.9 Programming/Erasing Flash Memory. 17.9.1 Program Mode 17.9.2 Program-Verify Mode 17.9.3 Erase Mode 17.9.4 Erase-Verify Mode. 17.10 Flash Memory Protection. 17.10.1 Hardware Protection
17.11
17.12 17.13
17.14 17.15
17.10.2 Software Protection 17.10.3 Error Protection Flash Memory Emulation 17.11.1 Emulation RAM. 17.11.2 Overlap. Interrupt Handling when Programming/Erasing Flash Memory Flash Memory Writer Mode 17.13.1 Writer Mode Setting 17.13.2 Socket Adapters Memory 17.13.3 Writer Mode Operation. 17.13.4 Memory Read Mode 17.13.5 Auto-Program Mode 17.13.6 Auto-Erase Mode. 17.13.7 Status Read Mode 17.13.8 Status Polling 17.13.9 Writer Mode Transition Time. 17.13.10 Notes Memory Programming. Flash Memory Programming Erasing Precautions. Notes when Converting F-ZTAT Application Software Mask-ROM Versions
Section Clock Pulse Generator
18.1 Overview. 18.1.1 Block Diagram. 18.1.2 Register Configuration. 18.2 Register Descriptions 18.2.1 System Clock Control Register (SCKCR). 18.3 Oscillator. 18.3.1 Connecting Crystal Resonator 18.3.2 External Clock Input 18.4 Duty Adjustment Circuit. 18.5 Medium-Speed Clock Divider 18.6 Master Clock Selection Circuit.
Section Power-Down Modes
19.1 Overview. 19.1.1 Register Configuration. 19.2 Register Descriptions 19.2.1 Standby Control Register (SBYCR) 19.2.2 System Clock Control Register (SCKCR). 19.2.3 Module Stop Control Register (MSTPCR). 19.3 Medium-Speed Mode. 19.4 Sleep Mode 19.5 Module Stop Mode
19.5.1 Module Stop Mode 19.5.2 Usage Notes 19.6 Software Standby Mode. 19.6.1 Software Standby Mode. 19.6.2 Clearing Software Standby Mode. 19.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode 19.6.4 Software Standby Mode Application Example 19.6.5 Usage Notes 19.7 Hardware Standby Mode 19.7.1 Hardware Standby Mode 19.7.2 Hardware Standby Mode Timing. 19.8 Clock Output Disabling Function
Section Electrical Characteristics
20.1 Electrical Characteristics F-ZTAT Version. 20.1.1 Absolute Maximum Ratings 20.1.2 Characteristics 20.1.3 Characteristics 20.1.4 Conversion Characteristics 20.1.5 Conversion Characteristics 20.1.6 Flash Memory Characteristics 20.2 Electrical Characteristics ZTAT, Mask ROM, On-chip Versions. 20.2.1 Absolute Maximum Ratings 20.2.2 Characteristics 20.2.3 Characteristics. 20.2.4 Conversion Characteristics 20.2.5 Conversion Characteristics 20.3 Operation Timing 20.3.1 Clock Timing 20.3.2 Control Signal Timing 20.3.3 Timing 20.3.4 Timing On-Chip Supporting Modules 20.4 Usage Note
Appendix Instruction
Instruction List Instruction Codes Operation Code Map. Number States Required Instruction Execution. States During Instruction Execution Condition Code Modification
xiii
Appendix Internal Register
Addresses Functions.
Appendix Port Block Diagrams
C.10 C.11 Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagram. Port Block Diagram. Port Block Diagram. Port Block Diagram. Port Block Diagram. Port Block Diagram Port Block Diagram.
Appendix States
Port States Each Mode
Appendix Appendix
Timing Transition Recovery from Hardware Standby Mode Product Code Lineup
Appendix Package Dimensions
Section Overview
Overview
H8S/2345 Series series microcomputers (MCUs: microcomputer units), built around H8S/2000 CPU, employing Hitachi's proprietary architecture, equipped with peripheral functions on-chip. H8S/2000 internal 32-bit architecture, provided with sixteen 16-bit general registers concise, optimized instruction designed high-speed operation, address 16-Mbyte linear address space. instruction upward-compatible with H8/300 H8/300H instructions object-code level, facilitating migration from H8/300, H8/300L, H8/300H Series. On-chip peripheral functions required system configuration include data transfer controller (DTC) masters, memory, a16-bit timer-pulse unit (TPU), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports. on-chip ROM*1 either single power supply flash memory (F-ZTATTM*2), PROM (ZTAT*2), mask ROM, with capacity 128, kbytes. connected 16-bit data bus, enabling both byte word data accessed state. Instruction fetching been speeded processing speed increased. Seven operating modes, modes provided, there choice address space single-chip mode external expansion mode. features H8S/2345 Series shown Table 1.1. Notes: H8S/2345, H8S/2344, H8S/2343, H8S/2341 have on-chip ROM. H8S/2340 does have on-chip ROM. F-ZTATis trademark Hitachi, Ltd. ZTAT trademark Hitachi, Ltd.
Table
Item
Overview
Specification General-register machine Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) High-speed operation suitable realtime control Maximum clock rate: High-speed arithmetic operations 8/16/32-bit register-register add/subtract 16-bit register-register multiply 1000 16-bit register-register divide 1000 Instruction suitable high-speed operation Sixty-five basic instructions 8/16/32-bit move/arithmetic logic instructions Unsigned/signed multiply divide instructions Powerful bit-manipulation instructions operating modes Normal mode: 64-kbyte address space (ZTAT, mask ROM, ROMless versions only) Advanced mode: 16-Mbyte address space
controller
Address space divided into areas, with specifications settable independently each area Chip select output possible areas Choice 8-bit 16-bit access space each area 2-state 3-state access space designated each area Number program wait states each area Burst directly connectable External release function activated internal interrupt software Multiple transfers multiple types transfer possible activation source Transfer possible repeat mode, block transfer mode, etc. Request sent interrupt that activated 6-channel 16-bit timer on-chip Pulse processing capability pins' Automatic 2-phase encoder count capability
Data transfer controller (DTC)
16-bit timer-pulse unit (TPU)
Item 8-bit timer channels
Specification 8-bit up-counter (external event count capability) time constant registers Two-channel connection possible Watchdog timer interval timer selectable Asynchronous mode synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: bits Input: channels High-speed conversion: minimum conversion time operation) Single scan mode selectable Sample hold circuit conversion activated external trigger timer trigger Resolution: bits Output: channels pins, input-only pins Flash memory, PROM, mask High-speed static kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes
Watchdog timer Serial communication interface (SCI) channels converter
converter
ports Memory
Product Name H8S/2345 H8S/2344 H8S/2343 H8S/2341 H8S/2340 Interrupt controller
Nine external interrupt pins (NMI, IRQ0 IRQ7) internal interrupt sources Eight priority levels settable
Item Power-down state
Specification Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Eight operating modes (F-ZTAT version) External Data On-Chip Initial Value Maximum Value
Operating modes
Operating Mode Mode Description Advanced User-programmable mode Advanced Boot mode
Advanced On-chip disabled Disabled bits expansion mode bits On-chip enabled expansion mode Single-chip mode Enabled bits
bits bits bits
Enabled
bits
bits
Enabled
bits
bits
Item Operating modes
Specification Seven operating modes (ZTAT, mask ROM, ROMless versions) External Data On-Chip Initial Value Maximum Value bits bits
Operating Mode Mode Description Product lineup Mask Version HD6432345 HD6432344 HD6432343 HD6432341 HD6412340 (ROMless versions) Normal
On-chip disabled Disabled bits expansion mode On-chip enabled expansion mode Single-chip mode Enabled Enabled bits
Advanced On-chip disabled Disabled bits expansion mode On-chip disabled Disabled bits expansion mode On-chip enabled expansion mode Single-chip mode Enabled Enabled bits
bits bits bits
Note: used ROMless versions. Clock pulse generator Packages Built-in duty correction circuit 100-pin plastic TQFP (TFP-100B, TFP-100G) 100-pin plastic (FP-100A, FP-100B) Model Name F-ZTATHD64F2345 ZTATHD6472345 ROM/RAM (Bytes) Packages TFP-100B TFP-100G FP-100A FP-100B
Block Diagram
Figure shows internal block diagram H8S/2345 Series.
/D15 /D14 /D13 /D12 /D11 /D10 Port Port
H8S/2000
Internal address
Internal data
controller
EXTAL XTAL STBY WDTOVF (FWE)*1
Clock pulse generator
Port
/A19 /A18 /A17 /A16
Interrupt controller LWR/ IRQ3 WAIT/IRQ2 BACK/ IRQ1 BREQ/ IRQ0 CS3/IRQ7 ADTRG/IRQ6 ROM*2 Port
Peripheral address
Port
Peripheral data
/A15 /A14 /A13 /A12 /A10 /SCK1/IRQ5 /SCK0/IRQ4 /RxD1 /RxD0 /TxD1 /TxD0
Port Port
8-bit timer Port
converter
converter
Port
Port Vref AVCC AVSS
Port /AN7/DA1 /AN6/DA0 /AN5 /AN4 /AN3 /AN2 /AN1 /AN0
/TIOCA0/A /TIOCB0/A /TIOCC0/TCLKA/A22 /TIOCD0/TCLKB/A23 /TIOCA1 /TIOCB1/TCLKC /TIOCA2 /TIOCB2/TCLKD
Notes: Functions WDTOVF ZTAT, mask ROM, ROMless versions. Functions F-ZTAT version, WDTOVF pin. present ROMless version.
Figure Block Diagram
/TIOCA3 /TIOCB3 /TIOCC3/TMRI0 /TIOCD3/TMCI0 /TIOCA4/TMRI1 /TIOCB4/TMCI1 /TIOCA5/TMO0 /TIOCB5/TMO1
1.3.1
Description
Arrangement
Figures show arrangement H8S/2345 Series.
P23/TIOCD3/TMCI0 P22/TIOCC3/TMRI0
WDTOVF (FWE*)
PF1/BACK/IRQ1
PF2/WAIT/IRQ2
PF3/LWR/IRQ3
P21/TIOCB3
P20/TIOCA3
PF4/HWR
PA3/A19
PA2/A18
PF0/BREQ/IRQ0 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS P24/TIOCA4/TMRI1 P25/TIOCB4/TMCI1 P26/TIOCA5/TMO0 P27/TIOCB5/TMO1 PG0/ADTRG/IRQ6 PG1/CS3/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 P10/TIOCA0/A20 P11/TIOCB0/A21
PA1/A17
PF5/RD
PF6/AS
EXTAL
STBY
XTAL
PA0/A16 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11
P12/TIOCC0/TCLKA/A22
P13/TIOCD0/TCLKB/A23
P34/SCK0/IRQ4
P15/TIOCB1/TCLKC
P17/TIOCB2/TCLKD
P35/SCK1/IRQ5
P14/TIOCA1
P16/TIOCA2
P30/TxD0
P31/TxD1
P32/RxD0
P33/RxD1
Note: Functions WDTOVF ZTAT, mask ROM, ROMless versions. Functions F-ZTAT version, WDTOVF pin.
Figure Arrangement (FP-100B, TFP-100B, TFP-100G: View)
PD2/D10
PE0/D0
PE1/D1
PE2/D2
PE3/D3
PE4/D4
PE5/D5
PE6/D6
PE7/D7
PD0/D8
PD1/D9
P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS P24/TIOCA4/TMRI1 P25/TIOCB4/TMCI1 P26/TIOCA5/TMO0 P27/TIOCB5/TMO1 PG0/ADTRG/IRQ6 PG1/CS3/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 Note: Functions WDTOVF ZTAT, mask ROM, ROMless versions. Functions F-ZTAT version, WDTOVF pin. P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1 P15/TIOCB1/TCLKC P16/TIOCA2 P17/TIOCB2/TCLKD P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/IRQ4 P35/SCK1/IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD7/D15 PD6/D14
Figure Arrangement (FP-100A: View)
Vref AVCC PF0/BREQ/IRQ0 PF1/BACK/IRQ1 PF2/WAIT/IRQ2 PF3/LWR/IRQ3 PF4/HWR PF5/RD PF6/AS EXTAL XTAL STBY WDTOVF (FWE*) P23/TIOCD3/TMCI0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 PA3/A19 PA2/A18 PA1/A17 PA0/A16
1.3.2
Functions Each Operating Mode
Table shows functions H8S/2345 Series each operating modes. Table
FP-100B, TFP-100B, TFP-100G FP-100A
Functions Each Operating Mode
Name Flash Memory Writer Mode*
Mode TIOCC0/ TCLKA TIOCD0/ TCLKB TIOCA1 TIOCB1/ TCLKC TIOCA2 TIOCB2/ TCLKD 0/TxD0 1/TxD1
Mode TIOCC0/ TCLKA TIOCD0/ TCLKB TIOCA1 TIOCB1/ TCLKC TIOCA2 TIOCB2/ TCLKD 0/TxD0 1/TxD1
Mode TIOCC0/ TCLKA TIOCD0/ TCLKB TIOCA1 TIOCB1/ TCLKC TIOCA2 TIOCB2/ TCLKD 0/TxD0 1/TxD1
Mode TIOCC0/ TCLKA/ TIOCD0/ TCLKB/ TIOCA1 TIOCB1/ TCLKC TIOCA2 TIOCB2/ TCLKD 0/TxD0 1/TxD1
Mode TIOCC0/ TCLKA/ TIOCD0/ TCLKB/ TIOCA1 TIOCB1/ TCLKC TIOCA2 TIOCB2/ TCLKD 0/TxD0 1/TxD1
Mode TIOCC0/ TCLKA/ TIOCD0/ TCLKB/ TIOCA1 TIOCB1/ TCLKC TIOCA2 TIOCB2/ TCLKD 0/TxD0 1/TxD1
Mode TIOCC0/ TCLKA TIOCD0/ TCLKB TIOCA1 TIOCB1/ TCLKC TIOCA2 TIOCB2/ TCLKD 0/TxD0 1/TxD1
PROM Mode*
2/RxD0 2/RxD0 2/RxD0 2/RxD0 2/RxD0 2/RxD0 2/RxD0 3/RxD1 3/RxD1 3/RxD1 3/RxD1 3/RxD1 3/RxD1 3/RxD1 SCK0/ IRQ4 SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 SCK0/ IRQ4 SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 SCK0/ IRQ4 SCK1/ IRQ5 SCK0/ IRQ4 SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 SCK0/ IRQ4 SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 SCK0/ IRQ4 SCK1/ IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 SCK0/ IRQ4 SCK1/ IRQ5
FP-100B, TFP-100B, TFP-100G FP-100A
Name Flash Memory Writer Mode* FA10 FA11 FA12 FA13 FA14 FA15 FA16
Mode PE5/D5 PE6/D6 PE7/D7
Mode PE5/D5 PE6/D6 PE7/D7 0/A0 1/A1 2/A2 3/A3 4/A4 5/A5 6/A6 7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15
Mode
Mode PE5/D5 PE6/D6 PE7/D7
Mode PE5/D5 PE6/D6 PE7/D7
Mode PE5/D5 PE6/D6 PE7/D7 0/A0 1/A1 2/A2 3/A3 4/A4 5/A5 6/A6 7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17
Mode
PROM Mode* EA10 EA11 EA12 EA13 EA14 EA15 EA16
FP-100B, TFP-100B, TFP-100G FP-100A
Name Flash Memory Writer Mode*
Mode TIOCA3 TIOCB3 TIOCC3/ TMRI0 TIOCD3/ TMCI0
Mode TIOCA3 TIOCB3 TIOCC3/ TMRI0 TIOCD3/ TMCI0
Mode TIOCA3 TIOCB3 TIOCC3/ TMRI0 TIOCD3/ TMCI0
Mode TIOCA3 TIOCB3 TIOCC3/ TMRI0 TIOCD3/ TMCI0
Mode TIOCA3 TIOCB3 TIOCC3/ TMRI0 TIOCD3/ TMCI0
Mode PA2/A18 PA3/A19 TIOCA3 TIOCB3 TIOCC3/ TMRI0 TIOCD3/ TMCI0
Mode TIOCA3 TIOCB3 TIOCC3/ TMRI0 TIOCD3/ TMCI0
PROM Mode*
WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF (FWE* (FWE* (FWE* (FWE* STBY XTAL EXTAL PF2/ WAIT/ IRQ2 PF1/ BACK/ IRQ1 STBY XTAL EXTAL PF2/ WAIT/ IRQ2 PF1/ BACK/ IRQ1 STBY XTAL EXTAL PF3/IRQ3 PF2/IRQ2 STBY XTAL EXTAL PF2/ WAIT/ IRQ2 PF1/ BACK/ IRQ1 STBY XTAL EXTAL PF2/ WAIT/ IRQ2 PF1/ BACK/ IRQ1 STBY XTAL EXTAL PF2/ WAIT/ IRQ2 PF1/ BACK/ IRQ1 STBY XTAL EXTAL PF3/IRQ3 PF2/IRQ2
XTAL EXTAL
PF1/IRQ1
PF1/IRQ1
FP-100B, TFP-100B, TFP-100G FP-100A
Name Flash Memory Writer Mode*
Mode PF0/ BREQ/ IRQ0 AVCC 0/AN0 1/AN1 2/AN2 3/AN3 4/AN4 5/AN5 6/AN6/ 7/AN7/ AVSS TIOCA4/ TMRI1 TIOCB4/ TMCI1 TIOCA5/ TMO0 TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG
Mode PF0/ BREQ/ IRQ0 AVCC 0/AN0 1/AN1 2/AN2 3/AN3 4/AN4 5/AN5 6/AN6/ 7/AN7/ AVSS TIOCA4/ TMRI1 TIOCB4/ TMCI1 TIOCA5/ TMO0 TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG
Mode PF0/IRQ0
Mode PF0/ BREQ/ IRQ0 AVCC 0/AN0 1/AN1 2/AN2 3/AN3 4/AN4 5/AN5 6/AN6/ 7/AN7/ AVSS TIOCA4/ TMRI1 TIOCB4/ TMCI1 TIOCA5/ TMO0 TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG
Mode PF0/ BREQ/ IRQ0 AVCC 0/AN0 1/AN1 2/AN2 3/AN3 4/AN4 5/AN5 6/AN6/ 7/AN7/ AVSS TIOCA4/ TMRI1 TIOCB4/ TMCI1 TIOCA5/ TMO0 TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG PG1/CS3/ IRQ7 PG2/CS2 PG3/CS1 PG4/CS0
Mode PF0/ BREQ/ IRQ0 AVCC 0/AN0 1/AN1 2/AN2 3/AN3 4/AN4 5/AN5 6/AN6/ 7/AN7/ AVSS TIOCA4/ TMRI1 TIOCB4/ TMCI1 TIOCA5/ TMO0 TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG PG1/CS3/ IRQ7 PG2/CS2 PG3/CS1 PG4/CS0
Mode PF0/IRQ0
PROM Mode*
AVCC 0/AN0 1/AN1 2/AN2 3/AN3 4/AN4 5/AN5 6/AN6/ 7/AN7/ AVSS TIOCA4/ TMRI1 TIOCB4/ TMCI1 TIOCA5/ TMO0 TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG
AVCC 0/AN0 1/AN1 2/AN2 3/AN3 4/AN4 5/AN5 6/AN6/ 7/AN7/ AVSS TIOCA4/ TMRI1 TIOCB4/ TMCI1 TIOCA5/ TMO0 TIOCB5/ TMO1 PG0/ IRQ6/ ADTRG
PG1/IRQ7 PG1/IRQ7 PG1/IRQ7 PG1/CS3/ IRQ7 PG4/CS0 PG4/CS0 PG2/CS2 PG3/CS1 PG4/CS0
PG1/IRQ7
FP-100B, TFP-100B, TFP-100G FP-100A
Name Flash Memory Writer Mode*
Mode TIOCA0 TIOCB0
Mode TIOCA0 TIOCB0
Mode TIOCA0 TIOCB0
Mode TIOCA0/ TIOCB0/
Mode TIOCA0/ TIOCB0/
Mode TIOCA0/ TIOCB0/
Mode TIOCA0 TIOCB0
PROM Mode*
Notes:
Modes available F-ZTAT version. Modes available ROMless version. ZTAT version only. F-ZTAT version only. only used F-ZTAT version. cannot used WDTOVF F-ZTAT version.
1.3.3
Functions
Table outlines functions H8S/2345 Series. Table Functions
FP-100B, TFP-100B, TFP-100G FP-100A
Type Power
Symbol
Input
Name Function Power supply: connection power supply. pins should connected system power supply. Ground: connection ground pins should connected system power supply Connects crystal oscillator. section Clock Pulse Generator, typical connection diagrams crystal oscillator external clock input. Connects crystal oscillator. EXTAL also input external clock. section Clock Pulse Generator, typical connection diagrams crystal oscillator external clock input.
Input
Clock
XTAL
Input
EXTAL
Input
Output System clock: Supplies system clock external device.
FP-100B, TFP-100B, TFP-100G FP-100A
Type
Symbol
Input
Name Function Mode pins: These pins operating mode. relation between settings pins operating mode shown below. These pins should changed while H8S/2345 Series operating. F-ZTAT Version Operating Mode Mode Mode Mode Mode Mode Mode Mode Mode
Operating mode control
FP-100B, TFP-100B, TFP-100G FP-100A
Type
Symbol
Input
Name Function ZTAT, mask ROM, ROMless versions Operating Mode Mode Mode Mode Mode Mode Mode Mode
Operating mode control
Note: used ROMless version. System control Input Reset input: When this driven low, chip reset. type reset selected according input level. power-on, input level should high. Standby: When this driven low, transition made hardware standby mode. request: Used external master issue request H8S/2345 Series.
STBY
Input
BREQ
Input
BACK
Output request acknowledge: Indicates that been released external master. Input Flash write enable: Enables disables writing flash memory.
FWE*
FP-100B, TFP-100B, TFP-100G FP-100A
Type Interrupts
Symbol
Input
Name Function Nonmaskable interrupt: Requests nonmaskable interrupt. When this used, should fixed high. Interrupt request These pins request maskable interrupt.
IRQ7 IRQ0 Address
100,
Input
Output Address bus: These pins output address.
Data control
Data bus: These pins constitute bidirectional data bus.
Output Chip select: Signals selecting areas Output Address strobe: When this low, indicates that address output address enabled. Output Read: When this low, indicates that external address space read. Output High write: strobe signal that writes external space indicates that upper half (D15 data enabled. Output write: strobe signal that writes external space indicates that lower half data enabled. Input Wait: Requests insertion wait state cycle when accessing external 3-state address space.
WAIT
FP-100B, TFP-100B, TFP-100G FP-100A
Type 16-bit timerpulse unit (TPU)
Symbol TCLKD TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1
Input
Name Function Clock input These pins input external clock. Input capture/ output compare match TGR0A TGR0D input capture input output compare output, output pins. Input capture/ output compare match TGR1A TGR1B input capture input output compare output, output pins. Input capture/ output compare match TGR2A TGR2B input capture input output compare output, output pins. Input capture/ output compare match TGR3A TGR3D input capture input output compare output, output pins. Input capture/ output compare match TGR4A TGR4B input capture input output compare output, output pins. Input capture/ output compare match TGR5A TGR5B input capture input output compare output, output pins.
100,
TIOCA2, TIOCB2
TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4
TIOCA5, TIOCB5
8-bit timer
TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1
Output Compare match output: compare match output pins. Input Counter external clock input: Input pins external clock input counter. Counter external reset input: counter reset input pins.
Input
Watchdog timer (WDT)
WDTOVF*
Output Watchdog timer overflows: counter overflows signal output watchdog timer mode.
FP-100B, TFP-100B, TFP-100G FP-100A
Type Serial communication interface (SCI) Smart Card interface
Symbol TxD1, TxD0 RxD1, RxD0 SCK1 SCK0 ADTRG
Name Function
Output Transmit data (channel Data output pins. Input Input Input Receive data (channel Data input pins. Serial clock (channel Clock pins. Analog Analog input pins. conversion external trigger input: input external trigger start conversion.
converter
converter converter converters
DA1, AVCC
Output Analog output: converter analog output pins. Input This power supply converter converter. When converter converter used, this should connected system power supply This ground converter converter. This should connected system power supply This reference voltage input converter converter. When converter converter used, this should connected system power supply Port 8-bit port. Input output designated each means port data direction register (P1DDR). Port 8-bit port. Input output designated each means port data direction register (P2DDR).
AVSS
Input
Vref
Input
ports
100,
FP-100B, TFP-100B, TFP-100G FP-100A
Type ports
Symbol
Name Function Port 6-bit port. Input output designated each means port data direction register (P3DDR). Port 8-bit input port. Port 4-bit port. Input output designated each means port data direction register (PADDR). Port 8-bit port. Input output designated each means port data direction register (PBDDR). Port 8-bit port. Input output designated each means port data direction register (PCDDR). Port 8-bit port. Input output designated each means port data direction register (PDDDR). Port 8-bit port. Input output designated each means port data direction register (PEDDR). Port 8-bit port. Input output designated each means port data direction register (PFDDR). Port 5-bit port. Input output designated each means port data direction register (PGDDR).
Input
Notes: F-ZTAT version only. Applies ZTAT, mask ROM, ROMless versions only.
Section
Overview
H8S/2000 high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 H8/300H CPUs. H8S/2000 sixteen 16-bit general registers, address 16-Mbyte (architecturally 4-Gbyte) linear address space, ideal realtime control. 2.1.1 Features
H8S/2000 following features. Upward-compatible with H8/300 H8/300H CPUs execute H8/300 H8/300H object programs General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) Sixty-five basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) @(d:32,ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, @aa:32] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8,PC) @(d:16,PC)] Memory indirect [@@aa:8] 16-Mbyte address space Program: Mbytes Data: Mbytes Gbytes architecturally)
High-speed operation frequently-used instructions execute states Maximum clock rate 8/16/32-bit register-register add/subtract 8-bit register-register multiply 8-bit register-register divide 16-bit register-register multiply 1000 16-bit register-register divide 1000 operating modes Normal mode (Supported ZTAT, mask ROM, ROMless versions only) Advanced mode Power-down state Transition power-down state SLEEP instruction clock speed selection 2.1.2 Differences between H8S/2600 H8S/2000
differences between H8S/2600 H8S/2000 shown below. Register configuration register supported only H8S/2600 CPU. Basic instructions four instructions MAC, CLRMAC, LDMAC, STMAC supported only H8S/2600 CPU. Number execution states number execution states MULXU MULXS instructions.
Internal Operation Instruction MULXU Mnemonic MULXU.B MULXU.W MULXS MULXS.B MULXS.W H8S/2600 H8S/2000
There also differences address space, register functions, power-down state, etc., depending product.
2.1.3
Differences from H8/300
comparison H8/300 CPU, H8S/2000 following enhancements. More general registers control registers Eight 16-bit expanded registers, 8-bit control register, have been added. Expanded address space Normal mode supports same 64-kbyte address space H8/300 CPU. (ZTAT, mask ROM, ROMless versions only) Advanced mode supports maximum 16-Mbyte address space. Enhanced addressing addressing modes have been enhanced make effective 16-Mbyte address space. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Signed multiply divide instructions have been added. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast. 2.1.4 Differences from H8/300H
comparison H8/300H CPU, H8S/2000 following enhancements. Additional control register 8-bit control register been added. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast.
Operating Modes
H8S/2000 operating modes: normal advanced. Normal mode supports maximum 64-kbyte address space. Advanced mode supports maximum 16-Mbyte total address space (architecturally maximum 16-Mbyte program area maximum Gbytes program data areas combined). mode selected mode pins microcontroller.
Maximum kbytes, program data areas combined
Normal mode
(Supported ZTAT, mask ROM, ROMless versions only) operating modes
Advanced mode
Maximum 16-Mbytes program data areas combined
Figure Operating Modes Normal Mode (ZTAT, Mask ROM, ROMless Versions Only) exception vector table stack have same structure H8/300 CPU. Address Space: maximum address space kbytes accessed. Extended Registers (En): extended registers used 16-bit registers, upper 16-bit segments 32-bit registers. When used 16-bit register contain value, even when corresponding general register (Rn) used address register. general register referenced register indirect addressing mode with pre-decrement (@-Rn) post-increment (@Rn+) carry borrow occurs, however, value corresponding extended register (En) will affected. Instruction Set: instructions addressing modes used. Only lower bits effective addresses (EA) valid.
Exception Vector Table Memory Indirect Branch Addresses: normal mode area starting H'0000 allocated exception vector table. branch address stored bits. configuration exception vector table normal mode shown figure 2.2. details exception vector table, section Exception Handling.
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Power-on reset exception vector Manual reset exception vector
(Reserved system use)
Exception vector table
Exception vector Exception vector
Figure Exception Vector Table (Normal Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. normal mode operand 16-bit word operand, providing 16bit branch address. Branch addresses stored area from H'0000 H'00FF. Note that this area also used exception vector table.
Stack Structure: When program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 2.3. When invalid, pushed onto stack. details, section Exception Handling.
bits)
EXR*1 Reserved*1,*3 CCR*3 bits)
Subroutine Branch
Exception Handling
Notes: When used stored stack. when used. Ignored when returning.
Figure Stack Structure Normal Mode Advanced Mode Address Space: Linear access provided 16-Mbyte maximum address space (architecturally maximum 16-Mbyte program area maximum 4-Gbyte data area, with maximum Gbytes program data areas combined). Extended Registers (En): extended registers used 16-bit registers, upper 16-bit segments 32-bit registers address registers. Instruction Set: instructions addressing modes used.
Exception Vector Table Memory Indirect Branch Addresses: advanced mode area starting H'00000000 allocated exception vector table units bits. each bits, upper bits ignored branch address stored lower bits (figure 2.4). details exception vector table, section Exception Handling.
H'00000000
Reserved Power-on reset exception vector
H'00000003 H'00000004 Reserved Manual reset exception vector H'00000007 H'00000008 Exception vector table
H'0000000B H'0000000C
(Reserved system use)
H'00000010
Reserved Exception vector
Figure Exception Vector Table (Advanced Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. advanced mode operand 32-bit longword operand, providing 32-bit branch address. upper bits these bits reserved area that regarded H'00. Branch addresses stored area from H'00000000 H'000000FF. Note that first part this range also exception vector table.
Stack Structure: advanced mode, when program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 2.5. When invalid, pushed onto stack. details, section Exception Handling.
Reserved bits)
EXR*1 Reserved*1,*3 bits)
Subroutine Branch
Exception Handling
Notes: When used stored stack. when used. Ignored when returning.
Figure Stack Structure Advanced Mode
Address Space
Figure shows memory H8S/2000 CPU. H8S/2000 provides linear access maximum 64-kbyte address space normal mode*, maximum 16-Mbyte (architecturally 4-Gbyte) address space advanced mode.
H'0000 H'00000000
H'FFFF
Program area
H'00FFFFFF
Data area
Cannot used H8S/2345 Series
H'FFFFFFFF Normal Mode* Advanced Mode
Figure Memory Note: ZTAT, mask ROM, ROMless versions only.
2.4.1
Register Configuration
Overview
internal registers shown figure 2.7. There types registers: general registers control registers.
General Registers (Rn) Extended Registers (En) (SP) Control Registers (CR) Legend EXR: CCR:
Stack pointer Program counter Extended control register Trace Interrupt mask bits Condition-code register Interrupt mask User interrupt mask bit*
Half-carry flag User Negative flag Zero flag Overflow flag Carry flag
Note: H8S/2345 Series, this cannot used interrupt mask.
Figure Registers
2.4.2
General Registers
eight 32-bit general registers. These general registers functionally alike used both address registers data registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. Figure illustrates usage general registers. usage each register selected independently.
Address registers 32-bit registers
16-bit registers registers (extended registers)
8-bit registers
registers (ER0 ER7) registers
registers (R0H R7H)
registers (R0L R7L)
Figure Usage General Registers
General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Free area
(ER7)
Stack area
Figure Stack 2.4.3 Control Registers
control registers 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR). Program Counter (PC): This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word), least significant ignored. (When instruction fetched, least significant regarded Extended Control Register (EXR): This 8-bit register contains trace three interrupt mask bits I0). 7-Trace (T): Selects trace mode. When this cleared instructions executed sequence. When this trace exception generated each time instruction executed. Bits 3-Reserved: These bits reserved. They always read
Bits 0-Interrupt Mask Bits I0): These bits designate interrupt mask level details, refer section Interrupt Controller. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. interrupts, including NMI, disabled three states after these instructions executed, except STC. Condition-Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. 7-Interrupt Mask (I): Masks interrupts other than when (NMI accepted regardless setting.) hardware start exceptionhandling sequence. details, refer section Interrupt Controller. 6-User Interrupt Mask (UI): written read software using LDC, STC, ANDC, ORC, XORC instructions. With H8S/2345 Series, this cannot used interrupt mask bit. 5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise. 4-User (U): written read software using LDC, STC, ANDC, ORC, XORC instructions. 3-Negative Flag (N): Stores value most significant (sign bit) data. 2-Zero Flag (Z): indicate zero data, cleared indicate non-zero data. 1-Overflow Flag (V): when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, store value shifted carry flag also used accumulator manipulation instructions.
Some instructions leave some flag bits unchanged. action each instruction flag bits, refer Appendix A.1, List Instructions. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. flags used branching conditions conditional branch (Bcc) instructions. 2.4.4 Initial Register Values
Reset exception handling loads CPU's program counter (PC) from vector table, clears trace sets interrupt mask bits other bits general registers initialized. particular, stack pointer (ER7) initialized. stack pointer should therefore initialized MOV.L instruction executed immediately after reset.
Data Formats
process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data. 2.5.1 General Register Data Formats
Figure 2.10 shows data formats general registers.
Data Type Register Number Data Format
1-bit data
Don't care
1-bit data
Don't care
4-bit data
Upper
Lower
Don't care
4-bit data
Don't care
Upper
Lower
Byte data
Don't care Don't care
Byte data
Figure 2.10 General Register Data Formats
Data Type
Register Number
Data Format
Word data
Word data Longword data
Legend ERn: General register General register General register RnH: General register RnL: General register MSB: Most significant LSB: Least significant
Figure 2.10 General Register Data Formats (cont)
2.5.2
Memory Data Formats
Figure 2.11 shows data formats memory. access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches.
Data Type Address 1-bit data Address Data Format
Byte data
Address
Word data
Address Address
Longword data
Address Address Address Address
Figure 2.11 Memory Data Formats When used address register access stack, operand size should word size longword size.
2.6.1
Instruction
Overview
H8S/2000 types instructions. instructions classified function table 2.1. Table
Function Data transfer
Instruction Classification
Instructions POP* PUSH* LDM, SMOVFPE, MOVTPE*
Size
Types
Arithmetic operations
ADD, SUB, CMP, ADDX, SUBX, DAA, INC, ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS
Logic operations Shift manipulation Branch System control Block data transfer
AND, XOR,
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* JMP, BSR, JSR,
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV
Notes: B-byte size; W-word size; L-longword size. POP.W PUSH.W identical MOV.W @SP+, MOV.W @-SP. POP.L PUSH.L identical MOV.L @SP+, MOV.L ERn, @-SP. general name conditional branch instructions. Cannot used H8S/2345 Series.
2.6.2
Instructions Addressing Modes
Table indicates combinations instructions addressing modes that H8S/2600 use. Table Combinations Instructions Addressing Modes
Addressing Modes @-ERn/@ERn+
@(d:16,ERn)
@(d:32,ERn)
@(d:8,PC)
@@aa:8
Function
Instruction @ERn
@(d:16,PC)
@aa:16
@aa:24
@aa:32
@aa:8
Data transfer
POP, PUSH LDM, SMOVFPE*, MOVTPE*
Arithmetic operations
ADD, ADDX, SUBX ADDS, SUBS INC, DAA, MULXU, DIVXU MULXS, DIVXS EXTU, EXTS
Logic operations
AND,
Shift manipulation Branch Bcc, JMP,
Addressing Modes @-ERn/@ERn+
@(d:16,ERn)
@(d:32,ERn)
@(d:8,PC)
@@aa:8
Function
Instruction @ERn
@(d:16,PC)
@aa:16
@aa:24
@aa:32
@aa:8
System control
TRAPA SLEEP ANDC, ORC, XORC
Block data transfer
Legend: Byte Word Longword Note: Cannot used H8S/2345 Series.
2.6.3
Table Instructions Classified Function
Table summarizes instructions each functional category. notation used table defined below.
Operation Notation (EAd) (EAs) #IMM disp :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical Logical Logical exclusive Move (logical complement) 16-, 24-, 32-bit length
Note: General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit registers (ER0 ER7).
Table
Type Data transfer
Instructions Classified Function
Instruction Size* B/W/L Function (EAs) (Ead) Moves data between general registers between general register memory, moves immediate data general register. Cannot used H8S/2345 Series. Cannot used H8S/2345 Series. @SP+ Pops register from stack. POP.W identical MOV.W @SP+, POP.L identical MOV.L @SP+, ERn. @-SP Pushes register onto stack. PUSH.W identical MOV.W @-SP. PUSH.L identical MOV.L ERn, @-SP. @SP+ (register list) Pops more general registers from stack. (register list) @-SP Pushes more general registers onto stack. #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from byte data general register. SUBX instruction.) #IMM Performs addition subtraction with carry borrow byte data general registers, immediate data data general register. Increments decrements general register (Byte operands incremented decremented only.) Adds subtracts value from data 32-bit register.
MOVFPE MOVTPE
PUSH
SArithmetic operations
B/W/L
ADDX SUBX
B/W/L
ADDS SUBS
Type Arithmetic operations
Instruction
Size*
Function decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4-bit data. Performs unsigned multiplication data general registers: either bits bits bits bits bits bits. Performs signed multiplication data general registers: either bits bits bits bits bits bits. Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16bit remainder. Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16bit remainder. #IMM Compares data general register with data another general register with immediate data, sets bits according result. Takes two's complement (arithmetic complement) data general register. (zero extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, padding with zeros left. (sign extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, extending sign bit. @ERd (<bit @Erd) Tests memory contents, sets most significant (bit
MULXU
MULXS
DIVXU
DIVXS
B/W/L
B/W/L
EXTU
EXTS
Type Logic operations
Instruction
Size* B/W/L
Function #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical exclusive operation general register another general register immediate data. (Rd) (Rd) Takes one's complement general register contents. (shift) Performs arithmetic shift general register contents. 1-bit 2-bit shift possible. (shift) Performs logical shift general register contents. 1-bit 2-bit shift possible. (rotate) Rotates general register contents. 1-bit 2-bit rotation possible. (rotate) Rotates general register contents through carry flag. 1-bit 2-bit rotation possible. (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register.
B/W/L
B/W/L
B/W/L
Shift operations
SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
B/W/L
B/W/L
B/W/L
B/W/L
Bitmanipulation instructions
BSET
BCLR
BNOT
BTST
Type Bitmanipulation instructions
Instruction BAND
Size*
Function (<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) Exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers specified general register memory operand carry flag. (<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand. (<bit-No.> <EAd>) Transfers inverse carry flag value specified general register memory operand. number specified 3-bit immediate data.
BIAND
BIOR
BXOR
BIXOR
BILD
BIST
Type Branch instructions
Instruction
Size*
Function Branches specified address specified condition true. branching conditions listed below. Mnemonic BRA(BT) BRN(BF) BCC(BHS) BCS(BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
System control TRAPA instructions SLEEP
Branches unconditionally specified address. Branches subroutine specified address. Branches subroutine specified address. Returns from subroutine Starts trap-instruction exception handling. Returns from exception-handling routine. Causes transition power-down state. (EAs) CCR, (EAs) Moves source operand contents immediate data EXR. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid.
Type
Instruction
Size*
Function (EAd), (EAd) Transfers contents general register memory. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid. #IMM CCR, #IMM Logically ANDs contents with immediate data. #IMM CCR, #IMM Logically contents with immediate data. #IMM CCR, #IMM Logically exclusive-ORs contents with immediate data. Only increments program counter. then Repeat @ER5+ @ER6+ R4L-1 Until else next; then Repeat @ER5+ @ER6+ R4-1 Until else next; Transfers data block according parameters general registers ER5, ER6. size block (bytes) ER5: starting source address ER6: starting destination address Execution next instruction begins soon transfer completed.
System control instructions
ANDC
XORC
Block data transfer instruction EEPMOV.B
EEPMOV.W
Note: Size refers operand size. Byte Word Longword
2.6.4
Basic Instruction Formats
instructions consist 2-byte (1-word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Figure 2.12 shows examples instruction formats.
Operation field only NOP, RTS, etc.
Operation field register fields ADD.B etc.
Operation field, register fields, effective address extension (disp) Operation field, effective address extension, condition field (disp) d:16, MOV.B @(d:16, Rn), etc.
Figure 2.12 Instruction Formats (Examples) Operation Field: Indicates function instruction, addressing mode, operation carried operand. operation field always includes first four bits instruction. Some instructions have operation fields. Register Field: Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension: Eight, bits specifying immediate data, absolute address, displacement. Condition Field: Specifies branching condition instructions.
2.7.1
Addressing Modes Effective Address Calculation
Addressing Mode
supports eight addressing modes listed table 2.4. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except program-counter relative memory indirect. manipulation instructions register direct, register indirect, absolute addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table
Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
Register Direct-Rn: register field instruction specifies 16-, 32-bit general register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32-bit registers. Register Indirect-@ERn: register field instruction code specifies address register (ERn) which contains address operand memory. address program instruction address, lower bits valid upper bits assumed (H'00). Register Indirect with Displacement-@(d:16, ERn) @(d:32, ERn): 16-bit 32-bit displacement contained instruction added address register (ERn) specified register field instruction, gives address memory operand. 16-bit displacement sign-extended when added.
Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn: Register indirect with post-increment-@ERn+ register field instruction code specifies address register (ERn) which contains address memory operand. After operand accessed, added address register contents stored address register. value added byte access, word transfer instruction, longword transfer instruction. word longword transfer instruction, register value should even. Register indirect with pre-decrement-@-ERn value subtracted from address register (ERn) specified register field instruction code, result becomes address memory operand. result also stored address register. value subtracted byte access, word transfer instruction, longword transfer instruction. word longword transfer instruction, register value should even. Absolute Address-@aa:8, @aa:16, @aa:24, @aa:32: instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24), bits long (@aa:32). access data, absolute address should bits (@aa:8), bits (@aa:16), bits (@aa:32) long. 8-bit absolute address, upper bits assumed (H'FFFF). 16-bit absolute address upper bits sign extension. 32-bit absolute address access entire address space. 24-bit absolute address (@aa:24) indicates address program instruction. upper bits assumed (H'00). Table indicates accessible absolute address ranges. Table Absolute Address Access Ranges
Normal Mode* bits (@aa:8) bits (@aa:16) bits (@aa:32) Program instruction address bits (@aa:24) H'FF00 H'FFFF H'0000 H'FFFF Advanced Mode H'FFFF00 H'FFFFFF H'000000 H'007FFF, H'FF8000 H'FFFFFF H'000000 H'FFFFFF
Absolute Address Data address
Note: ZTAT, mask ROM, ROMless versions only.
Immediate-#xx:8, #xx:16, #xx:32: instruction contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. ADDS, SUBS, INC, instructions contain immediate data implicitly. Some manipulation instructions contain 3-bit immediate data instruction code, specifying number. TRAPA instruction contains 2-bit immediate data instruction code, specifying vector address. Program-Counter Relative-@(d:8, @(d:16, PC): This mode used instructions. 8-bit 16-bit displacement contained instruction sign-extended added 24-bit contents generate branch address. Only lower bits this branch address valid; upper bits assumed (H'00). value which displacement added address first byte next instruction, possible branching range -126 +128 bytes (-63 words) -32766 +32768 bytes (-16383 +16384 words) from branch instruction. resulting value should even number. Memory Indirect-@@aa:8: This mode used instructions. instruction code contains 8-bit absolute address specifying memory operand. This memory operand contains branch address. upper bits absolute address assumed address range (H'0000 H'00FF normal mode, H'000000 H'0000FF advanced mode). normal mode memory operand word operand branch address bits long. advanced mode memory operand longword operand, first byte which assumed (H'00). Note that first part address range also exception vector area. further details, refer section Exception Handling. Note: ZTAT, mask ROM, ROMless versions only.
Specified @aa:8
Branch address
Specified @aa:8
Reserved Branch address
Normal Mode* Note: ZTAT, mask ROM, ROMless versions only.
Advanced Mode
Figure 2.13 Branch Address Specification Memory Indirect Mode address specified word longword memory access, branch address, least significant regarded causing data accessed instruction code fetched address preceding specified address. (For further information, section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation
Table indicates effective addresses calculated each addressing mode. normal mode* upper bits effective address ignored order generate 16-bit address. Note: ZTAT, mask ROM, ROMless versions only.
Table
Effective Address Calculation
Effective Address Calculation Effective Address (EA) Operand general register contents.
Addressing Mode Instruction Format Register direct (Rn)
Register indirect (@ERn)
General register contents Don't care
Register indirect with displacement @(d:16, ERn) @(d:32, ERn)
General register contents disp Sign extension disp Don't care
Register indirect with post-increment pre-decrement Register indirect with post-increment @ERn+
General register contents Don't care
Register indirect with pre-decrement @-ERn
General register contents Operand Size Byte Word Longword Value Added Don't care
Addressing Mode Instruction Format Absolute address
@aa:8
Effective Address Calculation
Effective Address (EA)
H'FFFF
Don't care
@aa:16
Don't care
Sign extension
@aa:24
Don't care
@aa:32
Don't care
Immediate #xx:8/#xx:16/#xx:32
Operand immediate data.
Program-counter relative @(d:8, PC)/@(d:16,
contents
disp
Sign extension
disp
Don't care
Addressing Mode Instruction Format Memory indirect @@aa:8 Normal mode*
Effective Address Calculation
Effective Address (EA)
H'000000
Don't care Memory contents
H'00
Advanced mode
H'000000
Memory contents
Don't care
Note: ZTAT, mask ROM, ROMless versions only.
2.8.1
Processing States
Overview
five main processing states: reset state, exception handling state, program execution state, bus-released state, power-down state. Figure 2.14 shows diagram processing states. Figure 2.15 indicates state transitions.
Reset state on-chip supporting modules have been initialized stopped. Exception-handling state transient state which changes normal processing flow response reset, interrupt, trap instruction. Processing states Program execution state executes program instructions sequence. Bus-released state external been released response request signal from master other than CPU. Sleep mode
Power-down state operation stopped conserve power.*
Software standby mode Hardware standby mode
Note: power-down state also includes medium-speed mode, module stop mode etc.
Figure 2.14 Processing States
request request
Program execution state request request SLEEP instruction with SSBY
Bus-released state exception handling Request exception handling
SLEEP instruction with SSBY
Sleep mode
Interrupt request Exception-handling state External interrupt high Software standby mode
Reset state*1
STBY high,
Hardware standby mode*2 Power-down state
Notes: From state except hardware standby mode, transition reset state occurs whenever goes low. transition also made reset state when watchdog timer overflows. From state, transition hardware standby mode occurs when STBY goes low.
Figure 2.15 State Transitions 2.8.2 Reset State
When input goes current processing stops enters reset state. enters power-on reset state when high, manual reset state when low. interrupts masked reset state. Reset exception handling starts when signal changes from high. reset state also entered watchdog timer overflow. details, refer section Watchdog Timer.
2.8.3
Exception-Handling State
exception-handling state transient state that occurs when alters normal processing flow reset, interrupt, trap instruction. fetches start address (vector) from exception vector table branches that address. Types Exception Handling Their Priority Exception handling performed traces, resets, interrupts, trap instructions. Table indicates types exception handling their priority. Trap instruction exception handling always accepted, program execution state. Exception handling stack structure depend interrupt control mode SYSCR. Table
Priority High
Exception Handling Types Priority
Type Exception Reset Detection Timing Synchronized with clock Start Exception Handling Exception handling starts immediately after low-to-high transition pin, when watchdog timer overflows. When trace trace starts current instruction current exception-handling sequence When interrupt requested, exception handling starts current instruction current exception-handling sequence Exception handling starts when trap (TRAPA) instruction executed*
Trace
instruction execution exception-handling sequence* instruction execution exception-handling sequence* When TRAPA instruction executed
Interrupt
Trap instruction
Notes: Traces enabled only interrupt control mode Trace exception-handling executed instruction. Interrupts detected ANDC, ORC, XORC, instructions, immediately after reset exception handling. Trap instruction exception handling always accepted, program execution state.
Reset Exception Handling After gone reset state been entered, when goes high again, reset exception handling starts. enters power-on reset state when high, manual reset state when low. When reset exception handling starts fetches start address (vector) from exception vector table starts program execution from that address. interrupts, including NMI, disabled during reset exception handling after ends. Traces Traces enabled only interrupt control mode Trace mode entered when When trace mode established, trace exception handling starts each instruction. trace exception-handling sequence, cleared trace mode cleared. Interrupt masks affected. saved stack retains value when instruction executed return from trace exception-handling routine, trace mode entered again. Trace exceptionhandling executed instruction. Trace mode entered interrupt control mode regardless state bit. Interrupt Exception Handling Trap Instruction Exception Handling When interrupt trap-instruction exception handling begins, references stack pointer (ER7) pushes program counter other control registers onto stack. Next, alters settings interrupt mask bits control registers. Then fetches start address (vector) from exception vector table program execution starts from that start address. Figure 2.16 shows stack after exception handling ends.
Normal mode*1
CCR*2 bits)
Reserved*2 CCR*2 bits)
Interrupt control mode
Interrupt control mode
Advanced mode
bits)
Reserved*2 bits)
Interrupt control mode Notes: ZTAT, mask ROM, ROMless versions only. Ignored when returning.
Interrupt control mode
Figure 2.16 Stack Structure after Exception Handling (Examples)
2.8.4
Program Execution State
this state executes program instructions sequence. 2.8.5 Bus-Released State
This state which been released response request from master other than CPU. While released, halts operations. There other master addition CPU: data transfer controller (DTC). further details, refer section Controller. 2.8.6 Power-Down State
power-down state includes both modes which stops operating modes which does stop. There three modes which stops operating: sleep mode, software standby mode, hardware standby mode. There also other power-down modes: medium-speed mode, module stop mode. medium-speed mode other masters operate medium-speed clock. Module stop mode permits halting operation individual modules, other than CPU. details, refer section Power-Down State. Sleep Mode: transition sleep mode made SLEEP instruction executed while software standby (SSBY) standby control register (SBYCR) cleared sleep mode, operations stop immediately after execution SLEEP instruction. contents registers retained. Software Standby Mode: transition software standby mode made SLEEP instruction executed while SSBY SBYCR software standby mode, clock halt operations stop. long specified voltage supplied, contents registers on-chip retained. ports also remain their existing states. Hardware Standby Mode: transition hardware standby mode made when STBY goes low. hardware standby mode, clock halt operations stop. on-chip supporting modules reset, long specified voltage supplied, on-chip contents retained.
2.9.1
Basic Timing
Overview
driven system clock, denoted symbol period from rising edge next referred "state." memory cycle cycle consists one, two, three states. Different methods used access on-chip memory, on-chip supporting modules, external address space. 2.9.2 On-Chip Memory (ROM, RAM)
On-chip memory accessed state. data bits wide, permitting both byte word transfer instruction. Figure 2.17 shows on-chip memory access cycle. Figure 2.18 shows states.
cycle Internal address Internal read signal Internal data Internal write signal Write access Internal data Write data Read data Address
Read access
Figure 2.17 On-Chip Memory Access Cycle
cycle
Address HWR, Data
Unchanged High High High High-impedance state
Figure 2.18 States during On-Chip Memory Access
2.9.3
On-Chip Supporting Module Access Timing
on-chip supporting modules accessed states. data either bits bits wide, depending particular internal register being accessed. Figure 2.19 shows access timing on-chip supporting modules. Figure 2.20 shows states.
cycle
Internal address
Address
Internal read signal Read access Internal data Internal write signal Write access Internal data Write data
Read data
Figure 2.19 On-Chip Supporting Module Access Cycle
cycle
Address
Unchanged
HWR,
High
High
High
Data
High-impedance state
Figure 2.20 States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing
external address space accessed with 8-bit 16-bit data width two-state three-state cycle. three-state access, wait states inserted. further details, refer section Controller.
Section Operating Modes
3.1.1
Overview
Operating Mode Selection (F-ZTATVersion)
H8S/2345 Series eight operating modes (modes 15). These modes determined mode (MD2 MD0) flash write enable (FWE) settings. operating mode initial width selected shown table 3.1. Table lists operating modes. Table Operating Mode Selection (F-ZTATVersion)
External Data On-Chip Initial Width Max. Width
Operating Operating Mode Mode Description Advanced User program mode Advanced Boot mode
Advanced On-chip disabled, Disabled bits bits expanded mode bits bits On-chip enabled, Enabled bits expanded mode Single-chip mode bits
Enabled bits
bits
Enabled bits
bits
CPU's architecture allows Gbytes address space, H8S/2345 Series actually accesses maximum Mbytes.
Modes externally expanded modes that allow access external memory peripheral devices. external expansion modes allow switching between 8-bit 16-bit modes. After program execution starts, 8-bit 16-bit address space each area, depending controller setting. 16-bit access selected area, 16-bit mode set; 8-bit access selected areas, 8-bit mode set. Note that functions each depend operating mode. Modes boot modes user program modes which flash memory programmed erased. details, section ROM. H8S/2345 Series only used modes This means that flash write enable mode pins must select these modes. change inputs mode pins during operation. 3.1.2 Operating Mode Selection (ZTAT, Mask ROM, ROMless Versions)
H8S/2345 Series seven operating modes (modes These modes enable selection operating mode, enabling/disabling on-chip ROM, initial width setting, setting mode pins (MD2 MD0). Table lists operating modes.
Table
Operating Mode Selection
External Data On-Chip Initial Width bits bits Max. Width
Operating Operating Mode Mode Description Normal
On-chip disabled, Disabled bits expanded mode On-chip enabled, Enabled bits expanded mode Single-chip mode
Advanced On-chip disabled, Disabled bits expanded mode bits On-chip enabled, Enabled bits expanded mode Single-chip mode
bits bits bits
Note: used ROMless version.
CPU's architecture allows Gbytes address space, H8S/2345 Series actually accesses maximum Mbytes. Modes externally expanded modes that allow access external memory peripheral devices. external expansion modes allow switching between 8-bit 16-bit modes. After program execution starts, 8-bit 16-bit address space each area, depending controller setting. 16-bit access selected area, 16-bit mode set; 8-bit access selected areas, 8-bit mode set. Note that functions each depend operating mode. H8S/2345 Series used only modes This means that mode pins must select these modes. change inputs mode pins during operation.
3.1.3
Register Configuration
H8S/2345 Series mode control register (MDCR) that indicates inputs mode pins MD0), system control register (SYSCR) system control register (SYSCR2)*2 that control operation H8S/2345 Series. Table summarizes these registers. Table
Name Mode control register System control register System control register
Registers
Abbreviation MDCR SYSCR SYSCR2 Initial Value Undetermined H'01 H'00 Address* H'FF3B H'FF39 H'FF42
Notes: Lower bits address. SYSCR2 register only used F-ZTAT version. ZTAT, mask ROM, ROMless versions, this register cannot written will return undefined value read.
3.2.1
Register Descriptions
Mode Control Register (MDCR)
MDS2 MDS1 MDS0
Initial value:
Note: Determined pins MD0.
MDCR 8-bit read-only register that indicates current operating mode H8S/2345 Series. 7-Reserved: Read-only bit, always read Bits 3-Reserved: Read-only bits, always read Bits 0-Mode Select (MDS2 MDS0): These bits indicate input levels pins (the current operating mode). Bits MDS2 MDS0 correspond MD0. MDS2 MDS0 read-only bits-they cannot written mode (MD2 MD0) input levels latched into these bits when MDCR read. These latches canceled power-on reset, retained after manual reset.
3.2.2
System Control Register (SYSCR)
INTM1 INTM0 NMIEG RAME
Initial value:
Bits 6-Reserved: Only should written these bits. Bits 4-Interrupt Control Mode (INTM1, INTM0): These bits select control mode interrupt controller. details interrupt control modes, section 5.4.1, Interrupt Control Modes Interrupt Operation.
INTM1 INTM0 Interrupt Control Mode
Description Control interrupts Setting prohibited Control interrupts bits Setting prohibited (Initial value)
3-NMI Edge Select (NMIEG): Selects valid edge interrupt input.
NMIEG Description interrupt requested falling edge input interrupt requested rising edge input (Initial value)
Bits 1-Reserved: Only should written these bits. 0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized when reset status released. initialized software standby mode.
RAME Description On-chip disabled On-chip enabled (Initial value)
3.2.3
System Control Register (SYSCR2) (F-ZTAT Version Only)
FLSHE
Initial value
SYSCR2 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 initialized H'00 reset hardware standby mode. SYSCR2 only accessed F-ZTAT version. other versions, this register cannot written will return undefined value read. Bits 4-Reserved: Read-only bits, always read 3-Flash Memory Control Register Enable (FLSHE): Controls access flash memory control registers (FLMCR1, FLMCR2, EBR1, EBR2). details, section ROM.
FLSHE Description Flash control registers selected addresses H'FFFFC8 H'FFFFCB (Initial value) Flash control registers selected addresses H'FFFFC8 H'FFFFCB
Bits 0-Reserved: Read-only bits, always read
3.3.1
Operating Mode Descriptions
Mode (ZTAT, Mask ROM, ROMless Versions Only)
access 64-kbyte address space normal mode. on-chip disabled, 8-bit mode set, immediately after reset. Ports function address bus, port functions data bus, part port carries control signals. However, note that 16-bit access designated controller, mode switches bits port becomes data bus. 3.3.2 Mode (ZTAT Mask Versions Only)
access 64-kbyte address space normal mode. on-chip enabled, 8-bit mode set. immediately after reset. Ports function input ports immediately after reset. They each output addresses setting corresponding bits data direction register (DDR) Port functions data bus, part port carries control signals. However, note that 16-bit access designated controller, mode switches bits port becomes data bus. amount on-chip that used limited kbytes. 3.3.3 Mode (ZTAT Mask Versions Only)
access 64-kbyte address space normal mode. on-chip enabled, external addresses cannot accessed. ports available input-output ports. amount on-chip that used limited kbytes. 3.3.4 Mode
access 16-Mbyte address space advanced mode. on-chip disabled. Pins P10, ports function address bus, ports function data bus, part port carries control signals. Pins function inputs immediately after reset. Each these pins output addresses setting corresponding data direction register (DDR) initial mode after reset bits, with 16-bit access areas. However, note that 8-bit access designated controller areas, mode switches bits.
3.3.5
Mode
access 16-Mbyte address space advanced mode. on-chip disabled. Pins P10, ports function address bus, port function data bus, part port carries control signals. Pins function inputs immediately after reset. They each output addresses setting corresponding bits data direction register (DDR) initial mode after reset bits, with 8-bit access areas. However, note that least area designated 16-bit access controller, mode switches bits port becomes data bus. 3.3.6 Mode
access 16-Mbyte address space advanced mode. on-chip enabled. Pins P10, ports function input ports immediately after reset. They each output addresses setting corresponding bits data direction register (DDR) Port functions data bus, part port carries control signals. initial mode after reset bits, with 8-bit access areas. However, area designated 16-bit access space controller, 16-bit mode port becomes data bus. 3.3.7 Mode
access 16-Mbyte address space advanced mode. on-chip enabled, external addresses cannot accessed. ports available input-output ports. Notes: used ROMless version. upper address pins A20) cannot used outputs modes immediately after reset. upper address pins (A23 A20) outputs, necessary first corresponding bits port data direction register (P1DDR) 3.3.8 Modes (F-ZTAT Version Only)
Modes supported H8S/2345 Series, must set.
3.3.9
Mode (F-ZTAT Version Only)
This flash memory boot mode. details, section ROM. operation same mode 3.3.10 Mode (F-ZTAT Version Only)
This flash memory boot mode. details, section ROM. operation same mode 3.3.11 Modes (F-ZTAT Version Only)
Modes supported H8S/2345 Series, must set. 3.3.12 Mode (F-ZTAT Version Only)
This flash memory user program mode. details, section ROM. operation same mode 3.3.13 Mode (F-ZTAT Version Only)
This flash memory user program mode. details, section ROM. operation same mode
Functions Each Operating Mode
functions ports vary depending operating mode. Table shows their functions each operating mode. Table Functions Each Mode
Mode Mode Mode Mode Mode Mode 1/T/A
Port Port Port Port Port Port Port Port
Mode Mode Mode Mode P/C*
Mode 1/T/A
P/C*
/T/A P/C*
P/C*
P/C*
Legend port Timer Address output Data Control signals, clock Notes: After reset used F-ZTAT. used ROMless version. Applies F-ZTAT version only.
Memory Each Operating Mode
Memory maps H8S/2345, H8S/2344, H8S/2343, H8S/2341, H8S/2340 shown figure figure 3.5. address space kbytes modes (normal modes)*, Mbytes modes (advanced modes). on-chip capacity H8S/2345 kbytes, that H8S/2344 kbytes, that H8S/2343 kbytes. However, only kbytes available modes (normal modes)*. address space divided into eight areas modes details, section Controller. Note: available F-ZTAT version.
Mode (normal expanded mode with on-chip disabled) H'0000
Mode (normal expanded mode with on-chip enabled) H'0000
Mode (normal single-chip mode)
H'0000
External address space
On-chip
On-chip
H'EC00 On-chip RAM*1 H'FC00
External address space
H'DFFF H'E000 External address space H'EC00 On-chip RAM*1
H'DFFF
H'EC00 On-chip H'FBFF
H'FC00
External address space
H'FE40 Internal registers H'FF08 External address
space
H'FE40 Internal registers External address H'FF08
space
H'FE40 Internal registers H'FF07 H'FF28 Internal registers H'FFFF
H'FF28 Internal registers H'FFFF
H'FF28 Internal registers H'FFFF
Notes: External addresses accessed clearing RAME SYSCR available F-ZTAT version.
Figure Memory Each Operating Mode H8S/2345
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000
Mode (advanced single-chip mode)
H'000000
On-chip
On-chip
External address space
H'00FFFF H'010000
H'00FFFF H'010000
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2
H'FFEC00 On-chip RAM*3 H'FFFC00
External address space
H'01FFFF H'020000 External address space H'FFEC00 On-chip RAM*3
H'01FFFF
H'FFEC00 On-chip H'FFFBFF
H'FFFC00
External address space
H'FFFE40 Internal registers H'FFFF08 External address
space
H'FFFE40 Internal registers H'FFFF08 External address
space
H'FFFE40 Internal registers H'FFFF07 H'FFFF28 Internal registers H'FFFFFF
H'FFFF28 Internal registers H'FFFFFF
H'FFFF28 Internal registers H'FFFFFF
Notes: When BCRL this area external address space. When cleared on-chip ROM. When BCRL this area reserved. When cleared on-chip ROM. External addresses accessed clearing RAME SYSCR
Figure Memory Each Operating Mode H8S/2345 (cont)
Mode 10*4 Boot Mode (advanced expanded mode with on-chip enabled) H'000000
Mode 11*4 Boot Mode (advanced single-chip mode) H'000000
On-chip
On-chip
H'00FFFF H'010000
H'00FFFF H'010000
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2
H'01FFFF H'020000 External address space H'FFEC00 On-chip RAM*3
H'01FFFF
H'FFEC00 On-chip RAM*3 H'FFFBFF
H'FFFC00 External address space H'FFFE40 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF
H'FFFE40 H'FFFF07
Internal registers
H'FFFF28 H'FFFFFF
Internal registers
Notes: When BCRL this area external address space. When cleared on-chip ROM. When BCRL this area reserved. When cleared on-chip ROM. On-chip used flash memory programming. clear RAME SYSCR. Modes provided F-ZTAT version only.
Figure Memory Each Operating Mode H8S/2345 (cont)
Mode 14*4 User Program Mode (advanced expanded mode with on-chip enabled) H'000000
Mode 15*4 User Program Mode (advanced single-chip mode) H'000000
On-chip
On-chip
H'00FFFF H'010000
H'00FFFF H'010000
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2
H'01FFFF H'020000 External address space H'FFEC00 On-chip RAM*3
H'01FFFF
H'FFEC00 On-chip RAM*3 H'FFFBFF
H'FFFC00 External address space H'FFFE40 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF
H'FFFE40 H'FFFF07
Internal registers
H'FFFF28 H'FFFFFF
Internal registers
Notes: When BCRL this area external address space. When cleared on-chip ROM. When BCRL this area reserved. When cleared on-chip ROM. On-chip used flash memory programming. clear RAME SYSCR. Modes provided F-ZTAT version only.
Figure Memory Each Operating Mode H8S/2345 (cont)
Mode (normal expanded mode with on-chip disabled) H'0000
Mode (normal expanded mode with on-chip enabled) H'0000
Mode (normal single-chip mode)
H'0000
External address space
On-chip
On-chip
H'EC00 On-chip RAM* H'FC00
External address space
H'DFFF H'E000 External address space H'EC00 On-chip RAM*
H'DFFF
H'EC00 On-chip H'FBFF
H'FC00
External address space
H'FE40 Internal registers H'FF08 External address
space
H'FE40 Internal registers H'FF08 External address
space
H'FE40 Internal registers H'FF07 H'FF28 Internal registers H'FFFF
H'FF28 Internal registers H'FFFF
H'FF28 Internal registers H'FFFF
Note: External addresses accessed clearing RAME SYSCR
Figure Memory Each Operating Mode H8S/2344
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000
Mode (advanced single-chip mode)
H'000000
On-chip
On-chip
External address space
H'00FFFF H'010000 On-chip ROM/ external address space*1 H'017FFF H'018000 Reserved area/ external address space*2 H'01FFFF H'020000 External address space H'FFEC00
H'00FFFF H'010000 On-chip ROM/ reserved area*3 H'017FFF H'018000 Reserved area H'01FFFF
H'FFEC00 On-chip RAM*4 H'FFFC00
External address space
H'FFEC00 On-chip H'FFFBFF
On-chip RAM*4 H'FFFC00
External address space
H'FFFE40 Internal registers H'FFFF08 External address
space
H'FFFE40 Internal registers H'FFFF08 External address
space
H'FFFE40 Internal registers H'FFFF07 H'FFFF28 Internal registers H'FFFFFF
H'FFFF28 Internal registers H'FFFFFF
H'FFFF28 Internal registers H'FFFFFF
Notes: When BCRL this area external address space. When cleared on-chip ROM. When BCRL this area external address space. When cleared reserved area. This area reserved when BCRL on-chip when cleared External addresses accessed clearing RAME SYSCR
Figure Memory Each Operating Mode H8S/2344 (cont)
Mode (normal expanded mode with on-chip disabled) H'0000
Mode (normal expanded mode with on-chip enabled) H'0000
Mode (normal single-chip mode)
H'0000
On-chip External address space
On-chip
H'EC00 H'F400 H'FC00
Reserved area* On-chip RAM*
External address space
H'DFFF H'E000 External address space H'EC00 Reserved area* H'F400 On-chip RAM* H'FC00
External address space
H'DFFF
H'F400 H'FBFF On-chip
H'FE40 Internal registers H'FF08 External address
space
H'FE40 Internal registers H'FF08 External address
space
H'FE40 Internal registers H'FF07 H'FF28 Internal registers H'FFFF
H'FF28 Internal registers H'FFFF
H'FF28 Internal registers H'FFFF
Note: External addresses accessed clearing RAME SYSCR
Figure Memory Each Operating Mode H8S/2343
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000
Mode (advanced single-chip mode)
H'000000
On-chip
On-chip
External address space
H'00FFFF H'010000
H'00FFFF
External address space/reserved area*1
H'FFEC00 H'FFF400
Reserved area*2 On-chip RAM*2
H'01FFFF H'020000 External address space H'FFEC00 Reserved area*2 H'FFF400 On-chip RAM*2 H'FFFC00 H'FFFF08
External address space External address space
H'FFF400 H'FFFBFF On-chip
H'FFFC00
External address space
H'FFFE40 Internal registers H'FFFF08 External address
space
H'FFFE40 Internal registers H'FFFF28 Internal registers H'FFFFFF
H'FFFE40 Internal registers H'FFFF07 H'FFFF28 Internal registers H'FFFFFF
H'FFFF28 Internal registers H'FFFFFF
Notes: When BCRL this area external address space. When cleared on-chip ROM. External addresses accessed clearing RAME SYSCR
Figure Memory Each Operating Mode H8S/2343 (cont)
Mode (normal expanded mode with on-chip disabled) H'0000
Mode (normal expanded mode with on-chip enabled) H'0000
Mode (normal single-chip mode)
H'0000
On-chip
On-chip
External address space
H'7FFF H'8000
H'7FFF
Reserved area
H'EC00 H'F400 H'FC00
Reserved area* On-chip RAM*
External address space
H'DFFF H'E000 External address space H'EC00 Reserved area* H'F400 On-chip RAM* H'FC00
External address space
H'F400 H'FBFF On-chip
H'FE40 Internal registers H'FF08 External address
space
H'FE40 Internal registers H'FF08 External address
space
H'FE40 Internal registers H'FF07 H'FF28 Internal registers H'FFFF
H'FF28 Internal registers H'FFFF
H'FF28 Internal registers H'FFFF
Note: External addresses accessed clearing RAME SYSCR
Figure Memory Each Operating Mode H8S/2341
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000
Mode (advanced single-chip mode)
H'000000
On-chip
On-chip
H'007FFF H'008000 Reserved area External address space
H'007FFF
H'00FFFF H'010000
External address space/reserved area*1
H'FFEC00 H'FFF400
Reserved area*2 On-chip RAM*2
H'01FFFF H'020000 External address space H'FFEC00 Reserved area*2 H'FFF400 On-chip RAM*2 H'FFFC00 H'FFFF08
External address space External address space
H'FFF400 H'FFFBFF On-chip
H'FFFC00
External address space
H'FFFE40 Internal registers H'FFFF08 External address
space
H'FFFE40 Internal registers H'FFFF28 Internal registers H'FFFFFF
H'FFFE40 Internal registers H'FFFF07 H'FFFF28 Internal registers H'FFFFFF
H'FFFF28 Internal registers H'FFFFFF
Notes: When BCRL this area external address space. When cleared on-chip ROM. External addresses accessed clearing RAME SYSCR
Figure Memory Each Operating Mode H8S/2341 (cont)
Mode (normal expanded mode with on-chip disabled) H'0000 External address space
Modes (advanced expanded modes with on-chip disabled) H'000000
H'EC00 H'F400
Reserved area* On-chip RAM*
H'FC00 External address space H'FE40 Internal registers H'FF08 External address space H'FF28 Internal registers H'FFFF
External address space
H'FFEC00 H'FFF400
Reserved area* On-chip RAM*
H'FFFC00 External address space H'FFFE40 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF Note: External addresses accessed clearing RAME SYSCR
Figure Memory Each Operating Mode H8S/2340 (Modes Only)
Section Exception Handling
4.1.1
Overview
Exception Handling Types Priority
table indicates, exception handling caused reset, trap instruction, interrupt. Exception handling prioritized shown table 4.1. more exceptions occur simultaneously, they accepted processed order priority. Trap instruction exceptions accepted times, program execution state. Exception handling sources, stack structure, operation vary depending interrupt control mode INTM0 INTM1 bits SYSCR. Table
Priority High
Exception Types Priority
Exception Type Reset Start Exception Handling Starts immediately after low-to-high transition pin, when watchdog timer overflows. enters power-on reset state when high, manual reset state when low. Starts when execution current instruction exception handling ends, trace Starts when execution current instruction exception handling ends, interrupt request been issued*
Trace* Interrupt
Trap instruction (TRAPA)*3 Started execution trap instruction (TRAPA)
Notes: Traces enabled only interrupt control mode Trace exception handling executed after execution instruction. Interrupt detection performed completion ANDC, ORC, XORC, instruction execution, completion reset exception handling. Trap instruction exception handling requests accepted times program execution state.
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions interrupts handled follows: program counter (PC), condition code register (CCR), extended register (EXR) pushed onto stack. interrupt mask bits updated. cleared vector address corresponding exception source generated, program execution starts from that address. reset exception, steps above carried out. 4.1.3 Exception Vector Table
exception sources classified shown figure 4.1. Different vector addresses assigned different exception sources. Table lists exception sources their vector addresses.
Reset Trace Exception sources Interrupts
Power-on reset Manual reset External interrupts: NMI, IRQ7 IRQ0 Internal interrupts: interrupt sources on-chip supporting modules
Trap instruction
Figure Exception Sources modes H8S/2345, on-chip available after power-on reset 64-kbyte area comprising addresses H'000000 H'00FFFF. Care required when setting vector addresses. this case, clearing BCRL enables 128-kbyte area comprising addresses H'000000 H'01FFFF used.
Table
Exception Vector Table
Vector Address
Exception Source Power-on reset Manual reset Reserved system
Vector Number
Normal Mode* H'0000 H'0001 H'0002 H'0003 H'0004 H'0006 H'0006 H'0007 H'0008 H'0009 H'000A H'000B H'000C H'000D H'000E H'000F H'0010 H'0011 H'0012 H'0013 H'0014 H'0015 H'0016 H'0017 H'0018 H'0019 H'001A H'001B H'001C H'001D H'001E H'001F H'0020 H'0021 H'0022 H'0023 H'0024 H'0025 H'0026 H'0027 H'0028 H'0029 H'002A H'002B H'002C H'002D H'002E H'002F H'0030 H'0031 H'00AE H'00AF
Advanced Mode H'0000 H'0003 H'0004 H'0007 H'0008 H'000B H'000C H'000F H'0010 H'0013 H'0014 H'0017 H'0018 H'001B H'001C H'001F H'0020 H'0023 H'0024 H'0027 H'0028 H'002B H'002C H'002F H'0030 H'0033 H'0034 H'0037 H'0038 H'003B H'003C H'003F H'0040 H'0043 H'0044 H'0047 H'0048 H'004B H'004C H'004F H'0050 H'0053 H'0054 H'0057 H'0058 H'005B H'005C H'005F H'0060 H'0063 H'015C H'015F
Trace Reserved system External interrupt
Trap instruction sources)
Reserved system
External interrupt
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
Internal interrupt
Notes: Lower bits address. details internal interrupt vectors, section 5.3.3, Interrupt Exception Handling Vector Table. ZTAT, mask ROM, ROMless versions only.
4.2.1
Reset
Overview
reset highest exception priority. When goes low, processing halts H8S/2345 Series enters reset state. reset initializes internal state registers on-chip supporting modules. Immediately after reset, interrupt control mode set. Reset exception handling begins when changes from high. level res
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