Cautions Keep safety first your circuit designs! Renesas Technolo
|
|
|
Top Searches for this datasheet
Cautions
Keep safety first your circuit designs! Renesas Technology Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) nonflammable material (iii) prevention against malfunction mishap. Notes regarding these materials These materials intended reference assist customers selection Renesas Technology Corporation product best suited customer's application; they convey license under intellectual property rights, other rights, belonging Renesas Technology Corporation third party. Renesas Technology Corporation assumes responsibility damage, infringement third-party's rights, originating product data, diagrams, charts, programs, algorithms, circuit application examples contained these materials. information contained these materials, including product data, diagrams, charts, programs algorithms represents information products time publication these materials, subject change Renesas Technology Corporation without notice product improvements other reasons. therefore recommended that customers contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor latest product information before purchasing product listed herein. information described here contain technical inaccuracies typographical errors. Renesas Technology Corporation assumes responsibility damage, liability, other loss rising from these inaccuracies errors. Please also attention information published Renesas Technology Corporation various means, including Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). When using information contained these materials, including product data, diagrams, charts, programs, algorithms, please sure evaluate information total system before making final decision applicability information products. Renesas Technology Corporation assumes responsibility damage, liability other loss resulting from information contained herein. Renesas Technology Corporation semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor when considering product contained herein specific purposes, such apparatus systems transportation, vehicular, medical, aerospace, nuclear, undersea repeater use. prior written approval Renesas Technology Corporation necessary reprint reproduce whole part these materials. these products technologies subject Japanese export control restrictions, they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations Japan and/or country destination prohibited. Please contact Renesas Technology Corporation further details these materials products contained therein.
HD404344R Series/HD404394 Series
Rev. Sept. 1999 Description
HD404344R series HD404394 series 4-bit microcomputers products HMCS400 series, which designed make application systems compact while realizing higher performance increasing program productivity. Each microcomputer converter, timers serial interface. HD404344R series includes HD404344R with on-chip 4-kword ROM, HD404342R with 2-kword ROM, HD404341R with 1-kword ROM. HD404394 series includes HD404394 with on-chip 4-kword ROM, HD404392 with 2-kword ROM, HD404391 with 1-kword ROM. HD4074344 HD4074394 PROM version ZTATmicrocomputers. Programs written PROM PROM writer, which dramatically shorten system development periods smooth process from debugging mass production. (The PROM program specifications same 27256.) ZTATTM: Zero Turn Around Time ZTAT Trademark Hitachi Ltd.
Features
Input/output pins HD404344R series, HD4074344: pins (10pins: Large-current pins) HD404394 series: pins pins: intermediate-voltage NMOS open drain I/O; pins: NMOS open drain with 15-mA high-current driver) timer/counters timer output event counter input (with programmable edge detection) 8-bit clock-synchronous serial interface channel) On-chip converter HD404344R series, HD4074344: channel HD404394 series: channel (with Vref pin) Built-in oscillator
HD404344R Series/HD404394 Series
HD404344R Series Ceramic oscillator, oscillation, External clock drive also possible. HD404394 Series, HD4074344 Ceramic oscillator, External clock drive also possible. Five interrupt sources external source (with programmable edge detection) Four internal sources Subroutine stack Maximum levels including interrupts low-power dissipation modes Standby mode Stop mode input signal return from stop mode Instruction cycle time (fOSC MHz)
HD404344R Series/HD404394 Series
Type Products
Product Name Type Mask HD404344R Series*1 HD404341RS HD40C4341RS HD404342RS HD40C4342RS HD404344RS HD40C4344RS HD404341RFP HD40C4341RFP HD404342RFP HD40C4342RFP HD404344RFP HD40C4344RFP HD404341RFT HD40C4341RFT HD404342RFT HD40C4342RFT HD404344RFT HD40C4344RFT HCD404344R HCD40C4344R ZTATHD4074344S HD4074344FP HD4074344FT Note: HD4074394S HD4074394FP HD4074394FT 4,096 DP-28S FP-28DA FP-30D 4,096 Chip HD404394FT 4,096 HD404392FT 2,048 HD404391FT 1,024 FP-30D HD404394FP 4,096 HD404392FP 2,048 HD404391FP 1,024 FP-28DA HD404394S 4,096 HD404392S 2,048 HD404394 Series HD404391S (words) 1,024 (digit) Package DP-28S
HD404344R Series available mask version only. ZTATchip shipment supprted. specifications shipped chips differ from those package product. Please contact sales staff details.
HD404344R Series/HD404394 Series
List Functions
Mask item Operating voltage Instruction cycle time (typ.) HD404341R (fosc MHz) (Words) (Digits) High-current pins (Sink max) Timer functions Free running timer Reload timer 1,024 HD404342R (fosc MHz) 2.048 HD404344R (fosc MHz) 4,096 HCD404344R HD40C4341R HD40C4342R HD40C4344R (fosc MHz) 4,096 1,024 2,048 4,096
Event counter Watchdog timer Serial interface converter Interrupt External Internal Low-power modes Stop mode 8bit
8bit
8bit
8bit
8bit
8bit
8bit
Standby mode Oscillator Ceramic oscillation oscillation Package DP-28S FP-28DA FP-30D Guaranteed operation temperature (°C)
DP-28S FP-28DA FP-30D
DP-28S FP-28DA FP-30D
Chip
DP-28S FP-28DA FP-30D
DP-28S FP-28DA FP-30D
DP-28S FP-28DA FP-30D
HD404344R Series/HD404394 Series
List Functions (cont)
Mask item Operating voltage Instruction cycle time (typ.) HCD40C4344R (Words) (Digits) High-current pins (Sink max) Timer functions Free running timer Reload timer 4,096 ZTATHD4074344 (fosc MHz) 4,096 PROM
Event counter Watchdog timer Serial interface converter Interrupt External Internal Low-power modes Stop mode 8bit
8bit
Standby mode Oscillator Ceramic oscillation oscillation Package Chip
DP-28S FP-28DA FP-30D
Guaranteed operation temperature (°C)
HD404344R Series/HD404394 Series
List Functions (cont)
Mask item Operating voltage Instruction cycle time (typ.) HD404391 (fosc MHz) (Words) (Digits) intermediatevoltage NMOS open drain NMOS open drain High current driver) Timer functions Free running timer Reload timer 1,024 HD404392 (fosc MHz) 2.048 HD404394 (fosc MHz) 4,096 ZTATHD4074394 (fosc MHz) 4,096 PROM
Event counter Watchdog timer Serial interface converter Interrupt External Internal Low-power modes Stop mode 8bit
8bit
8bit
8bit
Standby mode Oscillator Ceramic oscillation Package DP-28S FP-28DA FP-30D Guaranteed operation temperature (°C)
DP-28S FP-28DA FP-30D
DP-28S FP-28DA FP-30D
DP-28S FP-28DA FP-30D
HD404344R Series/HD404394 Series
Arrangement
HD404344R Series, HD4074344
OSC1 OSC2 R30/AN0 R31/AN1 R32/AN2
DP-28S FP-28DA
D4/STOPC D0/INT0/EVNB R03/TOC R02/SO R01/SI R00/SCK RESET TEST/VPP R33/AN3
OSC1 OSC2 R30/AN0 R31/AN1 R32/AN2
FP-30D
D4/STOPC D0/INT0/EVNB R03/TOC R02/SO R01/SI R00/SCK RESET TEST/VPP R33/AN3
view
HD404394 Series
OSC1 OSC2 Vref R31/AN1 R32/AN2
DP-28S FP-28DA
D4/STOPC D0/INT0/EVNB R03/TOC R02/SO R01/SI R00/SCK RESET TEST/VPP R33/AN3
OSC1 OSC2 Vref 1/AN1 2/AN2
FP-30D
D4/STOPC D0/INT0/EVNB R03/TOC R02/SO R01/SI R00/SCK RESET TEST/VPP R33/AN3
view
HD404344R Series/HD404394 Series
Arrangement
HCD404344R, HCD40C4344R
Type Code
Type Code: HD404344R (HCD404344R) HD40C4344R (HCD40C4344R)
HD404344R Series/HD404394 Series
Bonding Coordinates
HCD404344R, HCD40C4344R
Chip center (X=0, Y=0) Type Code
Chip size 3.23 3.65 (mm) Coordinates: center Home point position: Chip center size (µm) Chip thickness: (µm)
Coordinates Name OSC1 OSC2 (µm) -1425 -1425 -1425 -1425 -1425 -1425 -1425 -1425 -1425 -1257 -891 -526 -162 (µm) 1370 1050 -115 -732 -997 -1244 -1627 -1627 -1627 -1627 -1627 -1627
Coordinates Name TEST RESET (µm) 1360 1418 1418 1418 1418 1418 1418 1418 1418 1075 -329 -732 -1135 (µm) -1627 -1456 -1072 -690 -306 1098 1501 1627 1627 1627 1627 1627 1627
HD404344R Series/HD404394 Series
Description
HD404344R Series, HD4074344
Number Item Power supply Symbol Test Reset Oscillator TEST RESET DP-28S/ FP-28DA FP-30D Chip Function Applies power voltage Connects ground Cannot used user applications. Connect this GND. Resets Input/output pins internal oscillator. Connect these pins ceramic oscillator, OSC1 external oscillator circuit.
Port D0-D
23-28
25-30
22-27
Input/output pins addressed individually bits; pins sink max. Four-bit input/output pins. Pins 0-R2 sink max.
0-R0 0-R1 0-R2 0-R3 Interrupt Stop clear Serial interface INT0 STOPC Timer EVNB converter 0-AN
1-8, 12-15 19-22
1-8, 13-16, 21-24
18-21, 28-30, 1-5, 10-13
12-15
13-16
10-13
Input external interrupts Input transition from stop mode active mode Serial interface clock input/output Serial interface receive data input Serial interface transmit data output Timer output Event count input Analog input pins converter
HD404344R Series/HD404394 Series
HD404394 Series
Number Item Power supply Symbol Test Reset Oscillator TEST RESET DP-28S/ FP-28DA FP-30D Function Applies power voltage Connects ground Cannot used user applications. Connect this GND. Resets Input/output internal oscillator. Connect these pins ceramic oscillator, external oscillator circuit Port D0-D 23-28 25-30 1-8, 14-16, 21-24 Input/output pins addressed individually bits; pins sink max. Four-bit input/output pins. Pins 0-R1 NMOS intermediate-voltage open drain pins. Pins 3-R2 NMOS standard-voltage open drain pins which sink max. Input external interrupts Input transition from stop mode active mode
0-R0 1-8, 0-R1 13-15 0-R2 19-22 1-R3 Interrupt Stop clear Serial interface INT0 STOPC Timer EVNB converter Vref
14-16
Serial interface clock input/output Serial interface receive data input Serial interface transmit data output Timer output Event count input Power supply internal ladder resistor converter Analog input pins converter
1-AN 13-15
HD404344R Series/HD404394 Series
HD404344R Series, HD4074344 Block Diagram
STOPC RESET OSC1 OSC2 TEST
INT0
Interrupt control
System control (256 bits)
port
EVNB
Timer
bits) bits)
port Timer bits) bits) Internal address Serial interface Internal data port bits) Internal data
converter
port bit) bit) port
bits) bits) bits) Data Instruction decoder bits)
Large-current
(1,024 bits) (2,048 bits) (4,096 bits)
Bidirectional signal line
HD404344R Series/HD404394 Series
HD404394 Series Block Diagram
STOPC RESET OSC1 OSC2 TEST
INT0
Interrupt control
System control (256 bits)
port
EVNB
Timer
bits) bits)
port Timer bits) bits) Internal address Internal data Serial interface
port bits) Internal data
Vref converter
port
Data
bit)
bit) port
Large-current
bits) bits)
Intermediatevoltage NMOS open drain pins
bits) Instruction decoder bits)
Standardvoltage NMOS open drain pins
(1,024 bits) (2,048 bits) (4,096 bits)
Bidirectional signal line
HD404344R Series/HD404394 Series
Memory
Memory memory shown figure explained follows.
Vector address Zero-page subroutine words) $003F $0040 $000F $0010
$0000
$0000 JMPL instruction (jump RESET, STOPC routine) $0001 JMPL instruction (jump timer routine) JMPL instruction (jump timer routine) JMPL instruction (jump converter routine) JMPL instruction (jump serial routine) used JMPL instruction (jump INT0 routine) $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
1023 1024
HD404341R, HD40C4341R, HD404391 program/pattern (1,024 words) HD404342R, HD40C4342R, HD404392 program/pattern (2,048 words)
HD404344R, HD40C4344R, HCD404344R, HCD40C4344R,HD404394, HD4074344, HD4074394
$03FF $0400
2047 2048
$07FF $0800
4095 4096
program/pattern (4,096 words)
$0FFF $1000
used
16383
$3FFF
Figure Memory
HD404344R Series/HD404394 Series
Vector Address Area ($0000 $000F): When reset interrupt process executed, program will begin executing from vector address. JMPL instructions which branch reset routine interrupt routine should programmed these addresses. Zero-Page Subroutine Area ($0000-$003F): This area reserved subroutines. program branches subroutine this area response instruction. Pattern Area: HD404341R, HD40C4341R, HD404391-$0000 $03FF HD404342R, HD40C4342R, HD404392-$0000 $07FF HD404344R, HD40C4344R, HCD404344R, HCD40C4344R, HD404394, HD4074344, HD4074394- $0000 $0FFF This area contains data which referenced with instruction. Program Area: HD404341R, HD40C4341R, HD404391-$0000 $03FF HD404342R, HD40C4342R, HD404392-$0000 $07FF HD404344R, HD40C4344R, HCD404344R, HCD40C4344R, HD404394, HD4074344, HD4074394- $0000 $0FFF
HD404344R Series/HD404394 Series
Memory
contains digits bits which used memory registers, data stack areas. interrupt control bits area, special register area, register flag area mapped into memory. memory area shown figure explained follows.
$000 RAM-mapped registers $040 $050
Data (176 digits)
$100
Memory registers (MR)
used
$000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F
Interrupt control bits area Port mode register (PMRA) Serial mode register (SMR) Serial data register lower (SRL) Serial data register upper (SRU) used Timer mode register (TMB1) Timer (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register (TMC) Timer (TRCL/TWCL) (TRCU/TWCU)
used
$3C0 Stack digits)
$3FF $016 $017 $018 $019 $01A
channel register data register lower data register upper mode register mode register
(ACR) (ADRL) (ADRU) (AMR1) (AMR2)
used
$020 Register flag area $023 $024 Port mode register (PMRB) $025 Port mode register (PMRC) $026 Timer mode register (TMB2) used
Note: registers mapped same area ($00A, $00B, $00E, $00F).
$02C $02D
Read only Write only R/W: Read/write
$030 $031 $032 $033
Port D0-D3 Port used Port Port Port Port
(DCD0) (DCD1)
(DCR0) (DCR1) (DCR2) (DCR3)
used
$03F
$00A Timer read register lower (TRBL) Timer write register lower (TWBL) $00B Timer read register upper (TRBU) Timer write register upper (TWBU) $00E Timer read register lower (TRCL) Timer write register lower (TWCL) $00F Timer read register upper (TRCU) Timer write register upper (TWCU)
Figure Memory
HD404344R Series/HD404394 Series
Register Area ($000 $03F): Interrupt control bits area: $000 $003 This area made bits used interrupt control shown figure Each accessed only manipulation instructions (SEM/SEMD, REM/REMD, TM/TMD). Some bits however, have limitations along with certain instructions shown figure Special register area: $004 $01F, $024 $03F This area made mode registers data registers, such external interrupt, serial interface, timers, converter, data control ports. configurations shown figures These registers categorized write-only, read-only, write/read. They accessed manipulation instructions. Register flag area: $020 $023 This area used WDON flag other interrupt control flags. configuration shown figure Each accessed only SEM/SEMD, REM/REMD, TM/TMD instructions. Some bits however, have limitations along with certain instructions shown figure Data Area ($040 $0FF): Sixteen digits this area, from $040 $04F, memory registers. These registers accessed LAMR XMRA instructions. configuration shown figure Stack Area ($3C0 $3FF): This area used hold program counter (PC), status flag (ST), carry flag (CA) subroutine calls (CAL CALL instructions) interrupts. Since four digits used each level, this area used stacking subroutines. stacking order saved data storing bits shown figure program counter recovered RTNI instructions. status carry flags recovered only RTNI instruction. area used stack area available data storage.
HD404344R Series/HD404394 Series
Address
$0000
INT0)
(Interrupt enable flag)
INT0)
(Reset bit)
$0001
$0002
IMTC timer serial)
IFTC timer
IMTB timer IMAD A/D)
IFTB timer
IFAD A/D)
$0003
serial)
Interrupt control bits area
$020
ADSF (A/D start flag)
WDON (Watchdog flag)
used
$021
Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer
RAME (RAM enable flag)
IAOF (IAD flag)
$022
$023
Register flag area
Figure Configuration Interrupt Control Bits Register Flag Areas
SEM/SEMD IAOF RAME WDON ADSF used used processed processed used used processed
REM/REMD used used used processed Inhibited access processed
TM/TMD used used Inhibited access Inhibited access used Inhibited access
WDON reset reset stop mode release with STOPC. REM/REMD ADSF during conversion. instruction excuted inhibited non-existing bits, value becomes invaild.
Figure Limitations Manipulation Instructions
HD404344R Series/HD404394 Series
Register name
PMRA TMB1 TRBL/TWBL TRBU/TWBU TRCL/TWCL TRCU/TWCU
ADRL ADRU AMR1 AMR2
PMRB PMRC TMB2
DCD0 DCD1
DCR0 DCR1 DCR2 DCR3
$000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F
used
IMTC R00/SCK
IFTC R03/TOC
IFTB IFAD R02/SO
IMTB IMAD R01/SI Serial data transfer speed Serial data register (lower) Serial data register (upper)
Reload control
Pull-up control Reload control
Timer clock source Timer register (lower) Timer register (upper) PMOS control Timer clock source Timer register (lower) Timer register (upper)
R33/AN3
channel selection data register (lower) data register (upper) R32/AN2 R31/AN1
R30/AN0* conversion speed
RAME
ADSF IAOF
WDON
D4/STOPC
D0/INT0/EVNB idle level Transmit clock EVNB edge detection
DCR*
Note: Applies HD404344R series HD4074344. Does apply HD404394 series.
Figure Special Register Area
HD404344R Series/HD404394 Series
Memory registers $040 MR(0) $041 MR(1) $042 MR(2) $043 MR(3) $044 MR(4) $045 MR(5) $046 MR(6) $047 MR(7) $048 MR(8) $049 MR(9) $04A MR(10) $04B MR(11) $04C MR(12) $04D MR(13) $04E MR(14) $04F MR(15) $3C0 Stack area Level Level Level Level Level Level Level Level Level Level Level Level Level Level Level $3FF Level
$3FC $3FD $3FE $3FF
PC13
PC11
PC13 -PC0 Program counter Status flag Carry flag Note: Since HD404344R series, HD4074344 HD404394 series have 4-kword ROM, PC12 PC13 ignored.
Figure Configuration Memory Registers, Stack Area, Stack Position
HD404344R Series/HD404394 Series
Functional Description
Registers Flags nine registers flags. Their configurations shown figure explained follows.
Accumulator Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, (SPY) (SPX)
Carry Initial value: Undefined, (CA) Status Program counter Initial value: Stack pointer Initial value: $3FF, Initial value: (PC) (SP) (ST)
Figure Registers Flags
HD404344R Series/HD404394 Series
Accumulator (A), Register (B): accumulator register 4-bit registers used storing operation results data that transferred between memory ports between other registers. Register (W), Register (X), Register (Y): register 2-bit register registers 4-bit registers. These used indirect addressing RAM. register also used addressing port. Register (SPX), Register (SPY): registers 4-bit registers that supplement registers, respectively. Carry Flag (CA): carry flag latches overflow during arithmetic instruction execution. controlled SEC, REC, ROTL, ROTR instructions. carry flag stored during interrupt processing, then recovered from stack RTNI instruction. affected instruction.) Status Flag (ST): status flag latches overflow arithmetic instructions compara tive instructions, also results non-zero test instructions. then used branch conditions BRL, CAL, CALL instructions. status flag remains unchanged until next arithmetic instruction, comparative instruction, test executed. After BRL, CAL, CALL instruction executed, status flag will regardless instruction executed skipped. contents status flag stored stack during interrupt processing, then recovered from stack RTNI instruction. Program Counter (PC): This 14-bit binary counter maintains address information. Stack Pointer (SP): stack pointer 10-bit register which contains address next stack space used. initialized $3FF reset. When data stored onto stack, decremented when data pulled from stack, incremented four bits stack pointer fixed 1111, used maximum levels. There ways initializing stack pointer $3FF. reset other resetting with REMD instruction. Reset reset executed setting RESET low. RESET input must more than keep oscillator steady during power when stop mode cancelled. other cases, reset RESET input minimum instruction cycle times. Initialized values reset listed table
Certain bits interrupt control bits area register flag area reset SEM/SEMD REM/REMD instructions. Also these tested TM/TMD instruction. following specifies limitations each bit.
HD404344R Series/HD404394 Series
Table
Item Program counter
Initial Values After Reset
Abbr. (PC) Initial Value $0000 Contents Indicates program execution point from start address area Enables conditional branching Stack level Inhibits interrupts Indicates there interrupt request Prevents (masks) interrupt requests Enables output level Turns output buffer high impedance)
Status flag Stack pointer Interrupt flags/mask Interrupt enable flag Interrupt request flag Interrupt mask Port data register Data control register
(ST) (SP) (IE) (IF) (IM) (PDR) (DCD0, DCD1)
$3FF bits bits
(DCR0,- DCR3) bits Port mode register Port mode register Port mode register (PMRA) (PMRB) (PMRC) 0000 Refer description port mode register Refer description port mode register Refer description port mode register Refer description timer mode register Refer description timer mode register Refer description timer mode register Refer description serial mode register
Timer/ Timer mode register (TMB1) counters, serial interface Timer mode register (TMB2) Timer mode register Serial mode register Prescaler Timer counter Timer counter Timer write register Timer write register Octal counter (TMC) (SMR) (PSS) (TCB) (TCC)
0000 0000 $000
(TWBU, TWBL) (TWCU, TWCL)
HD404344R Series/HD404394 Series
Table
Item mode register mode register register
Initial Values After Reset (cont)
Abbr. (AMR1) (AMR2) Initial Value 0000 Contents Refer description mode register Refer description mode register Refer description timer Refer description converter Refer description converter Refer description I/O, serial interface
Watchdog timer flag (WDON) start flag flag (ADSF) (IAOF) (MIS)
Others
Miscellaneous register
Notes: statuses other registers flags after reset shown following table. indicates invalid value. indicates that does exist.
Table
Initial Values After Reset (cont)
After Stop Mode Release STOPC Input After Stop Mode Release RESET Input After Other Types Reset Program needs initialize these registers.
Carry
(CA)
Program needs initialize these registers.
Accumulator register register X/SPX register Y/SPY register Serial data register data register enable flag Port mode register
(X/SPX) (Y/SPY) (SRU, SRL) (ADRU, ADRL) Data before entering stop mode kept. (RAME) (PMRB3) Data before entering stop mode kept.
HD404344R Series/HD404394 Series
Interrupts There five kinds interrupts: external timer timer serial interface, converter. interrupt request flag interrupt mask vector address used each type interrupt. They used storing interrupt requests interrupt controls. interrupt enable flag also used total interrupt control. Interrupt Control Bits Interrupt Processing: interrupt control bits mapped from $000 $003 accessed manipulation instructions. However, interrupt request flag (IF) cannot software. reset initializes interrupt enable flag (IE) interrupt request flag (IF) interrupt mask (IM) block diagram interrupt control circuit shown figure interrupt priority order vector addresses listed table figure, along with conditions executing interrupt processing five types interrupt requests (table interrupt request occurs when interrupt request flag interrupt mask interrupt enable flag interrupt processing occurred. vector address which corresponds interrupt source generated from priority PLA. interrupt processing sequence shown figure interrupt processing flowchart shown figure After receiving interrupt, previous instruction completed first cycle. interrupt enable flag (IE) reset after cycles. contents carry flag, status flag, program counter stored onto stack second third cycles. Instruction execution restarted jumping vector address during third cycle. JMPL instructions, which branch start addresses interrupt routines, should programmed each vector address area. interrupt request which initiated interrupt processing should reset software instructions interrupt routine.
HD404344R Series/HD404394 Series
$000,0 (RESET, STOPC $000,2 INT0 interrupt $000,3 $002,0 Timer interrupt IFTB $002,1 IMTB $002,2 Timer interrupt IFTC $002,3 IMTC $003,0 interrupt IFAD $003,1 IMAD $003,2 Serial interrupt $003,3 Priority Controller Priority Order Vector Address $0000 $0002 $0008 $000A $000C $000E Interrupt request
Note: STOPC interrupt request enabled only when stop mode.
Figure Interrupt Control Circuit, Vector Addresses, Interrupt Priorities
HD404344R Series/HD404394 Series
Table Interrupt Processing Activation Conditions
Interrupt Source Interrupt Control IFTB IMTB IFTC IMTC IFAD IMAD INT0 Timer Timer Serial
Note: either Their values have effect operation.
Instruction cycles
Instruction execution*
Interrupt acceptance
Stacking; reset
Stacking; Vector address generation
Execution JMPL instruction vector address
Execution instruction start address interrupt routine
Note:
stack accessed interrupt enable flag reset after instruction executed, even two-cycle instruction.
Figure Interrupt Processing Sequence
HD404344R Series/HD404394 Series
Power
RESET
Interrupt request?
Accept interrupt
Execute instruction Reset
(PC)
Stack (PC) Stack (CA) Stack (ST)
$0002
INT0 interrupt?
$0008
Timer interrupt?
$000A
Timer interrupt?
$000C
interrupt?
$000E (serial interrupt)
Figure Interrupt Processing Flowchart
HD404344R Series/HD404394 Series
Interrupt Enable Flag (IE: $000, interrupt enable flag executes interrupt enable/disable interrupt requests listed table reset interrupt processing RTNI instruction. Table
Interrupt Enable Flag (IE: $000,
Interrupt Enabled/Disabled Disabled Enabled
External Interrupt (INT0): INT0 input should selected using port mode register (PMRB: $024), that external interrupt request flag (IF0) falling edge INT0 input. External Interrupt Request Flag (IF0: $000, external interrupt request flag INT0 input edge, listed table Table
External Interrupt Request Flag (IF0: $000,
Interrupt Request
External Interrupt Mask (IM0: $000, which masks interrupt request caused external interrupt request flag, listed table Table
External Interrupt Mask (IM0: $000,
Interrupt Request Enabled Disabled (masked)
Timer Interrupt Request Flag (IFTB: $002, timer interrupt request flag overflow output timer listed table Table
IFTB
Timer Interrupt Request Flag (IFTB: $002,
Interrupt Request
HD404344R Series/HD404394 Series
Timer Interrupt Mask (IMTB: $002, IMTB which masks interrupt request caused timer interrupt request flag, listed table Table
IMTB
Timer Interrupt Mask (IMTB: $002,
Interrupt Request Enabled Disabled (masked)
Timer Interrupt Request Flag (IFTC: $002, timer interrupt request flag overflow output timer listed table Table
IFTC
Timer Interrupt Request Flag (IFTC: $002,
Interrupt Request
Timer Interrupt Mask (IMTC: $002, IMTC which masks interrupt request caused timer interrupt request flag, listed table Table
IMTC
Timer Interrupt Mask (IMTC: $002,
Interrupt Request Enabled Disabled (masked)
Serial Interrupt Request Flag (IFS: $003, serial interrupt request flag when serial data transfer completed when data transfer suspended, listed table Table
Serial Interrupt Request Flag (IFS: $003
Interrupt Request
HD404344R Series/HD404394 Series
Serial Interrupt Mask (IMS1: $003, IMS1 which masks interrupt request caused serial interrupt request flag, listed table Table
Serial Interrupt Mask (IMS: $003,
Interrupt Request Enabled Disabled (masked)
Interrupt Request Flag (IFAD: $003, interrupt request flag after conversion completed, listed table Table
IFAD
Interrupt Request Flag (IFAD: $003,
Interrupt Request
Interrupt Mask (IMAD: $003, IMAD which masks interrupt request caused interrupt request flag, listed table Table
IMAD
Interrupt Mask (IMAD: $003,
Interrupt Request Enabled Disabled (masked)
HD404344R Series/HD404394 Series
Operating Modes
three operating modes shown table transitions between operating modes shown figure Table
Function System oscillator Timers Serial
Operations Each Operating Mode
Active Mode Standby Mode Retained Retained Retained* Stop Mode Stopped Reset Retained Reset Reset Reset Reset
Notes: implies operation. Since input/output circuits operation, current will flow in/out depending status standby mode. Note that this current addition standby mode dissipation current.
instruction Interrupt request Standby mode
Active mode
STOP instruction
RESET
RESET
Stop mode
RESET reset
RESET
Figure Status Transition
HD404344R Series/HD404394 Series
Active Mode: functions operate active mode. active mode, controlled oscillating circuit OSC1 OSC2. Standby Mode: switches standby mode when instruction executed. standby mode, oscillator continues operating, clocks related instruction execution stops running. This causes stop operating. However, contents retained. Also, ports, which output, maintain their status before entering standby mode. peripheral functions, such interrupt, timers, serial interface, converter, continue operating. Power dissipation standby mode less than active mode because operating. enters standby mode when instruction executed active mode. terminate standby mode, provide RESET input interrupt request. reset input given, will reset. interrupt request given, will change active mode next instruction will executed. After instruction execution, interrupt enable flag interrupt operation executed. interrupt enable flag normal instruction execution continues interrupt request left pending. standby mode flowchart shown figure Stop Mode: enters stop mode when STOP instruction received. stop mode, functions stop, except maintaining data. Power dissipation this mode therefore lowest operating modes. stop mode, OSC1 OSC2 oscillator stopped. terminate stop mode provide either RESET STOPC input shown figure When terminating stop mode, important ensure proper oscillation stabilization period least RESET STOPC input. (Refer characteristics tables.) After clearing stop mode, maintains data kept before entering stop mode. However, contents accumulator, register, register, X/SPX register, Y/SPY register, carry flag, serial data register maintained. Clearing Stop Mode Using STOPC: transition from stop mode active mode either RESET STOPC input. starts instruction execution from start program address Then enable flag (RAME: $021, accordingly, RAME RESET input RAME STOPC input. RESET input effective when mode. STOPC input however, effective only stop mode ignored other modes. when clearing stop mode with STOPC input program needs identify RAME status. (For example, when contents before entering stop mode used after transition active mode.) TEST instruction enable flag (RAME) should executed beginning program.
HD404344R Series/HD404394 Series
Table
Mode Active mode
Operating Modes Transition Conditions
Conditions Enter Mode RESET release Interrupt request STOPC release stop mode instruction RESET input Interrupt request RESET input STOPC input stop mode Conditions Exit Mode RESET input STOP/SBY instruction
Standby mode
Stop mode
STOP instruction
Stop mode Oscillator Internal clock
RESET STOPC STOP instruction execution
tres tres (stabilization period)
Figure Timing Stop Mode Cancellation
HD404344R Series/HD404394 Series
Stop Standby
Oscillator: Stop Peripheral clocks: Stop other clocks: Stop
Oscillator: Active Peripheral clocks: Active other clocks: Stop
RESET
RESET
STOPC
IFTB IMTB
IFTC IMTC
IFAD IMAD
RAME
RAME
Restart processor clocks
Execute next instruction
Restart processor clocks
Reset
Execute next instruction
Interrupt accept
Figure Process Flowchart
HD404344R Series/HD404394 Series
Operation Sequence: operates according flowcharts shown figures Since RESET asynchronous input, will reset mode that operating low-power mode operation sequence shown figure With flag cleared interrupt flag together with interrupt mask cleared, STOP/SBY instruction executed, instruction cancelled (regarded NOP) following instruction executed. Before executing STOP/SBY instruction, make sure interrupt flags cleared interrupts masked.
Power
RESET
RAME
operation cycle
Reset
Figure Operation Sequence (Power
HD404344R Series/HD404394 Series
operation cycle
Instruction execution
SBY/STOP instruction?
Stack (PC), (CA), (ST)
Low-power mode operation cycle
Next location
Vector address
Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag
Figure Operation Sequence (MCU Operation Cycle)
HD404344R Series/HD404394 Series
Low-power mode operation cycle
Standby mode (SBY)
Stop mode
STOPC
Hardware execution Hardware execution
RAME
Next Iocation
Next Iocation
Reset
Instruction execution
operation cycle
Note: operation, refer figure
Figure Operation Sequence (Low Power Mode Operation)
HD404344R Series/HD404394 Series
Oscillator Circuit
Figure shows block diagram clock generation circuit. Ceramic oscillator connected OSC2 listed table external clock also connected. addition, system oscillator HD404344R Series capable oscillation.
OSC2 OSC1
System fOSC division oscillator circuit
fcyc tcyc
Timing generator circuit
System clock generation
with ROM, RAM, registers, flags,
Peripheral function interrupt
Figure Clock Generation Circuit
OSC1 OSC2
Figure Typical Layout Ceramic Oscillator
HD404344R Series/HD404394 Series
Table Oscillator Circuit Examples
Circuit Configuration External clock operation
External oscillator
Circuit Constants
Open
Ceramic oscillator (OSC1,
Ceramic oscillator CSA4.00MG (Murata)
OSC1 Ceramic oscillator OSC2
±20% ±20% Ceramic oscillator: KBR-4.0MSA (Kyocera) ±20% ±20%
oscillation (OSC1, HD404344R series
OSC1 OSC2
Notes: Since circuit constants change depending ceramic oscillator stray capacitance board, user should consult with ceramic oscillator manufacturer determine circuit parameters. Wiring among OSC1, elements should short possible, must cross other wiring (see figure 18).
HD404344R Series/HD404394 Series
Input/Output
HD404344R series HD4074344 input/output pins (D0-D R00-R3 HD404394 input/output pins (D0-D5, R00-R2 R31-R3 These input/output pins have following features: pins HD404344R series HD4074344 have CMOS output circuit. pins 0-R2 large current input/output pins. Three input/output pins pins HD404394 series, R10-R12, have intermediate-voltage NMOS open drain output circuits. Five other input/output pins, R20-R23, have standard-voltage NMOS open drain output circuits. remaining input/output pins, D0-D5, R00-R0 R31-R33, have CMOS output circuits. pins R10-R2 high-current input/output pins. Some input/output pins multiplexed with peripheral functions, such timers serial interface. these pins, settings peripheral functions done prior ports settings. these pins peripheral functions, functions input/output selections automatically switch according settings. Program control input/output port selection, well peripheral function selection. peripheral function output pins CMOS output pins. However, 2/SO programmed NMOS open drain output. stop mode, peripheral function selections cleared because being reset. Also, input/output pins into high-impedance state. input/output pins both HD404344R series, HD4074344 HD404394 series except pins R10-R2 have built-in pull-up MOS. Therefore they individually turned software. When functions peripheral functions after selecting pins pull-up MOS, pins maintained pull-up from time selection. Also, pull-up selected software after setting functions peripheral functions. control input/output pins shown table circuit configuration each input/output shown table Table Programmable Control Standard Pins
PMOS NMOS Pull-up Note: indicates off.
MIS3 (bit MIS) DCD, CMOS buffer
HD404344R Series/HD404394 Series
Table Circuit Configurations Pins
Pins HD404344R Series, HD4074344
Pull-up control signal Buffer control signal DCD, Output data MIS3
HD404394 Series D0-D 1-R3
Type Input/output pins
Circuit
D0-D 0-R3
Input data Input control signal
None
Buffer control signal Output data
0-R2 (standard voltage pins)
Input data Input control signal Pull-up control signal Buffer control signal Output data MIS2 MIS3
Input data Input control signal Input data Input control signal
None
0-R1 (middle voltage pins)
HD404344R Series/HD404394 Series
Table Circuit Configurations Pins (cont)
Pins HD404344R HD404394 Series, Series HD4074344
Pull-up control signal MIS3
Type Peripheral function pins Input/ output pins
Circuit
Output data Input data
MIS3
Output pins
Pull-up control signal
PMOS control signal MIS2 Output data MIS3
Pull-up control signal
Output data
Input pins
Input data
MIS3 INT0, EVNB, STOPC MIS3
INT0, EVNB, STOPC
INT0, EVNB, STOPC
0-AN
1-AN
input
Input control
Note: stop mode, reset peripheral function selection cancelled. Also, signal goes low, input/output pins enter high-impedance state.
HD404344R Series/HD404394 Series
Port port consists input/output pins each addressed bit. ports reset SED/RED SEDD/REDD instructions. Output data stored port data register (PDR) each pin. Also, ports tested TD/TDD instructions. on/off status output buffers controlled D-port data control registers (DCD0, DCD1: $02C $02D), which mapped memory addresses (figure 19). Pins multiplexed with peripheral function pins INT0/EVNB, STOPC. Setting peripheral functions these pins executed bits (PMRB3, PMRB0) port mode register (PMRB: $024) (figure 20).
Data control register DCD0, DCD1 DCR0 DCR3 Initial value Read/Write name DCD03 (DCD0, DCD1: $02C, $02D) (DCR0 DCR3: $030 $033) DCD02 DCD01 DCD11 DCR01 DCR31 DCD00 DCD10 DCR00 DCR30 Bits CMOS Buffer Control CMOS buffer (high impedance) CMOS buffer
DCR03 DCR33
DCR02 DCR32
Correspondence between ports bits Register DCD0 DCD1 DCR0 DCR1 DCR2 DCR3 R30*
Note: Available HD404344R series HD4074344, available HD404394 series.
Figure Data Control Register (DCR)
HD404344R Series/HD404394 Series
Port mode register (PMRB: $024) Initial value Read/Write name
PMRB3 used used PMRB0
PMRB3 D4/STOPC Mode Selection STOPC
PMRB0
D0/INT0 /EVNB Mode Selection INT0 /EVNB
Figure Port Mode Register (PMRB)
HD404344R Series/HD404394 Series
Port port consists input/output pins each addressed bits. Input/output controlled instructions instructions. output data stored port data register (PDR) each pin. on/off status output buffers controlled R-port data control registers (DCR0-DCR3: $030-$033), which mapped memory addresses (figure 19). R10-R1 ports HD404394 series n-channel middle-voltage open drain input/output pins. R00-R03 pins also used peripheral function pins: SCK, TOC. Setting peripheral functions these pins executed (SMR3) serial mode register (SMR:$005) bits (PMRA2-PMRA0) port mode register (PMRA: $004), shown figures R30-R3 pins HD404344R series HD4074344 also used AN0-AN3 peripheral function pins. Pins R31-R33 HD404394 series also used 1-AN3 peripheral function pins. setting peripheral functions these pins executed bits (AMR13-AMR10) mode register (AMR1: $019). HD404394 series, AMR10 prohibited (figure 23).
Port mode register (PMRA: $004) Initial value Read/Write name
used PMRA2 PMRA1 PMRA0 PMRA0 R02/SO Mode Selection R01/SI Mode Selection
PMRA2
R03/TOC Mode Selection
PMRA1
Figure Port Mode Register (PMRA)
HD404344R Series/HD404394 Series
Serial mode register (SMR: $005) Initial value Read/Write name SMR3 SMR2 SMR1 SMR0
SMR3
R00/SCK Mode Selection
SMR2
SMR1
SMR0
Output
Clock Source Prescaler
Prescaler Division Ratio table
Output Input
System clock External clock
Figure Serial Mode Register (SMR)
mode register (AMR1: $019) Initial value Read/Write name AMR13 AMR12 AMR11 AMR10 AMR10* AMR12 AMR13 R32/AN2 Mode Selection R33/AN3 Mode Selection AMR11 R30/AN0 Mode Selection R31/AN1 Mode Selection
Note: Available HD404344R series HD4074344, available HD404394 series.
Figure Mode Register (AMR1)
HD404344R Series/HD404394 Series
Pull-Up Transistor Control Pull-up MOS, which controlled software, built into input/output pins except R10-R2 HD404394 series. on/off status pull-up pins controlled (MIS3) miscellaneous register (MIS: $00C) port data registers (PDR) each pin. Each therefore independently switch between with without pull-up (table figure 24). on/off status each transistor peripheral function mode each independently.
Miscellaneous register (MIS: $00C) Initial value Read/Write name MIS3 MIS2 MIS1 MIS0
MIS3
Pull-Up On/Off Selection Pull-up Pull-up
MIS2
PMOS On/Off Selection R02/SO
Programming MIS1 MIS0 prohibited.
Figure Miscellaneous Register Deal with Unused Pins When input/output pins being used left floating, necessary these pins reduce possibility malfunctions noise. This done selecting pull-up pins connecting external pull-up resistor about each unused pin.
HD404344R Series/HD404394 Series
Prescaler
built-in prescaler, (PSS). This divides system clock outputs divided clock peripheral function modules shown figure Clocks timers except external events, clocks serial interface except external clock selected from prescaler output programming each mode register. Prescaler 11-bit counter which inputs system clock. After reset clears prescaler $000, begins dividing system clock. Prescaler stops operating either reset stop mode. cannot stopped other mode.
Timer Timer System clock Prescaler Serial
Figure Prescaler Output Supply
HD404344R Series/HD404394 Series
Timers
built-in timers, functions each timer listed table Table
Functions Clock source Prescaler External event Timer functions Free-running Event counter Reload Watchdog Timer output
Timer Functions
Timer Available Available Available Available Available Timer Available Available Available Available Available
Timer Timer 8-bit multifunction timer that includes free-running, reload, event counter features. These described follows. setting timer mode register (TMB1: $009), seven internal clocks supplied from prescaler selected, timer used external event counter. setting timer mode register (TMB2: $026), timer incremented each edge detector input signals EVNB. setting timer write register (TWBL, TWBU: $00A, $00B), timer counter (TCB) written during reload timer operation. setting timer read register (TRBL, TRBU: $00A, $00B), contents timer counter read out. Timer Operation Free-running/reload timer operation: selection free-running/reload timer, input clock source, prescaler division ratio done timer mode register (TMB1: $009). Timer initialized data which written timer write register (TWBL: $00A, TWBU: $00B) software. data then incremented steps using input clock. clock input continued after timer $FF, overflow occurs. Timer then begins counting again, setting timer value timer write register (TWBL: $00A, TWBU: $00B) when reload timer selected, reset when free-running timer selected.
HD404344R Series/HD404394 Series
timer interrupt request flag overflow. Resetting timer interrupt request flag (IFTB: $002, executed either software reset. External event counter operation: setting external event input input clock source, timer operate external event counter. D0/INT 0/EVNB pins INT0/EVNB pins port mode register (PMRB: $024). detection edge external event counter timer selected rising edge, falling edge, rising/falling edge timer mode register (TMB2: $026). When rising/falling edge selected, period must more than 2tcyc between falling edge rising edge. Timer incremented using edge selection timer mode register (TMB2: $026). Other functions based free-running/reload timer.
Interrupt request flag timer (IFTB) Timer read register (TRBU)
Timer read register lower (TRBL)
Clock Internal data Free-running timer control Timer counter (TCB) Overflow
Timer write register upper (TWBU) Timer write register lower (TWBL)
EVNB Edge detector
Selector ÷128 ÷512 ÷2048
Timer mode register (TMB1)
System clock
Prescaler (PSS) Edge detection control
Timer mode register (TMB2)
Figure Timer Free-Running Reload Operation Block Diagram
HD404344R Series/HD404394 Series
Using Timer Registers Timer sets operation read/write data according following registers. Timer mode register (TMB1: $009) Timer mode register (TMB2: $026) Timer write register (TWBL: $00A, TWBU: $00B) Timer read register (TRBL: $00A, TRBU: $00B) Port mode register (PMRB: $024)
Timer mode register (TMB1: $009): Four-bit write-only register that selects free-running/reload timer, input clock, prescaler division ratio, shown figure reset reset. Data written timer mode register valid after instruction cycles. initial setting timer which writing timer write register (TWBL: $00A, TWBU: $00B), should programmed only after mode change been effective.
Timer mode register (TMB1: $009) Initial value Read/Write name TMB13 TMB12 TMB11 TMB10
TMB13
Free-Running/Reload Timer Selection Free-running timer Reload timer
TMB12
TMB11
TMB10
Input Clock Period Input Clock Source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc D0/INT0/EVNB (external event input)
Figure Timer Mode Register (TMB1)
HD404344R Series/HD404394 Series
Timer mode register (TMB2: $026): Two-bit write-only register that sets input edge detection EVNB, shown figure reset reset.
Timer mode register (TMB2: $026) Initial value Read/Write name TMB20 TMB20 EVNB Edge Detection Selection detection Falling-edge detection Rising-edge detection Rising- falling-edge detection
used used TMB21 TMB21
Figure Timer Mode Register (TMB2) Timer write register (TWBL: $00A, TWBU: $00B): Write-only register consisting lower digit (TWBL) upper digit (TWBU). lower digit reset reset, upper digit value cannot guaranteed. figures Timer initialized writing timer write register (TWBL: $00A, TWBU: $00B). this case, lower digit (TWBL) must written first, writing only lower digit does change timer value. Timer initialized value timer write register same time upper digit (TWBU) written When timer write register written again lower digit value needs change, writing only upper digit initializes timer
Timer write register (lower) (TWBL: $00A) Initial value Read/Write name TWBL3 TWBL2 TWBL1 TWBL0
Figure Timer Write Register (lower) (TWBL)
Timer write register (upper) (TWBU: $00B) Initial value Read/Write name
Undefined Undefined Undefined Undefined TWBU3 TWBU2 TWBU1 TWBU0
Figure Timer Write Register (upper) (TWBU)
HD404344R Series/HD404394 Series
Timer read register (TRBL: $00A, TRBU: $00B): Read-only register consisting lower digit (TRBL) upper digit (TRBU) that holds count timer upper digit. figures upper digit (TRBU) must read first. this time, count timer upper digit obtained, count timer lower digit latched lower digit (TRBL). After this, reading TRBL, count timer when TRBU read obtained.
Timer read register (lower) (TRBL: $00A) Initial value Read/Write name TRBL3 TRBL2 TRBL1 TRBL0
Undefined Undefined Undefined Undefined
Figure Timer Read Register (lower) (TRBL)
Timer read register (upper) (TRBU: $00B) Initial value Read/Write name TRBU3 TRBU2 TRBU1 TRBU0
Undefined Undefined Undefined Undefined
Figure Timer Read Register (upper) (TRBU) Port mode register (PMRB: $024): Write-only register that selects D0/INT 0/EVNB shown figure reset reset.
HD404344R Series/HD404394 Series
Timer Timer 8-bit multifunction timer that includes free-running, reload, watchdog timer features, which selected described follows. setting timer mode register (TMC: $00D), eight internal clocks supplied from prescaler selected. selecting with (PMRA2) port mode register (PMRA: $004), timer output (PWM output) enabled. setting timer write register (TWCL, TWCU: $00E, $00F), timer counter (TCC) written setting timer read register (TRCL, TRCU: $00E, $00F), contents timer counter read out. interrupt requested when timer counter overflows. Timer counter used watchdog timer detecting runaway programs.
HD404344R Series/HD404394 Series
System reset signal Watchdog flag (WDON) Watchdog timer controller Interrupt request flag timer (IFTC)
Timer read register (TRCU) Timer output controller Timer read register lower (TRCL)
Clock
Timer counter (TCC) Timer output control
Overflow Internal data
Timer write register upper (TWCU) Timer write register lower (TWCL)
Selector ÷128 ÷512 ÷1024 ÷2048
Free-running/ reload timer control
System clock
Prescaler (PSS)
Timer mode register (TMC)
Port mode register (PMRA)
Figure Timer Block Diagram Timer Operation Free-running/reload timer operation: selection free-running/reload timer, input clock source, prescaler division ratio done timer mode register (TMC: $00D). Timer initialized data, which written timer write register (TWCL: $00E, TWCU: $00F) software. data then incremented steps using input clock. clock input continued after timer $FF, overflow occurs. Timer then begins counting again, setting timer value timer write register (TWCL: $00E, TWCU: $00F) when reload timer selected, reset when free-running timer selected. timer interrupt request flag overflow. Resetting timer interrupt request flag (IFTC: $002, executed either software reset.
HD404344R Series/HD404394 Series
Watchdog timer operation: Timer used watchdog timer programs that control. watchdog timer enabled when setting watchdog flag (WDON: $020, When timer overflows, reset occurs. This usually controls programs running control initializing timer through software before timer counts (figure 34).
Overflow Timer count value
Time
operation
Normal operation
Timer clear
Normal operation
Timer clear
Program runaway
Reset
Normal operation
Figure Watchdog Timer Operation Flowchart Timer output operation: Timer select timer output mode selecting after setting (PMRA2) port mode register (PMRA: $004) output initialized reset. output pulse output function variable duty. output wave differs contents timer mode register timer write register shown figure
TMC3 (free-running timer) TMC3 (reload timer) (256 Notes: Input clock period supplied counter. (The clock input source system clock division ratio determined timer mode register Value timer write register (When ($FF), output fixed low.)
Figure Output Waveform
HD404344R Series/HD404394 Series
Using Timer Registers Timer sets operation read/write data according following registers. Timer mode register (TMC: $00D) Timer write register (TWCL: $00E, TWCU: $00F) Timer read register (TRCL: $00E, TRCU: $00F) Timer mode register (TMC: $00D): Four-bit write-only register that selects free-running/reload timer, input clock, prescaler division ratio, shown figure reset reset. data written timer mode register valid after instructions cycles. initial setting timer which writing timer write register (TWCL: $00E, TWCU: $00F), should programmed execute only after mode change been effective.
Timer mode register (TMC: $00D) Initial value Read/Write name TMC3 TMC2 TMC1 TMC0
TMC3
Free-Running/Reload Timer Selection Free-running timer Reload timer
TMC2
TMC1
TMC0
Input Clock Period 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc
Figure Timer Mode Register (TMC)
HD404344R Series/HD404394 Series
Timer write register (TWCL: $00E, TWCU: $00F): Write-only register consisting lower digit (TWCL: $00E) upper digit (TWCU: $00F), shown figures operation this register same that timer write register
Timer write register (lower) (TWCL: $00E) Initial value Read/Write name TWCL3 TWCL2 TWCL1 TWCL0
Figure Timer Write Register (lower) (TWCL)
Timer write register (upper) (TWCU: $00F) Initial value Read/Write name
Undefined Undefined Undefined Undefined TWCU3 TWCU2 TWCU1 TWCU0
Figure Timer Write Register (upper) (TWCU) Timer read register (TRCL: $00E, TRCU: $00F): Read-only register consisting lower digit (TRCL: $00E) upper digit (TRCU: $00F), which allows upper digit timer read directly (figures 40). operation this register same that timer read register
Timer read register (lower) (TRCL: $00E) Initial value Read/Write name TRCL3 TRCL2 TRCL1 TRCL0
Undefined Undefined Undefined Undefined
Figure Timer Read Register (lower) (TRCL)
Timer read register (upper) (TRCU: $00F) Initial value Read/Write name TRCU3 TRCU2 TRCU1 TRCU0
Undefined Undefined Undefined Undefined
Figure Timer Read Register (upper) (TRCU)
HD404344R Series/HD404394 Series
Notes When using timer output output, note following point. From update timer write register until occurrence overflow interrupt, output differs from period duty settings, shown table output should therefore used until after overflow interrupt following update timer write register. After overflow, output will have period duty cycle. Table Output Following Update Timer Write Register
Output Mode Free running Timer Write Register Updated during High Timer Write Register Updated during Output Output
Timer write register updated value Timer write register updated value
Interrupt request
Interrupt request
(255
(255
Reload
Timer write register updated value
Interrupt request
Timer write register updated value
Interrupt request
(255
(255
HD404344R Series/HD404394 Series
Serial Interface
one-channel 8-bit serial interface built with following features. different internal clocks external clock selected transmit clock. internal clocks include prescaler outputs divided four, system clock. During idle states, serial output controlled high output. Transmit clock errors detected. interrupt request generated when errors occurred data transfer completed.
Idle controller controller Clock
Octal counter (OC)
Serial interrupt request flag (IFS)
Serial data register (SR) Internal data
Selector ÷128 ÷512 ÷2048 Serial mode register (SMR)
System clock
Prescaler (PSS)
Selector
Transfer control signal
Port mode register (PMRC)
Figure Serial Interface Block Diagram
HD404344R Series/HD404394 Series
Serial Interface Operation Selection Changing Serial Interface Operation Mode: available settings port mode register (PMRA: $004) serial mode register (SMR: $005) shown table change operating mode initialize serial interface, write serial mode register. 0/SCK controlled writing data serial mode register (SMR: $005). 2/SO pins controlled writing data port mode register (PMRA: $004). Table
Serial Interface Operating Modes
PMRA Operating Mode Continuous clock output mode Transmit mode Receive mode Transmit/receive mode
Setting Serial Clock Source: transmit clock writing serial mode register (SMR: $005) port mode register (PMRC: $025). Serial Data Setting: Serial data sent writing serial data register (SRL: $006 SRU: $007). Serial data then obtained reading serial data register. Serial data shifted transmit clock. output undefined until first serial data output after reset, until output level control performed during idle state. Transfer Control: Serial interface operation initiated instruction. octal counter reset instruction then incremented rising edge transmit clock. eight rising edges from transmit clock input serial data transfer cut-off, counter reset 000, serial interrupt request flag (IFS: $003, set, serial data transfer stops. using built-in prescaler output transmit clock, selection transmit clock frequency from 4tcyc 8192t setting bits (SMR2-SMR0) serial mode register (SMR: $005) (PMRC0) port mode register (PMRC: $025). Writing these registers setting transmit clock shown table
HD404344R Series/HD404394 Series
Table
PMRC
Transmit Clock Selection (Prescaler Output)
Prescaler Division Ratio 2048 4096 1024 Transmit Clock Frequency 4096t 1024t 256t 8192t 2048t 512t 128t
Serial Interface Operating States: serial interface following operating states shown figure both external clock mode internal clock mode. wait state Transmit clock wait state Transfer state Continuous clock output (internal clock mode only)
wait state: serial interface into wait state reset (00, figure 42). While this state, serial interface initialized does operate, even transmit clock provided. instruction executed while this state (01, 11), serial interface transfers transmit clock wait state. Transmit clock wait state: Transmit clock wait state period starts from when instruction executed until first transmit clock falling edge. While transmit clock wait state, transmit clock input (02, 12), octal counter incremented transmit clock, data serial data register shifts, serial interface enters transfer state. However, note that continuous clock output mode selected internal clock mode, serial interface does enter transfer state enters continuous clock output state (17). writing serial mode register (SMR: $005) (04, while transmit clock wait state, serial interface changes wait state. Transfer state: transfer state period starts from first falling edge transmit clock eighth rising edge transmit clock. While transfer state, instruction executed eight pulses transmit clock applied, octal counter will reset state will change. instruction executed (05, 15), state changes transmit clock wait state. After
HD404344R Series/HD404394 Series
eight pulses transmit clock, state changes transmit clock wait state external clock mode (03). Also, state changes wait state internal clock mode (13). internal clock mode, transmit clock stops after eight pulses transmit clock output. While transfer state, serial mode register (SMR: $005) (06, written serial interface initialized state changes wait state. After transfer state changed another state, octal counter reset serial interrupt request flag (IFS: $003, set. Continuous clock output state (internal clock mode only): Continuous clock output state state which only transmit clock from output without data transfer. This done only while internal clock mode. When status bits (PMRA1, PMRA0) port mode register (PMRA: $004) while transmit clock wait state, state changed continuous clock output state enabling transmit clock (17). writing serial mode register (SMR: $005) while continuous clock output state (18), state will change wait state.
wait state (Octal counter 000, transmit clock disabled)
reset
write instruction Transmit clock Transmit clock wait state (Octal counter 000)
write (IFS
Transfer state (Octal counter 000)
transmit clocks instruction (IFS
External clock mode
write
wait state (Octal counter 000, transmit clock disabled)
reset
Continuous clock output state (PMRA
write instruction
transmit clocks write (IFS
Transmit clock
Transmit clock
Transmit clock wait state (Octal counter 000) Transfer state (Octal counter 000)
instruction (IFS
Internal clock mode
Note: Refer operating states section corresponding encircled numbers.
Figure Serial Interface State Transitions
HD404344R Series/HD404394 Series
Output Level Control During Idle States: output level during either wait state transmit clock wait state software. During idle states, output level controlled writing (PMRC1) port mode register (PMRC: $025). example output level control during idle states shown figure During transfer state, output level control cannot executed.
Transmit clock wait state State reset Port selection PMRA write External clock selection write Output level control idle states PMRC write Data write transmission SRL, write instruction (input) Undefined Dummy write state transition Output level control idle states wait state Transfer state Transmit clock wait state wait state
External clock mode Transmit clock wait state State reset Port selection PMRA write Internal clock selection write Output level control idle states PMRC write SRL, write instruction (output) Undefined Data write transmission Output level control idle states wait state Transfer state wait state Flag reset transfer completion
Internal clock mode Flag reset transfer completion
Figure Example Serial Interface Operation Sequence
HD404344R Series/HD404394 Series
Transmit Clock Error Detection (External Clock Mode): Serial interface will malfunction spurious pulse caused external noise conflicts with normal transmit clock during data transfer. transmit clock error this type detected shown figure more than eight transmit clocks input transfer state, eighth clock including spurious pulse noise, octal counter reaches 000, serial interrupt request flag (IFS: $003, set, transmit clock wait state entered. falling edge next normal clock signal, transfer state entered. After transfer completed reset, writing serial mode register (SMR: $005) changes state from transfer wait. this time serial interface transfer state, serial interrupt request flag (IFS: $003, again, therefore error detected.
Transfer completion (IFS
Interrupts inhibited
write
Transmit clock error processing
Normal termination Transmit clock error detection flowchart
Transmit clock wait state Transfer state Transfer state
Transmit clock wait state State
(input)
Noise Transfer state been entered transmit clock error. When written, set.
write
Flag because octal counter reaches 000. Flag reset transfer completion.
Transmit clock error detection procedure
Figure Transmit Clock Error Detection
HD404344R Series/HD404394 Series
Notes Use: Initializing after writing registers: port mode register (PMRA: $004) written transmit clock wait state transfer state, serial interface should reinitialized writing serial mode register (SMR: $005). Serial interrupt request flag (IFS: $003, set: serial interface, state changed from transfer state another writing serial mode register (SMR:$005) executing instruction during first pulse transmit clock, serial interrupt request flag (IFS: $003, set. serial interrupt request flag (IFS: $003, serial mode register (SMR: $005) write instruction execution must programmed executed after confirming that that after executing input instruction port Registers Serial Interface serial interface operation selected, serial data read written using following registers: Serial mode register (SMR: $005) Port mode register (PMRC: $025) Serial data registers (SRL: $006 SRU: $007) Port mode register (PMRA: $004) Miscellaneous register (MIS: $00C)
Serial Mode Register (SMRA: $005): This register following functions (figure 45): 0/SCK function selection Selection transmit clock Selection prescaler division ratio Serial interface initialization
write-only serial mode register reset reset. Writing serial mode register discontinues transmit clock input serial data registers (SRL: $006 SRU: $007) octal counter. octal counter then reset 000. serial mode register written during serial interface operation, data transfer will serial interrupt request flag (IFS: $003, will set. Data serial mode register becomes effective after instruction execution cycles from time serial mode register written therefore necessary program instruction executed cycles after serial mode register written
HD404344R Series/HD404394 Series
Serial mode register (SMR: $005) Initial value Read/Write name SMR3 SMR2 SMR1 SMR0
SMR3
R00/SCK Mode Selection
SMR2
SMR1
SMR0
Output
Clock Source Prescaler
Prescaler Division Ratio table
Output Input
System clock External clock
Figure Serial Mode Register (SMR) Port Mode Register (PMRC: $025): This register following functions: Prescaler division ratio selection Output level control during idle states Port mode register two-bit write-only register, which cannot changed during data transfer. (PMRC0) selects prescaler division ratio. Only this reset reset. enables output level control during idle state. output levels pins therefore changed when writing (PMRC1).
HD404344R Series/HD404394 Series
Port mode register (PMRC: $025) Initial value Read/Write name
Undefined
PMRC0
used used PMRC1
PMRC0 PMRC1
Transmit Clock Division Ratio Prescaler output divided Prescaler output divided Output Level Control Idle States level High level
Figure Port Mode Register (PMRC)
HD404344R Series/HD404394 Series
Serial Data Register (SRL: $006, SRU: $007): This register following functions (figures 48): Transmission data write shift Receive data shift read Data written serial data registers output from pin, first, synchronously with falling edge transmit clock. Also, data from (from LSB) input synchronously with rising edge transmit clock. Reading writing serial data register should performed after data transfer. Read/write operation this register during data transfer does guarantee valid data. input/output timing chart transmit clock data shown figure
Serial data register (lower) (SRL: $006) Initial value Read/Write name
Undefined Undefined Undefined Undefined
Figure Serial Data Register (SRL)
Serial data register (upper) (SRU: $007) Initial value Read/Write name
Undefined Undefined Undefined Undefined
Figure Serial Data Register (SRU)
Ttransmit clock Serial output data Serial input data latch timing
Figure Serial Interface Timing
HD404344R Series/HD404394 Series
Port Mode Register (PMRA: 004): This register following functions: 1/SI function selection 2/SO function selection Port mode register three-bit write-only register reset reset, listed figure
Port mode register (PMRA: $004) Initial value Read/Write name
used PMRA2 PMRA1 PMRA0 PMRA0 R02/SO Mode Selection R01/SI Mode Selection
PMRA2
R03/TOC Mode Selection
PMRA1
Figure Port Mode Register (PMRA) Miscellaneous Register miscellaneous register (MIS: $00C) following functions: Control 2/SO PMOS Pull-up on/off selection two-bit write-only register reset reset, listed figure
HD404344R Series/HD404394 Series
Miscellaneous register (MIS: $00C) Initial value Read/Write name MIS3 MIS2 MIS1 MIS0
MIS3
Pull-Up On/Off Selection Pull-up Pull-up
MIS2
PMOS On/Off Selection R02/SO
Programming MIS1 MIS0 prohibited.
Figure Miscellaneous Register
HD404344R Series/HD404394 Series
Converter
built-in converter that uses sequential comparison method with register ladder. perform digital conversion with analog inputs 8-bit resolution. following describes features converter. mode register (AMR1: $019) used select digital analog ports (figure 53). mode register (AMR2: $01A) used conversion speed (figure 54). channel register (ACR: $016) used select analog input channel (figure 55). conversion started setting start flag (ADSF: $020, After conversion completed, converted data stored data register, same time, start flag cleared (figure 56). setting flag (IAOF: $021, current flowing through resistance ladder even standby active mode (figure 57). data registers (ADRL: $017, ADRU: $018) read-only registers used store conversion result. (ADRL: lower bits, ADRU: upper bits.) These registers cannot cleared reset input. Also, data these registers guaranteed during conversion period. After conversion completed, 8-bit result these registers kept until next conversion starts (figures 60). Notes Use: SEMD instruction writing start flag (ADSF). write start flag during conversion. Data data register during conversion undefined. Since operation converter based clock from system oscillator, converter does operate stop mode. addition, save power dissipation while stop mode, current flowing through converter's resistance ladder off. Output signal level from other ports should fixed during conversion. port data register (PDR) initialized reset. this time, pull-up selected active miscellaneous register (MIS3), port will pulled When using shared port/analog input input pin, clear Otherwise, pull-up selected MIS3 selected mode register analog will remain pulled
HD404344R Series/HD404394 Series
interrupt request flag (IFAD) mode register (AMR1)
mode register (AMR2) data registers (ADRU, Internal data
R33/AN3 R32/AN2 R31/AN1
(R30/AN0)
Selector
Encoder
Comp (Vref)*2
controller
Control signal conversion time
channel register (ACR)
start flag (ADSF)
flag (IAOF)
Operating mode signal stop mode)
Notes: Available HD404344R series HD4074344. available HD404394 series. Connected HD404344R series HD4074344. Connected Vref HD404394 series.
Figure Converter Block Diagram
HD404344R Series/HD404394 Series
mode register (AMR1: $019) Initial value Read/Write name AMR13 AMR12 AMR11 AMR10 AMR10* AMR12 AMR13 R32/AN2 Mode Selection R33/AN3 Mode Selection AMR11 R30/AN0 Mode Selection R31/AN1 Mode Selection
Note: Available HD404344R series HD4074344, available HD404394 series.
Figure Mode Register (AMR1)
mode register (AMR2: $01A) Initial value Read/Write name
used used used AMR20
AMR20
Conversion Time 34tcyc 67tcyc
Figure Mode Register (AMR2)
HD404344R Series/HD404394 Series
channel register (ACR: $016) Initial value Read/Write name ACR3 ACR2 ACR1 ACR0
ACR3 ACR2 ACR1 ACR0
Analog Input Selection AN0*
Note: Available HD404344R series HD4074344, available HD404394 series.
Figure Channel Register (ACR)
start flag (ADSF: $020, Initial value Read/Write name used ADSF
WDON used
Start Flag (ADSF) conversion completed conversion started
WDON Refer description timers
Figure Start Flag (ADSF)
HD404344R Series/HD404394 Series
flag (IAOF: $021, Initial value Read/Write name RAME IAOF
used used
Flag (IAOF) current flows current RAME Refer description operating modes
Figure Flag (IAOF)
ADRU: $018 ADRL: $017
Result
Figure Data Register
data register lower (ADRL: $017) Initial value Read/Write name ADRL3 ADRL2 ADRL1 ADRL0
Figure Data Register Lower (ADRL)
HD404344R Series/HD404394 Series
data register upper (ADRU: $018) Initial value Read/Write name ADRU3 ADRU2 ADRU1 ADRU0
Figure Data Register Upper (ADRU)
HD404344R Series/HD404394 Series
Description PROM Mode
HD4074344 HD4074394 PROM versions ZTATmicrocomputer. PROM mode, stops operating, thus allowing user program on-chip PROM.
Number DP-28S/FP-28DA FP-30D Mode 0/AN0 1/AN1 2/AN2 3/AN3 TEST RESET 0/SCK 1/SI 2/SO 3/TOC D0/INT0/EVNB D4/STOPC RESET Vref PROM Mode Remarks
Notes: I/O: Input/output pin, Input pin, Output 0/AN0 HD404344R series HD404394 series mode.
HD404344R Series/HD404394 Series
Programmable Operation HD4074344 HD4074394 on-chip PROMs programmed PROM mode. PROM mode, does operate. programmed like standard 27256 EPROM using standard PROM programmer socket adapter shown figure Table lists recommended PROM programmers socket adapters. Since instructions HMCS400 series consists bits, HMCS400 series microcomputers incorporate conversion circuit enable general-purpose PROM programmer. this circuit, instruction read written using addresses, lower five bits upper five bits. example, kwords on-chip PROM programmed general-purpose PROM programmer, kbytes addresses ($0000-$1FFF) should specified.
Control signals
A12-A0 A12-A0
A14-A0 Address
O4-O0 RESET HD4074344 HD4074394 O4-O0
O7-O0 Data
28-to-28-pin socket adapter 30-to-28 socket adapter PROM programmer
Figure PROM Mode Connections
HD404344R Series/HD404394 Series
Table PROM Programmer Socket Adapter
PROM Programmer Maker DATA AVAL Corp. Type Name UNISITE PKW-3100
Socket Adapter Package DP-28S FP-28DA FP-30D Maker Hitachi Type Name HS4344ESS01H HS4344ESP01H HS4344ESF01H
Programming Verification HD4074344 HD4074394 high-speed programmed without causing voltage stress affecting data reliability. Table shows programming verification modes selected. Table PROM Mode Selection
Mode Programming Verification Programming inhibited High High High High O0-O4 Data input Data output High impedance
Precautions Addresses $0000 $1FFF should specified PROM programmed PROM programmer. address $2000 higher accessed, PROM programmed verified correctly. Note that plastic package type devices cannot erased reprogrammed. data unused addresses $FF. careful using wrong PROM programmer socket adapter, which cause overvoltage damage LSI. Make sure that firmly fixed onto socket adapter, that socket adapter firmly fixed programmer. PROM should programmed with 12.5 Other PROMs applied HD4074344 HD4074394, become permanently damaged. 12.5 Intel's 27256 VPP.
HD404344R Series/HD404394 Series
Addressing Modes
Addressing Modes Register Indirect Addressing Mode: contents registers bits total) used address. Direct Addressing Mode: direct addressing instruction consists words. first word contains opcode, contents second word bits) used address. Memory Register Addressing Mode: memory registers (MR), which located digits from $040 $04F, accessed with LAMR XMRA instructions. Addressing Modes Direct Addressing Mode: program branch address memory space executing JMPL, BRL, CALL instruction.
Instruction Opcode
address
address Memory Register Addressing
Register Indirect Addressing
Instruction
instruction instruction word word Opcode address Direct Addressing
Figure Addressing Modes
HD404344R Series/HD404394 Series
Current Page Addressing Mode: program branch address current page (256 words page) executing instruction. Zero-Page Addressing Mode: program branch subroutine located zero-page subroutine area ($0000-$003F) executing instruction. Table Data Addressing Mode: program branch address determined contents 4-bit immediate data, accumulator, register executing instruction.
instruction word
instruction word
Opcode
Opcode
Operand
Operand
Program counter Direct Addressing
Program counter Zero-Page Addressing
Operand Opcode
Operand
Opcode
Program counter Current Page Addressing
Program counter Table Data Addressing
Figure Addressing Modes
HD404344R Series/HD404394 Series
Addressing Mode Instruction: using instruction, data determined table data addressing referenced. lower-order bits data written accumulator register when data written port output registers when both data simultaneously written into accumulator, register, port output registers. (See figure 64.) program counter affected instruction.
Instruction Opcode Referenced address register Accumulator
RA13 RA12 RA11 RA10 Address
data
Accumulator, register
data
Output registers
Pattern Output
Figure Instruction
HD404344R Series/HD404394 Series
Branching Instruction Page Boundary: When instruction page boundary (256n 255), address program counter transferred over point next page done internal hardware. Therefore, executing instruction page boundary will cause program branch next page. (See figure 65.)
256n
256n 256n
Figure Instruction Page Boundary
HD404344R Series/HD404394 Series
Absolute Maximum Ratings
Item Supply voltage Programming voltage voltage Symbol Topr Tstg Value -0.3 +7.0 -0.3 +14.0 Unit Notes
-0.3 -0.3 +15.0
Total permissible input current Total permissible output current Maximum input current
Maximum output current Operating temperature Storage temperature
+125
Notes: Permanent damage occur these absolute maximum ratings exceeded. Normal operation must under conditions stated electrical characteristics tables. these conditions exceeded, malfunction reliability affected. Applies TEST (VPP) HD4074344 HD4074394. Applies following pins. HD404344R series HD4074344: D0-D HD404394 series: D0-D R13, R31-R3 Applies following pins. HD404394 series: 0-R1 total permissible input current total input currents simultaneously flowing from pins GND. total permissible output current total output currents simultaneously flowing from pins. maximum input current maximum current flowing from each GND. Applies Applies following pins. HD404344R series HD4074344: D3-D HD404394 series: D3-D R31-R3 maximum output current maximum current flowing from each pin. operating temperature indicates temperature range which power supplied (voltage shown electrical characteristics tables applied). case chips, storage specification differs from that package products. Please consult your Hitachi sales representative details.
HD404344R Series/HD404394 Series
Electrical Characteristics
Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: +75°C, HCD404344R, HCD40C4344R: +75°C, HD404394, HD404392, HD404391, HD4074344, HD4074394: +75°C, unless otherwise specified)
Item Input high voltage Symbol Pins RESET, SCK, INT0, STOPC, EVNB Input voltage RESET, SCK, INT0, STOPC, EVNB Output high voltage Output voltage leakage current |IIL| SCK, SCK, RESET, SCK, TOC, INT0, STOPC, EVNB Current dissipation active mode SBY1 Current dissipation standby mode SBY2 SBY3 -0.3 -0.3 0.3V 0.7V -0.3 0.2V 0.8V Unit Test Condition Notes
HD404344R Series/HD404394 Series
Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: +75°C, HCD404344R, HCD40C4344R: +75°C, HD404394, HD404392, HD404391, HD4074344, HD4074394: +75°C, unless otherwise specified) (cont)
Item Symbol Pins Unit Test Condition (RESET) VCC, (TEST) Stop mode retaining voltage VSTOP Notes
Current STOP dissipation stop mode
Notes: Excludes current flowing through pull-up output buffers. source current when current flowing while reset state. Test conditions: MCU: Reset Pins: RESET, TEST D0-D R0-R3 source current when current flowing while timer operating. Test conditions: MCU: reset Standby mode Pins: RESET TEST D0-D R0-R3 Applies HD404394 series HD4074344. Applies HD404344R series. current case excluding current through converters ladder resistance (flag IAOF "1"). Circuit structure circuit constants oscillator circuit following condition.
Circuit Structure OSC1 Ceramic oscillator OSC2
Circuit Constants Ceramic oscillator: KBR-800FTR (KYOSERA)
HD404344R Series/HD404394 Series
Characteristics Standard Pins (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: +75°C, HCD404344R, HCD40C4344R: +75°C, HD404394, HD404392, HD404391, HD4074344, HD4074394: +75°C, unless otherwise specified)
Pins Item Input high voltage Symbol
HD404344R HD404394 Series Series, HD4074344
0.7V
Unit Test Condition
Note
D0-D R0-R3
D0-D R13, 1-R3 D0-D R13, 1-R3 D0-D 1-R3
Input voltage
D0-D R0-R3
-0.3
0.3V
Output high voltage
D0-D R0-R3
Output voltage D0-D R0-R3
D0-D R13, 1-R3 D0-D R13, 1-R3 D0-D 1-R3
Input leakage current Pull-up current |IIL| D0-D R0-R3
4.5-5.5
D0-D R0-R3
Notes: Output buffer current pull-up current excluded. Applies HD404394 series.
HD404344R Series/HD404394 Series
Characteristics NMOS Intermediate-Voltage Pins HD404394 Series (VCC +75°C, unless otherwise specified)
Item Input high voltage Input voltage Output high voltage Output voltage Symbol Pins 0-R1 0-R1 0-R1 0-R1 0-R1 leakage current |IIL| 0-R1 12.0 Unit Test Condition Notes Notes: Applies HD404394 series. Excludes output buffer current.
0.7V -0.3 11.5
0.3V
Converter Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: +75°C, HCD404344R, HCD40C4344R: +75°C, HD404394, HD404392, HD404391, HD4074344, HD4074394: +75°C, unless otherwise specified)
Item Symbol Pins Vref Vref Unit Channel Channel MHz, Notes: Applies HD404344R series. Applies HD4074344. Applies HD404394 series. 25°C, Test Condition Note Vref
Analog reference voltage Vref Analog input voltage AVin
0.5V
0-AN 1-AN 0-AN
Current flowing between Vref Resolution Number input channels
Analog input capacitance
Absolute accuracy
0-AN -2.0 0-AN -2.5 1-AN -3.0
Vref
Conversion time Input impedance
0-AN
HD404344R Series/HD404394 Series
Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: +75°C, HCD404344R, HCD40C4344R: +75°C, HD404394, HD404392, HD404391, HD4074344, HD4074394: +75°C, unless otherwise specified)
Item Symbol Pins 0.89 Unit Test Condition Note
Clock oscillation frequency (ceramic oscillator) Clock oscillation frequency (resistor oscillator) Instruction cycle time (external clock, ceramic oscillator) Instruction cycle time (resistor oscillator) Oscillation setting time (external clock) Oscillation setting time (ceramic oscillator) Oscillation setting time (resistor oscillator) External clock high-level width External clock low-level width External clock rise time External clock fall time INT0, EVNB high-level width INT0, EVNB low-level width RESET low-level width STOPC low-level width RESET rise time STOPC rise time
Division Division Division
RSTL STPL RSTr STPr INT0, EVNB INT0, EVNB RESET STOPC RESET STOPC
1.14
Division
HD404344R Series/HD404394 Series
Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: +75°C, HCD404344R, HCD40C4344R: +75°C, HD404394, HD404392, HD404391, HD4074344, HD4074394: +75°C, unless otherwise specified) (cont)
Item Input capacitance Symbol Pins input pins except TEST, Vref R10-R1 TEST MHz, Vref 0-R1 Unit Test Condition Note MHz,
Notes: oscillation stabilization time period required oscillator stabilize following situations: After reaches minimum specification value power-on. After RESET input goes when stop mode cancelled. After STOPC input goes when stop mode cancelled. ensure oscillation stabilization time power-on when stop mode cancelled, RESET STOPC must input least duration When using ceramic oscillator, consult with manufacturer determine what stabilization time required, since will depend circuit constants stray capacitance. Refer figure Refer figure Refer figure Refer figure Applies HD404341R, HD404342R, HD404344R, HD404391, HD404392, HD404394. Applies HD4074344 HD4074394. Applies HD404394 series. Applies HD404344R series. Applies HD404394 series HD4074344. Applies HD40C4344R, HD40C4342R, HD404341R
HD404344R Series/HD404394 Series
Serial Interface Timing Characteristics (HD404344R, HD404342R, HD404341R, HD40C4344R, HD40C4342R, HD40C4341R: +75°C, HCD404344R, HCD40C4344R: +75°C, HD404394, HD404392, HD404391, HD4074344, HD4074394: +75°C, unless otherwise specified) During Transmit Clock Output
Item Transmit clock cycle time Transmit clock high width Transmit clock width Transmit clock rise time Transmit clock fall time Symbol Scyc SCKH SCKL SCKr SCKf Pins Test Condition Load shown figure Load shown figure Load shown figure Load shown figure Load shown figure Load shown figure Unit Scyc Scyc Note
Serial output data delay time Serial input data setup time Serial input data hold time
During Transmit Clock Input
Item Transmit clock cycle time Transmit clock high width Transmit clock width Transmit clock rise time Transmit clock fall time Symbol Scyc SCKH SCKL SCKr SCKf Pins Load shown figure Test Condition Unit Scyc Scyc Note
Serial output data delay time Serial input data setup time Serial input data hold time Note: Refer figure
HD404344R Series/HD404394 Series
1/fCP
tCPH
tCPL
tCPr
tCPf
Figure External Clock Timing
INT0, EVNB
0.8VCC
0.2VCC
Figure Interrupt Timing
RESET
0.8VCC
tRSTL 0.2VCC tRSTr
Figure RESET Timing
STOPC
0.8VCC
tSTPL 0.2VCC tSTPr
Figure STOPC Timing
HD404344R Series/HD404394 Series
Scyc SCKf (0.8VCC (0.2VCC)* 0.7V 0.3VCC SCKL SCKH SCKr
Note: threshold voltages transmit clock output, 0.8VCC 0.2VCC threshold voltages transmit clock input.
Figure Serial Interface Timing
Test point Hitachi 1S2074 equivalent
Figure Timing Load Circuit
HD404344R Series/HD404394 Series
25°C, fcyc fosc/4 Sample: (mA) fosc fosc fosc fosc fosc (mA) Characteristics (ceramic oscillator) 25°C, Sample: fosc (MHz) Characteristics (resistor oscillator) 25°C, Sample: fosc Characteristics (resistor oscillator) 25°C Sample: (mA) Characteristics (D1, pins) fosc Characteristics (resistor oscillator) 25°C, fcyc fosc/4 Sample:
fosc (MHz)
Figure Characteristics curve HD404344R series (consultation value)
HD404344R Series/HD404394 Series
Notes
Please attention following items regarding out. out, fill area indicated below with create same data size 4-kword versions (HD404344R HD404394). 4-kword data size required change data mask manufacturing data since program used 4-kword version. This limitation apply case using EPROM case using data base.
kwords version: HD404341R, HD40C4341R, HD404391 Address $0400 $0FFF $0000 Vector address $000F $0010 Zero page subroutine words) $003F $0040 Pattern program (1,024 words) $03FF $0400 used $0FFF Fill this area with $0FFF $07FF $0800 used $003F $0040 Pattern program (2,048 words) $000F $0010 Zero page subroutine words) $0000 Vector address kwords version: HD404342R, HD40C4342R, HD404392 Address $0800 $0FFF
HD404344R Series/HD404394 Series
HD40C4344R/HCD40C4344R Option List
Please check appropriate applications enter necessary information. Date order Customer Department Name code name number size HD404341R HD404342R HD404344R HCD404344R code media Please specify first type below (the upper bits lower bits mixed together), when using EPROM on-package microcomputer type (including ZTATversion). EPROM: upper bits lower bits mixed together. upper five bits lower five bits programmed same EPROM alternating order (i.e., LULULU.). EPROM: upper bits lower bits separated. upper five bits lower five bits programmed different EPROMS. System oscillator (OSC1-OSC2) (Shaded areas indicate selections that available.) Ceramic oscillator External clock oscillator Stop mode Used used Package type DP-28S FP-28DA FP-30D Chip Note: specifications shipped chips differ from package product. Please contact sales staff details. 1-kword 2-kword 4-kword 4-kword Ceramic oscillator External clock HD404341R HD404342R HD404344R 1-kword 2-kword 4-kword oscillator
HCD40C4344R 4-kword
HD404344R Series/HD404394 Series
HD404391/HD404392/HD404394 Option List
Please check appropriate applications enter necessary information. Date order Customer Department Name code name number size HD404391 HD404392 HD404394 1-kword 2-kword 4-kword
code media Please specify first type below (the upper bits lower bits mixed together), when using EPROM on-package microcomputer type (including ZTATversion). EPROM: upper bits lower bits mixed together. upper five bits lower five bits programmed same EPROM alternating order (i.e., LULULU.). EPROM: upper bits lower bits separated. upper five bits lower five bits programmed different EPROMS.
System oscillator (OSC1-OSC2) Ceramic oscillator External clock
Stop mode Used used
Package type DP-28S FP-28DA FP-30D
HD404344R Series/HD404394 Series
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such failsafes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Copyright Hitachi, Ltd., 1998. rights reserved. Printed Japan.
Other recent searches
PVT412 - PVT412 PVT412 Datasheet
MPC7410TRXNEPNS - MPC7410TRXNEPNS MPC7410TRXNEPNS Datasheet
MPC7410TRXnnnNE - MPC7410TRXnnnNE MPC7410TRXnnnNE Datasheet
MPC7410TRX400NE - MPC7410TRX400NE MPC7410TRX400NE Datasheet
MPC7410TRX450NE - MPC7410TRX450NE MPC7410TRX450NE Datasheet
MPC7410EC - MPC7410EC MPC7410EC Datasheet
IXTP1R6N50P - IXTP1R6N50P IXTP1R6N50P Datasheet
IXTY1R6N50P - IXTY1R6N50P IXTY1R6N50P Datasheet
HMC462 - HMC462 HMC462 Datasheet
CM1416 - CM1416 CM1416 Datasheet
CM1411 - CM1411 CM1411 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
