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MMCCMB3401 Controller Memory Board (CMB3401) User's Manual
Motorola reserves right make changes without further notice products herein improve reliability, function design. Motorola does assume liability arising application product circuit described herein; neither does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative
name logo OnCE name trademarks Motorola, Inc. other trademarks belong their respective owners. Motorola, Inc. 2000; RIGHTS RESERVED
CAUTION: Protection
development systems include open-construction printed circuit boards that contain static-sensitive components. These boards subject damage from electrostatic discharge (ESD). prevent such damage, must static-safe work surfaces grounding straps, defined ANSI/EOS/ESD S6.1 ANSI/EOS/ESD S4.1. handling these boards must accordance with ANSI/EAI 625.
MOTOROLA
MMCCMB3401UM/D User's Manual
Contents
Section Introduction
CMB3401 Features System User Requirements CMB3401 Layout
Section Configuration
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 Configuring Board Components Setting FSRAM Chip Select Header (W1) Setting FLASH Chip Select Header (W2). Setting FLASH Enable Header (W3) Setting SRAM Enable Header (W4) Setting Memory Access Switch (S1) Setting Software Select Switch (S2) Setting Memory Configuration Switch (S3). Setting Wait State Switch (S4). Making Computer-System Connections Performing CMB3401 Selftest Memory Maps.
Section Operation
Debugging Embedded Code 3.1.1 Using Picobug Monitor 3.1.2 Picobug Sample Session 3.1.3 Using Source-Level Debugger Downloading FLASH Memory 3.2.1 Using SysDS Loader 3.2.2 Restoring System Software Controlling CMB3401 LEDs
MMCCMB3401UM/D User's Manual
Section Using FPGA Device
Configuring Your Software Reprogramming FPGA Device. Using Periodic Interval Timers
Section Connector Information
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4) OnCE Connector (J13) NEXUS Connector (J23) Logic Analyzer Connectors (J25, J28, J32) Logic Analyzer Connectors (J29, J30, J33) TEA, Eyelets (J7, J18). RS232 Connectors (J57, J58)
Section Cross Reference Tables Index
MMCCMB3401UM/D User's Manual
Figures
5-10 5-11 5-12 5-13
MMCCMB3401 Computer Memory Board SysDS Loader Main Screen Upload File Dialog Display Flash/Ram Display Diagram Control/Status Register Layout MAPI Connector P1/J1 Assignments MAPI Connector P2/J2 Assignments MAPI Connector P3/J3 Assignments MAPI Connector P4/J4 Assignments OnCE Connector Assignments NEXUS Connector Assignments Logic Analyzer Connector Assignments Logic Analyzer Connector Assignments Logic Analyzer Connector Assignments Logic Analyzer Connector Assignments Logic Analyzer Connector Assignments Logic Analyzer Connector Assignments TEA, Eyelets
MMCCMM3401UM/D User's Manual
MMCCMM3401UM/D User's Manual
Tables
2-10 5-10 5-11 5-12 5-13
MMCCMB3401 Controller Memory Board Specifications Component Configuration Setting Subswitch Settings. Subswitch Settings. Subswitch Settings. Subswitch Settings. CMB3401 Selftest Patterns CMB3401 Default Memory FLASH Sector Boundaries CMB3401 Default Memory FLASH Sector Boundaries Picobug Commands Register Addresses. Control/Status Register Values MAPI Connector P1/J1 Signal Descriptions MAPI Connector P2/J2 Signal Descriptions MAPI Connector P3/J3 Signal Descriptions MAPI Connector P4/J4 Signal Descriptions OnCE Connector Signal Descriptions NEXUS Connector Signal Descriptions Logic Analyzer Connector Signal Descriptions Logic Analyzer Connector Signal Descriptions Logic Analyzer Connector Signal Descriptions Logic Analyzer Connector Signal Descriptions Logic Analyzer Connector Signal Descriptions Logic Analyzer Connector Signal Descriptions RS232 Connector J57, Assignments Cross Reference: 3401, FPGA, MAPI Connectors Cross Reference: 3401 FPGA, MAPI Connectors Cross Reference: MAPI FPGA, 3401
MMCCMB3401UM/D User's Manual
Cross Reference: MAPI, FPGA, 3401 Cross Reference:U2 FPGA Device Pins
MMCCMB3401UM/D User's Manual
CMB3401 Features
Section Introduction
This user's manual explains connection, configuration, operation information MMCCMB3401 Controller Memory Board (CMB3401), development tool Motorola's CMB3401 lets develop code embedded MMC3401 microcontroller unit. CMB3401 uses RS232 connection your computer. This connection lets Motorola's System Development Software (SysDS) source-level debugger. SysDS consists loader, Picobug monitor, monitor, built-in selftest. CMB3401 also OnCEconnector, enabling debugging tool application that requires one. Optionally, CMB3401 with different emulator product, such appropriate Motorola Embedded Background Debug Interface (EBDI). Motorola's SysDS Loader lets download your code into CMB3401's SRAM (for execution) FLASH memory (for execution storage non-volatile memory). Should your application overwrite system software FLASH memory device, SysDS Loader restore system software.
CMB3401 Features
CMB3401 features: Motorola M340 resident MCU. megabytes burst FLASH memory external interface module (EIM) bus. megabytes FLASH memory local (MLB). megabytes fast SRAM bus. megabytes fast SRAM MLB. Altera EPF10K100A FPGA device, with configuration chip. Four power regulators that provide four voltages: 3.2, 3.0, 1.8. Power supply that converts line power 12-volt power. Power adapter cable bench supply. RS232 channels serial communications. These channels internal universal asynchronous receiver/transmitters (UARTs). NEXUS port (also known GEPDIS port). MAPI connector interface ring, bottom CMB3401, easy connection other, compatible development boards.
MMCCMB3401UM/D User's Manual
Introduction
Motorola's SysDS. Altera MAX+plusII development software. source-level debugger (from Free Software Foundation). Three 38-pin Mictor logic analyzer connectors bus. Three 38-pin Mictor logic analyzer connectors MLB. Altera ByteBlaster cable.
System User Requirements
need compatible computer, running Windows WindowsNT (version 4.0) operating system. computer requires Pentium equivalent) microprocessor, megabytes RAM, megabytes free hard-disk space, SVGA color monitor, RS232 serial-communications port. Picobug monitor, also need Hyperterminal comparable terminal-emulation program. most from your CMB3401, should experienced assembly programmer. power supply that comes with your CMB3401 converts line power input power that CMB3401 needs: volts minimum amperes.
CMB3401 Layout
Figure shows layout CMB3401. Jumper header specifies FSRAM chip select jumper header specifies FLASH chip select Jumper header enables disables FLASH. Jumper header enables disables SRAM. Headers factory only: should remove jumpers from these headers. Connectors through board, MAPI interrupt connectors (the corresponding MAPI connectors bottom CMB3401 through J4).Connector OnCE connector. Connector reprogramming FPGA device location U2). Connector NEXUS connector. Connectors J25, J28, logic analyzer connectors. Connectors J29, J30, EIM-bus logic analyzer connectors. Connectors RS232 serial connectors. Connector connector 12-volt input power. eyelet connection MLB_OLD_TEA signal. eyelet connector MLB_OLD_TA signal.
MMCCMB3401UM/D User's Manual
CMB3401 Layout
Switch specifies memory-access mode, port size, first address accessed. Switch specifies software module upon reset. Switch controls several aspects memory configuration. Switch specifies number wait states. Switch master reset switch (resetting entire board). Switch resets only resident M340 location U3). Switch reconfigures FPGA device location U2).
Figure MMCCMB3401 Computer Memory Board Location CMB3401 fuse. indicates configuration completion FPGA device. confirms board power. LEDs through status indicators. NOTE: Some CMB3401 locations factory use, populated your board. Although populated, headers also factory only: should remove jumpers from these headers.
MMCCMB3401UM/D User's Manual
Introduction
Table lists CMB3401 specifications. Table MMCCMB3401 Controller Memory Board Specifications
Characteristic
extension ports Operating temperature Storage temperature Relative humidity Clock Power requirements Dimensions -40° +85° (non-condensing) volts minimum amperes, provided from separate power source inches (175
Specifications
HCMOS compatible
MMCCMB3401UM/D User's Manual
Configuring Board Components
Section Configuration
This chapter explains configure your CMB3401, hook your computer system.
Configuring Board Components
Configuring your CMB3401 involves setting several components. Table summary these settings; paragraphs 2.1.1 through 2.1.8 give additional information. Table Component Configuration Setting
Component
FSRAM Header,
Position
Effect
Selects chip-select must select chip select Factory setting.
Selects chip-select must select chip select Selects chip-select must select chip select
FLASH Header,
Selects chip-select must select chip select Factory setting.
FLASH Enable Header,
Enables FLASH. Factory setting. Disables FLASH
SRAM Enable Header,
Disables SRAM.
Enables SRAM. Factory setting.
MMCCMB3401UM/D User's Manual
Configuration
Table Component Configuration Setting
Component
Factory Headers,
Position
Factory only.
Effect
Factory setting. remove jumpers.
Memory Access Switch,
Configures Endian mode, 32-bit port booted internally, 0x0000_0000 first address accessed. (One many possible configurations.) Factory setting.
Configures Endian mode, 8-bit port pins D[15:8], 0x1000_0000 first address accessed. (Another many possible configurations.)
Configures Endian mode, 16-bit port pins D[31:16], 0x1000_0000 first address accessed. (Another many possible configurations.)
Software Select Switch,
Specifies Picobug upon reset. (One many possible configurations.) Factory setting.
MMCCMB3401UM/D User's Manual
Configuring Board Components
Table Component Configuration Setting
Component
Software Select Switch, (continued)
Position
Effect
Specifies user code upon reset. (Another many possible configurations.)
Specifies user code upon reset. (Another many possible configurations.)
Memory Configuration Switch,
Configures memory mapping starting address 0x0000_0000, FLASH before SRAM memory map, memory activated CMB. (One many possible configurations.) Factory setting.
Configures memory mapping starting address 0x0000_0000, FLASH after SRAM memory map, memory activated CMB. (Another many possible configurations.)
Configures memory mapping starting address 0x0100_0000 memory deactivated CMB. (Another many possible configurations.)
MMCCMB3401UM/D User's Manual
Configuration
Table Component Configuration Setting
Component
Wait State Switch,
Position
Effect
Configures wait state clock cycles. (One many possible configurations.) Factory setting.
Configures wait state clock cycles. (Another many possible configurations.)
Configures wait state clock cycles. Another many possible configurations.)
Master Reset Switch,
Push reset board components.
Reset Switch,
Push reset only resident (location U3).
FPGA Configuration Switch,
Push reconfigure FPGA device (location
MMCCMB3401UM/D User's Manual
Configuring Board Components
2.1.1 Setting FSRAM Chip Select Header (W1)
Jumper header specifies chip select megabytes FSRAM bus. diagram below shows factory configuration: jumper between pins selects chip select
FSRAM
select instead chip select reposition jumper between pins NOTE: Jumper headers must specify opposite chip selects. specifies chip select diagram above, must specify chip select
2.1.2 Setting FLASH Chip Select Header (W2)
Jumper header specifies chip select megabytes FLASH bus. diagram below shows factory configuration: jumper between pins selects chip select
FLASH
select instead chip select reposition jumper between pins NOTE: Jumper headers must specify opposite chip selects. specifies chip select diagram above, must specify chip select
MMCCMB3401UM/D User's Manual
Configuration
2.1.3 Setting FLASH Enable Header (W3)
Jumper header enables disables megabytes FLASH memory MLB. diagram below shows factory configuration: jumper between pins enables FLASH.
FLASH
disable FLASH, reposition jumper between pins
2.1.4 Setting SRAM Enable Header (W4)
Jumper header enables disables megabytes FSRAM MLB. diagram below shows factory configuration: jumper between pins enables FSRAM.
SRAM
disable FSRAM, reposition jumper between pins
MMCCMB3401UM/D User's Manual
Configuring Board Components
2.1.5 Setting Memory Access Switch (S1)
Switch specifies memory-access mode, port size, first address accessed. diagram below shows factory configuration: BIG_E subswitch other subswitches OFF. This configures: Endian mode, 32-bit port, booted internally, 0x0000_0000 first address accessed.
BIG_E DSZ2 DSZ1 DSZ0
configure Little Endian mode, BIG_E subswitch OFF. NOTE: switch Little Endian mode unless that mode stages your code development: writing, compiling, debugging.
configure different port size first address, other subswitches Table 2-2. Table Subswitch Settings
Port Size bits bits bits bits bits bits bits bits Port Location D[31:24] pins D[23:16] pins D[15:8] pins D[7:0] pins D[31:16] pins D[15:0] pins D[31:0] pins internal (MLB) First Address Accessed 0x1000_0000 0x1000_ 0000 0x1000_0000 0x1000_0000 0x1000_0000 0x1000_0000 0x1000_0000 0x0000_0000 DSZ2 Subswitch DSZ1 Subswitch DSZ0 Subswitch
MMCCMB3401UM/D User's Manual
Configuration
2.1.6 Setting Software Select Switch (S2)
Switch specifies software upon reset. diagram below shows factory configuration: GSB0 GSB1 subswitches OFF, GSB2 subswitch This specifies Picobug.
GSB0 GSB1 GSB2 GSB3
specify different software module, reset subswitches Table 2-3. Table Subswitch Settings
Software Module Built-In selftest SysDS Programmer monitor Picobug Picobug Picobug user code user code GSB0 Subswitch GSB1 Subswitch GSB2 Subswitch
NOTES: GSB3 subswitch nonfunctional. monitor requires additional debug software your computer compatibility with your CMB3401; source such software, product release guide. monitor compatible only with Endian mode, subswitch S1-1 must also switch control your application software. Subsection explains this additional role.
MMCCMB3401UM/D User's Manual
Configuring Board Components
2.1.7 Setting Memory Configuration Switch (S3)
Switch specifies several aspects memory configuration. diagram below shows factory configuration: MEM_SW RM_FST subswitches MIM_EN DIS_CL subswitches OFF. This configures: Memory mapping starting address 0x0000_0000, FLASH before SRAM memory map, memory enabled CMB3401.
MEM_SW MIM_EN RM_FST DIS_CL
different configurations, subswitches Table 2-4. Table Subswitch Settings
Subswitch MEM_SW (Memory swap) RM_FST (ROM First) DIS_CL (Disable CMB) Effect
Memory mapping begins address 0x0000_0000. Puts FLASH (ROM) before SRAM memory (provided that MEM_SW subswitch starts mapping address 0x0000_0000. Disables internal memory.
Effect
Memory mapping begins address 0x0F00_0000. Puts FLASH (ROM) after SRAM memory (provided that MEM_SW subswitch starts mapping address 0x0000_0000. Enables internal memory.
NOTE:
MIM_EN subswitch nonfunctional.
MMCCMB3401UM/D User's Manual
Configuration
2.1.8 Setting Wait State Switch (S4)
Switch specifies length wait states. diagram below shows factory configuration: subswitches position. This configures wait state clock cycles.
WAIT_SEL3 WAIT_SEL2 WAIT_SEL1 WAIT_SEL0
configure different number clock cycles, subswitches Table 2-5. Table Subswitch Settings
Wait State Clock Cycles WAIT_SEL3 Subswitch WAIT_SEL2 Subswitch WAIT_SEL1 Subswitch WAIT_SEL0 Subswitch
NOTE:
switch setting does override software wait-state setting.
MMCCMB3401UM/D User's Manual
Making Computer-System Connections
Making Computer-System Connections
When have configured your CMB3401, ready connect your computer system: Make sure that power disconnected. will RS232 communication with your host computer, connect RS232 cable between CMB3401 connector appropriate serial port your computer. (Optional: your application must have higher UART addresses, connector your RS232 communication.) will OnCE-compatible emulator with your CMB3401, connect appropriate 14-lead ribbon cable between CMB3401 connector your emulator. Then appropriate cable connect your emulator your host computer. will NEXUS-compatible emulator with your CMB3401, connect appropriate NEXUS cable between CMB3401 connector your emulator. Then appropriate cable connect your emulator your host computer. Optional: CMB3401 with another, compatible development board, must connect boards their MAPI rings. hold CMB3401 directly above other board. Turn CMB3401 that right-triangle silk screen markings line Then press CMB3401 down onto other board. CMB3401 connectors through bottom board, must connect with corresponding MAPI connectors through other board. Optional: logic analyzer with CMB3401. connect appropriate cables logic analyzer connectors: J25, with regard MLB. J29, J30, with regard bus.
Optional: will reprogram FPGA device, connect ByteBlaster cable CMB3401 connector J14. Make sure that wire connects connector. Connect other ByteBlaster cable parallel port your computer, instructions your Altera documentation. (Section gives additional information about reprogramming device.) Connect +12-volt power supply CMB3401 connector line power. lights confirm that CMB3401 powered converting input voltage. Should light, need replace fuse location (Use GMA-1.5A fuse, compatible.) This completes system connections: ready perform selftest, instructions subsection 2.3, below. ready begin debugging other development activities, instructions Section
MMCCMB3401UM/D User's Manual
Configuration
Performing CMB3401 Selftest
Once have configured your CMB3401, perform selftest components. NOTE: open Hyperterminal, instructions subsection 3.1.1, Hyperterminal displays progress selftest. Should selftest fail, Hyperterminal indicates address which test failed.
Make sure that CMB3401 power disconnected. power should out. switch built-in selftest: GSB0, GSB1, GSB2 subswitches Apply power. comes CMB3401 automatically begins selftest. LEDs through (also designated GCB0 through GCB3, respectively) flash rapid patterns during test. Then four LEDs flash each second two, unison, confirming that CMB3401 passed. Flashing fewer than four LEDs indicates failure, Table 2-6. case such failure, should contact Motorola customer support assistance. Table CMB3401 Selftest Patterns
(GCB0)
(GCB1)
(GCB2)
(GCB3)
Meaning
failure. failure. FLASH failure.
Turn power. Configure switch your next development activity before restoring power CMB3401.
Memory Maps
Table shows default memory bus. Table lists FLASH sector boundaries. Table shows default memory bus. Table 2-10 lists FLASH sector boundaries. shaded cells Table Table 2-10 indicate sectors that contain system software. NOTE: either SRAM SRAM, first kilobytes contain system software. should confine your code data remainder SRAM.
MMCCMB3401UM/D User's Manual
Memory Maps
Table CMB3401 Default Memory
Address Range
0x0000_0000 0x001F_FFFF 0x0020_0000 0x003F_7FFF 0x0040_0000 0x005F_FFFF 0x0060_8000 0x0060_FFFF 0x0100_0000 0x01FF_FFFF 0x0200_0000 0x02FF_FFFF 0x0300_0000 0x03FF_FFFF 0x0400_0000 0x04FF_FFFF 0x0500_0000 0x05FF_FFFF 0x0600_0000 0x060F_FFFF 0x0610_0000 0x061F_FFFF 0x0620_0000 0x062F_FFFF 0x0630_0000 0x063F_FFFF 0x0640_0000 0x064F_FFFF 0x0FFF_FFFF NOTES: this address range FLASH, Table lists sector (block) boundaries. this address range FLASH (that switch S3-1 OFF), Table lists sector (block) boundaries.
Contents
FLASH (2M)1 Reserved Fast SRAM (2M)2 Reserved
Related Signals
FLASH_CS_b
FSRAM_CS_b
Chip select (16M)
CS_b[0]
Chip select (16M)
CS_b[1]
Chip select (16M)
CS_b[2]
Chip select (16M)
CS_b[3]
Chip select (16MK)
CS_b[4]
Chip select (1M)
CS_b[5]
Chip select (1M)
CS_b[6]
Chip select (1M)
CS_b[7]
Chip select (1M)
CS_b[8]
Chip select
CS_b[9]
MMCCMB3401UM/D User's Manual
Configuration
Table FLASH Sector Boundaries
Sector (Block)
Range (S3-3
0x0000_0000 0x0000_7FFF 0x0000_8000 0x0000_BFFF 0x0000_C000 0x0000_FFFF 0x0001_0000 0x0001_FFFF 0x0002_0000 0x0003_FFFF 0x0004_0000 0x0005_FFFF 0x0006_0000 0x0007_FFFF 0x0008_0000 0x0009_FFFF 0x000A_0000 0x000B_FFFF 0x000C_0000 0x000D_FFFF 0x000E_0000 0x000F_FFFF 0x0010_0000 0x0011_FFFF 0x0012_0000 0x0013_FFFF 0x0014_0000 0x0015_FFFF 0x0016_0000 0x0017_FFFF 0x0018_0000 0x0019_FFFF 0x001A_0000 0x001B_FFFF 0x001C_0000 0x001D_FFFF 0x001E_0000 0x001F_FFFF
Range (S3-3 OFF)
0x0040_0000 0x0040_7FFF 0x0040_8000 0x0040_BFFF 0x0040_C000 0x0040_FFFF 0x0041_0000 0x0041_FFFF 0x0042_0000 0x0043_FFFF 0x0044_0000 0x0045_FFFF 0x0046_0000 0x0047_FFFF 0x0048_0000 0x0049_FFFF 0x004A_0000 0x004B_FFFF 0x004C_0000 0x004D_FFFF 0x004E_0000 0x004F_FFFF 0x0050_0000 0x0051_FFFF 0x0052_0000 0x0053_FFFF 0x0054_0000 0x0055_FFFF 0x0056_0000 0x0057_FFFF 0x0058_0000 0x0059_FFFF 0x005A_0000 0x005B_FFFF 0x005C_0000 0x005D_FFFF 0x005E_0000 0x005F_FFFF
MMCCMB3401UM/D User's Manual
Memory Maps
Table CMB3401 Default Memory
Address Range
0x0000_0000 0x003F_FFFF 0x0040_0000 0x005F_FFFF 0x0060_0000 0x0060_7FFF 0x0060_8000 0x0060_FFFF 0x1000_0000 0x11FF_FFFF 0x1200_0000 0x12FF_FFFF 0x1300_0000 0x13FF_FFFF 0x1400_0000 0x14FF_FFFF 0x1500_0000 0x15FF_FFFF 0x1600_0000 0x16FF_FFFF 0x1700_0000 0xFFFF_FFFF
Contents
Reserved Reserved Reserved Reserved
Comments
Chip select (16M)
Active low. used either FLASH FSRAM.1 Active low. used either FLASH FSRAM.1. Active low. used DUART Active low. used DUART Active low.
Chip select (16M)
Chip select (16M)
Chip select (16M)
Chip select (16M)
Chip select (16M)
Active low.
Reserved
NOTES: Table 2-10 shows sector (block) boundaries FLASH memory. These sectors take entire memory range that either chip select chip select specifies. address DUART 0x1300_8000. DUART interrupt, associated with connector J57, connects p_int_b[23] processor. address DUART 0x1400_0000. DUART interrupt, associated with connector J58, connects p_int_b[21] processor.
MMCCMB3401UM/D User's Manual
Configuration
Table 2-10 FLASH Sector Boundaries
Sector (Block)
Range Selects CS0)
0x1000_0000 0x1000_3FFF 0x1000_4000 0x1000_7FFF 0x1000_8000 0x1000_BFFF 0x1000_C000 0x1000_FFFF 0x1001_0000 0x1001_3FFF 0x1001_4000 0x1001_7FFF 0x1001_8000 0x1001_BFFF 0x1001_C000 0x1001_FFFF 0x1002_0000 0x1003_FFFF 0x1004_0000 0x1005_FFFF 0x1006_0000 0x1007_FFFF 0x1008_0000 0x1009_FFFF 0x100A_0000 0x100B_FFFF 0x100C_0000 0x100D_FFFF 0x100E_0000 0x101F_FFFF 0x1010_0000 0x1011_FFFF 0x1012_0000 0x1013_FFFF 0x1014_0000 0x1015_FFFF 0x1016_0000 0x1017_FFFF 0x1018_0000 0x1019_FFFF 0x101A_0000 0x101B_FFFF 0x101C_0000 0x101D_FFFF 0x101E_0000 0x101F_FFFF 0x1020_0000 0x1021_FFFF 0x1022_0000 0x1023_FFFF 0x1024_0000 0x1025_FFFF 0x1026_0000 0x1027_FFFF 0x1028_0000 0x1029_FFFF 0x102A_0000 0x102B_FFFF 0x102C_0000 0x102D_FFFF 0x102E_0000 0x102F_FFFF 0x1030_0000 0x1031_FFFF 0x1032_0000 0x1033_FFFF 0x1034_0000 0x1035_FFFF 0x1036_0000 0x1037_FFFF 0x1038_0000 0x1039_FFFF 0x103A_0000 0x103B_FFFF 0x103C_0000 0x103D_FFFF 0x103E_0000 0x103F_FFFF
Range Selects CS1)
0x1200_0000 0x1200_3FFF 0x1200_4000 0x1200_7FFF 0x1200_8000 0x1200_BFFF 0x1200_C000 0x1200_FFFF 0x1201_0000 0x1201_3FFF 0x1201_4000 0x1201_7FFF 0x1201_8000 0x1201_BFFF 0x1201_C000 0x1201_FFFF 0x1202_0000 0x1203_FFFF 0x1204_0000 0x1205_FFFF 0x1206_0000 0x1207_FFFF 0x1208_0000 0x1209_FFFF 0x120A_0000 0x120B_FFFF 0x120C_0000 0x120D_FFFF 0x120E_0000 0x121F_FFFF 0x1210_0000 0x1211_FFFF 0x1212_0000 0x1213_FFFF 0x1214_0000 0x1215_FFFF 0x1216_0000 0x1217_FFFF 0x1218_0000 0x1219_FFFF 0x121A_0000 0x121B_FFFF 0x121C_0000 0x121D_FFFF 0x121E_0000 0x121F_FFFF 0x1220_0000 0x1221_FFFF 0x1222_0000 0x1223_FFFF 0x1224_0000 0x1225_FFFF 0x1226_0000 0x1227_FFFF 0x1228_0000 0x1229_FFFF 0x122A_0000 0x122B_FFFF 0x122C_0000 0x122D_FFFF 0x122E_0000 0x122F_FFFF 0x1230_0000 0x1231_FFFF 0x1232_0000 0x1233_FFFF 0x1234_0000 0x1235_FFFF 0x1236_0000 0x1237_FFFF 0x1238_0000 0x1239_FFFF 0x123A_0000 0x123B_FFFF 0x123C_0000 0x123D_FFFF 0x123E_0000 0x123F_FFFF
MMCCMB3401UM/D User's Manual
Debugging Embedded Code
Section Operation
This section explains begin using debugging tools available your MMCCMB3401 Controller Memory Board, well Motorola's SysDS Loader.
Debugging Embedded Code
With your CMB3401, Picobug monitor, standalone software. Optionally, source-level debugger with Picobug monitor. Other firms produce still additional software run, test, modify code develop embedding MMC3401 MCU. Motorola System Development Software download transfer control your code, must careful program only ranges FLASH memory SRAM that allocated user code user space. Programming over ranges that contain system software data storage would impair destroy usefulness software. (Subsection 3.2.1 identifies contents memory ranges; subsection 3.2.2 explains SysDS Loader restore factory programming.)
3.1.1 Using Picobug Monitor
Picobug monitor comes burned into FLASH memory device your CMB3401. Before start Picobug monitor, make sure that have RS232 connection between CMB3401 connector serial port your computer. start Picobug monitor, standalone debugger: switch Picobug monitor. factory setting, example, specifies Picobug: GSB0 GSB1 subswitches OFF, GSB2 subswitch Apply power CMB3401 press reset switch), then press enter key. Picobug monitor starts automatically, displaying command prompt: picobug>. Activate Hyperterminal comparable terminal-emulation program. different terminal-emulation program, must make corresponding changes commands menu selections these instructions, instructions paragraph 3.1.2.) From File menu, select Properties. This opens properties dialog box. Click Configure button dialog box. This opens configuration dialog box. configuration dialog make these communications settings: 19,200 baud, bits, parity, stop bit, flow control. Also correct communications port (for example, COM1). Click button dialog box.
MMCCMB3401UM/D User's Manual
Operation
Picobug debug monitor, merely enter commands prompt. Table explains these commands. list these commands your computer screen, enter question mark extra command command prompt Table Picobug Commands
Command
baud [value]
Explanation
Baud Rate: With optional value value, sets that rate (9600, 19200, 38400). Without value value, sets default rate: 19200 baud. Breakpoint: With optional address value, sets breakpoint that address. Without address value, lists current breakpoints. With optional address value, starts code execution from that address. Without address value, starts code execution from current program-counter value. either case, execution stops when arrives breakpoint. Return: Executes code from current program-counter value return address calling routine. (Should execution arrive breakpoint before encountering return address, execution stops breakpoint.) Address: Executes code from current program-counter value specified address value. (Should execution arrive breakpoint before encountering specified address, execution stops breakpoint.) Help Displays available commands, identical command. Download: With optional address value, downloads binary image that address SRAM. Without address value, downloads SRAM S-record text file. Memory Display: With optional address1 address2 values, displays memory contents between addresses. With optional address1 value, displays contents memory bytes. With address value, defaults last address viewed. optional size value specifies format: (bytes, default), (half words), (words), (instructions). Memory Display 256: With optional address value, displays contents memory bytes, starting that address. With address value, displays contents memory bytes, starting from last address viewed.
[address]
[address]
address
[address]
[address1 [address2]] [;size]
[address]
MMCCMB3401UM/D User's Manual
Debugging Embedded Code
Table Picobug Commands (Continued)
Command
[address [value]] [;size]
Explanation
Modify Memory: With optional address value parameter values, assigns that value address location. With optional address value value parameter value, prompts value address location, then prompts value next location. stop modification, enter period instead value. With optional address value, prompts value last address viewed, then prompts value next location. stop modification, enter period instead value. optional size value, specifies format: (bytes, default), (half words), (words), (instructions). Breakpoint: With optional address value, removes breakpoint from that address. Without address value, removes breakpoints. Reset: Resets peripherals. Register Display: With optional name value, displays value that register. Without name value, displays values registers. Register Modify: Assigns value parameter value name register. Trace (Step): Single steps instruction; identical command. Step (Trace): Single steps instruction; identical command. Help Displays available commands, identical command.
nobr [address]
reset [name]
name value
3.1.2 Picobug Sample Session
This sample session begins with Picobug prompt:
picobug
contents registers, enter Register Display (rd) command without name value:
picobug>
system responds with display such this:
00400286 80000100 ss0-ss4 bad0beef r0-r7 004027f8 r8-r15 0010a000 epsr 20000c00 00000050 00020000 00400286 80000100 20008000 0000ea60 20000c00 fpsr 20010042 00405f94 004067c0 0010a000 00020000 00000801 00406708 00000000 80070101 00405f94 00405c00 00000200 10005000 00000040 00400286
MMCCMB3401UM/D User's Manual
Operation
contents specific register, such register, enter Register Display (rd) command with name value:
picobug>
system responds with display such this:
epc: 00400286
contents specific memory location, enter Memory Display (md) command with location address. optional size value this case word) part command:
picobug> 0x00401000
system responds with display such this:
00401000: 8EF0B37E
contents memory range, enter Memory Display (md) command with beginning ending addresses. optional size value this case byte) part command:
picobug> 0x00400000 0x00400010
system responds with display such this:
00400000: 00400010: $.UUUU.
download into SRAM program executable, S-record format, enter Download (lo) command without address value:
picobug>
system waits send program executable file. open Transfer menu select Send Text File. This opens file-select dialog box. this dialog specify appropriate S-record file, then click Open button. soon download complete (this take several minutes), Picobug prompt reappears:
picobug>
contents registers, enter Register Display (rd) command again, without name value:
picobug>
MMCCMB3401UM/D User's Manual
Debugging Embedded Code
system responds with updated display, which shows that register value reflects start program just downloaded:
0040022a 80000000 ss0-ss4 bad0beef r0-r7 bad0beef r8-r15 0010a000 epsr 20000c00 00000050 004066b8 2d00108a 80070101 20008000 00000000 004067d7 fpsr 20010042 d89f69ab 00406948 0010a000 00020000 00000801 00405f20 00406714 80000000 00406708 00405c00 00000200 004067c8 00000024 2d0001c4
breakpoint address 0x0040025C, enter this address part Breakpoint (br) command:
picobug> 0x0040025c
Picobug prompt reappears, confirming that system breakpoint:
picobug>
list breakpoints, enter Breakpoint (br) command without address value:
picobug>
system responds with addresses breakpoints, this case only breakpoint step
0040025C
start program execution, enter command:
picobug>
this instance, breakpoint during step stops code execution. system responds with this display register values:
breakpoint!! 0040025c 80000100 ss0-ss4 bad0beef r0-r7 004027f8 r8-r15 0010a000 epsr 20000c00 00000050 004066b8 0040025c 80000100 20008000 0000ea60 004067d7 fpsr 20010042 d89f69ab 00406948 0010a000 00020000 00000801 00405f20 00406714 80000000 00406708 00405c00 00000200 10005010 00000040 004002a2
remove breakpoints, enter Breakpoint (nobr) command, without address value:
picobug> nobr
Picobug prompt reappears, confirming that system removed breakpoints:
picobug>
list breakpoints again, once more enter Breakpoint (br) command without address value:
picobug>
MMCCMB3401UM/D User's Manual
Operation
there longer breakpoints, system responds with Picobug prompt:
picobug>
continue with this example session, enter another appropriate command. example, resume program execution, enter command. your Picobug session, remove power from close terminal-emulation program.
3.1.3 Using Source-Level Debugger
source-level debugger CD-ROM that comes with your CMB3401. This software works with Picobug monitor provide source-level debugging your code. CMB3401 software release guide gives instructions loading software, making connections different from standalone Picobug connections. Make sure that Picobug communications-speed setting 19200 baud: this only communications speed software.
Downloading FLASH Memory
Motorola SysDS Loader lets program code into FLASH memory, upload FLASH contents file, verify that FLASH contents match those download file, display memory contents, erase FLASH memory, erase sector FLASH memory, blank check sector FLASH memory.
3.2.1 Using SysDS Loader
Follow these steps Loader: have already installed SysDS Loader onto your computer hard disk, CMB3401 product release guide includes installation instructions. Hyperterminal emulation program running, stop program. (The SysDS Loader needs same computer serial port that Hyperterminal uses.) switch Picobug monitor. factory setting, example, specifies Picobug: GSB0 GSB1 subswitches OFF, GSB2 subswitch Press switch reset CMB3401.
MMCCMB3401UM/D User's Manual
Downloading FLASH Memory
Start SysDS Loader. main screen (Figure 3-1) appears.
Figure SysDS Loader Main Screen File name field. know full pathname file programmed, enter pathname this field. know full pathname file programmed, click Browse button. This brings standard file-select dialog box: select file click button. This returns FLASH/RAM page, entering pathname File name field. your only action this Loader session will uploading FLASH contents, leave File name field blank.)
Make sure that SYSTEM field shows value CMB3401. Flash area configure FLASH type, width, size. value Base Address field automatic, according entry SYSTEM field. (Optionally, select value <CUSTOM>, which brings Custom Address dialog box. Enter appropriate address, then click dialog button return main screen.)
MMCCMB3401UM/D User's Manual
Operation
Communications area, Port field specify serial port, Speed field specify communications rate. (The default rate 19200 baud.) program FLASH memory, click Download button. software downloads file specified, progress message appears Status dialog box. Download successful message appears downloading: ready code FLASH memory. this first action this Loader session, software downloads algorithm file before downloading file specified. progress message appears during downloading this algorithm file. software cannot find algorithm file, appropriate error message identifies file. Click message's button bring file-select dialog box, then this dialog specify location algorithm file. necessary, recopy file from transmittal CD-ROM. Click button resume programming FLASH memory. error message Unable Validate Flash configuration indicates some problem with programming. likely such problem that chip select base address does correspond configured chip select. Correct problem, then click again Program button.
upload FLASH memory contents file your click Upload button. This brings Upload File dialog box, Figure 3-2:
Figure Upload File Dialog Enter name destination file. Optionally, click Browse button, select file standard file-select dialog box. Start Address field indicates start CMB3401 FLASH memory. default address value corresponds value SYSTEM field main screen FLASH/RAM page, enter different address, appropriate.
MMCCMB3401UM/D User's Manual
Downloading FLASH Memory
Size Bytes field value corresponds value Size field FLASH/RAM page. appropriate, enter different value.) system determines value Address field from Start Address Size bytes values. default Mode field value Byte. When Upload File dialog shows appropriate values, click Save button. progress message appears during uploading. uploaded values include addresses ASCII representations.
NOTE:
verify that contents Flash memory match selected download file, click Verify button. progress message appears verification begins. Verify successful message appears verification. this first action this Loader session, software downloads algorithm file before verifying FLASH. progress message appears during downloading this algorithm file. (Should software unable find algorithm file, appropriate error message appears, explained under program FLASH memory step, above.) verification fails, error message specifies location that have expected contents. recover from verification failure, downloading Flash again, replace selected download file.
view contents Flash memory, click Display button. This brings Display Flash/Ram display, Figure 3-3:
Figure Display Flash/Ram Display
MMCCMB3401UM/D User's Manual
Operation
this first action this Loader session, software downloads algorithm file before displaying FLASH contents. progress message appears during downloading this algorithm file. (Should software unable find algorithm file, appropriate error message appears, explained under program FLASH memory step, above.) Address field shows first address value display. change display enter different address this field. Another change value display scroll bars. Mode field specify byte, half-word, word values display. When done viewing display, click Close button return main screen.
erase FLASH memory, click Erase FLASH button. programmer erases contents FLASH memory except sectors that contain system software. Erasing takes seconds. this first action this Loader session, software downloads algorithm file before erasing FLASH. progress message appears during downloading this algorithm file. (Should software unable find algorithm file, appropriate error message appears, explained under program FLASH memory step, above.) erase sector FLASH memory, click Erase Sector button. This brings Flash Sector Number dialog box. Enter number sector erased, then click button. this first action this Loader session, software downloads algorithm file before erasing FLASH sector. progress message appears during downloading this algorithm file. (Should software unable find algorithm file, appropriate error message appears, explained under program FLASH memory step, above.) Flash: system does erase sectors that contain system software. (Table shows these sectors.) Flash: specify sectors that contain system software, message reminds you. (Table 2-10 shows these sectors.) Buttons message cancel erasure proceed with erasure. erase system-software sectors, unless absolutely necessary. must erase such sector, subsequently restore factory programming following instructions subsection 3.2.2.
NOTE:
MMCCMB3401UM/D User's Manual
Controlling CMB3401 LEDs
verify that FLASH sector blank, click Blank Check button. This brings dialog that asks sector number. Enter number sector blank checked, then click button. message tells results blank check. sector blank, erase sector different sector.) your Loader session, merely close main screen.
3.2.2 Restoring System Software
must overwrite FLASH sectors through subsequently SysDS Loader restore SysDS software. follow these instructions: BIG_E subswitch Press switch reset CMB3401. Look SysDS Loader main screen (Figure 3-1). Between SYSTEM field Restore System Software button there untitled field. Make sure that value this untitled field Endian. FLASH area main screen, value Type field INTEL. Click Restore System Software button main screen. system software your current hard-disk directory, Loader automatically restores factory programming FLASH sectors through main screen reappears confirm successful programming. receive message that system software does exist, because software different hard-disk directory. make that directory active click again Restore System Software button.
Controlling CMB3401 LEDs
Section explained LEDs through flicker part CMB3401 self-test. Your code also control these LEDs, assigning values four least-significant bits global control register (GCR): controls (GCB0). controls (GCB1). controls (GCB2). controls (GCB3).
MMCCMB3401UM/D User's Manual
Operation
value these bits turns corresponding LED. value these bits turns corresponding LED. example assembly routine below writes value 0x0000_1110 GCR. This writes other three bits. Accordingly, this routine turns turns other LEDs
turn_on_led_0: 0x0E mtcr //LED GCB0
MMCCMB3401UM/D User's Manual
Configuring Your Software
Section Using FPGA Device
This section explains Altera Max+plusII software reprogram FPGA device CMB3401 location Additionally, this section explains periodic interval timers (PITs) FPGA device.
Configuring Your Software
NOTE: steps below guidance starting Altera MAX+plusII software. Should have difficulty preparing your MAX+plusII software, phone Altera customer service assistance.
must prepare your Altera development software before with your CMB3401. Follow Altera instructions Install Altera development software. Obtain install your Verilog authorization code file. registration information, this takes only hours; Altera customer service provide number.) Start Altera software. Start project. This completes software preparation. ready develop application suitable downloading CMB3401 device.
Reprogramming FPGA Device
Follow steps through below, develop application suitable downloading FPGA device location Most these steps typical using MAX+plusII software develop application project. These steps rigid instructions. case difficulty using MAX+plusII software, should call Altera customer service assistance. transmittal CD-ROM that contains this manual also contains example application files: symbol counter, Verilog counter, Verilog port. Windows Explorer create name folder project. Start MAX+plusII software. Open File menu select Project. From subordinate menu, select Name. This brings Project Name dialog box.
MMCCMB3401UM/D User's Manual
Using FPGA Device
Project Name dialog select newly created project folder, enter name project. (The project name should contain spaces; usually convenient give project same name folder.) Click button close dialog box. Open File menu select New. This brings dialog box. Select Text editor file, then click button. This closes dialog opens text editor window. Write Verilog code your application. (Consult Altera Verilog manuals instructions.) When your code done, leave text editor window open. Click Open Compiler Window toolbar button. software immediately compiles your code. compiler finds errors, correct them text editor window, then compile again. When compilation succeeds, your ready create default symbol. Still leaving text editor window open, open File menu select Create Default Symbol. software automatically creates graphic representation compiled code, symbol that later schematic design. Open File menu select Project. From subordinate menu, select Name. This brings Project Name dialog box. Project Name dialog select same folder selected Step Enter project name: this project will .hex file, Motorola suggests that append letter name used Step Click button close dialog box. Open File menu select New. This brings dialog box. Select graphic editor file, then click button. This closes dialog opens graphic editor window. Open Symbol menu select Enter. This brings Enter Symbol dialog box. Select symbol created Step symbol appears graphic editor window. inputs outputs symbol, then compile again. (The only errors likely this point mismatched signal names forgotten signal. Correct errors recompile.) When compilation succeeds, ready assign device. Open Assign menu select Device. This brings Device dialog box. Device Family area, select FLEX 10KA. Devices area, select EPF10K100ABC600-1. Click Device Options button, bring Individual Device Options dialog box.
MMCCMB3401UM/D User's Manual
Reprogramming FPGA Device
Individual Device Options dialog box: Device Options area. Click check these items: Release Clears Before Tri-States, Enable Chip-Wide Reset (DEV_CLRn), Enable Chip-Wide Output Enable (DEV_OE), Enable INIT_DONE Output, Low-Voltage Configuration Device, Configuration Device Pull-Up Resistor.
Find Configuration Device field: field value EPC2LC20. Elsewhere Individual Device Options dialog box, find Configuration Scheme field: field value Passive Serial (can Configuration Device). Affected Configuration Scheme area, make sure that both CLKUSR boxes have grey check marks. Make sure that only check marks those that Steps through specify, then click button return Device dialog box.
Click Device dialog button return main screen. This completes device assignment. ready assign signals pins. best give signals (wires) same names their corresponding pins. Open Assign menu select Pin/Location/Chip. This brings Pin/Location/Chip dialog box. Click Search button bring subordinate dialog that lists pins. (Click LIST button list.) listed names inputs outputs created part Step 14.) Select (highlight) pin, then click button. This returns Pin/Location/Chip dialog box; selected name will Node Name field. Chip Resource area dialog box. field, enter name FPGA pin. (This value column cross-reference table 6-5.) alternative using Search button select Pin, activating Type field. Select appropriate type from small pull-down menu, then enter name appropriate field, enter signal name Node Name field.
NOTE:
This completes assignment first pin.
MMCCMB3401UM/D User's Manual
Using FPGA Device
Repeat Step other signals. When done, close Pin/Location/Chip dialog box. NOTE: each finished design, Altera software creates .acf file: text file that edit. your first design, must Step each signal. subsequent designs, copy edit .acf file.
have already done configure ByteBlaster programming hardware Altera instructions. Compile your application file again. When compilation succeeds, ready create .pof file. Open MAX+plusII menu select Programmer. This brings Programmer dialog box. (You will anything this dialog box, must open this point.) Open JTAG menu select Multi-Device JTAG Chain Setup. This brings Multi-Device JTAG Chain Setup dialog box. Device Name pull-down menu select EPF10K100A, then click button. EPF10K100A name appears list center dialog box, without associated programming. Device Name pull-down menu select EPC2, then click button. EPC2 name appears list center dialog box, without associated programming. Device Name pull-down menu select EPC2 second time, then click Select Programming File button. This brings Select Programming File dialog box. Select Programming File dialog select .pof file your project. Click button return Multi-Device JTAG Chain Setup dialog box. Click button. This again adds EPC2 name list center dialog box, shows association with selected .pof file. Click Save button. This brings subordinate dialog that lets name save listed files JTAG chain file. Click button return Multi-Device JTAG Chain Setup dialog box. Click Multi-Device JTAG Chain Setup dialog button return Programmer dialog box. This completes file creation; ready download files FPGA device.
Apply power your CMB3401. Connect ByteBlaster between CMB3401 connector parallel port your computer. Make sure that wire cable connects
MMCCMB3401UM/D User's Manual
Using Periodic Interval Timers
Click Program button Programmer dialog box. percentage indicator shows progress downloading files device CMB3401. this downloading, disconnect ByteBlaster cable from connector J14. Press CMB3401 switch transfer downloaded application FPGA device. This completes reprogramming device. close MAX+plusII software.
Using Periodic Interval Timers
FPGA device location includes periodic interval timers (PITs), which provide precise interrupts with minimal processor intervention. Each timer either count down from modulus-latch value free-running down counter. Figure diagram such PIT.
PITCSR
STOP STEP PITIE PITIF
PITADR Count 32-bit Down Counter Control Block load counter
PIT_INT
PITDR 32-bit Modulus Latch DBUG_n
Figure Diagram Each consists control block three registers: data register (PITDR), which contains timer modulus. Your code this modulus writing this register. Your code find modulus reading from this register. alternate data register (PITADR), which contains current counter value. Your code find current timer value reading from this register. control/status register (PITCSR), which controls timer operation. Your code control timer writing reading bits through this register.
Each PIT_INT output signal, which connects processor interrupt. When count reaches control block sets interrupt flag (PITIF, control/status register. This asserts PIT_INT signal, which alert processor that interrupt pending. signal remains asserted until control block your code) clears flag bit. PIT_INT signal PIT1 connects p_int_b[9] processor. PIT_INT signal PIT2 connects p_int_b[11] processor.
MMCCMB3401UM/D User's Manual
Using FPGA Device
set-and-forget timer, your code must reload control (RLD, control/status register. Then, your code must write appropriate modulus latch value data register. alternate data register copies modulus latch value from data register. Upon each system clock cycle, alternate data register decrements value When counter value reaches (0x0000_0000), control block sets interrupt flag (PITIF) control/status register. interrupt enable (PITIE, also set, PIT_INT interrupt-pending signal goes processor. alternate data register again copies modulus latch value from data register, counting cycle begins again. Your code change modulus latch value time, writing data register. force count immediately, your code must overwrite enable (OVW, control/status register, then write value data register.
free-running timer, your code must clear reload control (RLD, control/status register. This tells alternate address register ignore modulus latch value data register. Upon each system clock cycle, alternate data register decrements value When counter value reaches control block sets interrupt flag (PITIF) control/status register. interrupt enable (PITIE, also set, PIT_INT interrupt-pending signal goes processor. next clock cycle, alternate data register decrements value 0xFFFF_FFFF, counting cycle begins again. force count immediately, your code must overwrite enable (OVW, control/status register, then write value data register. Your code change modulus latch value time, writing data register. However, timer will ignore modulus latch value long set.
Table lists register addresses both PITs. Figure shows layout control/status register. Table explains control bits control/status register. Table Register Addresses
Registers
Control/Status Register (PITCSR) Data Register (PITDR) Alternate Data Register (PITADR)
PIT1 Addresses
0x0021_1124 0x0021_1128 0x0021_112C
PIT2 Addresses
0x0021_2224 0x0021_2228 0x0021_222C
MMCCMB3401UM/D User's Manual
Using Periodic Interval Timers
STOP
STEP
LOAD PITIE PITIF
Figure Control/Status Register Layout
Table Control/Status Register Values
Name
Reload Control (RLD)
Value
Effect/Meaning
After reaching 0x0000_0000, counter decrements 0xFFFF_FFFF continues counting down. After reaching 0x0000_0000, counter loads modulus latch value continues counting down. interrupt present. write this unasserts interrupt signal. write data register also clears this bit.) interrupt present. write effect.) Prevents interrupt signal from reaching interrupt controller. Allows interrupt signal reach interrupt controller. data register holds modulus latch value. When count alternate data register reaches alternate data register reads modulus latch value. alternate data register immediately reads modulus latch value from data register, regardless current count value. Counter functionality continues while debug mode. Debug mode freezes counter. None. read this always returns write effect.) Copies modulus latch value from data register alternate data register. (Hardware automatically clears this after loading.) None. read this always returns write effect.) Steps counter clock cycle. (Hardware automatically clears this after stepping. write effect counter stopped.) Starts counting. Stepping possible. Stops (freezes counter. Stepping possible.
Interrupt Flag (PITIF)
Interrupt Enable (PITIE) Overwrite Enable (OVW)
Debug Mode (DBG) Load Counter (LOAD)
Step Counter (STEP)
Stop Counter (STOP)
NOTE:
Your code step counter from step counter from modulus latch value. Setting counter value directly does cause interrupt.
MMCCMB3401UM/D User's Manual
Using FPGA Device
MMCCMB3401UM/D User's Manual
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4)
Section Connector Information
This section consists assignments signal descriptions CMB3401 connectors.
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4)
Connectors through 2-by-50-pin connectors, CMB3401 MAPI connectors. (Connectors through bottom CMB3401, have same assignments.) diagram below shows orientation CMB3401 MAPI connectors. Figure through Figure 5-4, Table through Table 5-4, give assignments signal descriptions these connectors.
MMCCMB3401UM/D User's Manual
Connector Information
P1/J1
VPP1 CS8_b CS9_b PTJ1[94] VDD5V PTJ1[88] PTJ1[86] PTJ1[84] PTJ1[82] PTJ1[80] PTJ1[78] PTJ1[76] PTJ1[72] PTJ1[70] PTJ1[68] PTJ1[66] PTJ1[64] PTJ1[62] VDD3V MID0 INT_b[14] INT_b[12] MID1 INT_b[10] INT_b[8] PTJ1[44] PTJ1[42] MID2 PTJ1[38] PTJ1[36] MID3 PTJ1[32] PTJ1[30] GND1 PTJ1[24] PTJ1[22] PTJ1[20] PTJ1[18] PTJ1[16] PTJ1[14] GND1 GND2 PTJ18] PTJ1[6] PTJ1[4] GND2 VDD3V CS4_b CS5_b CS6_b CS7_b PTJ1[87] PTJ1[85] PTJ1[83] PTJ1[81] PTJ1[79] PTJ1[77] PTJ1[75] DVSP_b[0] RS11 PTJ1[67] PTJ1[65] PTJ1[63] PTJ1[61] VDD3V PTJ1[57] PTJ1[55] PTJ1[53] PTJ1[51] PTJ1[49] PTJ1[47] PTJ1[45] PTJ1[43] PTJ1[39] PTJ1[37] PTJ1[35] PTJ1[33] PTJ1[31] PTJ1[29] PTJ1[27] PTJ1[25] PTJ1[23] PTJ1[21] PTJ1[19] PTJ1[17] PTJ1[15] PTJ1[13] PTJ1[11] PTJ1[9] PTJ1[7] PTJ1[5] PTJ1[3] PTJ1[1]
Figure MAPI Connector P1/J1 Assignments
MMCCMB3401UM/D User's Manual
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4)
Table MAPI Connector P1/J1 Signal Descriptions
98-95,
Mnemonic
VPP1 VDD3V Programming Voltage +3.2-volt power.
Signal
CS9_b CS4_b CHIP SELECTS (lines 9-4) Active-low output lines that provide chip selects (not exact external devices. order) PTJ1[x] Pass Through
88-75, 68-61, 45-42, 39-35, 33-29, 25-13, 9-3,
VDD5V DVSP_b[0] RS11 MID0 MID3 INT_b[14], INT_b[12], INT_b[10], INT_b[8] GND1 GND2
GROUND +5-volt power. DATA DENY Active-low signal that requests non-CMB devices access data bus. Reserved. IDENTIFICATION CODE (lines 0-3) Signals that identify host processor board. EXTRNAL INTERRUPTS (lines Bidirectional interrupt lines that form external interface general-purpose module.
GROUND Connection Ground plane. GROUND Connection Ground plane.
MMCCMB3401UM/D User's Manual
Connector Information
P2/J2
PTJ2[100] PTJ2[98] PTJ2[96] PTJ2[94] PTJ2[92] PTJ2[90] PTJ2[88] PTJ2[86] VDD3V PTJ2[80] PTJ2[78] PTJ2[76] PTJ2[74] PTJ2[72] PTJ2[70] PTJ2[68] PTJ2[66] VDD3V RS56 RS54 RS52 RS50 RS48 RS46 RS44 VDD3V RS40 RS38 RS36 RS34 RS32 RS30 RS28 PTJ2[28] PTJ2[26] PTJ2[24] PTJ2[22] VDD3V PTJ2[16] PTJ2[14] PTJ2[12] PTJ2[10] PTJ2[8] PTJ2[6] PTJ2[4] PTJ2[2] GND3 PTJ2[97] PTJ2[95] PTJ2[93] PTJ2[91] PTJ2[89] PTJ2[87] GND3 VPP3 VDD5V PTJ2[77] PTJ2[75] PTJ2[73] PTJ2[71] PTJ2[69] PTJ2[67] PTJ2[65] PTJ2[61] RS57 RS55 RS53 RS51 RS49 RS47 RS45 VDD5V RS41 RS39 RS37 RS35 RS33 SDCPS VDD5V PTJ2[27] PTJ2[25] PTJ2[23] PTJ2[21] VPP2 GND2 PTJ2[13] PTJ2[11] PTJ2[9] PTJ2[7] PTJ2[5] PTJ2[3] GND2
Figure MAPI Connector P2/J2 Assignments
MMCCMB3401UM/D User's Manual
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4)
Table MAPI Connector P2/J2 Signal Descriptions
100, 98-86, 78-65, 28-21, 14-2 60-47, 40-32,
Mnemonic
PTJ2[x] Pass Through
Signal
GND3 VDD3V VPP3 VDD5V
GROUND Connection Ground plane. GROUND +3.2-volt power. Programming Voltage. +5-volt power.
RS57-RS44, Reserved. RS41-RS32, RS30, RS28 (not exact order) SDCPS SHUT DOWN POWER SUPPLY Signal, from connected board that supplies power, disable on-board power supply. Programming Voltage. GROUND Connection Ground plane.
VPP2 GND2
MMCCMB3401UM/D User's Manual
Connector Information
P3/J3
VDD3V VPP4 CLKCTL FREZ_b GPIO SIZ1_b SIZ0_b DE_b J_TDI J_TDO VSTBY IDVDD VDD5V TBUSY_B RS67 MAPI_TC2 MAPI_TC1 MAPI_TC0 VDD3V PTJ3[58] PTJ3[56] BKREQ_b LPMD0 LPMD1 ABORT_b PTJ3[46] PTJ3[44] PTJ3[42] PTJ3[40] PTJ3[38] PTJ3[36] PTJ3[34] PTJ3[32] PTJ3[30] PTJ3[28] PTJ3[26] PTJ3[24] PTJ3[22] PTJ3[20] PTJ3[18] PTJ3[16] PTJ3[14] PTJ3[12] PTJ3[10] PTJ3[8] PTJ3[6] PTJ3[4] PTJ3[2] VDD3V EXTAL GPIOSO J_TRST_B J_TCLK J_TMS RSTOUT_B RIN_b PSTAT3 PSTAT2 PSTAT1 PSTAT0 MID9 MID8 VDD3V PTJ3[57] MID4 PTJ3[53] PTJ3[51] MID5 PTJ3[47] PTJ3[45] PTJ3[41] PTJ3[39] MID6 PTJ3[35] PTJ3[33] MID7 PTJ3[29] PTJ3[27] GND4 PTJ3[21] PTJ3[19] PTJ3[17] PTJ3[15] PTJ3[13] PTJ3[11] GND4 GND3 PTJ3[5] PTJ3[3] GND3
Figure MAPI Connector P3/J3 Assignments
MMCCMB3401UM/D User's Manual
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4)
Table MAPI Connector P3/J3 Signal Descriptions
100,
Mnemonic
VDD3V VPP4 CLKCTL FREZ_b EXTAL GPIO GPIOSO +3.2-volt power Programming Voltage GROUND
Signal
CLOCK CONTROL Clock control signal clock. DEBUG MODE INDICATOR Active-low signal indicating that processor debug mode. EXTERNAL CLOCK Off-board clock signal. TRI-STATE CONTROL Signal that puts processor tri-state mode. GENERAL PURPOSE INPUT/OUTPUT General-purpose signal. GENERAL PURPOSE SERIAL OUTPUT General-purpose serial output signal.
SIZ1_b], SIZ0_b TRANSFER SIZE (lines Signals that indicate size external transfer. J_TRST_b TEST RESET Active-low input signal Schmitt trigger, asynchronously initializing test controller. J_TRST_b internal pullup resistor. TEST CLOCK Input signal that synchronizes JTAG test logic. internal pullup resistor. DEBUG EVENT Open-drain, active-low debug signal. input signal from external command controller, causes enter debug mode. output signal, acknowledges that debug mode. TEST MODE SELECT Input signal that sequences test controller's state machine, sampled rising edge signal. internal pullup resistor. TEST DATA INPUT Serial input signal test instructions data, sampled rising edge signal. internal pullup resistor. TEST DATA OUTPUT Serial output signal test instructions data. Three-stateable actively driven Shift-IR Shift-DR controller states, this signal changes falling edge signal. RESET Active-low output signal that resets external components. Activation internal reset sources asserts this line. STANDBY VOLTAGE Standby power M340 on-board RAM. RESET Active-low input signal that starts system reset: reset PowerStrike device most peripherals. This signal does affect debug module (which system provides TRST* line). IDENTIFICATION POWER Special 3-volt power signal MAPI identification code (MID) signals. SHOW CYCLE STROBE Active-low signal output signal indicating that address data valid show cycles. OPERATING VOLTAGE Transmission line +5-volt CMB3401 input power. PROCESSOR STATUS (lines 3-0) Output signals that provide external status indications resident MCU. BUSY Signal indicating that cycle progress.
J_TCLK DE_b
J_TMS
J_TDI
J_TDO
RSTOUT_b VSTBY RIN_b
IDVDD VDD5V PSTAT3 PSTAT0 TBUSY_b
MMCCMB3401UM/D User's Manual
Connector Information
Table MAPI Connector P3/J3 Signal Descriptions (Continued)
58-56, 47-44, 42-38, 36-32, 30-26, 22-10,
Mnemonic
RS67 MAPI_TC2 MAPI_TC0 MID9 MID4 (not exact order) PTJ3[x] Reserved.
Signal
TRANSFER CODE (lines 2-0) Signals indicating general type transfer. IDENTIFICATION CODE (lines 9-4) Signals that identify host processor board. Pass Through.
BKREQ_b LPMD0, LPMD1
BREAKPOINT REQUEST Active-low signal that requests hardware breakpoint. POWER MODE (lines Signals asserted processor upon execution doze, stop, wait instruction. Optionally, external source assert these signals low-power stopped state. TRANSFER ABORT Active-low signal from processor that requested access must aborted. GROUND Connection Ground plane. GROUND Connection Ground plane.
ABORT_b GND4 GND3
MMCCMB3401UM/D User's Manual
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4)
P4/J4
VDD5V CSE1 CSE0 RS73 RS72 OE_b[0] EBD_b EBC_b EBA_b EBB_b TEA_b VDD3V VDD3V CLKOUT CS_b[3] CS_b[2] CS_b[1] CS_b[0] R_W_b TREQ_b MAPI_TA_b VDD3V
Figure MAPI Connector P4/J4 Assignments
MMCCMB3401UM/D User's Manual
Connector Information
Table MAPI Connector P4/J4 Signal Descriptions
Mnemonic
VDD5V VDD3V CSE1, CSE0 +5-volt power. +3.2-volt power.
Signal
CHIP SELECT, EMULATION (lines Emulation chip select signals. GROUND
CLKOUT RS73, RS72 CS_b[3] CS_B[0] OE_b[0]
CLOCK OUTPUT external clock source from processor. Reserved. FPGA CHIP SELECTS (lines 3-0) Active-low output lines that provide chip selects external devices. These signals driven from FPGA address space. FPGA OUTPUT ENABLE Active-low signal that indicates that access read access; enables slave devices drive data bus. This signal driven from FPGA address space.
EBD_b, EBC_b, FPGA ENABLE BYTES Active-low outputs active during EBA_b, EBB_b operation corresponding data bits (D31-D24 enable byte D23-D16 enable byte D7-D0 enable byte D15-D8 enable byte (These signals driven from FPGA address space.) configure these bytes assert write cycles both read write cycles. R_W_b FPGA READ/WRITE ENABLE Active-low signal that indicates whether current access read access write access. This signal driven from FPGA address space. FPGA TRANSMIT REQUEST Active-low signal indicating access request. resident drives this signal. This signal driven from FPGA address space. TRANSFER ERROR ACKNOWLEDGE Active-low signal that indicates transfer error. FPGA TRANSFER ACKNOWLEDGE Active-low signal indicating completion data transfer, either read write cycle. This signal driven from FPGA address space. ADDRESS (lines 31-0) Output lines addressing external devices. These lines change state only during external-memory accesses. DATA (lines 31-0) Bi-directional data lines accessing external memory. hardware reset external-bus activity hods these lines their previous logic state.
TREQ_b
TEA_b MAPI_TA_b
74-59, 56-41
(not exact order) (not exact order)
38-29, 26-17, 14-3
MMCCMB3401UM/D User's Manual
OnCE Connector (J13)
OnCE Connector (J13)
Connector J13, 2-by-7-pin connector, conveys data control signals from OnCE control block. Figure Table give assignments signal descriptions this connector.
EVTI_b RESET_b EVTO_b
(NC) RDY_b TRST_b
Figure OnCE Connector Assignments
Table OnCE Connector Signal Descriptions
Mnemonic
EVTI_b
Signal
TEST DATA INPUT Data command serial input line OnCE controller. GROUND TEST DATA OUTPUT Serial data output line from OnCE controller. TEST CLOCK Serial clock input line OnCE control block. EVENT Active-low signal. reset, enables disables NEXUS block. other times, provided that NEXUS messages causes synchronization message. connection RESET Active-low input line OnCE controller, signalling reset. TEST MODE SELECT Input signal that tells OnCE control block advance mode state cycle mode states). OPERATING VOLTAGE Transmission line +3.2-volt operating power. READ/WRITE READY Active-low signal that NEXUS read write access ready. WATCHPOINT EVENT Active-low signal that NEXUS watchpoint occurred, providing exact timing reference. TEST RESET Active-low input line external reset signal OnCE controller.
(NC) RESET_b RDY_b EVTO_b TRST_b
MMCCMB3401UM/D User's Manual
Connector Information
NEXUS Connector (J23)
Connector J23, 2-by-15-pin connector, conveys data control signals from NEXUS (GEPDIS) control block. Figure Table give assignments signal descriptions this connector.
RESET_b EVTI_b TRST_b RESINOUT[1] TCLK RESINOUT[2] RDY_b MDO1 MDO0 MCLK0 MSEO_b EVTO_b
VREF GPIO
Figure NEXUS Connector Assignments
Table NEXUS Connector Signal Descriptions
Mnemonic
RESET_b VREF EVTI_b
Signal
RESET Active-low input line NEXUS controller, signalling reset. VOLTAGE REFERENCE Transmission line +3.3-volt operating power. EVENT Active-low signal. reset, enables disables NEXUS block. other times, provided that NEXUS messages causes synchronization message. GROUND TEST RESET Active-low input line external reset signal NEXUS controller. TEST MODE SELECT Input signal that tells NEXUS control block advance mode state cycle mode states). RESERVED IN/OUT (lines connection. TEST DATA INPUT Data command serial input line NEXUS controller. TEST CLOCK Serial clock input line NEXUS control block. TEST DATA OUTPUT Serial data output line from NEXUS controller.
even, 4-28
TRST_b RESINOUT[1], RESINOUT[2] TCLK
MMCCMB3401UM/D User's Manual
NEXUS Connector (J23)
Table NEXUS Connector Signal Descriptions (Continued)
RDY_b MDO1, MDO0 MCLK0 MSEO_b READ/WRITE READY Active-low signal that NEXUS read write access ready. MESSAGE DATA (lines Output signals NEXUS messages. CLOCK Clock signal used resident MCU. MESSAGE START/END Active-low output indicating that NEXUS message starting ending., variable-length packet, message. WATCHPOINT EVENT Active-low signal that NEXUS watchpoint occurred, providing exact timing reference. GENERAL PURPOSE INPUT/OUTPUT General-purpose signal.
EVTO_b GPIO
MMCCMB3401UM/D User's Manual
Connector Information
Logic Analyzer Connectors (J25, J28, J32)
Connectors J25, J28, J32, 2-by-19-pin Mictor connectors, logic analyzer connectors. Figure through Figure give assignments these connectors. Table through Table give signal descriptions these connectors.
MLB_CLK
RW_b
Figure Logic Analyzer Connector Assignments
Table Logic Analyzer Connector Signal Descriptions
Mnemonic
MLB_CLK (not exact order) RW_b connection
Signal
CLOCK OUTPUT External clock source. ADDRESS Output lines 31-0, addressing external devices. These lines change state only during external-memory accesses. READ/WRITE ENABLE Active-low signal that indicates whether current access read access write access.
MMCCMB3401UM/D User's Manual
Logic Analyzer Connectors (J25, J28, J32)
TREQ_b TSIZ1 TSIZ0 BURST_b PSTAT4 PSTAT3 PSTAT2 PSTAT1 PSTAT0 RESET_b BG_b ABORT_b TBUSY_b
MLB_TA_b BR_b CI_b TSCD_b IDLY4_b IPEND_b IFETCH_b FINT_b] INT_b INT_RAW_b FINT_RAW_b LPMD1 LPMD0 ALT_ADDR1 ALT_ADDR0
Figure Logic Analyzer Connector Assignments
Table Logic Analyzer Connector Signal Descriptions
Mnemonic
TREQ_b TSIZ1, TSIZ0 BURST_b PSTAT4- PSTAT0 RESET_b BG_b ABORT_b TBUSY_b connection
Signal
TRANSMIT REQUEST Active-low signal indicating access request. resident drives this signal. TRANSFER CODE (lines 2-0) Signals indicating general type transfer. TRANSFER SIZE (lines Signals that indicate size external transfer. BURST Active-low signal indicating that current access cache line burst. PROCESSOR STATUS (lines 4-0) Output signals that provide external status indications resident MCU. RESET Active-low input signal that resets initializes most debug-module logic. GRANT Active-low output signal that grants interface-bus ownership alternate master. TRANSFER ABORT Active-low signal from processor that requested access must aborted. TRANSFER BUSY Active-low signal indicating that access progress. resident drives this signal.
MMCCMB3401UM/D User's Manual
Connector Information
Table Logic Analyzer Connector Signal Descriptions (Continued)
Mnemonic
ALT_ADDR0, ALT_ADDR1 LPMD0, LPM1
Signal
ALTERNATE ADDRESS (lines 0,1) Signals that enable on-chip memory devices derive addresses alternate memory blocks. This enables devices support both little-endian big-endian modes. POWER MODE (lines Signals asserted processor upon execution doze, stop, wait instruction. Optionally, external source assert these signals low-power stopped state. FAST INTERRUPT REQUEST Active-low input fast-interrupt-request signal asynchronous interrupt pending output processor core. INTERRUPT REQUEST Active-low input interrupt-request signal asynchronous interrupt pending output processor core. INTERRUPT REQUEST Active-low output signal that requests normal interrupt processor core. FAST INTERRUPT REQUEST Active-low output signal that requests fast interrupt processor core. INSTRUCTION FETCH Active-low output signal that defines current cycle access instruction prefetch cache line fill instruction prefetch. INTERRUPT PENDING Active-low output signal indicating that interrupt pending: processor recognized interrupt request internally, appropriate enabled interrupt. IDLY4 STATUS Active-low output signal indicating that processor core idly4 instruction sequence. TRI-STATE CONTROL DATA Active-low output signal that toggles alternate master's ability drive data TBUSY_b signal. CACHE INHIBIT Active-low signal (asserted accessed lave device) cache current read access. REQUEST Active-low signal from alternate master, requesting ownership interface bus. TRANSMIT ACKNOWLEDGE Active-low signal that indicates data-transfer completion, either read cycle write cycle.
FINT_RAW_b INT_RAW_b INT_b FINT_b IFETCH_b
IPEND_b
IDLY4_b TSCD_b CI_b BR_b MLB_TA_b
MMCCMB3401UM/D User's Manual
Logic Analyzer Connectors (J25, J28, J32)
TA_b
TSCA_b
Figure Logic Analyzer Connector Assignments
Table Logic Analyzer Connector Signal Descriptions
Mnemonic
TA_b (not exact order) TSCA_b connection
Signal
TRANSMIT ACKNOWLEDGE Active-low signal that indicates data-transfer completion, either read cycle write cycle. DATA Bi-directional data lines 31-0, accessing external memory.
TRI-STATE CONTROL ADDRESS Active-low output signal that toggles alternate master's ability drive address attributes.
MMCCMB3401UM/D User's Manual
Connector Information
Logic Analyzer Connectors (J29, J30, J33)
Connectors J29, J30, J33, 2-by-19-pin Mictor connectors, EIM-bus logic analyzer connectors. Figure 5-10 through Figure 5-12 give assignments these connectors. Table 5-10 through Table 5-12 give signal descriptions these connectors.
CLKOUT EIM_A31 EIM_A30 EIM_A29 EIM_A28 EIM_A27 EIM_A26 EIM_A25 EIM_A24 EIM_A23 EIM_A22 EIM_A21 EIM_A20 EIM_A19 EIM_A18 EIM_A17 EIM_A16
EIM_RW_b EIM_A15 EIM_A14 EIM_A13 EIM_A12 EIM_A11 EIM_A10 EIM_A9 EIM_A8 EIM_A7 EIM_A6 EIM_A5 EIM_A4 EIM_A3 EIM_A2 EIM_A1 EIM_A0
Figure 5-10 Logic Analyzer Connector Assignments
Table 5-10 Logic Analyzer Connector Signal Descriptions
Mnemonic
CLKOUT EIM_A31 EIM_A0 (not exact order) EIM_RW_b connection
Signal
CLOCK OUTPUT External clock source. ADDRESS Output lines 31-0, addressing external devices. These lines change state only during external-memory accesses.
READ/WRITE ENABLE Active-low signal that indicates whether current access read access write access.
MMCCMB3401UM/D User's Manual
Logic Analyzer Connectors (J29, J30, J33)
EIM_BAA_b TREQ_b TSIZ1 TSIZ0 E_RW_b PSTAT4 PSTAT3 PSTAT2 PSTAT1 PSTAT0 RESET_b EIM_LBA_b ABORT_b TBUSY_b
TEA_b RESINOUT6 RESINOUT5 RESINOUT4 RESINOUT3 IFETCH_b EIM_EB3_b] EIM_EB2_b EIM_EB1_b EIM_EB0_b EIM_CS5_b EIM_CS4_b EIM_CS1_b EIM_CS0_b
Figure 5-11 Logic Analyzer Connector Assignments
Table 5-11 Logic Analyzer Connector Signal Descriptions
Mnemonic
EIM_BAA_b connection
Signal
BURST ADDRESS ADVANCE Active-low output signal asserted during burst mode accesses, that burst-capable devices increment internal burst counters next sequential memory locations. TRANSMIT REQUEST Active-low signal indicating access request. resident drives this signal. TRANSFER CODE (lines 2-0) Signals indicating general type transfer. TRANSFER SIZE (lines Signals that indicate size external transfer. READ/WRITE ENABLE Active-low signal that indicates whether current access read access write access. PROCESSOR STATUS (lines 4-0) Output signals that provide external status indications resident MCU. RESET Active-low input signal that resets initializes most debug-module logic. LOAD BURST ADDRESS Active-low output signal asserted during burst mode accesses that burst-capable devices load starting burst addresses.
TREQ_b TSIZ1, TSIZ0 EIM_RW_b PSTAT4- PSTAT0 RESET_b EIM_LBA_b
MMCCMB3401UM/D User's Manual
Connector Information
Table 5-11 Logic Analyzer Connector Signal Descriptions (Continued)
ABORT_b TBUSY_b EIM_CS0_b, EIM_CS1_b, EIM_CS4_b, EIM_CS5_b TRANSFER ABORT Active-low signal from processor that requested access must aborted. TRANSFER BUSY Active-low signal indicating that access progress. resident drives this signal. CHIP SELECTS (lines Active-low chip-select signals bus.
EIM_EB0_b ENABLE BYTES Active-low outputs active during operation corresponding data bits (D31-D24 enable byte D23-D16 enable EIM_EB3_b byte D7-D0 enable byte D15-D8 enable byte configure these bytes assert write cycles both read write cycles. IFETCH_b INSTRUCTION FETCH Active-low output signal that defines current cycle access instruction prefetch cache line fill instruction prefetch.
RESINOUT3 RESERVED IN/OUT (lines 3-6) connection. RESINOUT6 TEA_b TRANSFER ERROR ACKNOWLEDGE Active-low signal that indicates transfer error.
MIM_TA_b EIM_D31 EIM_D30 EIM_D29 EIM_D28 EIM_D27 EIM_D26 EIM_D25 EIM_D24 EIM_D23 EIM_D22 EIM_D21 EIM_D20 EIM_D19 EIM_D18 EIM_D17 EIM_D16
EIM_BCLK EIM_D15 EIM_D14 EIM_D13 EIM_D12 EIM_D11 EIM_D10 EIM_D9 EIM_D8 EIM_D7 EIM_D6 EIM_D5 EIM_D4 EIM_D3 EIM_D2 EIM_D1 EIM_D0
Figure 5-12 Logic Analyzer Connector Assignments
MMCCMB3401UM/D User's Manual
TEA, Eyelets (J7, J18)
Table 5-12 Logic Analyzer Connector Signal Descriptions
Mnemonic
MIM_TA_b EIM_D31 EIM_D0 (not exact order) EIM_BCLK connection
Signal
TRANSMIT ACKNOWLEDGE Active-low signal that indicates data-transfer completion MIM, either read cycle write cycle. DATA Bi-directional data lines 31-0, accessing external memory.
BURST CLOCK Output clock signal that external burst-capable devices synchronize address loading, address incrementing, burst-read data delivery.
TEA, Eyelets (J7, J18)
Figure 5-13 depicts special eyelet connectors J18, between Mictor connector MAPI connector
Figure 5-13 TEA, Eyelets provides signal MLB_OLD_TEA. This TRANSFER ERROR ACKNOWLEDGE signal, double-latched, before gets M340 core. provides signal MLB_OLD_TA. This TRANSFER ACKNOWLEDGE signal, double-latched, before gets M340 core.
MMCCMB3401UM/D User's Manual
Connector Information
RS232 Connectors (J57, J58)
Connectors J58, RS232 connectors, have format. diagram below shows numbering these connectors. Table 5-13 lists assignments signal directions these connectors.
Table 5-13 RS232 Connector J57, Assignments
Signal
Communication Detect Transmitted Data Received Data Data Terminal Ready GROUND Data Ready Clear Send Request Send Ring Indicator
Signal Direction
NOTE:
Connector channel connector channel Accordingly, respective assignments thought CDB. Similarly, respective assignments thought TXDA TXDB, forth.
MMCCMB3401UM/D User's Manual
Section Cross Reference Tables
During your application development, need trace signal from resident 3401 device, through FPGA device, MAPI-ring connector. Conversely, need trace signal other direction. tables this chapter help such tracing: Table lists trace relationships 3401 device signals. Table lists trace relationships 3401 device pins. Table lists trace relationships MAPI-ring signals. Table lists trace relationships MAPI-ring pins. Table lists pins FPGA device, showing their relationships pins either 3401 device MAPI-ring connectors.
MMCCMB3401UM/D User's Manual
Cross Reference Tables
Table Cross Reference: 3401, FPGA, MAPI Connectors
3401 Device Signal
ITC_IRQ_B1 ITC_IRQ_B3 ITC_IRQ_B5 ITC_IRQ_B7 ITC_IRQ_B25 ITC_IRQ_B27 ITC_IRQ_B29 ITC_IRQ_B31 ITC_IRQ_B32 ITC_IRQ_B34 ITC_IRQ_B36 ITC_IRQ_B38 ITC_IRQ_B40 ITC_IRQ_B42 ITC_IRQ_B44 ITC_IRQ_B46 ITC_IRQ_B48 ITC_IRQ_B50 ITC_IRQ_B52 ITC_IRQ_B54 ITC_IRQ_B56 ITC_IRQ_B58 ITC_IRQ_B60 ITC_IRQ_B62 ITC_IRQ_B63 JD_DEBUG_B JD_MCU_DE_B JD_OFF_BUS_B J_TCLK J_TDI J_TDO J_TMS J_TRST_B MIM_TA_B MIM_TEA_B mlb_abort_b mlb_addr0 mlb_addr1 mlb_addr2
FPGA Device
AL34 AL35 AK33 AP19
MAPI Connectors Default Signal
ITC_IRQ_B1 ITC_IRQ_B3 ITC_IRQ_B5 ITC_IRQ_B7 ITC_IRQ_B25 ITC_IRQ_B27 ITC_IRQ_B29 ITC_IRQ_B31 ITC_IRQ_B32 ITC_IRQ_B34 ITC_IRQ_B36 ITC_IRQ_B38 ITC_IRQ_B40 ITC_IRQ_B42 ITC_IRQ_B44 ITC_IRQ_B46 ITC_IRQ_B48 ITC_IRQ_B50 ITC_IRQ_B52 ITC_IRQ_B54 ITC_IRQ_B56 ITC_IRQ_B58 ITC_IRQ_B60 ITC_IRQ_B62 ITC_IRQ_B63 JD_DEBUG_B JD_MCU_DE_B JD_OFF_BUS_B J_TCLK J_TDI J_TDO J_TMS J_TRST_B MIM_TA_B MIM_TEA_B MAPI_ABORT_B FPGA_ADDR0 FPGA_ADDR1 FPGA_ADDR2
3401 Side
Ring Side
J1-61 J1-63 J1-65 J1-67 J1-32 J1-36 J1-55 J1-57 J1-31 J2-72 J2-65 J2-74 J2-76 J2-78 J2-80 J1-33 J1-35 J1-37 J1-39 J1-43 J1-45 J1-47 J1-49 J1-51 J1-53 J3-84 J3-94 J2-77 J3-85 J3-82 J3-80 J3-83 J3-87 J2-73 J2-75 J3-48 J4-42 J4-41 J4-44
MMCCMB3401UM/D User's Manual
Table Cross Reference: 3401, FPGA, MAPI Connectors (Continued)
3401 Device Signal
mlb_addr3 mlb_addr4 mlb_addr5 mlb_addr6 mlb_addr7 mlb_addr8 mlb_addr9 mlb_addr10 mlb_addr11 mlb_addr12 mlb_addr13 mlb_addr14 mlb_addr15 mlb_addr16 mlb_addr17 mlb_addr18 mlb_addr19 mlb_addr20 mlb_addr21 mlb_addr22 mlb_addr23 mlb_addr24 mlb_addr25 mlb_addr26 mlb_addr27 mlb_addr28 mlb_addr29 mlb_addr30 mlb_addr31 mlb_alt_addr0 mlb_alt-addr1 mlb_avec_b mlb_bg_b MLB_BIGEND_B mlb_br_b mlb_burst_b mlb_ci_b MLB_CLKOUT mlb_data0 mlb_data1
FPGA Device
AL25
MAPI Connectors Default Signal
FPGA_ADDR3 FPGA_ADDR4 FPGA_ADDR5 FPGA_ADDR6 FPGA_ADDR7 FPGA_ADDR8 FPGA_ADDR9 FPGA_ADDR10 FPGA_ADDR11 FPGA_ADDR12 FPGA_ADDR13 FPGA_ADDR14 FPGA_ADDR15 FPGA_ADDR16 FPGA_ADDR17 FPGA_ADDR18 FPGA_ADDR19 FPGA_ADDR20 FPGA_ADDR21 FPGA_ADDR22 FPGA_ADDR23 FPGA_ADDR24 FPGA_ADDR25 FPGA_ADDR26 FPGA_ADDR27 FPGA_ADDR28 FPGA_ADDR29 FPGA_ADDR30 FPGA_ADDR31 FPGA_ALT_ADDR0 FPGA_ALT_ADDR1 MAPI_AVEC_B MAPI_BG_B MLB_BIGEND_B MAPI_BR_B MAPI_BURST_B FPGA_CI_B MLB_CLKOUT FPGA_DATA0 FPGA_DATA1
3401 Side
Ring Side
AH31 AK34 AJ33 AJ34 AJ35 AH32 AG31 AH33 AH34 AH35 AG32 AG33 AG34 AF31 AF33 AF34 AF35 AE31 AM35 AA31 AA32 AA35 AL32 AM33 AR26
J4-43 J4-46 J4-45 J4-48 J4-47 J4-50 J4-49 J4-52 J4-51 J4-54 J4-53 J4-56 J4-55 J4-60 J4-59 J4-62 J4-61 J4-64 J4-63 J4-66 J4-65 J4-68 J4-67 J4-70 J4-69 J4-72 J4-71 J4-74 J4-73 J3-39 J3-41 J1-80 J3-51 J3-40 J3-53 J3-46 J3-27 J4-95 J4-4 J4-3
MMCCMB3401UM/D User's Manual
Cross Reference Tables
Table Cross Reference: 3401, FPGA, MAPI Connectors (Continued)
3401 Device Signal
mlb_data2 mlb_data3 mlb_data4 mlb_data5 mlb_data6 mlb_data7 mlb_data8 mlb_data9 mlb_data10 mlb_data11 mlb_data12 mlb_data13 mlb_data14 mlb_data15 mlb_data16 mlb_data17 mlb_data18 mlb_data19 mlb_data20 mlb_data21 mlb_data22 mlb_data23 mlb_data24 mlb_data25 mlb_data26 mlb_data27 mlb_data28 mlb_data29 mlb_data30 mlb_data31 mlb_fint_b mlb_fint_raw_b mlb_idly4_b mlb_ifetch_b mlb_int_b mlb_int_raw_b mlb_ipend_b MLB_LPMD0 MLB_LPMD1 MLB_PSTAT0
FPGA Device
MAPI Connectors Default Signal
FPGA_DATA2 FPGA_DATA3 FPGA_DATA4 FPGA_DATA5 FPGA_DATA6 FPGA_DATA7 FPGA_DATA8 FPGA_DATA9 FPGA_DATA10 FPGA_DATA11 FPGA_DATA12 FPGA_DATA13 FPGA_DATA14 FPGA_DATA15 FPGA_DATA16 FPGA_DATA17 FPGA_DATA18 FPGA_DATA19 FPGA_DATA20 FPGA_DATA21 FPGA_DATA22 FPGA_DATA23 FPGA_DATA24 FPGA_DATA25 FPGA_DATA26 FPGA_DATA27 FPGA_DATA28 FPGA_DATA29 FPGA_DATA30 FPGA_DATA31 MAPI_FINT_B MAPI_FINT_RAW_B MAPI_IDLY4_B MAPI_IFETCH_B FPGA_INT_B MAPI_INT_RAW_B MAPI_IPEND_B MLB_LPMD0 MLB_LPMD1 MLB_PSTAT0
3401 Side
AN25 AP25 AM24
Ring Side
AM25 AL24 AR25 AP20 AL19
J4-6 J4-5 J4-8 J4-7 J4-10 J4-9 J4-12 J4-11 J4-14 J4-13 J4-18 J4-17 J4-20 J4-19 J4-22 J4-21 J4-24 J4-23 J4-26 J4-25 J4-30 J4-29 J4-32 J4-31 J4-34 J4-33 J4-36 J4-35 J4-38 J4-37 J1-62 J1-70 J3-26 J3-28 J1-79 J1-72 J1-78 J3-52 J3-50 J3-67
MMCCMB3401UM/D User's Manual
Table Cross Reference: 3401, FPGA, MAPI Connectors (Continued)
3401 Device Signal
MLB_PSTAT1 MLB_PSTAT2 MLB_PSTAT3 MLB_PSTAT4 mlb_reset_b mlb_rw_b mlb_tbusy_b mlb_tc0 mlb_tc1 mlb_tc2 MLB_TE_B mlb_treq_b mlb_tsca_b mlb_tscd_b mlb_tsiz0 mlb_tsiz1 mlb_vec0 mlb_vec1 mlb_vec2 mlb_vec3 mlb_vec4 mlb_vec5 mlb_vec6 MLB_WAKEUP_B M_POR RESINOUT7 RESINOUT8 RESINOUT9 RESINOUT10 RESINOUT11 RESINOUT12 RESINOUT13 RESINOUT14 RESINOUT15 RESINOUT16 RESINOUT17 RESINOUT18 TC_IN TC_MUX_MODE TC_OUT
FPGA Device
AM22 AP22 AM17 AR16 AN16 AL16 AP15 AL15 AP14 AR24 AM23 AP23 AN24 AL23 AN23 AM20 AL22 AN22 AN17 AL17 AP16 AM16 AR15 AM15 AR14 AL21
MAPI Connectors Default Signal
MLB_PSTAT1 MLB_PSTAT2 MLB_PSTAT3 MLB_PSTAT4 MAPI_RESET_B FPGA_RW_B MAPI_TBUSY_B MAPI_TC0 MAPI_TC1 MAPI_TC2 MLB_TE_B FPGA_TREQ_B MAPI_TSCA_B MAPI_TSCD_B FPGA_TSIZ0 FPGA_TSIZ1 MAPI_VEC0 MAPI_VEC1 MAPI_VEC2 MAPI_VEC3 MAPI_VEC4 MAPI_VEC5 MAPI_VEC6 MLB_WAKEUP_B M_POR RESINOUT7 RESINOUT8 RESINOUT9 RESINOUT10 RESINOUT11 RESINOUT12 RESINOUT13 RESINOUT14 RESINOUT15 RESINOUT16 RESINOUT17 RESINOUT18 TC_IN TC_MUX_MODE TC_OUT
3401 Side
Ring Side
J3-69 J3-71 J3-73 J3-70 J3-77 J4-81 J3-72 J3-62 J3-64 J3-66 J3-57 J4-79 J3-45 J3-47 J3-86 J3-88 J1-81 J1-82 J1-83 J1-84 J1-85 J1-86 J1-87 J3-38 J3-32 J2-22 J2-24 J2-26 J2-28 J2-66 J2-68 J2-70 J2-21 J2-23 J2-25 J2-27 J2-71 J3-30 J3-34 J3-29
MMCCMB3401UM/D User's Manual
Cross Reference Tables
Table Cross Reference: 3401, FPGA, MAPI Connectors (Continued)
3401 Device Signal
TC_TEST_EN TC_TRISTATE UARTA_INT10 UARTB_INT11
FPGA Device
AP27 AN27 AM27 AL27 AN11
MAPI Connectors Default Signal
TC_TEST_EN TC_TRISTATE UARTA_INT10 UARTB_INT11 BIG_TEST FPGA_CS_B0 FPGA_CS_B1 FPGA_CS_B2 FPGA_CS_B3 FPGA_CS_B4 FPGA_CS_B5 FPGA_CS_B6 FPGA_CS_B7 FPGA_CS_B8 FPGA_CS_B9 FPGA_EB_B0 FPGA_EB_B1 FPGA_EB_B2 FPGA_EB_B3 FPGA_OE_B MAPI_TA_B MAPI_TEA_B MLB_DEVSP0_B
3401 Side
Ring Side
J3-56 J3-92 J1-30 J1-38 J1-27 J4-85 J4-87 J4-89 J4-91 J1-97 J1-95 J1-93 J1-91 J1-98 J1-96 J4-86 J4-84 J4-80 J4-82 J4-88 J4-77 J4-78 J1-73
MMCCMB3401UM/D User's Manual
Table Cross Reference: 3401 FPGA, MAPI Connectors
3401 Device
FPGA Device 3401 Side
MAPI Connectors Default Signal
FPGA_DATA13 FPGA_DATA14 FPGA_DATA15 FPGA_DATA16 FPGA_DATA17 FPGA_DATA18 FPGA_DATA19 FPGA_DATA20 FPGA_DATA21 FPGA_DATA22 FPGA_DATA23 FPGA_DATA24 FPGA_DATA25 FPGA_DATA26 FPGA_DATA27 FPGA_DATA28 FPGA_DATA29 FPGA_DATA31 FPGA_DATA30 TC_TRISTATE TC_MUX_MODE TC_IN TC_OUT
Signal
mlb_data13 mlb_data14 mlb_data15 mlb_data16 mlb_data17 mlb_data18 mlb_data19 mlb_data20 mlb_data21 mlb_data22 mlb_data23 mlb_data24 mlb_data25 mlb_data26 mlb_data27 mlb_data28 mlb_data29 mlb_data31 mlb_data30 TC_TRISTATE TC_MUX_MODE TC_IN TC_OUT MLB_TE_B MLB_PSTAT4 MLB_PSTAT2 MLB_PSTAT0 mlb_vec2 mlb_fint_b mlb_int_b J_TDI J_TCLK JD_OFF_BUS_B J_TDO RESINOUT18 RESINOUT16 ITC_IRQ_B58 ITC_IRQ_B50 ITC_IRQ_B46
Ring Side
J4-17 J4-20 J4-19 J4-22 J4-21 J4-24 J4-23 J4-26 J4-25 J4-30 J4-29 J4-32 J4-31 J4-34 J4-33 J4-36 J4-35 J4-37 J4-38 J3-92 J3-34 J3-30 J3-29 J3-57 J3-70 J3-71 J3-67 J1-83 J1-62 J1-79 J3-82 J3-85 J2-77 J3-80 J2-71 J2-25 J1-47 J1-37 J1-33
AM20
MLB_TE_B MLB_PSTAT4 MLB_PSTAT2 MLB_PSTAT0
AN16
AP16
MAPI_VEC2 MAPI_FINT_B FPGA_INT_B J_TDI J_TCLK JD_OFF_BUS_B J_TDO RESINOUT18 RESINOUT16 ITC_IRQ_B58 ITC_IRQ_B50 ITC_IRQ_B46
MMCCMB3401UM/D User's Manual
Cross Reference Tables
Table Cross Reference: 3401 FPGA, MAPI Connectors (Continued)
3401 Device
FPGA Device 3401 Side
AP22 AM22 AM24 AL16 AM17
MAPI Connectors Default Signal
ITC_IRQ_B40 MAPI_TSCD_B MAPI_TSCA_B MLB_PSTAT1 MAPI_RESET_B MAPI_IPEND_B MAPI_AVEC_B MAPI_VEC3 MAPI_VEC0 J_TMS J_TRST_B
Signal
ITC_IRQ_B40 mlb_tscd_b mlb_tsca_b MLB_PSTAT1 mlb_reset_b mlb_ipend_b mlb_avec_b mlb_vec3 mlb_vec0 J_TMS J_TRST_B mlb_fint_raw_b MIM_TEA_B RESINOUT15 ITC_IRQ_B56 ITC_IRQ_B54 ITC_IRQ_B48 ITC_IRQ_B36 ITC_IRQ_B31 mlb_rw_b mlb_tc1 mlb_tc0 mlb_idly4_b MLB_PSTAT3 MLB_BIGEND_B M_POR mlb_vec6 mlb_vec1 JD_MCU_DE_B TC_TEST_EN JD_DEBUG_B MIM_TA_B RESINOUT17 ITC_IRQ_B63 ITC_IRQ_B52 ITC_IRQ_B38 ITC_IRQ_B27 mlb_treq_b mlb_alt_addr0 mlb_tc2
Ring Side
AN22 AL22 AR25 AM16 AN17
J2-76 J3-47 J3-45 J3-69 J3-77 J1-78 J1-80 J1-84 J1-81 J3-83 J3-87 J1-70 J2-75 J2-23 J1-45 J1-43 J1-35 J2-65 J1-57 J4-81 J3-64 J3-62 J3-26 J3-73 J3-40 J3-32 J1-87 J1-82 J3-94 J3-56 J3-84 J2-73 J2-27 J1-53 J1-39 J2-74 J1-36 J4-79 J3-39 J3-66
MAPI_FINT_RAW_B MIM_TEA_B RESINOUT15 ITC_IRQ_B56 ITC_IRQ_B54 ITC_IRQ_B48 ITC_IRQ_B36 ITC_IRQ_B31
AM23 AR24 AN25
AL23 AN24 AM25
FPGA_RW_B MAPI_TC1 MAPI_TC0 MAPI_IDLY4_B MLB_PSTAT3 MLB_BIGEND_B M_POR MAPI_VEC6 MAPI_VEC1 JD_MCU_DE_B TC_TEST_EN
AP14 AR16
AR14 AL17
AP19
JD_DEBUG_B MIM_TA_B RESINOUT17 ITC_IRQ_B63 ITC_IRQ_B52 ITC_IRQ_B38 ITC_IRQ_B27
AP23
AN23
FPGA_TREQ_B FPGA_ALT_ADDR0 MAPI_TC2
MMCCMB3401UM/D User's Manual
Table Cross Reference: 3401 FPGA, MAPI Connectors (Continued)
3401 Device
FPGA Device 3401 Side
AP25 AP15
MAPI Connectors Default Signal
FPGA_TSIZ1 MAPI_BG_B MAPI_IFETCH_B MAPI_VEC4 MAPI_INT_RAW_B ITC_IRQ_B62 ITC_IRQ_B42 ITC_IRQ_B34 ITC_IRQ_B32 ITC_IRQ_B25
Signal
mlb_tsiz1 mlb_bg_b mlb_ifetch_b mlb_vec4 mlb_int_raw_b ITC_IRQ_B62 ITC_IRQ_B42 ITC_IRQ_B34 ITC_IRQ_B32 ITC_IRQ_B25 mlb_tbusy_b mlb_burst_b mlb_alt-addr1 mlb_tsiz0 mlb_vec5 ITC_IRQ_B60 ITC_IRQ_B44 ITC_IRQ_B29 UARTA_INT10 MLB_WAKEUP_B MLB_LPMD1 MLB_LPMD0 mlb_abort_b UARTB_INT11 mlb_ci_b mlb_br_b mlb_addr2 mlb_addr1 mlb_addr0 mlb_addr6 mlb_addr5 mlb_addr4 mlb_addr3 MLB_CLKOUT RESINOUT14 RESINOUT13 mlb_addr11 mlb_addr10 mlb_addr9 mlb_addr8
Ring Side
AL32 AL24 AR15
J3-88 J3-51 J3-28 J1-85 J1-72 J1-51 J2-78 J2-72 J1-31 J1-32 J3-72 J3-46 J3-41 J3-86 J1-86 J1-49 J2-80 J1-55 J1-30 J3-38 J3-50 J3-52 J3-48 J1-38 J3-27 J3-53 J4-44 J4-41 J4-42 J4-48 J4-45 J4-46 J4-43 J4-95 J2-21 J2-70 J4-51 J4-52 J4-49 J4-50
AL25 AL15
AR26 AM15
MAPI_TBUSY_B MAPI_BURST_B FPGA_ALT_ADDR1 FPGA_TSIZ0 MAPI_VEC5 ITC_IRQ_B60 ITC_IRQ_B44 ITC_IRQ_B29 UARTA_INT10
AL21 AL19 AP20 AM33 AK33 AL35 AL34 AJ34 AJ33 AK34 AH31
MLB_WAKEUP_B MLB_LPMD1 MLB_LPMD0 MAPI_ABORT_B UARTB_INT11 FPGA_CI_B MAPI_BR_B FPGA_ADDR2 FPGA_ADDR1 FPGA_ADDR0 FPGA_ADDR6 FPGA_ADDR5 FPGA_ADDR4 FPGA_ADDR3 MLB_CLKOUT RESINOUT14 RESINOUT13
AH34 AH33 AG31 AH32
FPGA_ADDR11 FPGA_ADDR10 FPGA_ADDR9 FPGA_ADDR8
MMCCMB3401UM/D User's Manual
Cross Reference Tables
Table Cross Reference: 3401 FPGA, MAPI Connectors (Continued)
3401 Device
FPGA Device 3401 Side
MAPI Connectors Default Signal
FPGA_ADDR7 RESINOUT12 RESINOUT11 RESINOUT10 RESINOUT9
Signal
mlb_addr7 RESINOUT12 RESINOUT11 RESINOUT10 RESINOUT9 mlb_addr14 mlb_addr13 mlb_addr12 RESINOUT8 mlb_addr17 mlb_addr16 mlb_addr15 RESINOUT7 mlb_addr21 mlb_addr20 mlb_addr19 mlb_addr18 mlb_addr24 mlb_addr23 mlb_addr22 mlb_addr27 mlb_add[26 mlb_addr25 ITC_IRQ_B7 mlb_addr28 mlb_addr29 mlb_addr30 mlb_addr31 mlb_data0 mlb_data1 mlb_data2 mlb_data3 mlb_data4 ITC_IRQ_B5 mlb_data5 mlb_data6 mlb_data7 ITC_IRQ_B1 ITC_IRQ_B3 mlb_data8
Ring Side
AJ35
J4-47 J2-68 J2-66 J2-28 J2-26 J4-56 J4-53 J4-54 J2-24 J4-59 J4-60 J4-55 J2-22 J4-63 J4-64 J4-61 J4-62 J4-68 J4-65 J4-66 J4-69 J4-70 J4-67 J1-67 J4-72 J4-71 J4-74 J4-73 J4-4 J4-3 J4-6 J4-5 J4-8 J1-65 J4-7 J4-10 J4-9 J1-61 J1-63 J4-12
AG33 AG32 AH35 AF33 AF31 AG34 AM35 AE31 AF35 AF34 AA35 AA32 AA31
FPGA_ADDR14 FPGA_ADDR13 FPGA_ADDR12 RESINOUT8 FPGA_ADDR17 FPGA_ADDR16 FPGA_ADDR15 RESINOUT7 FPGA_ADDR21 FPGA_ADDR20 FPGA_ADDR19 FPGA_ADDR18 FPGA_ADDR24 FPGA_ADDR23 FPGA_ADDR22 FPGA_ADDR27 FPGA_ADDR26 FPGA_ADDR25 ITC_IRQ_B7 FPGA_ADDR28 FPGA_ADDR29 FPGA_ADDR30 FPGA_ADDR31 FPGA_DATA0 FPGA_DATA1 FPGA_DATA2 FPGA_DATA3 FPGA_DATA4 ITC_IRQ_B5 FPGA_DATA5 FPGA_DATA6 FPGA_DATA7 ITC_IRQ_B1 ITC_IRQ_B3
FPGA_DATA8
MMCCMB3401UM/D User's Manual
Table Cross Reference: 3401 FPGA, MAPI Connectors (Continued)
3401 Device
FPGA Device 3401 Side
MAPI Connectors Default Signal
FPGA_DATA9 FPGA_DATA10 FPGA_DATA11 FPGA_DATA12 BIG_TEST FPGA_CS_B0 FPGA_CS_B1 FPGA_CS_B2 FPGA_CS_B3 FPGA_CS_B4 FPGA_CS_B5 FPGA_CS_B6 FPGA_CS_B7 FPGA_CS_B8 FPGA_CS_B9 FPGA_EB_B0 FPGA_EB_B1 FPGA_EB_B2 FPGA_EB_B3 FPGA_OE_B MAPI_TA_B MAPI_TEA_B MLB_DEVSP0_B
Signal
mlb_data9 mlb_data10 mlb_data11 mlb_data12
Ring Side
AP27 AN27 AM27 AL27 AN11
J4-11 J4-14 J4-13 J4-18 J1-27 J4-85 J4-87 J4-89 J4-91 J1-97 J1-95 J1-93 J1-91 J1-98 J1-96 J4-86 J4-84 J4-80 J4-82 J4-88 J4-77 J4-78 J1-73
MMCCMB3401UM/D User's Manual
Cross Reference Tables
Table Cross Reference: MAPI FPGA, 3401
MAPI Connectors Default Signal
BIG_TEST FPGA_ADDR0 FPGA_ADDR1 FPGA_ADDR2 FPGA_ADDR3 FPGA_ADDR4 FPGA_ADDR5 FPGA_ADDR6 FPGA_ADDR7 FPGA_ADDR8 FPGA_ADDR9 FPGA_ADDR10 FPGA_ADDR11 FPGA_ADDR12 FPGA_ADDR13 FPGA_ADDR14 FPGA_ADDR15 FPGA_ADDR16 FPGA_ADDR17 FPGA_ADDR18 FPGA_ADDR19 FPGA_ADDR20 FPGA_ADDR21 FPGA_ADDR22 FPGA_ADDR23 FPGA_ADDR24 FPGA_ADDR25 FPGA_ADDR26 FPGA_ADDR28 FPGA_ADDR27 FPGA_ADDR29 FPGA_ADDR30 FPGA_ADDR31 FPGA_ALT_ADDR0 FPGA_ALT_ADDR1 FPGA_CI_B FPGA_CS_B0 FPGA_CS_B1 FPGA_CS_B2
FPGA Device Ring Side
AL34 AL35 AK33 AH31 AK34 AJ33 AJ34 AJ35 AH32 AG31 AH33 AH34 AH35 AG32 AG33 AG34 AF31 AF33 AF34 AF35 AE31 AM35 AA31 AA32 AA35
3401 Device Signal
mlb_addr0 mlb_addr1 mlb_addr2 mlb_addr3 mlb_addr4 mlb_addr5 mlb_addr6 mlb_addr7 mlb_addr8 mlb_addr9 mlb_addr10 mlb_addr11 mlb_addr12 mlb_addr13 mlb_addr14 mlb_addr15 mlb_addr16 mlb_addr17 mlb_addr18 mlb_addr19 mlb_addr20 mlb_addr21 mlb_addr22 mlb_addr23 mlb_addr24 mlb_addr25 mlb_add[26 mlb_addr28 mlb_addr27 mlb_addr29 mlb_addr30 mlb_addr31 mlb_alt_addr0 mlb_alt-addr1 mlb_ci_b
J1-27 J4-42 J4-41 J4-44 J4-43 J4-46 J4-45 J4-48 J4-47 J4-50 J4-49 J4-52 J4-51 J4-54 J4-53 J4-56 J4-55 J4-60 J4-59 J4-62 J4-61 J4-64 J4-63 J4-66 J4-65 J4-68 J4-67 J4-70 J4-72 J4-69 J4-71 J4-74 J4-73 J3-39 J3-41 J3-27 J4-85 J4-87 J4-89
3401 Side
MMCCMB3401UM/D User's Manual
Table Cross Reference: MAPI FPGA, 3401 (Continued)
MAPI Connectors Default Signal
FPGA_CS_B3 FPGA_CS_B4 FPGA_CS_B5 FPGA_CS_B6 FPGA_CS_B7 FPGA_CS_B8 FPGA_CS_B9 FPGA_DATA0 FPGA_DATA1 FPGA_DATA2 FPGA_DATA3 FPGA_DATA4 FPGA_DATA5 FPGA_DATA6 FPGA_DATA7 FPGA_DATA8 FPGA_DATA9 FPGA_DATA10 FPGA_DATA11 FPGA_DATA12 FPGA_DATA13 FPGA_DATA14 FPGA_DATA15 FPGA_DATA16 FPGA_DATA17 FPGA_DATA18 FPGA_DATA19 FPGA_DATA20 FPGA_DATA21 FPGA_DATA22 FPGA_DATA23 FPGA_DATA24 FPGA_DATA25 FPGA_DATA26 FPGA_DATA27 FPGA_DATA28 FPGA_DATA29 FPGA_DATA30 FPGA_DATA31 FPGA_EB_B0
FPGA Device Ring Side
AP27 AN27 AM27 AL27
3401 Device Signal
J4-91 J1-97 J1-95 J1-93 J1-91 J1-98 J1-96 J4-4 J4-3 J4-6 J4-5 J4-8 J4-7 J4-10 J4-9 J4-12 J4-11 J4-14 J4-13 J4-18 J4-17 J4-20 J4-19 J4-22 J4-21 J4-24 J4-23 J4-26 J4-25 J4-30 J4-29 J4-32 J4-31 J4-34 J4-33 J4-36 J4-35 J4-38 J4-37 J4-86
3401 Side
mlb_data0 mlb_data1 mlb_data2 mlb_data3 mlb_data4 mlb_data5 mlb_data6 mlb_data7 mlb_data8 mlb_data9 mlb_data10 mlb_data11 mlb_data12 mlb_data13 mlb_data14 mlb_data15 mlb_data16 mlb_data17 mlb_data18 mlb_data19 mlb_data20 mlb_data21 mlb_data22 mlb_data23 mlb_data24 mlb_data25 mlb_data26 mlb_data27 mlb_data28 mlb_data29 mlb_data30 mlb_data31
MMCCMB3401UM/D User's Manual
Cross Reference Tables
Table Cross Reference: MAPI FPGA, 3401 (Continued)
MAPI Connectors Default Signal
FPGA_EB_B1 FPGA_EB_B2 FPGA_EB_B3 FPGA_INT_B FPGA_OE_B FPGA_RW_B FPGA_TREQ_B FPGA_TSIZ0 FPGA_TSIZ1 ITC_IRQ_B1 ITC_IRQ_B3 ITC_IRQ_B5 ITC_IRQ_B7 ITC_IRQ_B25 ITC_IRQ_B27 ITC_IRQ_B29 ITC_IRQ_B31 ITC_IRQ_B32 ITC_IRQ_B34 ITC_IRQ_B36 ITC_IRQ_B38 ITC_IRQ_B40 ITC_IRQ_B42 ITC_IRQ_B44 ITC_IRQ_B46 ITC_IRQ_B48 ITC_IRQ_B50 ITC_IRQ_B52 ITC_IRQ_B54 ITC_IRQ_B56 ITC_IRQ_B58 ITC_IRQ_B60 ITC_IRQ_B62 ITC_IRQ_B63 JD_DEBUG_B JD_MCU_DE_B JD_OFF_BUS_B J_TCLK J_TDI J_TDO
FPGA Device Ring Side
3401 Device Signal
J4-84 J4-80 J4-82 J1-79 J4-88 J4-81 J4-79 J3-86 J3-88 J1-61 J1-63 J1-65 J1-67 J1-32 J1-36 J1-55 J1-57 J1-31 J2-72 J2-65 J2-74 J2-76 J2-78 J2-80 J1-33 J1-35 J1-37 J1-39 J1-43 J1-45 J1-47 J1-49 J1-51 J1-53 J3-84 J3-94 J2-77 J3-85 J3-82 J3-80
3401 Side
mlb_int_b mlb_rw_b mlb_treq_b mlb_tsiz0 mlb_tsiz1 ITC_IRQ_B1 ITC_IRQ_B3 ITC_IRQ_B5 ITC_IRQ_B7 ITC_IRQ_B25 ITC_IRQ_B27 ITC_IRQ_B29 ITC_IRQ_B31 ITC_IRQ_B32 ITC_IRQ_B34 ITC_IRQ_B36 ITC_IRQ_B38 ITC_IRQ_B40 ITC_IRQ_B42 ITC_IRQ_B44 ITC_IRQ_B46 ITC_IRQ_B48 ITC_IRQ_B50 ITC_IRQ_B52 ITC_IRQ_B54 ITC_IRQ_B56 ITC_IRQ_B58 ITC_IRQ_B60 ITC_IRQ_B62 ITC_IRQ_B63
AP19
JD_DEBUG_B JD_MCU_DE_B JD_OFF_BUS_B J_TCLK J_TDI J_TDO
MMCCMB3401UM/D User's Manual
Table Cross Reference: MAPI FPGA, 3401 (Continued)
MAPI Connectors Default Signal
J_TMS J_TRST_B MAPI_ABORT_B MAPI_AVEC_B MAPI_BG_B MAPI_BR_B MAPI_BURST_B MAPI_FINT_B MAPI_FINT_RAW_B MAPI_IDLY4_B MAPI_IFETCH_B MAPI_INT_RAW_B MAPI_IPEND_B MAPI_RESET_B MAPI_TA_B MAPI_TBUSY_B MAPI_TC0 MAPI_TC1 MAPI_TC2 MAPI_TEA_B MAPI_TSCA_B MAPI_TSCD_B MAPI_VEC0 MAPI_VEC1 MAPI_VEC2 MAPI_VEC3 MAPI_VEC4 MAPI_VEC5 MAPI_VEC6 MIM_TA_B MIM_TEA_B MLB_BIGEND_B MLB_CLKOUT MLB_DEVSP0_B MLB_LPMD0 MLB_LPMD1 MLB_PSTAT0 MLB_PSTAT1 MLB_PSTAT2 MLB_PSTAT3
FPGA Device Ring Side 3401 Side
3401 Device Signal
J_TMS J_TRST_B
J3-83 J3-87 J3-48 J1-80 J3-51 J3-53 J3-46 J1-62 J1-70 J3-26 J3-28 J1-72 J1-78 J3-77 J4-77 J3-72 J3-62 J3-64 J3-66 J4-78 J3-45 J3-47 J1-81 J1-82 J1-83 J1-84 J1-85 J1-86 J1-87 J2-73 J2-75 J3-40 J4-95 J1-73 J3-52 J3-50 J3-67 J3-69 J3-71 J3-73
AL32 AM33 AR26 AM25 AL24 AR25 AN24 AL23 AN23 AL22 AN22 AN17 AL17 AP16 AM16 AR15 AM15 AR14 AN11 AP20 AL19
AL25 AN25 AP25 AM24 AR24 AM23 AP23 AM22 AP22 AM17 AR16 AN16 AL16 AP15 AL15 AP14
mlb_abort_b mlb_avec_b mlb_bg_b mlb_br_b mlb_burst_b mlb_fint_b mlb_fint_raw_b mlb_idly4_b mlb_ifetch_b mlb_int_raw_b mlb_ipend_b mlb_reset_b mlb_tbusy_b mlb_tc0 mlb_tc1 mlb_tc2 mlb_tsca_b mlb_tscd_b mlb_vec0 mlb_vec1 mlb_vec2 mlb_vec3 mlb_vec4 mlb_vec5 mlb_vec6 MIM_TA_B MIM_TEA_B MLB_BIGEND_B MLB_CLKOUT MLB_LPMD0 MLB_LPMD1 MLB_PSTAT0 MLB_PSTAT1 MLB_PSTAT2 MLB_PSTAT3
MMCCMB3401UM/D User's Manual
Cross Reference Tables
Table Cross Reference: MAPI FPGA, 3401 (Continued)
MAPI Connectors Default Signal
MLB_PSTAT4 MLB_TE_B MLB_WAKEUP_B M_POR RESINOUT7 RESINOUT8 RESINOUT9 RESINOUT10 RESINOUT11 RESINOUT12 RESINOUT13 RESINOUT14 RESINOUT15 RESINOUT16 RESINOUT17 RESINOUT18 TC_IN TC_MUX_MODE TC_OUT TC_TEST_EN TC_TRISTATE UARTA_INT10 UARTB_INT11
FPGA Device Ring Side
AM20 AL21
3401 Device Signal
MLB_PSTAT4 MLB_TE_B MLB_WAKEUP_B M_POR RESINOUT7 RESINOUT8 RESINOUT9 RESINOUT10 RESINOUT11 RESINOUT12 RESINOUT13 RESINOUT14 RESINOUT15 RESINOUT16 RESINOUT17 RESINOUT18 TC_IN TC_MUX_MODE TC_OUT TC_TEST_EN TC_TRISTATE UARTA_INT10 UARTB_INT11
J3-70 J3-57 J3-38 J3-32 J2-22 J2-24 J2-26 J2-28 J2-66 J2-68 J2-70 J2-21 J2-23 J2-25 J2-27 J2-71 J3-30 J3-34 J3-29 J3-56 J3-92 J1-30 J1-38
3401 Side
MMCCMB3401UM/D User's Manual
Table Cross Reference: MAPI, FPGA, 3401
MAPI Connectors
J1-27 J1-30 J1-31 J1-32 J1-33 J1-35 J1-36 J1-37 J1-38 J1-39 J1-43 J1-45 J1-47 J1-49 J1-51 J1-53 J1-55 J1-57 J1-61 J1-62 J1-63 J1-65 J1-67 J1-70 J1-72 J1-73 J1-78 J1-79 J1-80 J1-81 J1-82 J1-83 J1-84 J1-85 J1-86 J1-87 J1-91 J1-93 J1-95
FPGA Device Ring Side
3401 Device Signal
UARTA_INT10 ITC_IRQ_B32 ITC_IRQ_B25 ITC_IRQ_B46 ITC_IRQ_B48 ITC_IRQ_B27 ITC_IRQ_B50 UARTB_INT11 ITC_IRQ_B52 ITC_IRQ_B54 ITC_IRQ_B56 ITC_IRQ_B58 ITC_IRQ_B60 ITC_IRQ_B62 ITC_IRQ_B63 ITC_IRQ_B29 ITC_IRQ_B31 ITC_IRQ_B1
Default Signal
BIG_TEST UARTA_INT10 ITC_IRQ_B32 ITC_IRQ_B25 ITC_IRQ_B46 ITC_IRQ_B48 ITC_IRQ_B27 ITC_IRQ_B50 UARTB_INT11 ITC_IRQ_B52 ITC_IRQ_B54 ITC_IRQ_B56 ITC_IRQ_B58 ITC_IRQ_B60 ITC_IRQ_B62 ITC_IRQ_B63 ITC_IRQ_B29 ITC_IRQ_B31 ITC_IRQ_B1 MAPI_FINT_B ITC_IRQ_B3 ITC_IRQ_B5 ITC_IRQ_B7 MAPI_FINT_RAW_B MAPI_INT_RAW_B MLB_DEVSP0_B MAPI_IPEND_B FPGA_INT_B MAPI_AVEC_B MAPI_VEC0 MAPI_VEC1 MAPI_VEC2 MAPI_VEC3 MAPI_VEC4 MAPI_VEC5 MAPI_VEC6 FPGA_CS_B7 FPGA_CS_B6 FPGA_CS_B5
3401 Side
mlb_fint_b ITC_IRQ_B3 ITC_IRQ_B5 ITC_IRQ_B7
AN11 AR25 AN17 AL17 AP16 AM16 AR15 AM15 AR14 AN27 AP27
AM24 AM17 AR16 AN16 AL16 AP15 AL15 AP14
mlb_fint_raw_b mlb_int_raw_b mlb_ipend_b mlb_int_b mlb_avec_b mlb_vec0 mlb_vec1 mlb_vec2 mlb_vec3 mlb_vec4 mlb_vec5 mlb_vec6
MMCCMB3401UM/D User's Manual
Cross Reference Tables
Table Cross Reference: MAPI, FPGA, 3401 (Continued)
MAPI Connectors
J1-96 J1-97 J1-98 J2-21 J2-22 J2-23 J2-24 J2-25 J2-26 J2-27 J2-28 J2-65 J2-66 J2-68 J2-70 J2-71 J2-72 J2-73 J2-74 J2-75 J2-76 J2-77 J2-78 J2-80 J3-26 J3-27 J3-28 J3-29 J3-30 J3-32 J3-34 J3-38 J3-39 J3-40 J3-41 J3-45 J3-46 J3-47 J3-48 J3-50
FPGA Device Ring Side
AL27 AM27
3401 Device Signal
Default Signal
FPGA_CS_B9 FPGA_CS_B4 FPGA_CS_B8 RESINOUT14 RESINOUT7 RESINOUT15 RESINOUT8 RESINOUT16 RESINOUT9 RESINOUT17 RESINOUT10 ITC_IRQ_B36 RESINOUT11 RESINOUT12 RESINOUT13 RESINOUT18 ITC_IRQ_B34 MIM_TA_B ITC_IRQ_B38 MIM_TEA_B ITC_IRQ_B40 JD_OFF_BUS_B ITC_IRQ_B42 ITC_IRQ_B44 MAPI_IDLY4_B FPGA_CI_B MAPI_IFETCH_B TC_OUT TC_IN M_POR TC_MUX_MODE MLB_WAKEUP_B FPGA_ALT_ADDR0 MLB_BIGEND_B FPGA_ALT_ADDR1 MAPI_TSCA_B MAPI_BURST_B MAPI_TSCD_B MAPI_ABORT_B MLB_LPMD1
3401 Side
RESINOUT14 RESINOUT7 RESINOUT15 RESINOUT8 RESINOUT16 RESINOUT9 RESINOUT17 RESINOUT10 ITC_IRQ_B36 RESINOUT11 RESINOUT12 RESINOUT13 RESINOUT18 ITC_IRQ_B34 MIM_TA_B ITC_IRQ_B38 MIM_TEA_B ITC_IRQ_B40 JD_OFF_BUS_B ITC_IRQ_B42 ITC_IRQ_B44 AM25 AL24 AN25 AP25 mlb_idly4_b mlb_ci_b mlb_ifetch_b TC_OUT TC_IN M_POR TC_MUX_MODE AL21 AL22 AR26 AN22 AL19 AM22 AL25 AP22 MLB_WAKEUP_B mlb_alt_addr0 MLB_BIGEND_B mlb_alt-addr1 mlb_tsca_b mlb_burst_b mlb_tscd_b mlb_abort_b MLB_LPMD1
MMCCMB3401UM/D User's Manual
Table Cross Reference: MAPI, FPGA, 3401 (Continued)
MAPI Connectors
J3-51 J3-52 J3-53 J3-56 J3-57 J3-62 J3-64 J3-66 J3-67 J3-69 J3-70 J3-71 J3-72 J3-73 J3-77 J3-80 J3-82 J3-83 J3-84 J3-85 J3-86 J3-87 J3-88 J3-92 J3-94 J4-3 J4-4 J4-5 J4-6 J4-7 J4-8 J4-9 J4-10 J4-11 J4-12 J4-13 J4-14 J4-17 J4-18 J4-19
FPGA Device Ring Side
AL32 AP20 AM33 AM20 AN24 AL23 AN23 AR24 AM23 AP23
3401 Device Signal
mlb_bg_b MLB_LPMD0 mlb_br_b TC_TEST_EN MLB_TE_B mlb_tc0 mlb_tc1 mlb_tc2 MLB_PSTAT0 MLB_PSTAT1 MLB_PSTAT4 MLB_PSTAT2
Default Signal
MAPI_BG_B MLB_LPMD0 MAPI_BR_B TC_TEST_EN MLB_TE_B MAPI_TC0 MAPI_TC1 MAPI_TC2 MLB_PSTAT0 MLB_PSTAT1 MLB_PSTAT4 MLB_PSTAT2 MAPI_TBUSY_B MLB_PSTAT3 MAPI_RESET_B J_TDO J_TDI J_TMS JD_DEBUG_B J_TCLK FPGA_TSIZ0 J_TRST_B FPGA_TSIZ1 TC_TRISTATE JD_MCU_DE_B FPGA_DATA1 FPGA_DATA0 FPGA_DATA3 FPGA_DATA2 FPGA_DATA5 FPGA_DATA4 FPGA_DATA7 FPGA_DATA6 FPGA_DATA9 FPGA_DATA8 FPGA_DATA11 FPGA_DATA10 FPGA_DATA13 FPGA_DATA12 FPGA_DATA15
3401 Side
mlb_tbusy_b MLB_PSTAT3 mlb_reset_b J_TDO J_TDI J_TMS
AP19
JD_DEBUG_B J_TCLK mlb_tsiz0 J_TRST_B mlb_tsiz1 TC_TRISTATE JD_MCU_DE_B
mlb_data1 mlb_data0 mlb_data3 mlb_data2 mlb_data5 mlb_data4 mlb_data7 mlb_data6 mlb_data9 mlb_data8 mlb_data11 mlb_data10 mlb_data13 mlb_data12 mlb_data15
MMCCMB3401UM/D User's Manual
Cross Reference Tables
Table Cross Reference: MAPI, FPGA, 3401 (Continued)
MAPI Connectors
J4-20 J4-21 J4-22 J4-23 J4-24 J4-25 J4-26 J4-29 J4-30 J4-31 J4-32 J4-33 J4-34 J4-35 J4-36 J4-37 J4-38 J4-41 J4-42 J4-43 J4-44 J4-45 J4-46 J4-47 J4-48 J4-49 J4-50 J4-51 J4-52 J4-53 J4-54 J4-55 J4-56 J4-59 J4-60 J4-61 J4-62 J4-63 J4-64 J4-65
FPGA Device Ring Side
AL35 AL34 AH31 AK33 AJ33 AK34 AJ35 AJ34 AG31 AH32 AH34 AH33 AG32 AH35 AG34 AG33 AF33 AF31 AF35 AF34 AM35 AE31 AA32
3401 Device Signal
mlb_data14 mlb_data17 mlb_data16 mlb_data19 mlb_data18 mlb_data21 mlb_data20 mlb_data23 mlb_data22 mlb_data25 mlb_data24 mlb_data27 mlb_data26 mlb_data29 mlb_data28 mlb_data31 mlb_data30 mlb_addr1 mlb_addr0 mlb_addr3 mlb_addr2 mlb_addr5 mlb_addr4 mlb_addr7 mlb_addr6 mlb_addr9 mlb_addr8 mlb_addr11 mlb_addr10 mlb_addr13 mlb_addr12 mlb_addr15 mlb_addr14 mlb_addr17 mlb_addr16 mlb_addr19 mlb_addr18 mlb_addr21 mlb_addr20 mlb_addr23
Default Signal
FPGA_DATA14 FPGA_DATA17 FPGA_DATA16 FPGA_DATA19 FPGA_DATA18 FPGA_DATA21 FPGA_DATA20 FPGA_DATA23 FPGA_DATA22 FPGA_DATA25 FPGA_DATA24 FPGA_DATA27 FPGA_DATA26 FPGA_DATA29 FPGA_DATA28 FPGA_DATA31 FPGA_DATA30 FPGA_ADDR1 FPGA_ADDR0 FPGA_ADDR3 FPGA_ADDR2 FPGA_ADDR5 FPGA_ADDR4 FPGA_ADDR7 FPGA_ADDR6 FPGA_ADDR9 FPGA_ADDR8 FPGA_ADDR11 FPGA_ADDR10 FPGA_ADDR13 FPGA_ADDR12 FPGA_ADDR15 FPGA_ADDR14 FPGA_ADDR17 FPGA_ADDR16 FPGA_ADDR19 FPGA_ADDR18 FPGA_ADDR21 FPGA_ADDR20 FPGA_ADDR23
3401 Side
MMCCMB3401UM/D User's Manual
Table Cross Reference: MAPI, FPGA, 3401 (Continued)
MAPI Connectors
J4-66 J4-67 J4-68 J4-69 J4-70 J4-71 J4-72 J4-73 J4-74 J4-77 J4-78 J4-79 J4-80 J4-81 J4-82 J4-84 J4-85 J4-86 J4-87 J4-88 J4-89 J4-91 J4-95
FPGA Device Ring Side
AA31 AA35
3401 Device Signal
mlb_addr22 mlb_addr25 mlb_addr24 mlb_addr27 mlb_add[26 mlb_addr29 mlb_addr28 mlb_addr31 mlb_addr30
Default Signal
FPGA_ADDR22 FPGA_ADDR25 FPGA_ADDR24 FPGA_ADDR27 FPGA_ADDR26 FPGA_ADDR29 FPGA_ADDR28 FPGA_ADDR31 FPGA_ADDR30 MAPI_TA_B MAPI_TEA_B FPGA_TREQ_B FPGA_EB_B2 FPGA_RW_B FPGA_EB_B3 FPGA_EB_B1 FPGA_CS_B0 FPGA_EB_B0 FPGA_CS_B1 FPGA_OE_B FPGA_CS_B2 FPGA_CS_B3 MLB_CLKOUT
3401 Side
mlb_treq_b mlb_rw_b
MLB_CLKOUT
MMCCMB3401UM/D User's Manual
Cross Reference Tables
Table Cross Reference:U2 FPGA Device Pins
AA31 AA32 AA35 AE31 AF31 AF33 AF34 AF35 AG31 AG32 AG33 AG34 AH31
Component
U3-P1 U3-P2 U3-P3 J4-66 J4-65 J4-68 U3-N2 U3-N3 U3-N4 U3-M1 U3-M2 U3-M3 U3-L1 U3-L2 U3-L3 U3-K1 U3-K2 U3-K3 U3-K4 U3-K5 U3-J1 J4-64 U3-J2 U3-J3 U3-J4 U3-H2 J4-60 J4-59 J4-62 J4-61 U3-H1 U3-H3 J4-49 J4-53 J4-56 J4-55 U3-N1 J4-43 U3-G2
AH32 AH33 AH34 AH35 AJ33 AJ34 AJ35 AK33 AK34 AL15 AL16 AL17 AL19 AL21 AL22 AL23 AL24 AL25 AL27 AL32 AL34 AL35 AM15 AM16 AM17 AM20 AM22 AM23 AM24 AM25 AM27 AM33 AM35 AN11 AN16 AN17 AN23 AN22
Component
J4-50 J4-52 J4-51 J4-54 U3-D5 J4-45 J4-48 J4-47 J4-44 J4-46 U3-E9 U3-B8 J1-82 J3-50 J3-38 J3-45 J3-64 J3-28 U3-E2 J1-96 J3-51 J4-42 J4-41 J1-86 J1-84 U3-B9 J3-57 U3-B3 U3-C2 U3-B6 J3-26 J1-98 J3-53 J4-63 J1-73 U3-A5 J1-81 J3-66 J3-47
AN24 AN25 AN27 AP14 AP15 AP16 AP19 AP20 AP22 AP23 AP25 AP27 AR14 AR15 AR16 AR24 AR25 AR26
Component
J3-62 U3-C4 J1-91 U3-C8 U3-D9 J1-83 J3-84 J3-52 U3-B2 U3-D3 U3-D6 J1-93 J3-40 J1-87 J1-85 U3-C9 U3-C3 J1-78 J3-46 U3-B12 U3-B7 J3-86 J1-95 J4-85 U3-D10 J1-70 J1-80 U3-G1 U3-D4 J4-82 J1-97 J4-88 J2-73 J1-72 J3-88 J4-80 J4-91 J4-77 J2-75
Component
U3-A6 J4-84 J4-89 U3-E1 J4-95 J1-79 J1-62 J3-27 U3-E6 J4-78 J4-86 J4-87 J3-72 U3-AE4 U3-AE3 U3-B5 J3-77 J4-37 J4-38 J1-27 U3-AE1 U3-AD4 U3-C1 J4-81 J4-35 J4-36 J4-34 U3-AD1 U3-AD2 U3-AD3 U3-AF1 J4-33 J4-31 J4-32 U3-AB3 U3-AC1 U3-AC2 U3-AC3 J4-29
MMCCMB3401UM/D User's Manual
Table Cross Reference:U2 FPGA Device Pins (Continued)
Component
J4-30 J4-26 U3-AA5 U3-AB2 U3-AB1 J4-21 J4-24 J4-23 J4-22 U3-AA4 U3-AA3 U3-AA2 U3-AA1 J4-20 J4-19 U3-Y5
Component
U3-Y4 U3-Y3 J4-14 J4-13 J4-18 J4-17 U3-Y2 U3-Y1 U3-W3 J4-10 J4-9 J4-12 J4-11 U3-W2 U3-W1 U3-V3
Component
U3-V2 J4-5 J4-8 J4-7 U3-V1 U3-U4 U3-U3 J3-48 J4-4 J4-3 J4-6 U3-F5 U3-D1 U3-E3 U3-D2 J3-39
Component
J3-41 J4-79 U3-U2 U3-U1 U3-T3 U3-T2 J4-71 J4-74 J4-73 U3-R1 U3-R2 U3-R3 J4-67 J4-70 J4-69 J4-72
MMCCMB3401UM/D User's Manual
Cross Reference Tables
MMCCMB3401UM/D User's Manual
Index
CMB3401 layout specifications components setting 13-22 computer system connections configuration 13-28 configuring development software connections, computer system connector information 49-70 connector asignments MAPI connectors P1/J1-P4/J4 connector assignments logic analyzer connector logic analyzer connector logic analyzer connector MAPI connectors P1/J1-P4/J4 logic analyzer connector logic analyzer connector logic analyzer connector NEXUS connector OnCE connector RS232 connectors connector signal descriptions logic analyzer connector logic analyzer connector logic analyzer connector MAPI connectors P1/J1-P4/J4 logic analyzer connector logic analyzer connector logic analyzer connector NEXUS connector OnCE connector controlling LEDs cross reference (MAPI pins) 87-91 cross reference (MAPI signals) 82-86 cross reference pins) cross reference pins) 77-81 cross reference signals) 72-76 cross reference tables 71-93
FLASH chip select header (W2) FSRAM chip select header (W1) logic analyzer connectors 66-69 eyelet connector eyelet connector
features FPGA device, reprogramming 41-45 FPGA device, using 41-47
source-level debugger
introduction 9-12
layout, CMB3401 logic analyzer connectors 62-69
MAPI connectors 49-58 memory access switch (S1) memory maps 24-28 FLASH enable header (W3) logic analyzer connectors 62-65 memory configuration switch (S3) SRAM enable header (W4)
NEXUS (GEPDIS) connector
TEA, eyelets OnCE connector operation 29-40
debugging embedded code 29-34 development software, configuring downloading FLASH memory 34-39
periodic interval timers 45-47 Picobug debug monitor commands MOTOROLA
MMCCMB3401UM/D User's Manual
Picobug monitor sample session 31-34 using 29-31 assignments logic analyzer connector logic analyzer connector logic analyzer connector MAPI connectors P1/J1-P4/J4 logic analyzer connector logic analyzer connector logic analyzer connector OnCE connector RS232 connectors J57, assignmentsNEXUS connector positions, components 13-16
user requirements using FPGA device 41-47 using PITs 45-47
wait state switch (S4)
reprogramming FPGA device 41-45 requirements, system/user RS232 connectors
self-test selftest, performing setting components 13-22 FLASH chip select header (W2) FSRAM chip select header (W1) memory access switch (S1) FLASH enable header (W3) memory configuration switch (S3) SRAM enable header (W4) software select switch (S2) wait state switch (S4) signal descriptions logic analyzer connector logic analyzer connector logic analyzer connector MAPI connectors P1/J1-P4/J4 logic analyzer connector logic analyzer connector logic analyzer connector NEXUS connector OnCE connector software select switch (S2) specifications SysDS loader restoring system software steps 34-39 system requirements system software, restoring
MOTOROLA
MMCCMB3401UM/D User's Manual
Revision History
Revision Number Original
Date 2000
Author DDOC
Summary Changes Original document.
MMCCMB3401UM/D User's Manual
MOTOROLA
Revision Hi
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