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CAUTION: ESD Protection

MOTOROLA 2

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and B are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity / Affirmative
CAUTION: ESD Protection
M·CORE development systems include open-construction printed circuit boards that contain static-sensitive components. These boards are subject to damage from electrostatic discharge (ESD). To prevent such damage, you must use static-safe work surfaces and grounding straps, as defined in ANSI / EOS / ESD S6.1 and ANSI / EOS / ESD S4.1. All handling of these boards must be in accordance with ANSI / EAI 625.
MOTOROLA 2
Contents
Section 1 Introduction
Section 2 Configuration
Section 3 Operation
Section 4 Using the FPGA Device
Section 5 Connector Information
Figures
Tables
CMB3401 Features
Section 1 Introduction
1.1 CMB3401 Features
The CMB3401 features: · · · · · · · · · · · · Motorola M340 resident MCU. 2 megabytes burst FLASH memory on the external interface module (EIM) bus. 2 megabytes FLASH memory on the M·CORE local bus (MLB). 2 megabytes fast SRAM on the EIM bus. 2 megabytes fast SRAM on the MLB. Altera EPF10K100A FPGA device, with a configuration chip. Four power regulators that provide four voltages: 5, 3.2, 3.0, and 1.8. Power supply that converts line power to 12-volt power. Power adapter cable for a bench supply. Two RS232 channels for serial communications. These channels use internal universal asynchronous receiver / transmitters (UARTs). A NEXUS port (also known as a GEPDIS port). A MAPI 400 connector interface ring, on the top and bottom of the CMB3401, for easy connection to other, compatible development boards.
Introduction
1.2 System and User Requirements
You need an IBM PC or compatible computer, running the Windows 95 or WindowsNT (version 4.0) operating system. The computer requires a Pentium (or equivalent) microprocessor, 16 megabytes of RAM, 50 megabytes of free hard-disk space, an SVGA color monitor, and an RS232 serial-communications port. To use the Picobug monitor, you also need Hyperterminal or a comparable terminal-emulation program. To get the most from your CMB3401, you should be an experienced C or M·CORE assembly programmer. The power supply that comes with your CMB3401 converts line power to the input power that the CMB3401 needs: 12 volts at a minimum of 0.5 amperes.
1.3 CMB3401 Layout
CMB3401 Layout
Switch S1 specifies memory-access mode, port size, and first address to be accessed. Switch S2 specifies the software module to be run upon reset. Switch S3 controls several aspects of memory configuration. Switch S4 specifies the number of wait states. Switch S5 is the master reset switch (resetting the entire board). Switch S6 resets only the resident M340 MCU (at location U3). Switch S7 reconfigures the FPGA device (at location U2).
J14 W1
J13 W2 DS1 W3
J23 J25 J28 W4 P4 W6 W7 S4 P3 J29
J30 J32
J33 P1
S5 P2 DS2 F1
DS4 DS6 DS3 DS5 J57 S6 J58 S7
Figure 1-1 MMCCMB3401 Computer and Memory Board Location F1 is for the CMB3401 fuse. LED DS1 indicates configuration completion for the FPGA device. LED DS2 confirms board power. LEDs DS3 through DS6 are status indicators. NOTE: Some CMB3401 locations are for factory use, so are not populated on your board. Although populated, headers W6 and W7 also are for factory use only: you should not remove the jumpers from these headers.
Introduction
Table 1-1 lists CMB3401 specifications. Table 1-1 MMCCMB3401 Controller and Memory Board Specifications
Characteristic
Specifications
HCMOS compatible
Configuring Board Components
Section 2 Configuration
This chapter explains how to configure your CMB3401, and how to hook it up to your computer system.
2.1 Configuring Board Components
Configuring your CMB3401 involves setting several components. Table 2-1 is a summary of these settings paragraphs 2.1.1 through 2.1.8 give additional information. Table 2-1 Component Configuration Setting
Component
EIM FSRAM Header, W1
Position
Effect
Selects chip-select 1. (So W2 must select chip select 0.) Factory setting.
Selects chip-select 0. (So W2 must select chip select 1.) Selects chip-select 1. (So W1 must select chip select 0.)
EIM FLASH Header, W2
Selects chip-select 0. (So W1 must select chip select 1.) Factory setting.
MLB FLASH Enable Header, W3
Enables MLB FLASH. Factory setting. Disables MLB FLASH
MLB SRAM Enable Header, W4
Disables MLB SRAM.
Enables MLB SRAM. Factory setting.
Configuration
Table 2-1 Component Configuration Setting
Component
Factory Headers, W6, W7
Position
Factory use only.
Effect
Factory setting. - Do not remove jumpers.
Memory Access Switch, S1
Software Select Switch, S2
Specifies Picobug to be run upon reset. (One of many possible S2 configurations.) Factory setting.
Configuring Board Components
Table 2-1 Component Configuration Setting
Component
Software Select Switch, S2 (continued)
Position
Effect
Specifies MLB user code to be run upon reset. (Another of many possible S2 configurations.)
Specifies EIM user code to be run upon reset. (Another of many possible S2 configurations.)
Memory Configuration Switch, S3
Configuration
Table 2-1 Component Configuration Setting
Component
Wait State Switch, S4
Position
Effect
Configures a wait state of 4 clock cycles. (One of many possible S4 configurations.) Factory setting.
Configures a wait state of 6 clock cycles. (Another of many possible S4 configurations.)
Configures a wait state of 10 clock cycles. Another of many possible S4 configurations.)
Master Reset Switch, S5
Push to reset all board components.
Reset Switch, S6
Push to reset only the resident MCU (location U3).
FPGA Configuration Switch, S7
Push to reconfigure the FPGA device (location U2)
Configuring Board Components
2.1.1 Setting the EIM FSRAM Chip Select Header (W1)
Jumper header W1 specifies the chip select for the 2 megabytes of FSRAM on the EIM bus. The diagram below shows the factory configuration: the jumper between pins 1 and 2 selects chip select 1.
CS1 1 CS0 3 FSRAM W1
To select instead chip select 0, reposition the W1 jumper between pins 2 and 3. NOTE: Jumper headers W1 and W2 must specify opposite chip selects. If W1 specifies chip select 1, as in the diagram above, W2 must specify chip select 0.
2.1.2 Setting the EIM FLASH Chip Select Header (W2)
Jumper header W2 specifies the chip select for the 2 megabytes of FLASH on the EIM bus. The diagram below shows the factory configuration: the jumper between pins 2 and 3 selects chip select 0.
FLASH
To select instead chip select 1, reposition the W2 jumper between pins 1 and 2. NOTE: Jumper headers W1 and W2 must specify opposite chip selects. If W2 specifies chip select 0, as in the diagram above, W2 must specify chip select 1.
Configuration
2.1.3 Setting the MLB FLASH Enable Header (W3)
Jumper header W3 enables or disables the 2 megabytes of FLASH memory on the MLB. The diagram below shows the factory configuration: the jumper between pins 1 and 2 enables FLASH.
MLB W3 DIS 3 FLASH ENB 1
To disable MLB FLASH, reposition the W3 jumper between pins 2 and 3.
2.1.4 Setting the MLB SRAM Enable Header (W4)
Jumper header W4 enables or disables the 2 megabytes of FSRAM on the MLB. The diagram below shows the factory configuration: the jumper between pins 2 and 3 enables FSRAM.
W4 MLB SRAM
To disable MLB FSRAM, reposition the W4 jumper between pins 1 and 2.
Configuring Board Components
2.1.5 Setting the Memory Access Switch (S1)
To configure a different port size or first address, set the other S1 subswitches per Table 2-2. Table 2-2 S1 Subswitch Settings
Configuration
2.1.6 Setting the Software Select Switch (S2)
Switch S2 specifies the software to be run upon a reset. The diagram below shows the factory configuration: the GSB0 and GSB1 subswitches OFF, and the GSB2 subswitch ON. This specifies Picobug.
ON 5 S2 4 GSB0 GSB1 GSB2 8 GSB3 1
To specify a different software module, reset the S2 subswitches per Table 2-3. Table 2-3 S2 Subswitch Settings
Software Module Built-In selftest SysDS Programmer ESL monitor Picobug Picobug Picobug MLB user code EIM user code GSB0 Subswitch ON OFF ON OFF ON OFF ON OFF GSB1 Subswitch ON ON OFF OFF ON ON OFF OFF GSB2 Subswitch ON ON ON ON OFF OFF OFF OFF
NOTES: 1. The S2 GSB3 subswitch is nonfunctional. 2. ESL monitor requires additional debug software on your computer for compatibility with your CMB3401 for a source of such software, see the product release guide. ESL monitor is compatible only with Big Endian mode, so subswitch S1-1 must be ON. 3. You also may use switch S2 for control of your own application software. Subsection 3.3 explains this additional role.
Configuring Board Components
2.1.7 Setting the MLB Memory Configuration Switch (S3)
For different configurations, set the S3 subswitches per Table 2-4. Table 2-4 S3 Subswitch Settings
Effect Set OFF
NOTE:
Configuration
2.1.8 Setting the Wait State Switch (S4)
Switch S4 specifies the length of wait states. The diagram below shows the factory configuration: all subswitches in the OFF position. This configures a wait state of 4 clock cycles.
To configure a different number of clock cycles, set the S4 subswitches per Table 2-5. Table 2-5 S4 Subswitch Settings
NOTE:
The switch S4 setting does not override a software wait-state setting.
Making Computer-System Connections
2.2 Making Computer-System Connections
When you have configured your CMB3401, you are ready to connect it to your computer system: 1. Make sure that power is disconnected. 2. If you will use RS232 communication with your host computer, connect an RS232 cable between CMB3401 connector J57 and the appropriate serial port of your computer. (Optional: If your application must have the higher UART addresses, use connector J58 for your RS232 communication.) 3. If you will use a OnCE-compatible emulator with your CMB3401, connect an appropriate 14-lead ribbon cable between CMB3401 connector J13 and your emulator. Then use an appropriate cable to connect your emulator to your host computer. 4. If you will use a NEXUS-compatible emulator with your CMB3401, connect an appropriate NEXUS cable between CMB3401 connector J23 and your emulator. Then use an appropriate cable to connect your emulator to your host computer. 5. Optional: If you use the CMB3401 with another, compatible development board, you must connect the boards via their MAPI rings. To do so, hold the CMB3401 directly above the other board. Turn the CMB3401 so that the right-triangle silk screen markings line up. Then press the CMB3401 down onto the other board. CMB3401 connectors J1 through J4, on the bottom of the board, must connect with the corresponding MAPI connectors P1 through P4, on the top of the other board. 6. Optional: You may use a logic analyzer with the CMB3401. If you do, connect appropriate cables to any of the logic analyzer connectors: · · J25, 28, or J32 with regard to the MLB. J29, J30, or J33 with regard to the EIM bus.
7. Optional: If you will reprogram the U2 FPGA device, connect the ByteBlaster cable to CMB3401 connector J14. Make sure that the red wire connects to pin 1 of the connector. Connect the other end of the ByteBlaster cable to a parallel port of your computer, per the instructions of your Altera documentation. (Section 4 gives additional information about reprogramming the U2 device.) 8. Connect the +12-volt power supply to CMB3401 connector J59 and to line power. LED DS2 lights to confirm that the CMB3401 is powered and converting input voltage. Should DS2 not light, you may need to replace the fuse at location F1. (Use a BUS GMA-1.5A fuse, or compatible.) 9. This completes system connections: you are ready to perform a selftest, per the instructions of subsection 2.3, below. You are ready to begin debugging or other development activities, per the instructions of Section 3.
Configuration
2.3 Performing the CMB3401 Selftest
Once you have configured your CMB3401, you can perform a selftest of its components. NOTE: If you open Hyperterminal, per the instructions of subsection 3.1.1, Hyperterminal displays the progress of the selftest. Should the selftest fail, Hyperterminal indicates the address at which the test failed.
1. Make sure that CMB3401 power is disconnected. The power LED DS2 should be out. 2. Set switch S2 for the built-in selftest: the GSB0, GSB1, and GSB2 subswitches all ON. 3. Apply power. LED DS2 comes on, and the CMB3401 automatically begins its selftest. 4. LEDs DS3 through DS6 (also designated GCB0 through GCB3, respectively) flash in rapid patterns during the test. Then the four LEDs flash each second or two, in unison, confirming that the CMB3401 has passed. 5. Flashing of fewer than four LEDs indicates a failure, per Table 2-6. In case of such a failure, you should contact Motorola customer support for assistance. Table 2-6 CMB3401 Selftest LED Patterns
DS3 (GCB0)
OFF OFF ON
DS4 (GCB1)
OFF OFF OFF
DS5 (GCB2)
ON OFF ON
DS6 (GCB3)
ON ON OFF
Meaning
EIM RAM failure. MLB RAM failure. MLB FLASH failure.
6. Turn off power. 7. Configure switch S2 for your next development activity before restoring power to the CMB3401.
2.4 Memory Maps
Table 2-7 shows the default memory map for the MBL bus. Table 2-8 lists the MLB FLASH sector boundaries. Table 2-9 shows the default memory map for the EIM bus. Table 2-10 lists the EIM FLASH sector boundaries. The shaded cells of Table 2-8 and Table 2-10 indicate the sectors that contain system software. NOTE: For either MLB SRAM or EIM SRAM, the first 64 kilobytes contain system software. You should confine your code or data to the remainder of the SRAM.
Memory Maps
Table 2-7 CMB3401 MLB Default Memory Map
Address Range
Contents
FLASH (2M)1 Reserved Fast SRAM (2M)2 Reserved
Related Signals
Chip select 0 (16M)
Chip select 1 (16M)
Chip select 2 (16M)
Chip select 3 (16M)
Chip select 4 (16MK)
Chip select 5 (1M)
Chip select 6 (1M)
Chip select 6 1M)
Configuration
Table 2-8 MLB FLASH Sector Boundaries
Sector (Block)
Range (S3-3 ON)
Range (S3-3 OFF)
Memory Maps
Table 2-9 CMB3401 EIM Default Memory Map
Address Range
Contents
Reserved Reserved Reserved Reserved
Comments
Chip select 0 (16M)
Active low. Can be used either for FLASH or FSRAM.1 Active low. Can be used either for FLASH or FSRAM.1. Active low. Can be used for DUART A.2 Active low. Can be used for DUART B.3 Active low.
Chip select 1 (16M)
Chip select 2 (16M)
Chip select 3 (16M)
Chip select 4 (16M)
Chip select 5 (16M)
Active low.
Reserved
Configuration
Table 2-10 EIM FLASH Sector Boundaries
Sector (Block)
Range (W2 Selects CS0)
Range (W2 Selects CS1)
Debugging Embedded Code
Section 3 Operation
3.1 Debugging Embedded Code
With your CMB3401, you may use the Picobug monitor, as standalone software. Optionally, you may use the GNU source-level debugger with the Picobug monitor. Other firms may produce still additional software to run, test, and modify the code you develop for embedding in an MMC3401 MCU. To use the Motorola System Development Software to download and transfer control to your code, you must be careful to program only the ranges of FLASH memory or SRAM that are allocated for user code or user space. Programming over ranges that contain system software or data storage would impair or destroy the usefulness of the software. (Subsection 3.2.1 identifies the contents of memory ranges subsection 3.2.2 explains how to use the SysDS Loader to restore factory programming.)
3.1.1 Using the Picobug Monitor
Operation
To use the Picobug debug monitor, merely enter commands at the prompt. Table 3-1 explains these commands. To see a list of these commands on your computer screen, enter a question mark or the extra command he at the command prompt . Table 3-1 Picobug Commands
Command
baud value
Explanation
br address
g address
gt address
he lo address
md address1 address2 size
mds address
Debugging Embedded Code
Table 3-1 Picobug Commands (Continued)
Command
mm address value size
Explanation
Modify Memory: · With optional address and value parameter values, assigns that value to the address location. · With optional address value but no value parameter value, prompts for a value for the address location, then prompts for a new value for the next location. To stop modification, enter a period instead of a new value. · With no optional address value, prompts for a value for the last address viewed, then prompts for a new value for the next location. To stop modification, enter a period instead of a new value. · The optional size value, specifies the format: b (bytes, the default), h (half words), w (words), or i (instructions). No Breakpoint: · With optional address value, removes the breakpoint from that address. · Without any address value, removes all the breakpoints. Reset: Resets the CPU and peripherals. Register Display: · With optional name value, displays the value of that CPU register. · Without any name value, displays the values of all CPU registers. Register Modify: Assigns the value parameter value to the name CPU register. Trace (Step): Single steps one instruction identical to the s command. Step (Trace): Single steps one instruction identical to the t command. Help Displays available commands, identical to the he command.
nobr address
reset rd name
3.1.2 Picobug Sample Session
1. This sample session begins with the Picobug prompt:
picobug
2. To see the contents of all registers, enter the Register Display (rd) command without any name value:
The system responds with a display such as this:
pc 00400286 psr 80000100 ss0-ss4 bad0beef r0-r7 004027f8 r8-r15 0010a000 epc epsr 20000c00 00000050 00020000 00400286 80000100 20008000 0000ea60 20000c00 fpc fpsr 20010042 00405f94 004067c0 0010a000 00020000 00000801 00406708 00000000 vbr 80070101 00405f94 00405c00 00000200 10005000 00000040 00400286
Operation
3. To see the contents of a specific register, such as the epc register, enter the Register Display (rd) command with the name value:
The system responds with a display such as this:
epc: 00400286
4. To see the contents of a specific memory location, enter the Memory Display (md) command with the location address. An optional size value (in this case w, for word) may be part of the command:
The system responds with a display such as this:
00401000: 8EF0B37E
5. To see the contents of a memory range, enter the Memory Display (md) command with the beginning and ending addresses. An optional size value (in this case b, for byte) may be part of the command:
The system responds with a display such as this:
6. To download into SRAM a program executable, in S-record format, enter the Download (lo) command without any address value:
The system waits for you to send the program executable file. To do so, open the Transfer menu and select Send Text File. This opens a file-select dialog box. Use this dialog box to specify the appropriate S-record file, then click on the Open button. As soon as the download is complete (this may take several minutes), the Picobug prompt reappears:
7. To see the new contents of registers, enter the Register Display (rd) command again, without any name value:
Debugging Embedded Code
The system responds with an updated display, which shows that the pc register value reflects the start of the program just downloaded:
pc 0040022a psr 80000000 ss0-ss4 bad0beef r0-r7 bad0beef r8-r15 0010a000 epc epsr 20000c00 00000050 004066b8 2d00108a 80070101 20008000 00000000 004067d7 fpc fpsr 20010042 d89f69ab 00406948 0010a000 00020000 00000801 00405f20 00406714 vbr 80000000 00406708 00405c00 00000200 004067c8 00000024 2d0001c4
8. To set a breakpoint at address 0x0040025C, enter this address as part of the Breakpoint (br) command:
The Picobug prompt reappears, confirming that the system set the breakpoint:
9. To see the list of breakpoints, enter the Breakpoint (br) command without any address value:
The system responds with the addresses of breakpoints, in this case only the breakpoint set in step 8:
0040025C
10. To start program execution, enter the Go (g) command:
In this instance, the breakpoint set during step 8 stops code execution. The system responds with this new display of register values:
11. To remove all breakpoints, enter the No Breakpoint (nobr) command, without any address value:
The Picobug prompt reappears, confirming that the system has removed the breakpoints:
12. To see the list of breakpoints again, once more enter the Breakpoint (br) command without any address value:
Operation
As there are no longer any breakpoints, the system responds with the Picobug prompt:
13. To continue with this example session, enter another appropriate command. For example, to resume program execution, enter the Go (g) command. 14. To end your Picobug session, remove power from the EVB and close the terminal-emulation program.
3.1.3 Using the GNU Source-Level Debugger
The GNU source-level debugger is on the CD-ROM that comes with your CMB3401. This GNU software works with the Picobug monitor to provide source-level debugging for your code. The CMB3401 software release guide gives the instructions for loading the GNU software, and for making any connections different from standalone Picobug connections. Make sure that the Picobug communications-speed setting is 19200 baud: this is the only communications speed for the GNU software.
3.2 Downloading to FLASH Memory
The Motorola SysDS Loader lets you program code into FLASH memory, upload FLASH contents to a PC file, verify that FLASH contents match those of a download file, display memory contents, erase FLASH memory, erase a sector of FLASH memory, or blank check a sector of FLASH memory.
3.2.1 Using the SysDS Loader
Follow these steps to use the Loader: 1. If you have not already installed the SysDS Loader onto your computer hard disk, do so. The CMB3401 product release guide includes installation instructions. 2. If the Hyperterminal emulation program is running, stop the program. (The SysDS Loader needs the same computer serial port that Hyperterminal uses.) 3. Set switch S2 for the Picobug monitor. The factory setting, for example, specifies Picobug: the GSB0 and GSB1 subswitches OFF, and the GSB2 subswitch ON. 4. Press switch S5 to reset the CMB3401.
Downloading to FLASH Memory
5. Start the SysDS Loader. The main screen (Figure 3-1) appears.
Figure 3-1 SysDS Loader Main Screen 6. Go to the File name field. · · If you know the full pathname of the file to be programmed, enter the pathname in this field. If you do not know the full pathname of the file to be programmed, click on the Browse button. This brings up a standard file-select dialog box: select the file and click on the OK button. This returns you to the FLASH / RAM page, entering the pathname in the File name field. (If your only action for this Loader session will be uploading FLASH contents, you may leave the File name field blank.)
Operation
11. To upload FLASH memory contents to a file in your PC, click on the Upload button. This brings up the Upload To File dialog box, Figure 3-2:
Figure 3-2 Upload To File Dialog Box · · Enter the name of the destination file. Optionally, click on the Browse button, to select a file via a standard file-select dialog box. The Start Address field indicates the start of CMB3401 FLASH memory. The default address value corresponds to the value of the SYSTEM field of the main screen FLASH / RAM page, but you may enter a different address, if appropriate.
Downloading to FLASH Memory
The Size in Bytes field value corresponds to the value of the Size field of the FLASH / RAM page. (If appropriate, you may enter a different value.) The system determines the value of the End Address field from the Start Address and Size in bytes values. The default Mode field value is Byte. When the Upload To File dialog box shows appropriate values, click on the Save button. A progress message appears during uploading. The uploaded values do not include addresses or ASCII representations.
NOTE:
12. To verify that the contents of Flash memory match the selected download file, click on the Verify button. A progress message appears as verification begins. A Verify successful message appears at the end of verification. · If this is the first action of this Loader session, the software downloads an algorithm file before verifying FLASH. A progress message appears during the downloading of this algorithm file. (Should the software be unable to find the algorithm file, an appropriate error message appears, as explained under the program FLASH memory step, above.) If verification fails, an error message specifies the location that did not have the expected contents. To recover from a verification failure, try downloading Flash again, to replace the selected download file.
13. To view the contents of Flash memory, click on the Display button. This brings up the Display Flash / Ram display, Figure 3-3:
Figure 3-3 Display Flash / Ram Display
Operation
If this is the first action of this Loader session, the software downloads an algorithm file before displaying FLASH contents. A progress message appears during the downloading of this algorithm file. (Should the software be unable to find the algorithm file, an appropriate error message appears, as explained under the program FLASH memory step, above.) The Address field shows the first address of the value display. One way to change the display is to enter a different address in this field. Another way to change the value display is to use the scroll bars. Use the Mode field to specify byte, half-word, or word values in the display. When you are done viewing the display, click on the Close button to return to the main screen.
14. To erase FLASH memory, click on the Erase FLASH button. The programmer erases all contents of the FLASH memory except for sectors that contain the system software. Erasing takes 20 to 30 seconds. If this is the first action of this Loader session, the software downloads an algorithm file before erasing FLASH. A progress message appears during the downloading of this algorithm file. (Should the software be unable to find the algorithm file, an appropriate error message appears, as explained under the program FLASH memory step, above.) 15. To erase a sector of FLASH memory, click on the Erase Sector button. This brings up the Flash Sector Number dialog box. Enter the number of the sector to be erased, then click on the OK button. · If this is the first action of this Loader session, the software downloads an algorithm file before erasing the FLASH sector. A progress message appears during the downloading of this algorithm file. (Should the software be unable to find the algorithm file, an appropriate error message appears, as explained under the program FLASH memory step, above.) For MLB Flash: The system does not let you erase any of the sectors that contain system software. (Table 2-8 shows these sectors.) For EIM Flash: If you specify any of the sectors that contain system software, a message so reminds you. (Table 2-10 shows these sectors.) Buttons of the message box let you cancel the erasure or proceed with the erasure. Do not erase EIM system-software sectors, unless it is absolutely necessary. If you must erase such a sector, you subsequently can restore factory programming by following the instructions of subsection 3.2.2.
NOTE:
Controlling CMB3401 LEDs
16. To verify that a FLASH sector is blank, click on the Blank Check button. This brings up a dialog box that asks for a sector number. Enter the number of the sector to be blank checked, then click on the OK button. A message tells you the results of the blank check. (If the sector is not blank, you can erase the sector or try a different sector.) 17. To end your Loader session, merely close the main screen.
3.2.2 Restoring EIM System Software
3.3 Controlling CMB3401 LEDs
Section 2 explained how LEDs DS3 through DS6 flicker as part of the CMB3401 self-test. Your own code also can control these LEDs, by assigning values to the four least-significant bits of the global control register (GCR): · · · · GCR bit 0 controls LED DS3 (GCB0). GCR bit 1 controls LED DS4 (GCB1). GCR bit 2 controls LED DS5 (GCB2). GCR bit 3 controls LED DS6 (GCB3).
Operation
Configuring Your Software
Section 4 Using the FPGA Device
This section explains how to use the Altera Max+plusII software to reprogram the FPGA device at CMB3401 location U2. Additionally, this section explains how to use the periodic interval timers (PITs) of the FPGA device.
4.1 Configuring Your Software
NOTE: The steps below are guidance for starting to use Altera MAX+plusII software. Should you have difficulty preparing your MAX+plusII software, phone Altera customer service for assistance.
You must prepare your Altera development software before you can for use it with your CMB3401. Follow the Altera instructions to: 1. Install the Altera development software. 2. Obtain and install your Verilog authorization code file. (If you FAX registration information, this takes only a few hours Altera customer service can provide the FAX number.) 3. Start the Altera software. 4. Start a project. This completes software preparation. You are ready to develop an application suitable for downloading to the CMB3401 U2 device.
4.2 Reprogramming the FPGA Device
Follow steps 1 through 29, below, to develop an application suitable for downloading to the FPGA device at location U2. Most of these steps are typical for using the MAX+plusII software to develop any new application project. These steps are not rigid instructions. In case of difficulty using the MAX+plusII software, you should call Altera customer service for assistance. The transmittal CD-ROM that contains this manual also contains example application files: a symbol counter, a Verilog counter, and a Verilog port. 1. Use Windows Explorer to create and name a new folder for the project. 2. Start the MAX+plusII software. 3. Open the File menu and select Project. From the subordinate menu, select Name. This brings up the Project Name dialog box.
Using the FPGA Device
4. Use the Project Name dialog box to select the newly created project folder, and to enter a name for the project. (The project name should not contain any spaces usually it is convenient to give the project the same name as the folder.) Click on the OK button to close the dialog box. 5. Open the File menu and select New. This brings up the New dialog box. Select Text editor file, then click on the OK button. This closes the dialog box and opens the text editor window. 6. Write the Verilog code for your application. (Consult the Altera Verilog manuals for instructions.) 7. When your code is done, leave the text editor window open. Click on the Open Compiler Window toolbar button. The software immediately compiles your code. 8. If the compiler finds errors, correct them in the text editor window, then compile again. When compilation succeeds, your are ready to create a default symbol. 9. Still leaving the text editor window open, open the File menu and select Create Default Symbol. The software automatically creates a graphic representation of the compiled code, a symbol that you later can use in a schematic design. 10. Open the File menu and select Project. From the subordinate menu, select Name. This brings up the Project Name dialog box. 11. Use the Project Name dialog box to select the same folder you selected in Step 4. Enter a new project name: as this project will be for a .hex file, Motorola suggests that you append the letter h to the name you used in Step 4. Click on the OK button to close the dialog box. 12. Open the File menu and select New. This brings up the New dialog box. Select graphic editor file, then click on the OK button. This closes the dialog box and opens the graphic editor window. 13. Open the Symbol menu and select Enter. This brings up the Enter Symbol dialog box. Select the symbol you created in Step 9. The symbol appears in the graphic editor window. 14. Add all the inputs and outputs to the symbol, then compile again. (The only errors likely at this point are mismatched signal names or a forgotten signal. Correct any errors and recompile.) When compilation succeeds, you are ready to assign a device. 15. Open the Assign menu and select Device. This brings up the Device dialog box. In the Device Family area, select FLEX 10KA. In the Devices area, select EPF10K100ABC600-1. Click on the Device Options button, to bring up the Individual Device Options dialog box.
Reprogramming the FPGA Device
Find the Configuration Device field: set the field value to be EPC2LC20. Elsewhere in the Individual Device Options dialog box, find the Configuration Scheme field: set the field value to be Passive Serial (can use Configuration Device). In the Not Affected By Configuration Scheme area, make sure that both CLKUSR boxes have grey check marks. Make sure that the only check marks are those that Steps a through d specify, then click on the OK button to return to the Device dialog box.
17. Click on the Device dialog box OK button to return to the main screen. This completes device assignment. You are ready to assign signals to pins. 18. It is best to give signals (wires) the same names as their corresponding pins. Open the Assign menu and select Pin / Location / Chip. This brings up the Pin / Location / Chip dialog box. a. Click on the Search button to bring up a subordinate dialog box that lists the pins. (Click on the LIST button to see the list.) The listed pin names are the inputs and outputs you created as part of Step 14.) Select (highlight) a pin, then click on the OK button. This returns you to the Pin / Location / Chip dialog box the selected pin name will be in the Node Name field. Go to the Chip Resource area of the dialog box. In the Pin field, enter the name of the FPGA pin. (This is the value in the U2 column of cross-reference table 6-5.) An alternative to using the Search button is to select Pin, activating the Pin Type field. Select the appropriate type from the small pull-down menu, then enter the pin name in the appropriate field, and enter the signal name in the Node Name field.
NOTE:
This completes assignment for the first pin.
Using the FPGA Device
19. Repeat Step 18 for all other signals. When you are done, close the Pin / Location / Chip dialog box. NOTE: For each finished design, the Altera software creates a .acf file: a text file that you can edit. For your first design, you must do Step 18 for each signal. But for subsequent designs, you can copy and edit a .acf file.
20. If you have not already done so, configure ByteBlaster programming hardware per Altera instructions. 21. Compile your application file again. When compilation succeeds, you are ready to create a .pof file. 22. Open the MAX+plusII menu and select Programmer. This brings up the Programmer dialog box. (You will not do anything in this dialog box, but it must be open at this point.) 23. Open the JTAG menu and select Multi-Device JTAG Chain Setup. This brings up the Multi-Device JTAG Chain Setup dialog box. a. Use the Device Name pull-down menu to select EPF10K100A, then click on the Add button. The EPF10K100A name appears in the list at the center of the dialog box, but without any associated programming. Use the Device Name pull-down menu to select EPC2, then click on the ADD button. The EPC2 name appears in the list at the center of the dialog box, but without any associated programming. Use the Device Name pull-down menu to select EPC2 a second time, then click on the Select Programming File button. This brings up the Select Programming File dialog box. Use the Select Programming File dialog box to select the .pof file for your project. Click on the OK button to return to the Multi-Device JTAG Chain Setup dialog box. Click on the Add button. This again adds the EPC2 name to the list at the center of the dialog box, but shows the association with the selected .pof file. Click on the Save JCF button. This brings up a subordinate dialog box that lets you name and save the listed files as a JTAG chain file. Click on the OK button to return to the Multi-Device JTAG Chain Setup dialog box. Click on the Multi-Device JTAG Chain Setup dialog box OK button to return to the Programmer dialog box. This completes file creation you are ready to download the files to the FPGA device.
24. Apply power to your CMB3401. 25. Connect the ByteBlaster between CMB3401 connector J14 and a parallel port of your computer. Make sure that the red wire of the cable connects to J14 pin 1.
Using the Periodic Interval Timers
26. Click on the Program button of the Programmer dialog box. A percentage indicator shows the progress of downloading the files to a ROM device of the CMB3401. 27. At the end of this downloading, disconnect the ByteBlaster cable from connector J14. 28. Press CMB3401 switch S7 to transfer the downloaded application to the U2 FPGA device. 29. This completes reprogramming of the U2 device. You may close the MAX+plusII software.
4.3 Using the Periodic Interval Timers
The FPGA device at location U2 includes two periodic interval timers (PITs), which can provide precise interrupts with minimal processor intervention. Each timer can either count down from a modulus-latch value or be a free-running down counter. Figure 4-1 is a diagram of such a PIT.
PITCSR
STOP STEP LO AD DBG O VW PITIE PITIF RLD
Figure 4-1 PIT Diagram Each PIT consists of a control block and three registers: · PIT data register (PITDR), which contains the timer modulus. Your code can set this modulus by writing to this register. Your code can find the modulus by reading from this register. PIT alternate data register (PITADR), which contains the current counter value. Your code can find the current timer value by reading from this register. PIT control / status register (PITCSR), which controls timer operation. Your code can control the timer by writing to or reading bits 8 through 1 of this register.
Using the FPGA Device
Table 4-1 lists the register addresses for both PITs. Figure 4-2 shows the layout of the control / status register. Table 4-2 explains the control bits of the control / status register. . Table 4-1 PIT Register Addresses
Registers
Control / Status Register (PITCSR) Data Register (PITDR) Alternate Data Register (PITADR)
PIT1 Addresses
PIT2 Addresses
Using the Periodic Interval Timers
8 STOP
7 STEP
6 4 2 5 3 LOAD DBG OVW PITIE PITIF
Figure 4-2 PIT Control / Status Register Layout
Table 4-2 Control / Status Register Bit Values
Bit Name
Reload Control (RLD)
Bit Value
Effect / Meaning
PIT Interrupt Flag (PITIF)
1 3 PIT Interrupt Enable (PITIE) Overwrite Enable (OVW) 0 1 4 0
Debug Mode (DBG) Load Counter (LOAD)
Step Counter (STEP)
Stop Counter (STOP)
NOTE:
Your code may not step a PIT counter from 1 to 0, nor may it step a PIT counter from 0 to the modulus latch value. Setting the counter value to 0 directly does not cause a PIT interrupt.
Using the FPGA Device
MAPI Connectors (P1 / J1, P2 / J2, P3 / J3, P4 / J4)
Section 5 Connector Information
This section consists of pin assignments and signal descriptions for CMB3401 connectors.
5.1 MAPI Connectors (P1 / J1, P2 / J2, P3 / J3, P4 / J4)
Connectors P1 through P4, all 2-by-50-pin connectors, are the CMB3401 MAPI connectors. (Connectors J1 through J4, on the bottom of the CMB3401, have the same pin assignments.) The diagram below shows the orientation of the CMB3401 MAPI connectors. Figure 5-1 through Figure 5-4, and Table 5-1 through Table 5-4, give the pin assignments and signal descriptions for these connectors.
100 1 P4 100
Connector Information
Figure 5-1 MAPI Connector P1 / J1 Pin Assignments
MAPI Connectors (P1 / J1, P2 / J2, P3 / J3, P4 / J4)
Table 5-1 MAPI Connector P1 / J1 Signal Descriptions
Mnemonic
VPP1 VDD3V Programming Voltage +3.2-volt power.
Signal
GROUND +5-volt power. DATA BUS DENY - Active-low signal that requests non-CMB devices to not access the data bus. Reserved. IDENTIFICATION CODE (lines 0-3) - Signals that identify the host processor board. EXTRNAL INTERRUPTS (lines 14, 12, 10, 8) - Bidirectional interrupt lines that form the external interface to the general-purpose I / O module.
GROUND - Connection to the Ground 1 plane. GROUND - Connection to the Ground 2 plane.
Connector Information
PTJ2100 PTJ298 PTJ296 PTJ294 PTJ292 PTJ290 PTJ288 PTJ286 GND VDD3V PTJ280 PTJ278 PTJ276 PTJ274 PTJ272 PTJ270 PTJ268 PTJ266 GND VDD3V RS56 RS54 RS52 RS50 RS48 RS46 RS44 GND VDD3V RS40 RS38 RS36 RS34 RS32 RS30 RS28 PTJ228 PTJ226 PTJ224 PTJ222 VDD3V GND PTJ216 PTJ214 PTJ212 PTJ210 PTJ28 PTJ26 PTJ24 PTJ22 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 99 97 95 93 91 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 GND3 PTJ297 PTJ295 PTJ293 PTJ291 PTJ289 PTJ287 GND3 GND VPP3 VDD5V PTJ277 PTJ275 PTJ273 PTJ271 PTJ269 PTJ267 PTJ265 GND PTJ261 RS57 RS55 RS53 RS51 RS49 RS47 RS45 VDD5V GND RS41 RS39 RS37 RS35 RS33 SDCPS VDD5V PTJ227 PTJ225 PTJ223 PTJ221 VPP2 GND GND2 PTJ213 PTJ211 PTJ29 PTJ27 PTJ25 PTJ23 GND2
Figure 5-2 MAPI Connector P2 / J2 Pin Assignments
MAPI Connectors (P1 / J1, P2 / J2, P3 / J3, P4 / J4)
Table 5-2 MAPI Connector P2 / J2 Signal Descriptions
Mnemonic
PTJ2x Pass Through
Signal
GND3 GND VDD3V VPP3 VDD5V
GROUND - Connection to the Ground 3 plane. GROUND +3.2-volt power. Programming Voltage. +5-volt power.
RS57-RS44, Reserved. RS41-RS32, RS30, RS28 (not in exact order) SDCPS SHUT DOWN CMB POWER SUPPLY - Signal, from a connected board that supplies power, to disable the on-board CMB power supply. Programming Voltage. GROUND - Connection to the Ground 2 plane.
VPP2 GND2
Connector Information
Figure 5-3 MAPI Connector P3 / J3 Pin Assignments
MAPI Connectors (P1 / J1, P2 / J2, P3 / J3, P4 / J4)
Table 5-3 MAPI Connector P3 / J3 Signal Descriptions
Mnemonic
Signal
CLOCK CONTROL - Clock control signal for the MCU clock. DEBUG MODE INDICATOR - Active-low signal indicating that the processor is in debug mode. EXTERNAL CLOCK - Off-board clock signal. TRI-STATE CONTROL - Signal that puts the processor in tri-state mode. GENERAL PURPOSE INPUT / OUTPUT - General-purpose I / O signal. GENERAL PURPOSE SERIAL OUTPUT - General-purpose I / O serial output signal.
Connector Information
Table 5-3 MAPI Connector P3 / J3 Signal Descriptions (Continued)
Mnemonic
Signal
TRANSFER CODE (lines 2-0) - Signals indicating the general type of transfer. IDENTIFICATION CODE (lines 9-4) - Signals that identify the host processor board. Pass Through.
BREAKPOINT REQUEST - Active-low signal that requests a hardware breakpoint. LOW POWER MODE (lines 0, 1) - Signals asserted by the processor upon execution of a doze, stop, or wait instruction. Optionally, an external source can assert these signals to put the CMB in its low-power stopped state. TRANSFER ABORT - Active-low signal from the processor that a requested access must be aborted. GROUND - Connection to the Ground 4 plane. GROUND - Connection to the Ground 3 plane.
MAPI Connectors (P1 / J1, P2 / J2, P3 / J3, P4 / J4)
Figure 5-4 MAPI Connector P4 / J4 Pin Assignments
Connector Information
Table 5-4 MAPI Connector P4 / J4 Signal Descriptions
Mnemonic
VDD5V VDD3V CSE1, CSE0 GND +5-volt power. +3.2-volt power.
Signal
CHIP SELECT, EMULATION (lines 1, 0) - Emulation chip select signals. GROUND
CLOCK OUTPUT - An external clock source from the processor. Reserved. FPGA CHIP SELECTS (lines 3-0) - Active-low output lines that provide chip selects to external devices. These signals are driven from the FPGA MLB address space. FPGA OUTPUT ENABLE - Active-low signal that indicates that a bus access is a read access enables slave devices to drive the data bus. This signal is driven from the FPGA MLB address space.
A31 - A0 (not in exact order) D31 - D0 (not in exact order)
OnCE Connector (J13)
5.2 OnCE Connector (J13)
Connector J13, a 2-by-7-pin connector, conveys data and control signals to and from the OnCE control block. Figure 5-5 and Table 5-5 give the pin assignments and signal descriptions for this connector.
Figure 5-5 OnCE Connector J13 Pin Assignments
Table 5-5 OnCE Connector J13 Signal Descriptions
Mnemonic
Signal
TEST DATA INPUT - Data and command serial input line to the OnCE controller. GROUND TEST DATA OUTPUT - Serial data output line from the OnCE controller. TEST CLOCK - Serial clock input line to the OnCE control block. EVENT IN - Active-low signal. At reset, enables or disables the NEXUS block. At other times, provided that NEXUS messages are on, causes a synchronization message. No connection RESET IN - Active-low input line to the OnCE controller, signalling a reset. TEST MODE SELECT - Input signal that tells the OnCE control block to advance one mode state (of the cycle of mode states). OPERATING VOLTAGE - Transmission line for +3.2-volt MCU operating power. READ / WRITE READY - Active-low signal that a NEXUS read or write access is ready. WATCHPOINT EVENT OUT - Active-low signal that a NEXUS watchpoint occurred, providing an exact timing reference. TEST RESET - Active-low input line for an external reset signal to the OnCE controller.
Connector Information
5.3 NEXUS Connector (J23)
Connector J23, a 2-by-15-pin connector, conveys data and control signals to and from the NEXUS (GEPDIS) control block. Figure 5-6 and Table 5-6 give the pin assignments and signal descriptions for this connector.
VREF GND GND GND GND GND GND GND GND GND GND GND GND GND GPIO
Figure 5-6 NEXUS Connector J23 Pin Assignments
Table 5-6 NEXUS Connector J23 Signal Descriptions
Mnemonic
Signal
RESET IN - Active-low input line to the NEXUS controller, signalling a reset. VOLTAGE REFERENCE - Transmission line for +3.3-volt MCU operating power. EVENT IN - Active-low signal. At reset, enables or disables the NEXUS block. At other times, provided that NEXUS messages are on, causes a synchronization message. GROUND TEST RESET - Active-low input line for an external reset signal to the NEXUS controller. TEST MODE SELECT - Input signal that tells the NEXUS control block to advance one mode state (of the cycle of mode states). RESERVED IN / OUT (lines 1, 2) - No connection. TEST DATA INPUT - Data and command serial input line to the NEXUS controller. TEST CLOCK - Serial clock input line to the NEXUS control block. TEST DATA OUTPUT - Serial data output line from the NEXUS controller.
even, 4-28 5 7 9, 15 11 13 17
NEXUS Connector (J23)
Table 5-6 NEXUS Connector J23 Signal Descriptions (Continued)
Connector Information
5.4 MLB Logic Analyzer Connectors (J25, J28, J32)
Connectors J25, J28, and J32, all 2-by-19-pin Mictor connectors, are the MLB logic analyzer connectors. Figure 5-7 through Figure 5-9 give the pin assignments for these connectors. Table 5-7 through Table 5-9 give the signal descriptions for these connectors.
Figure 5-7 MLB Logic Analyzer Connector J25 Pin Assignments
Table 5-7 MLB Logic Analyzer Connector J25 Signal Descriptions
Mnemonic
Signal
CLOCK OUTPUT - External clock source. ADDRESS BUS - Output lines 31-0, for addressing external devices. These lines change state only during external-memory accesses. READ / WRITE ENABLE - Active-low signal that indicates whether the current bus access is a read access or write access.
MLB Logic Analyzer Connectors (J25, J28, J32)
Figure 5-8 MLB Logic Analyzer Connector J28 Pin Assignments
Table 5-8 MLB Logic Analyzer Connector J28 Signal Descriptions
Mnemonic
Signal
TRANSMIT REQUEST - Active-low signal indicating a new access request. The resident MCU drives this signal. TRANSFER CODE (lines 2-0) - Signals indicating the general type of transfer. TRANSFER SIZE (lines 1, 0) - Signals that indicate the size of an external transfer. BURST - Active-low signal indicating that the current access is a cache line burst. PROCESSOR STATUS (lines 4-0) - Output signals that provide external status indications for the resident MCU. RESET IN - Active-low input signal that resets and initializes most CPU and debug-module logic. BUS GRANT - Active-low output signal that grants interface-bus ownership to an alternate master. TRANSFER ABORT - Active-low signal from the processor that a requested access must be aborted. TRANSFER BUSY - Active-low signal indicating that an access is in progress. The resident MCU drives this signal.
Connector Information
Table 5-8 MLB Logic Analyzer Connector J28 Signal Descriptions (Continued)
Mnemonic
Signal
MLB Logic Analyzer Connectors (J25, J28, J32)
Figure 5-9 MLB Logic Analyzer Connector J32 Pin Assignments
Table 5-9 MLB Logic Analyzer Connector J32 Signal Descriptions
Mnemonic
Signal
TRANSMIT ACKNOWLEDGE - Active-low I / O signal that indicates data-transfer completion, for either a read cycle or a write cycle. DATA BUS - Bi-directional data lines 31-0, for accessing external memory.
Connector Information
5.5 EIM Logic Analyzer Connectors (J29, J30, J33)
Connectors J29, J30, and J33, all 2-by-19-pin Mictor connectors, are the EIM-bus logic analyzer connectors. Figure 5-10 through Figure 5-12 give the pin assignments for these connectors. Table 5-10 through Table 5-12 give the signal descriptions for these connectors.
Figure 5-10 EIM Logic Analyzer Connector J29 Pin Assignments
Table 5-10 EIM Logic Analyzer Connector J29 Signal Descriptions
Mnemonic
Signal
CLOCK OUTPUT - External clock source. EIM ADDRESS BUS - Output lines 31-0, for addressing external devices. These lines change state only during external-memory accesses.
EIM READ / WRITE ENABLE - Active-low signal that indicates whether the current EIM bus access is a read access or write access.
EIM Logic Analyzer Connectors (J29, J30, J33)
Figure 5-11 EIM Logic Analyzer Connector J30 Pin Assignments
Table 5-11 EIM Logic Analyzer Connector J30 Signal Descriptions
Mnemonic
Signal
EIM BURST ADDRESS ADVANCE - Active-low output signal asserted during burst mode accesses, so that burst-capable devices increment internal burst counters to the next sequential memory locations. TRANSMIT REQUEST - Active-low signal indicating a new access request. The resident MCU drives this signal. TRANSFER CODE (lines 2-0) - Signals indicating the general type of transfer. TRANSFER SIZE (lines 1, 0) - Signals that indicate the size of an external transfer. EIM READ / WRITE ENABLE - Active-low signal that indicates whether the current EIM bus access is a read access or write access. PROCESSOR STATUS (lines 4-0) - Output signals that provide external status indications for the resident MCU. RESET IN - Active-low input signal that resets and initializes most CPU and debug-module logic. EIM LOAD BURST ADDRESS - Active-low output signal asserted during burst mode accesses so that burst-capable devices load new starting burst addresses.
Connector Information
Table 5-11 EIM Logic Analyzer Connector J30 Signal Descriptions (Continued)
Figure 5-12 EIM Logic Analyzer Connector J33 Pin Assignments
Old TEA, TA Eyelets (J7, J18)
Table 5-12 EIM Logic Analyzer Connector J33 Signal Descriptions
Mnemonic
Signal
MIM TRANSMIT ACKNOWLEDGE - Active-low I / O signal that indicates data-transfer completion for the MIM, for either a read cycle or a write cycle. EIM DATA BUS - Bi-directional data lines 31-0, for accessing external memory.
EIM BURST CLOCK - Output clock signal that external burst-capable devices use to synchronize address loading, address incrementing, and burst-read data delivery.
5.6 Old TEA, TA Eyelets (J7, J18)
Figure 5-13 depicts the special eyelet connectors J7 and J18, between Mictor connector J28 and MAPI connector P1.
OLD TEA J7
J18 OLD TA
Connector Information
5.7 RS232 Connectors (J57, J58)
Connectors J57 and J58, the RS232 connectors, have DCE format. The diagram below shows the pin numbering of these connectors. Table 5-13 lists the pin assignments and signal directions for these connectors.
Table 5-13 RS232 Connector J57, J58 Pin Assignments
Signal
CD Communication Detect TXD Transmitted Data RXD Received Data DTR Data Terminal Ready GROUND DSR Data Set Ready CTS Clear to Send RTS Request to Send RI Ring Indicator
Signal Direction
Out Out In IN - Out In Out In
NOTE:
Connector J57 is for channel A, and connector J58 is for channel B. Accordingly, the respective pin 1 assignments can be thought of as CDA and CDB. Similarly, the respective pin 2 assignments can be thought of as TXDA and TXDB, and so forth.
Section 6 Cross Reference Tables
During your application development, you may need to trace a signal from a pin of the resident 3401 device, through the FPGA device, to a MAPI-ring connector. Conversely, you may need to trace a signal in the other direction. The tables of this chapter help such tracing: · · · · · Table 6-1 lists trace relationships by 3401 device signals. Table 6-2 lists trace relationships by 3401 device pins. Table 6-3 lists trace relationships by MAPI-ring signals. Table 6-4 lists trace relationships by MAPI-ring pins. Table 6-5 lists pins of the FPGA device, showing their relationships to pins of either the 3401 device or of the MAPI-ring connectors.
Cross Reference Tables
Table 6-1 Cross Reference: U3 3401, U2 FPGA, MAPI Connectors
U3 3401 Device Signal
U2 FPGA Device Pin
W28 W29 V27 R29 D29 C28 E26 B28 D27 D26 B27 C26 A28 D25 E24 A26 B25 A25 C23 B24 B22 A22 E21 D20 C20 C12 C10 A10 A9 A8 A11 B10 B11 C18 B19 F5 H3 H2 H1 V1 AG2 AF5 AG1 C21 D21 U31 AL34 AL35 AK33 AP19
MAPI Connectors Default Signal
3401 Side
Ring Side
J1-61 J1-63 J1-65 J1-67 J1-32 J1-36 J1-55 J1-57 J1-31 J2-72 J2-65 J2-74 J2-76 J2-78 J2-80 J1-33 J1-35 J1-37 J1-39 J1-43 J1-45 J1-47 J1-49 J1-51 J1-53 J3-84 J3-94 J2-77 J3-85 J3-82 J3-80 J3-83 J3-87 J2-73 J2-75 J3-48 J4-42 J4-41 J4-44
Table 6-1 Cross Reference: U3 3401, U2 FPGA, MAPI Connectors (Continued)
U3 3401 Device Signal
U2 FPGA Device Pin
J4 J3 J2 J1 K5 K4 K3 K2 K1 L3 L2 L1 M3 M2 M1 N4 N3 N2 N1 P3 P2 P1 R3 R2 R1 T2 T3 U1 U2 D2 E3 B7 D5 C6 G2 E2 G1 J26 U3 U4 U4 U2 AH4 AL25 B25
MAPI Connectors Default Signal
3401 Side
AF4 AF3 AF2 AE5 AE3 AE2 AE1 AD5 AD4 AD3 AD2 AD1 AC5 AC4 AC2 AC1 AB4 AB3 AH3 AA5 AA4 AA1 Y5 Y4 Y3 W5 W4 W3 W2 V5 V4 A24 AJ1
Ring Side
AH31 AK34 AJ33 AJ34 AJ35 AH32 AG31 AH33 AH34 AH35 AG32 AG33 AG34 AF31 AF33 AF34 AF35 AE31 AM35 AA31 AA32 AA35 Y32 Y33 Y34 Y35 W32 W33 W34 V31 V33 B24 AL32 AR6 AM33 AR26 E24 E18 U32 U33