Download

PDF Abstract Text:

CAUTION: ESD Protection

MOTOROLA 2

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and B are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity / Affirmative
CAUTION: ESD Protection
M·CORE development systems include open-construction printed circuit boards that contain static-sensitive components. These boards are subject to damage from electrostatic discharge (ESD). To prevent such damage, you must use static-safe work surfaces and grounding straps, as defined in ANSI / EOS / ESD S6.1 and ANSI / EOS / ESD S4.1. All handling of these boards must be in accordance with ANSI / EAI 625.
MOTOROLA 2
Contents
Section 1 Introduction
Section 2 Configuration
Section 3 Operation
Section 4 Board Design and the FPGA Device
Section 5 Connector information
Figures
Tables
CMB2102 Features
Section 1 Introduction
1.1 CMB2102 Features
Introduction
Three 38-pin Mictor logic analyzer connectors. Altera ByteBlaster cable (for connector J19). Altera Max+plusII software.
1.2 System and User Requirements
You need an IBM PC or compatible computer, running the Windows 95 or WindowsNT (version 4.0) operating system. The computer requires a Pentium (or equivalent) microprocessor, 16 megabytes of RAM, 50 megabytes of free hard-disk space, an SVGA color monitor, and an RS232 serial-communications port. To use the Picobug monitor, you also need Hyperterminal or a comparable terminal-emulation program. To get the most from your CMB2102, you should be an experienced C or M·CORE assembly programmer. Your CMB2102 requires 12-volt input power, at 1 ampere. The power supply that comes with your CMB2102 provides this voltage from line power.
1.3 CMB2102 Layout
Figure 1-1 shows the layout of the CMB2102. The board has two FPGA devices: · · The XILINX FPGA device, at location U1, acts as an M210S core. Accordingly, this is the core FPGA device. The Altera FPGA device, at location U11, provides address conditioning for most communication between the MAPI connectors and the core FPGA device. Accordingly, U11 device is the MAPI FPGA device.
Connectors P1 through P4, on the top of the board, are the MAPI I / O and interrupt connectors (the corresponding MAPI connectors on the bottom of the CMB2102 are J1 through J4). Connectors J5, J8, and J14 are the logic analyzer connectors. Connector J9 is for supplying external configuration data for the core FPGA device. (This requires a user-supplied XILINX in-system programming cable and software.) Connector J12 is for reprogramming the memory-controller device at location U8. (This requires a user-supplied Vantis ISP cable and software.) Connector J19 is for in-circuit programming of the U11 MAPI FPGA device. (This requires the Altera ByteBlaster cable supplied with your CMB2102.) Connector J24 is the connector for an external clock signal. Connectors J27 and J28 are the RS232 serial connectors. Connector J29 is the OnCE connector. Connector J30 is the connector for 12-volt input power.
CMB2102 Layout
DS1 - DS6 DS7 W6
DS8 DS9 DS10
J12 J14 P3
DS11 S5 S6 J19 U11 W12 P4 F1 J29 J27 J28 J30 DS12 S7 S8
Figure 1-1 MMCCMB2102 Computer and Memory Board Switch S1 emulates a power-on-reset condition. Switch S2 starts configuration for the core FPGA device. Switch S3 selects the configuration mode for the core FPGA device. Switch S4 is the memory configuration switch. Switch S5 is the pass enable switch. Switch S6 is the global status bit switch. Switch S7 starts configuration for the MAPI FPGA device. Switch S8 is the reset switch. Location F1 is for the CMB2102 fuse. LEDs DS1 and DS2 indicate low-power mode (bits 0 and 1, respectively). LEDs DS3 through DS6 are indicators for global control bits GCB0 through GCB3. LED DS7 indicates debug mode. LED DS8 indicates that configuration of the core FPGA device is in progress. LEDs DS9, DS10, and DS11 confirm power to the three voltage planes: 5-volt, 2.5-volt, and 3.3-volt, respectively. LED DS12 indicates that configuration of the MAPI FPGA device is in progress.
Introduction
Jumper header W6 the source of configuration data for the U1 core FPGA device. Jumper header W7 enables several board functions. Jumper header W12 selects the clock-signal source. Table 1-1 lists CMB2102 specifications. Table 1-1 MMCCMB2102 Controller and Memory Board Specifications
Characteristic
Specifications
HCMOS compatible
Configuring Board Components
Section 2 Configuration
This section explains how to configure your CMB2102, and how to hook it up to your computer system.
2.1 Configuring Board Components
Configuring your CMB2102 involves setting several components. Table 2-1 is a summary of these settings subsections 2.1.1 through 2.1.7 give additional information. Table 2-1 Component Configuration Settings
Component
Core FPGA Configuration Header, W6
Position
Effect
Selects on-board devices U2 and U3 as the source of core FPGA (U1) configuration data. (Appropriate for master-serial mode.) Factory setting. Selects an external source of core FPGA (U1) configuration data, via connector J9. (Appropriate for boundary scan or slave-serial mode.) Enables all four functions: MAPI, DUART, FSRAM, and FLASH. Factory setting.
Function Jumper Header, W7 (The four jumpers are independent.)
Enables MAPI, DUART, and FLASH functionality, but disables FSRAM functionality. (One of many possible configurations.)
Enables MAPI and FSRAM functionality, but disables DUART and FLASH functionality. (Another of many possible configurations.)
Configuration
Table 2-1 Component Configuration Settings (Continued)
Component
Function Jumper Header, W7 (continued)
Position
Effect
Disables all four functionalities. (Another of many possible configurations.)
Clock Select Header, W12
Selects the 8-megahertz oscillator (Y1) clock source. Factory setting. Selects the external clock signal connected to J24.
Power On Reset Switch, S1
Push to emulate power on reset.
Core Configuration Switch, S2
Push to start configuration of the core FPGA device.
Core Configuration Mode Switch, S3
Selects master-serial mode.
(W6 jumper must be installed.) Factory setting. Selects boundary scan mode, for external configuration data via connector J9.
(W6 jumper must be removed user-supplied XILINX cable and software are required.) Selects slave-serial mode, for external configuration data via connector J9.
(W6 jumper must be removed user-supplied XILINX cable and software are required.)
Configuring Board Components
Table 2-1 Component Configuration Settings (Continued)
Component
Memory Configuration Switch, S4
Position
Effect
Pass Enable Switch, S5
Passes MLB and INT-bus signals directly to the M·CORE device, without processing or latching. Enables MAPI FPGA outputs as configured. (One of many possible configurations.) Factory setting.
Configuration
Table 2-1 Component Configuration Settings (Continued)
Component
Pass Enable Switch, S5 (continued)
Position
Effect
Passes INT-bus signals directly to the M·CORE device, without processing. Latches MLB signals from the M·CORE device before sending them to the MAPI ring. Tri-states MAPI FPGA outputs. (Another of many possible configurations.) Passes INT-bus and MLB signals directly to the M·CORE device, without processing or latching. Tri-states MAPI FPGA outputs. (Another of many possible configurations.)
Processes INT-bus signals before sending them to the M·CORE device. Latches MLB signals before sending them to the M·CORE device. Enables MAPI FPGA outputs. (Another of many possible configurations correct for configuring the FPGA I / O peripheral board.) Specifies the built-in selftest, to be executed in FLASH, upon a reset. (One of many possible configurations.) Factory setting.
Software Select Switch, S6
Specifies the programmer, to be executed in FLASH, upon a reset. (Another of many possible configurations.)
Specifies Picobug, to be executed in FSRAM, upon a reset. (Another of many possible configurations.)
Configuring Board Components
Table 2-1 Component Configuration Settings (Continued)
Component
Software Select Switch, S6 (continued)
Position
Effect
Specifies user code, to be executed in FSRAM, upon a reset. (Another of many possible configurations.)
MAPI Configuration Switch, S7
Push to start configuration of the MAPI FPGA device.
Reset Switch, S8
Push to reset the board.
2.1.1 Setting the Core FPGA Configuration Header (W6)
Jumper header W6 specifies the configuration-data source for the core FPGA device (location U1). The diagram below shows the factory configuration: the installed jumper specifies on-board devices U2 and U3 as the configuration source.
Alternatively, you may specify an external source of configuration data, via connector J9. To do so, remove the jumper from header W6. NOTE: 1. Supplying configuration data from an external source requires a user-supplied XILINX ISP cable and user-supplied XILINX software. This action requires that the W6 jumper be removed and that switch S3 specify boundary scan or slave-serial configuration mode. 2. Make sure that the W6 jumper is installed if switch S3 specifies master-serial configuration mode.
Configuration
2.1.2 Setting the Function Jumper Header (W7)
Jumper header W7 enables or disables these board functions: MAPI, DUART, FSRAM, and FLASH. The diagram below shows the factory configuration: the four jumpers enable all four functions.
8 W7 7 MAPI DUART FSRAM FLASH 1
To disable a function, remove the corresponding jumper: · · · · To disable FLASH memory, remove the jumper from W7 pins 1 and 2. To disable FSRAM, remove the jumper from W7 pins 3 and 4. To disable the DUARTs, remove the jumper from W7 pins 5 and 6. To disable the MAPI connection, remove the jumper from W7 pins 7 and 8.
2.1.3 Setting the Clock Select Jumper Header(W12)
Jumper header W12 selects the source of the CMB2102 clock signal. The diagram below shows the factory configuration: the jumper between W12 pins 1 and 2 selects the 8-megahertz canned oscillator at board location Y1.
CLKSEL
Alternatively, you may supply an external clock signal. To do so, · · Connect the external clock signal to connector J24, and Reposition the W12 jumper to pins 2 and 3.
Configuring Board Components
2.1.4 Setting the Core Configuration Mode Switch (S3)
Switch S3 specifies the configuration mode for the core FPGA device (U1). The diagram below shows the factory configuration: subswitches CMD0, CMD1, and CMD2 in the ON position. (The position of the CMD3 subswitch is irrelevant.) This configures master-serial mode.
CMD0 CMD1 CMD2 CMD3
Table 2-3 explains the other positions for the S3 subswitches. Note that you must configure jumper header W6 appropriately for each mode. Table 2-2 Core Configuration Mode Switch Positions
CMD0 Subswitch ON OFF OFF CMD1 Subswitch ON ON OFF CMD2 Subswitch ON OFF OFF Configuration Mode
Master-serial (W6 jumper must be installed.) Boundary scan (W6 jumper must be removed.) Slave-serial (W6 jumper must be removed.)
NOTE:
Boundary scan and slave-serial modes are appropriate only if you supply configuration data from an external source, via connector J9. Doing so requires a user-supplied XILINX ISP cable and user-supplied XILINX software.
Configuration
2.1.5 Setting the Memory Configuration Switch (S4)
1 HI / LO SWAP SEL1 SEL0 4 ON S4 8
Cycles in Waits 0 1 2 3 SEL0 Subswitch ON OFF ON OFF SEL1 Subswitch ON ON OFF OFF
Configuring Board Components
2.1.6 Setting the Pass Enable Switch (S5)
Switch S5 controls passing methods for interrupt-bus (INT-bus) signals and M·CORE local-bus (MLB) signals. The diagram below shows the factory configuration. Both IPASS and MPASS subswitches OFF directs the CMB2102 to pass these signals directly from the MAPI ring to the M·CORE device, without any processing or latching. The OE subswitch OFF enables MAPI FPGA outputs as configured.
MPASS IPASS
NOTE:
The subswitch for S5 pins 4 and 5 is not connected.
INT-bus signals are another subset of the many available at the MAPI connectors, a subset related to interrupts. The S5 IPASS subswitch specifies what the FPGA device is to do, once it receives these signals from the MAPI ring. · · If the IPASS subswitch is OFF, the FPGA device passes the INT-bus signals directly to the M·CORE device, without any processing. If the IPASS subswitch is ON, the FPGA device processes the INT-bus signals before sending them to the M·CORE device.
MLB signals are a subset of those available at the MAPI connectors, a subset related to external bus connections. The S5 MPASS subswitch specifies what the FPGA device is to do, once it receives these signals from the MAPI ring. · · If the MPASS subswitch is OFF, the FPGA device passes the unlatched MLB signals directly to the M·CORE device. (Chip selects are not available in this mode.) If the MPASS subswitch is ON, the FPGA device latches the MLB signals before sending them to the M·CORE device.
The S5 OE subswitch specifies whether MAPI FPGA outputs are tri-stated. · · If the OE subswitch is OFF, it enables the MAPI FPGA outputs as configured. If the OE subswitch is ON, it tri-states the MAPI FPGA outputs.
Configuration
2.1.7 Setting the Software Select Switch (S6)
Switch S6 specifies the software to be run upon a reset, and where that software is to be executed. The diagram below shows the factory configuration: the GSB3 subswitch ON specifies execution in FLASH memory subswitches GSB2 through GSB0 all ON specify the built-in selftest.
1 GSB3 GSB2 GSB1 GSB0 4 S6 5 ON 8
To specify execution in FSRAM, set the GSB3 subswitch to OFF. To specify a different software module, reposition subswitches GSB2 through GSB0 per Table 2-4. Table 2-4 S6 Subswitch Settings
Software Module Built-in selftest Programmer Picobug User code GSB2 Subswitch ON ON ON OFF GSB1 Subswitch ON ON OFF OFF GSB0 Subswitch ON OFF ON OFF
2.2 Making Computer-System Connections
When you have configured your CMB2102, you are ready to connect it to your computer system: 1. Make sure that power is disconnected. 2. If you will use RS232 communication with your host computer, connect an RS232 cable between CMB2102 connector J28 and the appropriate serial port of your computer. Communication settings for the computer serial port must be 19200 baud, 8 bits, no parity, 1 stop bit, and no flow control. (Optional: If your application must have the higher UART addresses, use connector J27 for your RS232 communication.) 3. If you will use a OnCE-compatible emulator with your CMB2102, connect an appropriate 14-lead ribbon cable between CMB2102 connector J29 and your emulator. Then use an appropriate cable to connect your emulator to your host computer.
Making Computer-System Connections
Configuration
13. (Optional) For scope observation of specific I / O or interrupt signals, you may use connectors P1 through P4. You may clip individual lines to the pins of these connectors, or use appropriate connectors. (An MMCLAB01 logic analyzer board provides easy access to the MAPI-pin signals. Section 5 gives pin assignments and signal descriptions for these connectors.)
2.3 Performing the CMB2102 Selftest
Once you have configured your CMB2102, you can perform a selftest of its components. NOTE: If you open Hyperterminal, per the instructions of subsection 3.1.1, Hyperterminal displays the progress of the selftest. Should the selftest fail, Hyperterminal indicates the address at which the test failed.
1. Make sure that CMB2102 power is turned off or disconnected. The power LEDs DS9, DS10, and DS11 should be out. 2. Make sure that a jumper is installed in header W6. Make sure that switch S3 selects master-serial core configuration mode: CMD0, CMD1, and CMD2 subswitches all ON. 3. Set switch S6 for the built-in selftest: all subswitches ON. 4. Apply power. Green LEDs DS9, DS10, and DS11 come on to confirm power. LED DS8 lights briefly, during core FPGA configuration. LED DS12 flashes briefly, during MAPI FPGA configuration. 5. The CMB2102 begins its selftest: LEDs DS3 through DS6 light and go out during the test, according to the sequence of Table 2-5. (In normal operation, LEDs DS1 and DS2 always are ON.) Table 2-5 CMB2102 Selftest LED Sequence
DS3 (GCB0)
ON OFF ON OFF OFF OFF OFF OFF ON OFF ON OFF
DS4 (GCB1)
ON OFF OFF ON OFF OFF OFF ON OFF OFF ON OFF
DS5 (GCB2)
ON OFF OFF ON OFF OFF ON OFF OFF OFF ON OFF
DS6 (GCB3)
ON OFF ON OFF OFF ON OFF OFF OFF OFF ON OFF
Memory Map
6. When all four LEDs go out at the end of this sequence, the CMB2102 has passed the selftest. (If any LEDs stay lit, the CMB2102 has failed the selftest: contact Motorola customer support for assistance.) 7. Turn off power. 8. Configure switch S6 for your next development activity before restoring power to the CMB2102.
2.4 Memory Map
Table 2-6 is the default memory map for your CMB2102.
Configuration
Table 2-6 CMB2102 Default Memory Map
Address Range
Contents
FLASH (4M)
Related Signals
NOTES: 1. Table 2-7 lists the sector (block) boundaries. 2. Section 4 explains individual addresses and register fields of this range.
Memory Map
Table 2-7 FLASH Sector Boundaries
Sector (Block)
Range
Size (Kbytes)
64 32 32 128 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 Boot code Programmer
Contents
Built-in selftest Device drivers Reserved Picobug Reserved User code User code User code User code User code User code User code User code User code User code User code User code
Configuration
Debugging Embedded Code
Section 3 Operation
3.1 Debugging Embedded Code
With your CMB2102, you may use the Picobug monitor, as standalone software. Optionally, you may use the GNU source-level debugger with the Picobug monitor. Other firms may produce still additional software to run, test, and modify the code you develop for embedding in an MMC2102 MCU. To use the Motorola System Development Software to download and transfer control to your code, you must be careful to program only the ranges of FLASH memory or SRAM that are allocated for user code. Programming over ranges that contain system software or data storage would impair or destroy the usefulness of software. (Subsection X identifies the contents of memory ranges subsection Y explains how to use the SysDS Loader to restore system software.)
3.1.1 Using the Picobug Monitor
Operation
To use the Picobug debug monitor, merely enter commands at the prompt. Table 3-1 explains these commands. To see a list of these commands on your computer screen, enter a question mark or the extra command he at the command prompt. . Table 3-1 Picobug Commands
Command
br address
Explanation
g address
gt address
he lo address
md address1 address2 size
mds address
mm address value size
Debugging Embedded Code
Table 3-1 Picobug Commands (Continued)
Command
nobr address
Explanation
No Breakpoint: · With optional address value, removes the breakpoint from that address. · Without any address value, removes all the breakpoints. Reset: Resets the CPU and peripherals. Register Display: · With optional name value, displays the value of that CPU register. · Without any name value, displays the values of all CPU registers. Register Modify: Assigns the value parameter value to the name CPU register. Trace (Step): Single steps one instruction identical to the s command. Step (Trace): Single steps one instruction identical to the t command. Help Displays available commands, identical to the he command.
reset rd name
3.1.2 Picobug Sample Session
1. This sample session begins with the Picobug prompt:
picobug
2. To see the contents of all registers, enter the Register Display (rd) command without any name value:
The system responds with a display such as this:
pc 0041d000 psr 80000000 ss0-ss4 bad0beef r0-r7 bad0beef r8-r15 00406024 epc epsr 00010000 00000400 00010050 ffffffff ffffffff ffffffff 00010000 0000000f fpc fpsr ffffffff 00403f34 00000080 ffffffff ffffffff ffffffff 00403b24 ffffffff vbr 7ffffff6 00000012 00403c00 00000020 00000012 00408000 000000b2
Operation
3. To see the contents of a specific register, such as the epc register, enter the Register Display (rd) command with the name value:
The system responds with a display such as this:
epc: FFFFFFFF
4. To see the contents of a specific memory location, enter the Memory Display (md) command with the location address. An optional size value (in this case w, for word) may be part of the command:
The system responds with a display such as this:
0041D000: 710E1210
5. To see the contents of a memory range, enter the Memory Display (md) command with the beginning and ending addresses. An optional size value (in this case b, for byte) may be part of the command:
The system responds with a display such as this:
6. To download into SRAM a program executable, in S-record format, enter the Download (lo) command without any address value:
The system waits for you to send the program executable file. To do so, open the Transfer menu and select Send Text File. This opens a file-select dialog box. Use this dialog box to specify the appropriate S-record file, then click on the Open button. As soon as the download is complete (this may take several minutes), the Picobug prompt reappears:
7. To see the new contents of registers, enter the Register Display (rd) command again, without any name value:
Debugging Embedded Code
The system responds with an updated display, which shows that the pc register value reflects the start of the program just downloaded:
pc 0041d000 psr 80000000 ss0-ss4 bad0beef r0-r7 bad0beef r8-r15 00406024 epc epsr 00010000 00000400 00010050 ffffffff ffffffff ffffffff 00010000 0000000f fpc fpsr ffffffff 00403f34 00000080 ffffffff ffffffff ffffffff 00403b24 ffffffff vbr 7ffffff6 00000012 00403c00 00000020 00000012 00408000 000000b2
8. To set a breakpoint at address 0x0041D056, enter this address as part of the Breakpoint (br) command:
The Picobug prompt reappears, confirming that the system set the breakpoint:
9. To see the list of breakpoints, enter the Breakpoint (br) command without any address value:
The system responds with the addresses of breakpoints, in this case only the breakpoint set in step 8:
0041D056
10. To start program execution, enter the Go (g) command:
In this instance, the breakpoint set during step 8 stops code execution. The system responds with this new display of register values:
11. To remove all breakpoints, enter the No Breakpoint (nobr) command, without any address value:
The Picobug prompt reappears, confirming that the system has removed the breakpoints:
Operation
12. To see the list of breakpoints again, once more enter the Breakpoint (br) command without any address value:
As there are no longer any breakpoints, the system responds with the Picobug prompt:
13. To continue with this example session, enter another appropriate command. For example, to resume program execution, enter the Go (g) command. 14. To end your Picobug session, remove power from the EVB and close the terminal-emulation program.
3.1.3 Using the GNU Source-Level Debugger
The GNU source-level debugger is on the CD-ROM that comes with your CMB2102. This GNU software works with the Picobug debug monitor to provide source-level debugging for your code. The CMB2102 software release guide gives the instructions for loading the GNU software, and for making any connections different from standalone Picobug connections.
3.2 Downloading to FLASH Memory
The Motorola SysDS Loader lets you program code into FLASH memory, upload FLASH contents to a PC file, verify that FLASH contents match those of a download file, display memory contents, erase FLASH memory, erase a sector of FLASH memory, or blank check a sector of FLASH memory.
3.2.1 Using the SysDS Loader
Follow these steps to use the Loader: 1. If you have not already installed the Loader onto your computer hard disk, do so. The CMB2102 product release guide includes installation instructions. 2. Important: If the Hyperterminal emulation program is running, stop the program. (The SysDS Loader needs the same computer serial port that Hyperterminal uses.) 3. Set switch S6 for the Picobug monitor: GSB2 subswitch ON. GSB1 subswitch OFF, and GSB0 subswitch ON. Set S6 subswitch GSB3 ON, to specify execution in FLASH. 4. Press switch S8 to reset the CMB2102.
Downloading to FLASH Memory
5. Start the SysDS Loader. The main screen (Figure 3-1) appears.
Figure 3-1 SysDS Loader Main Screen 6. Go to the File name field of the FLASH / RAM page. · · If you know the full pathname of the file to be programmed, enter the pathname in this field. If you do not know the full pathname of the file to be programmed, click on the Browse button. This brings up a standard file-select dialog box: select the file and click on the OK button. This returns you to the FLASH / RAM page, entering the pathname in the File name field. (If your only action for this Loader session will be restoring system software, you may leave the File name field blank.)
7. Make sure that the SYSTEM field shows the value CMB / EVB2102.
Operation
11. To upload FLASH memory contents to a file in your PC, click on the Upload button. This brings up the Upload To File dialog box, Figure 3-2:
Figure 3-2 Upload To File Dialog Box
Downloading to FLASH Memory
Enter the name of the destination file. Optionally, click on the Browse button, to select a file via a standard file-select dialog box. The Start Address field indicates the start of CMB2102 FLASH memory. The default address value corresponds to the value of the SYSTEM field of the main screen FLASH / RAM page, but you may enter a different address, if appropriate. The Size in Bytes field value corresponds to the value of the Size field of the FLASH / RAM page. The system determines the value of the End Address field from the Start Address and Size in bytes values. The default Mode filed value is Byte. When the Upload To File dialog box shows appropriate values, click on the Save button. A progress message appears during uploading. The uploaded values do not include addresses or ASCII representations.
NOTE:
12. To verify that the contents of Flash memory match the selected download file, click on the Verify button. A progress message appears as verification begins. A Verify successful message appears at the end of verification. · If this is the first action of this SysDS loader session, the software downloads an algorithm file before verifying FLASH. A progress message appears during the downloading of this algorithm file. (Should the software be unable to find the algorithm file, an appropriate error message appears, as explained under the program FLASH memory step, above.) If verification fails, an error message specifies the location that did not have the expected contents. To recover from a verification failure, try downloading Flash again, to replace the selected download file.
Operation
13. To view the contents of Flash memory, click on the Display button. This brings up a Display Flash / RAM display, such as (Figure 3-3).
Figure 3-3 Display FLASH / RAM Display · If this is the first action of this SysDS loader session, the software downloads an algorithm file before displaying FLASH contents. A progress message appears during the downloading of this algorithm file. (Should the software be unable to find the algorithm file, an appropriate error message appears, as explained under the program FLASH memory step, above.) The Address field shows the first address of the value display. One way to change the display is to enter a different address in this field. Another way to change the value display is to use the scroll bars. Use the Mode field to specify byte, half-word, or word values in the display. When you are done viewing the display, click on the Close button to return to the main screen FLASH / RAM page.
14. To erase FLASH memory, click on the Erase FLASH button. The SysDS loader erases all contents of the FLASH memory except for sectors that contain the system software. Erasing takes 20 to 30 seconds. If this is the first action of this Loader session, the software downloads an algorithm file before erasing FLASH. A progress message appears during the downloading of this algorithm file. (Should the software be unable to find the algorithm file, an appropriate error message appears, as explained under the program FLASH memory step, above.) 15. To erase a sector of FLASH memory, click on the Erase Sector button. This brings up the Flash Sector Number dialog box. Enter the number of the sector to be erased, then click on the OK button.
Downloading to FLASH Memory
If this is the first action of this Loader session, the software downloads an algorithm file before erasing the FLASH sector. A progress message appears during the downloading of this algorithm file. (Should the software be unable to find the algorithm file, an appropriate error message appears, as explained under the program FLASH memory step, above.) If you specify any of the sectors that contain system software (0 through 6), a message so reminds you. Buttons of the message box let you cancel the erasure or proceed with the erasure. Do not erase sectors 0 through 6, which contain system software, unless it is absolutely necessary. Table 2-7 lists the boundaries of these sectors. If you must erase any of these sectors, you subsequently can restore factory programming by clicking on the Restore System Software button, provided that you do so before you end your SysDS loader session. Paragraph 3.2.2 gives additional information about restoring system software.
NOTE:
CAUTION:
Failure to restore system software, or failure to correctly set the reset vector, during the same SysDS loader session, puts you into an unrecoverable situation. Subsequent restoration of system software may require sending your CMB2102 back to the factory.
3.2.2 Restoring System Software
If you must overwrite system-software FLASH sectors, you may use the SysDS loader to restore system software, provided that you do so before the end of your SysDS loader session. To do so, follow these instructions: 1. Press switch S8, to reset the CMB2102. 2. Make sure that jumper header W7 enables FLASH, FSRAM, and the DUART. 3. Set all S4 subswitches ON.
Operation
4. Set switch S6 for the Programmer: subswitches GSB2, GSB1, and GSB0 all ON. 5. Click on the Restore System Software button of the FLASH / RAM page. · If the system software is in your current hard-disk directory, the Loader automatically restores system software to the appropriate FLASH sectors. The main screen reappears to confirm successful programming. Should you receive a message that the system software does not exist, it may be because the software is in a different hard-disk directory. If so, make that directory the active one and click again on the Restore System Software button.
3.3 Controlling CMB2102 LEDs
Section 2 explained how LEDs DS3 through DS6 show the progress of the CMB2102 selftest, or give other status information. Your own code can control these LEDs, by assigning values to the four least-significant bits of the global control register (GCR): · · · · GCR bit 0 controls LED DS3 (GCB0). GCR bit 1 controls LED DS4 (GCB1). GCR bit 2 controls LED DS5 (GCB2). GCR bit 3 controls LED DS6 (GCB3).
The value 0 in any of these bits turns ON the corresponding LED. The value 1 in any of these bits turns OFF the corresponding LED. The example assembly routine below uses an assembly code function the opcode mtcr to move bit patterns from register X (r2) to the GCR. This this routine turns the status LEDs ON, the OFF.
CMB2102 Design
Section 4 Board Design and the FPGA Device
This section explains a few important relationships among components of your CMB2102, and explains important functions of the U11 MAPI FPGA device. Additionally, this section explains how to use the Altera Max+plusII software to reprogram the MAPI FPGA device.
4.1 CMB2102 Design
Figure 4-1 is a simplified diagram of CMB2102 functionality. The core FPGA device simulates an M210 core. Most communication is through the MAPI FPGA device and the MAPI ring, via the M·CORE local bus (MLB).
TA, TEA Control, Decode
FLASH MEMORY CONTROLLER FLASH
DUART
MAPI RING
CORE FPGA (M210 core)
MAPI FPGA: Interrupt Control Periodic Interval Timer External Interface
Figure 4-1 Functionality Diagram The functionality of the MAPI FPGA device includes an interrupt controller, a periodic interval timer (PIT), and an external interface controller. The external interface controller generates the off-board chip selects, and conditions the off-board address and data signals. The CMB2102 memory map includes FLASH, RAM, DUART, and the MAPI FPGA. The memory controller provides address decode for such functions, and generates the TA and TEA control signals back to the core FPGA. Subsections 4.1.1 through 4.1.4 explain the interrupt controller, the periodic interval timer (PIT), the external interface, and port F. Table 4-1 lists the registers and addresses for these functions.
Board Design and the FPGA Device
Table 4-1 Interrupt, PIT, Port F Addresses
Function
Interrupt controller
Register
Interrupt source Normal interrupt enable Fast interrupt enable Normal interrupt pending Fast interrupt pending Interrupt control
Address
Periodic interval timer
Control / status register Data register Alternate data register
Port F
Control and data direction Edge detect enable Pin data
Address Decode
CS0 base address CS1 base address
4.1.1 Using the Interrupt Controller
The MAPI FPGA device includes an interrupt controller example, which Figure 4-2 represents.
Figure 4-2 Interrupt Controller Diagram
CMB2102 Design
The interrupt controller consists of a priority logic block and these registers: · Interrupt source register (INTSRC), which consists of 32 bits, each associated with a single interrupt source. Positions 0, 1, 2, 29, 30, and 31 always are forced to the value 1. This means that your code can force an interrupt by enabling interrupts for one of these positions. Normal interrupt enable register (NIEN), a 32-bit register for individual bit masking of the INTSRC. Each clear bit of the NIEN masks the corresponding INTSRC bit value: even if that INTSRC bit is set, no interrupt request goes forward. Each set bit of the NIEN lets the corresponding INTSRC bit value determine the request. Normal interrupt pending register (NIPND), which indicates the priority of normal interrupts. Fast interrupt enable register (FIEN), a 32-bit register for individual bit masking of the INTSRC. Each clear bit of the FIEN masks the corresponding INTSRC bit value: even if that INTSRC bit is set, no interrupt request goes forward. Each set bit of the FIEN lets the corresponding INTSRC bit value determine the request. Fast interrupt pending register (FIPND), which indicates the priority of fast interrupts. Interrupt control register (ICR), a 32-bit register that can elevate any fast interrupt to the highest-priority level, specifying the servicing vector.
Board Design and the FPGA Device
31 30 29 28 27 26 25 - 6 1 1 1 IN28 IN27 IN26 IN25 - IN6
Figure 4-3 Interrupt Source Register Layout
Table 4-2 Interrupt Source Assignments
Active
High High High Low Low High High High Edge Edge Edge Edge Edge Edge Edge Edge
Active
Low Low Low Low Low Low Low Low Low Low Low Low Low High High High
CMB2102 Design
31 - 17 0 (not used)
16 15 14 13, 12 BRKRQ ENABLE DBGRQ 0 (not used)
11 - 7 Source
6 -0 Vector
Note the necessary conditions for an interrupt request to be elevated to highest priority: 1. A bit is set in the INTSRC register, 2. The corresponding bit is set in the FIEN register, and 3. The ICR ENABLE bit is set.
Board Design and the FPGA Device
4.1.2 Using the Periodic Interval Timer
The MAPI FPGA device includes a periodic interval timer (PIT), which can provide precise interrupts with minimal processor intervention. This timer can either count down from a modulus-latch value or be a free-running down counter. Figure 4-2 is a diagram of this PIT.
PITCSR
STOP STEP LO AD DBG O VW PITIE PITIF RLD
Figure 4-5 PIT Diagram NOTE: To use the PIT, you must set subswitches S5-1 and S5-2 OFF. Either subswitch set ON deactivates PIT functionality.
The PIT consists of a control block and three registers: · PIT data register (PITDR), which contains the timer modulus. Your code can set this modulus by writing to this register. Your code can find the modulus by reading from this register. PIT alternate data register (PITADR), which contains the current counter value. Your code can find the current timer value by reading from this register. PIT control / status register (PITCSR), which controls timer operation. Your code can control the timer by writing to or reading bits 8 through 1 of this register.
CMB2102 Design
Figure 4-6 shows the layout of the control / status register. Table 4-3 explains the control bits of the control / status register.
8 STOP
7 STEP
6 4 2 5 3 LOAD DBG OVW PITIE PITIF
Figure 4-6 PIT Control / Status Register Layout
Board Design and the FPGA Device
Table 4-3 Control / Status Register Bit Values
Bit Name
Reload Control (RLD)
Bit Value
Effect / Meaning
PIT Interrupt Flag (PITIF)
1 3 PIT Interrupt Enable (PITIE) Overwrite Enable (OVW) 0 1 4 0
Debug Mode (DBG) Load Counter (LOAD)
Step Counter (STEP)
Stop Counter (STOP)
NOTE:
Your code may not step a PIT counter from 1 to 0, nor may it step a PIT counter from 0 to the modulus latch value. Setting the counter value to 0 directly does not cause a PIT interrupt.
4.1.3 Port F Control Pins
The MAPI FPGA device has eight digital I / O pins, which are available for control functions. These pins, the edge-detect logic for each pin, and the controlling registers make up the port F module of the U11 device.
CMB2102 Design
Figure 4-7 Port F Edge Control Register Layout
Figure 4-8 Port F Data Direction Register Layout
Board Design and the FPGA Device
Figure 4-9 Port F Edge Detect Register Layout
Figure 4-10 Port F Data Register Layout A reset configures all port F pins as falling-edge-detect inputs. By writing to the PORTFC register, your code can make individual pins rising-edge detect. By writing to the DDR register, your code can make individual pins outputs. Your code can read the PORTFE register to determine which port F pins have detected their edge transitions. NOTE: Once set, a PORTFE register bit remains set until a reset clears it, or until your code writes a 0 to the bit. Before such clearing, subsequent changes to the corresponding port F pin have no effect on the register bit.
You code can read from or write to the PORTF register to control the functionality of the port F pins. · · · If the data direction is input, a read of PORTF returns the current values of the port F pins. If the data direction is input, a write to PORTF stores the data to be driven on the port F pins. If the data direction is output, a read of PORTF returns the current value of the PORTF register.
4.1.4 Address Decoder
The MAPI FPGA can expose a latched MLB to the MAPI ring. This capability permits communication with (and programming of) the configuration circuit of the MMCFPGA1200 board. This latch mode makes address, data, and control signals on the MAPI ring behave similarly to the way they would behave on a RIM interface. To configure this latch mode, set CMB2102 switch S5, subswitch 2 ON.
Configuring Your Software
4.2 Configuring Your Software
NOTE: The steps below are guidance for starting to use Altera MAX+plusII software. Should you have difficulty preparing your MAX+plusII software, phone Altera customer service for assistance.
Follow the steps below to prepare your Altera development software for use with your CMB2102. 1. Install the Altera development software, per the Altera instructions. 2. Obtain your Verilog authorization code, per the Altera instructions. (If you FAX registration information, this takes only a few hours Altera customer service can provide the FAX number.) 3. Start the Altera software. From the Windows desktop, click on Start, select Programs, select MAX+plusII, and select MAX+plusII again. 4. Open the Options menu and select Authorization Code. This brings up the Authorization Code dialog box. Enter your authorization code in the appropriate field. NOTE: Your authorization code is case sensitive. Make sure to use the correct capital or lower-case letters as your enter the code.
5. Click on the Validate button. The software verifies your authorization code, then displays your software guard ID number. Click on the OK button to close the dialog box. 6. The MAX+plusII main screen appears. If you are new to Altera software, you should go through the Altera tutorial. 7. This completes software preparation. You are ready to develop an application suitable for downloading to the CMB2102 U11 device.
Board Design and the FPGA Device
4.3 Reprogramming the FPGA Device
Follow steps 1 through 29, below, to develop an application suitable for downloading to the FPGA device at location U11. Most of these steps are typical for using the MAX+plusII software to develop any new application project. These steps are not rigid instructions. In case of difficulty using the MAX+plusII software, you should call Altera customer service for assistance. The transmittal CD-ROM that contains this manual also contains example application files: a symbol counter, a Verilog counter, and a Verilog port. 1. Use Windows Explorer to create and name a new folder for the project. 2. Start the MAX+plusII software. 3. Open the File menu and select Project. From the subordinate menu, select Name. This brings up the Project Name dialog box. 4. Use the Project Name dialog box to select the newly created project folder, and to enter a name for the project. (The project name should not contain any spaces usually it is convenient to give the project the same name as the folder.) Click on the OK button to close the dialog box. 5. Open the File menu and select New. This brings up the New dialog box. Select Text editor file, then click on the OK button. This closes the dialog box and opens the text editor window. 6. Write the Verilog code for your application. (Consult the Altera Verilog manuals for instructions.) 7. When your code is done, leave the text editor window open. Click on the Open Compiler Window toolbar button. The software immediately compiles your code. 8. If the compiler finds errors, correct them in the text editor window, then compile again. When compilation succeeds, your are ready to create a default symbol. 9. Still leaving the text editor window open, open the File menu and select Create Default Symbol. The software automatically creates a graphic representation of the compiled code, a symbol that you later can use in a schematic design. 10. Open the File menu and select Project. From the subordinate menu, select Name. This brings up the Project Name dialog box. 11. Use the Project Name dialog box to select the same folder you selected in Step 4. Enter a new project name: as this project will be for a .hex file, Motorola suggests that you append the letter h to the name you used in Step 4. Click on the OK button to close the dialog box. 12. Open the File menu and select New. This brings up the New dialog box. Select graphic editor file, then click on the OK button. This closes the dialog box and opens the graphic editor window.
Reprogramming the FPGA Device
Find the Configuration Device field: set the field value to be EPC2LC20. Elsewhere in the Individual Device Options dialog box, find the Configuration Scheme field: set the field value to be Passive Serial (can use Configuration Device). In the Not Affected By Configuration Scheme area, make sure that both CLKUSR boxes have grey check marks. Make sure that the only check marks are those that Steps a through d specify, then click on the OK button to return to the Device dialog box.
17. Click on the Device dialog box OK button to return to the main screen. This completes device assignment. You are ready to assign signals to pins. 18. It is best to give signals (wires) the same names as their corresponding pins. Open the Assign menu and select Pin / Location / Chip. This brings up the Pin / Location / Chip dialog box. a. Click on the Search button to bring up a subordinate dialog box that lists the pins. (Click on the LIST button to see the list.) The listed pin names are the inputs and outputs you created as part of Step 14.) Select (highlight) a pin, then click on the OK button. This returns you to the Pin / Location / Chip dialog box the selected pin name will be in the Node Name field. Go to the Chip Resource area of the dialog box. In the Pin field, enter the name of the FPGA pin. (This is the value in the U2 column of cross-reference table 6-5.)
Board Design and the FPGA Device
NOTE:
An alternative to using the Search button is to select Pin, activating the Pin Type field. Select the appropriate type from the small pull-down menu, then enter the pin name in the appropriate field, and enter the signal name in the Node Name field.
This completes assignment for the first pin. 19. Repeat Step 18 for all other signals. When you are done, close the Pin / Location / Chip dialog box. NOTE: For each finished design, the Altera software creates a .acf file: a text file that you can edit. For your first design, you must do Step 18 for each signal. But for subsequent designs, you can copy and edit a .acf file.
20. If you have not already done so, configure ByteBlaster programming hardware per Altera instructions. 21. Compile your application file again. When compilation succeeds, you are ready to create a .pof file. 22. Open the MAX+plusII menu and select Programmer. This brings up the Programmer dialog box. (You will not do anything in this dialog box, but it must be open at this point.) 23. Open the JTAG menu and select Multi-Device JTAG Chain Setup. This brings up the Multi-Device JTAG Chain Setup dialog box. a. Use the Device Name pull-down menu to select EPF10K100A, then click on the Add button. The EPF10K100A name appears in the list at the center of the dialog box, but without any associated programming. Use the Device Name pull-down menu to select EPC2, then click on the Select Programming File button. This brings up the Select Programming File dialog box. Use the Select Programming File dialog box to select the .pof file for your project. Click on the OK button to return to the Multi-Device JTAG Chain Setup dialog box. Click on the Add button. This dds the EPC2 name to the list at the center of the dialog box, showing the association with the selected .pof file. Click on the Save JCF button. This brings up a subordinate dialog box that lets you name and save the listed files as a JTAG chain file. Click on the OK button to return to the Multi-Device JTAG Chain Setup dialog box. Click on the Multi-Device JTAG Chain Setup dialog box OK button to return to the Programmer dialog box. This completes file creation you are ready to download the files to the FPGA device.
24. Apply power to your CMB2102. 25. Connect the ByteBlaster between CMB2102 connector J19 and a parallel port of your computer. Make sure that the red wire of the cable connects to J19 pin 1.
Reprogramming the FPGA Device
26. Click on the Program button of the Programmer dialog box. A percentage indicator shows the progress of downloading the files to a ROM device of the CMB2102. 27. At the end of this downloading, disconnect the ByteBlaster cable from connector J19. 28. Press CMB2102 switch S7 to transfer the downloaded application to the U11 FPGA device. 29. This completes reprogramming of the U11 device. You may close the MAX+plusII software.
Board Design and the FPGA Device
MAPI Connectors (P1 / J1, P2 / J2, P3 / J3, P4 / J4)
Section 5 Connector information
This chapter consists of pin assignments and signal descriptions for CMB2102 connectors.
5.1 MAPI Connectors (P1 / J1, P2 / J2, P3 / J3, P4 / J4)
Connectors P1 through P4, all 2-by-50-pin connectors, are the CMB2102 MAPI connectors. (Connectors J1 through J4, on the bottom of the CMB2102, have the same pin assignments.) The diagram below shows the orientation of the CMB2102 MAPI connectors. Figure 5-1 through Figure 5-4, and Table 5-1 through Table 5-4, give the pin assignments and signal descriptions for these connectors.
100 1 P4 100
Connector information
Figure 5-1 MAPI Connector P1 / J1 Pin Assignments
MAPI Connectors (P1 / J1, P2 / J2, P3 / J3, P4 / J4)
Table 5-1 MAPI Connector P1 / J1 Signal Descriptions
Mnemonic
PTJ1x Pass Through
Signal
+3.3-volt power. CHIP SELECTS (lines 4-9) - Active-low output lines that provide chip selects to external devices.
GROUND +5-volt power. EXTERNAL INTERRUPT VECTOR (lines 6-0) - Signals that make up the interrupt vector number. EXTERNAL INTERNAL VECTOR REQUEST - Signal that requests internal generation of the interrupt vector number. EXTERNAL NORMAL INTERRUPT - Normal interrupt request signal to the MAPI FPGA. EXTERNAL INTERRUPT PENDING - Signal indicating that a MAPI FPGA interrupt is pending. DEVELOPMENT SPACE 0 - Signal indicating access to development space 0. EXTERNAL NORMAL UNSYNCHRONIZED INTERRUPT - Signal that requests a normal unsynchronized interrupt.
MID0 - MID3 MAPI IDENTIFICATION CODE (lines 0-3) - Signals that identify the host processor board. The respective values 0, 1, 1, 0 indicate the CMB2102. PORTF7 - PORTF0 GND1 GND2 PORT F - Edge-detect I / O pins. GROUND - Connection to the Ground 1 plane. GROUND - Connection to the Ground 2 plane.
Connector information
PTJ2100 PTJ298 PTJ296 PTJ294 PTJ292 PTJ290 PTJ288 GND3 GND VDD3V PTJ280 PTJ278 PTJ276 PTJ274 PTJ272 PTJ270 PTJ268 PTJ266 GND VDD3V PTJ260 PTJ258 PTJ256 PTJ254 PTJ252 PTJ250 PTJ248 GND VDD3V PTJ242 PTJ240 PTJ238 PTJ236 PTJ234 PTJ232 PTJ230 PTJ228 PTJ226 PTJ224 PTJ222 VDD3V GND GND2 PTJ214 PTJ212 PTJ210 PTJ28 PTJ26 PTJ24 PTJ22 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 99 97 95 93 91 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 GND3 PTJ297 PTJ295 PTJ293 PTJ291 PTJ289 PTJ287 GND3 GND PTJ281 VDD5V PTJ277 PTJ275 PTJ273 PTJ271 PTJ269 PTJ267 PTJ265 GND PTJ261 PTJ259 PTJ257 PTJ255 PTJ253 PTJ251 PTJ249 PTJ247 VDD5V GND PTJ241 PTJ239 PTJ237 PTJ235 PTJ233 SDCPS VDD5V PTJ227 PTJ225 PTJ223 PTJ221 PTJ219 GND GND2 PTJ213 PTJ211 PTJ29 PTJ27 PTJ25 PTJ23 GND2
Figure 5-2 MAPI Connector P2 / J2 Pin Assignments
MAPI Connectors (P1 / J1, P2 / J2, P3 / J3, P4 / J4)
Table 5-2 MAPI Connector P2 / J2 Signal Descriptions
Mnemonic
PTJ2x Pass Through
Signal
GND3 GND VDD3V VDD5V SDCPS
GROUND - Connection to the Ground 3 plane. GROUND +3.3-volt power. +5-volt power. SHUT DOWN CMB POWER SUPPLY - Signal, from a connected board that supplies power, to disable the on-board CMB power supply. GROUND - Connection to the Ground 2 plane.
Connector information
Figure 5-3 MAPI Connector P3 / J3 Pin Assignments
MAPI Connectors (P1 / J1, P2 / J2, P3 / J3, P4 / J4)
Table 5-3 MAPI Connector P3 / J3 Signal Descriptions
Mnemonic
VDD3V PTJ3x +3.3-volt power Pass Through
Signal
MID9 - MID4 IDENTIFICATION CODE (lines 9-4) - Signals that identify the host processor (not in exact board. The respective values (bits 9 - 4) are 0, 0, 0, 1, 0, 0, indicating the order) CMB2102.
Connector information
Table 5-3 MAPI Connector P3 / J3 Signal Descriptions (Continued)
Mnemonic
Signal
MAPI Connectors (P1 / J1, P2 / J2, P3 / J3, P4 / J4)
Figure 5-4 MAPI Connector P4 / J4 Pin Assignments
Connector information
Table 5-4 MAPI Connector P4 / J4 Signal Descriptions
Mnemonic
VDD5V VDD3V PTJ4x GND +5-volt power. +3.3-volt power. Pass Through GROUND
Signal
CLOCK OUTPUT - Clock signal the CMB2102 provides for external devices. CHIP SELECTS (lines 3-0) - Active-low output lines that provide chip selects to external devices. OUTPUT ENABLE - Active-low signal that indicates that a bus access is a read access enables slave devices to drive the data bus. ENABLE BYTES 0, 1, 3, 2 - Active-low outputs active during an operation to corresponding data bits (D31-D24 for enable byte 0, D23-D16 for enable byte 1, D7-D0 for enable byte 3, D15-D8 for enable byte 2). You can configure these bytes to assert for write cycles or for both read and write cycles. READ / WRITE - Active-low signal indicating that the current bus access is a write access. TRANSMIT REQUEST - Active-low signal indicating an access request. The processor drives this signal. TRANSFER ERROR ACKNOWLEDGE - Active-low I / O signal that indicates a bus transfer error. The source of this signal is external to the core. TRANSFER ACKNOWLEDGE - Active-low I / O signal indicating completion of a data transfer, for either a read or a write cycle. The source of this signal is external to the core.
OnCE Connector (J29)
5.2 OnCE Connector (J29)
Connector J29, a 2-by-7-pin connector, conveys data and control signals to and from the OnCE control block. Figure 5-5 and Table 5-5 give the pin assignments and signal descriptions for this connector.
Figure 5-5 OnCE Connector J29 Pin Assignments
Table 5-5 OnCE Connector J29 Signal Descriptions
Mnemonic
Signal
Connector information
5.3 Logic Analyzer Connectors (J5, J8, J14)
Connectors J5, J8, and J14, all 2-by-19-pin Mictor connectors, are the logic analyzer connectors. Figure 5-6 through Figure 5-8 give the pin assignments for these connectors. Table 5-6 through Table 5-8 give the signal descriptions for these connectors.
Figure 5-6 Logic Analyzer Connector J5 Pin Assignments
Table 5-6 Logic Analyzer Connector J5 Signal Descriptions
Mnemonic
Signal
MAPI OUTPUT ENABLE - Active-low signal that indicates that a bus access is a read access enables slave devices to drive the data bus. This signal is driven from the MAPI address space. TRANSFER REQUEST - Active-low signal indicating a new access request. The processor drives this signal. TRANSFER CODE (lines 2-0) - Signals indicating the general type of transfer. TRANSFER SIZE (lines 1, 0) - Signals that indicate the size of an external transfer. SEQUENTIAL ACCESS - Active-low signal indicating that a sequential access is in progress. PROCESSOR STATUS (lines 3-0) - Output signals that provide external status indications for the processor.
Logic Analyzer Connectors (J5, J8, J14)
Table 5-6 Logic Analyzer Connector J5 Signal Descriptions (Continued)
Mnemonic
Signal
MASTER RESET - Active-low signal indicating a core master reset. BUS GRANT - Active-low output signal that grants MLB ownership to an alternate master. PROCESSOR ABORT - Active-low signal indicating a core transfer abort. TRANSFER BUSY - Active-low signal indicating that