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MMCCMB2102 Controller Memory Board (CMB2102) User's Manual
Motorola reserves right make changes without further notice products herein improve reliability, function design. Motorola does assume liability arising application product circuit described herein; neither does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative
name logo OnCE name trademarks Motorola, Inc. other trademarks belong their respective owners. Motorola, Inc. 2000
CAUTION: Protection
development systems include open-construction printed circuit boards that contain static-sensitive components. These boards subject damage from electrostatic discharge (ESD). prevent such damage, must static-safe work surfaces grounding straps, defined ANSI/EOS/ESD S6.1 ANSI/EOS/ESD S4.1. handling these boards must accordance with ANSI/EAI 625.
MOTOROLA
MMCCMB2102UM/D User's Manual
Contents
Section Introduction
CMB2102 Features System User Requirements CMB2102 Layout
Section Configuration
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 Configuring Board Components Setting Core FPGA Configuration Header (W6) Setting Function Jumper Header (W7) Setting Clock Select Jumper Header(W12) Setting Core Configuration Mode Switch (S3) Setting Memory Configuration Switch (S4) Setting Pass Enable Switch (S5) Setting Software Select Switch (S6) Making Computer-System Connections Performing CMB2102 Selftest Memory
Section Operation
Debugging Embedded Code 3.1.1 Using Picobug Monitor 3.1.2 Picobug Sample Session 3.1.3 Using Source-Level Debugger Downloading FLASH Memory 3.2.1 Using SysDS Loader 3.2.2 Restoring System Software Controlling CMB2102 LEDs
MMCCMB2102UM/D User's Manual
Section Board Design FPGA Device
CMB2102 Design 4.1.1 Using Interrupt Controller 4.1.2 Using Periodic Interval Timer 4.1.3 Port Control Pins. 4.1.4 Address Decoder Configuring Your Software Reprogramming FPGA Device.
Section Connector information
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4) OnCE Connector (J29) Logic Analyzer Connectors (J5, J14) Core FPGA Configuration Connector (J9) Memory Controller Connector (J12) MAPI FPGA Configuration Connector (J19) RS232 Connectors (J27, J28)
Section Cross Reference Tables Index
MMCCMB2102UM/D User's Manual
Figures
4-10 5-10 5-11
MMCCMB2102 Computer Memory Board SysDS Loader Main Screen Upload File Dialog Display FLASH/RAM Display. Functionality Diagram Interrupt Controller Diagram Interrupt Source Register Layout Interrupt Control Register Layout. Diagram Control/Status Register Layout Port Edge Control Register Layout Port Data Direction Register Layout Port Edge Detect Register Layout Port Data Register Layout MAPI Connector P1/J1 Assignments MAPI Connector P2/J2 Assignments MAPI Connector P3/J3 Assignments MAPI Connector P4/J4 Assignments OnCE Connector Assignments Logic Analyzer Connector Assignments Logic Analyzer Connector Assignments Logic Analyzer Connector Assignments Core Configuration Connector Assignments Memory Controller Connector Assignments MAPI FPGA Configuration Connector Assignments
MMCCMM2102UM/D User's Manual
MMCCMM2102UM/D User's Manual
Tables
5-10 5-11 5-12
MMCCMB2102 Controller Memory Board Specifications Component Configuration Settings Core Configuration Mode Switch Positions Wait State Switch Positions Subswitch Settings. CMB2102 Selftest Sequence CMB2102 Default Memory FLASH Sector Boundaries Picobug Commands Interrupt, PIT, Port Addresses Interrupt Source Assignments. Control/Status Register Values MAPI Connector P1/J1 Signal Descriptions MAPI Connector P2/J2 Signal Descriptions MAPI Connector P3/J3 Signal Descriptions MAPI Connector P4/J4 Signal Descriptions OnCE Connector Signal Descriptions Logic Analyzer Connector Signal Descriptions Logic Analyzer Connector Signal Descriptions. Logic Analyzer Connector Signal Descriptions. Core Configuration Connector Signal Descriptions Memory Controller Connector Signal Descriptions. MAPI FPGA Confoguration Connector Signal Descriptions RS232 Connector J27, Assignments Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring Cross Reference: MAPI Ring, MAPI FPGA, Core FPGA Cross Reference: MAPI Ring, MAPI FPGA, Core FPGA Cross Reference: MAPI FPGA Pins Cross Reference: MAPI, MAPI FPGA, FPGA Board
MMCCMB2102UM/D User's Manual
MMCCMB2102UM/D User's Manual
CMB2102 Features
Section Introduction
This user's manual explains connection, configuration, operation information MMCCMB2102 Controller Memory Board (CMB2102), development tool Motorola's CMB2102 uses RS232 connection your computer. This connection lets Motorola's System Development Software (SysDS) source-level debugger. SysDS consists loader, Picobug monitor, built-in selftest. CMB2102 also OnCEconnector, enabling debugging application that requires one. Optionally, CMB2102 with several other emulator products. Motorola's SysDS Loader lets download your code into CMB2102's SRAM (for execution) FLASH memory (for execution storage non-volatile memory). Should your application overwrite system software FLASH memory device, SysDS Loader restore system software. CMB2102 will combine easily with other, optional development boards from Motorola. factory ships such boards with CMB2102: MMCLAB01 Logic Analyzer Board, MMCFPGA1200 Field Programmable Gate Array Peripheral Board. (Another compatible board MMCPFB1200 Platform Board.) Such optional boards expand CMB2102 capacity, enhance CMB2102 performance, CMB2102 features.
CMB2102 Features
CMB2102 features: XILINX FPGA device, configured Motorola M210S core. megabytes FLASH memory. megabytes FSRAM (fast static RAM). Altera EPF10K FPGA device, with configuration chip. Power regulators that provide three voltages: 3.3, 2.5. Power supply that converts line power 12-volt power. RS232 channels serial communications. These channels on-board universal asynchronous receiver/transmitter (UART). MAPI connector interface ring, bottom CMB2102, easy connection other, compatible development boards. Motorola's SysDS. source-level debugger (from Free Software Foundation).
MMCCMB2102UM/D User's Manual
Introduction
Three 38-pin Mictor logic analyzer connectors. Altera ByteBlaster cable (for connector J19). Altera Max+plusII software.
System User Requirements
need compatible computer, running Windows WindowsNT (version 4.0) operating system. computer requires Pentium equivalent) microprocessor, megabytes RAM, megabytes free hard-disk space, SVGA color monitor, RS232 serial-communications port. Picobug monitor, also need Hyperterminal comparable terminal-emulation program. most from your CMB2102, should experienced assembly programmer. Your CMB2102 requires 12-volt input power, ampere. power supply that comes with your CMB2102 provides this voltage from line power.
CMB2102 Layout
Figure shows layout CMB2102. board FPGA devices: XILINX FPGA device, location acts M210S core. Accordingly, this core FPGA device. Altera FPGA device, location U11, provides address conditioning most communication between MAPI connectors core FPGA device. Accordingly, device MAPI FPGA device.
Connectors through board, MAPI interrupt connectors (the corresponding MAPI connectors bottom CMB2102 through J4). Connectors logic analyzer connectors. Connector supplying external configuration data core FPGA device. (This requires user-supplied XILINX in-system programming cable software.) Connector reprogramming memory-controller device location (This requires user-supplied Vantis cable software.) Connector in-circuit programming MAPI FPGA device. (This requires Altera ByteBlaster cable supplied with your CMB2102.) Connector connector external clock signal. Connectors RS232 serial connectors. Connector OnCE connector. Connector connector 12-volt input power.
MMCCMB2102UM/D User's Manual
CMB2102 Layout
DS10
DS11 DS12
Figure MMCCMB2102 Computer Memory Board Switch emulates power-on-reset condition. Switch starts configuration core FPGA device. Switch selects configuration mode core FPGA device. Switch memory configuration switch. Switch pass enable switch. Switch global status switch. Switch starts configuration MAPI FPGA device. Switch reset switch. Location CMB2102 fuse. LEDs indicate low-power mode (bits respectively). LEDs through indicators global control bits GCB0 through GCB3. indicates debug mode. indicates that configuration core FPGA device progress. LEDs DS9, DS10, DS11 confirm power three voltage planes: 5-volt, 2.5-volt, 3.3-volt, respectively. DS12 indicates that configuration MAPI FPGA device progress.
MMCCMB2102UM/D User's Manual
Introduction
Jumper header source configuration data core FPGA device. Jumper header enables several board functions. Jumper header selects clock-signal source. Table lists CMB2102 specifications. Table MMCCMB2102 Controller Memory Board Specifications
Characteristic
extension ports Operating temperature Storage temperature Relative humidity Clock Power requirements Dimensions -40° +85° (non-condensing) volts ampere, provided from separate power source inches (175
Specifications
HCMOS compatible
MMCCMB2102UM/D User's Manual
Configuring Board Components
Section Configuration
This section explains configure your CMB2102, hook your computer system.
Configuring Board Components
Configuring your CMB2102 involves setting several components. Table summary these settings; subsections 2.1.1 through 2.1.7 give additional information. Table Component Configuration Settings
Component
Core FPGA Configuration Header,
Position
Effect
Selects on-board devices source core FPGA (U1) configuration data. (Appropriate master-serial mode.) Factory setting. Selects external source core FPGA (U1) configuration data, connector (Appropriate boundary scan slave-serial mode.) Enables four functions: MAPI, DUART, FSRAM, FLASH. Factory setting.
Function Jumper Header, (The four jumpers independent.)
Enables MAPI, DUART, FLASH functionality, disables FSRAM functionality. (One many possible configurations.)
Enables MAPI FSRAM functionality, disables DUART FLASH functionality. (Another many possible configurations.)
MMCCMB2102UM/D User's Manual
Configuration
Table Component Configuration Settings (Continued)
Component
Function Jumper Header, (continued)
Position
Effect
Disables four functionalities. (Another many possible configurations.)
Clock Select Header,
Selects 8-megahertz oscillator (Y1) clock source. Factory setting. Selects external clock signal connected J24.
Power Reset Switch,
Push emulate power reset.
Core Configuration Switch,
Push start configuration core FPGA device.
Core Configuration Mode Switch,
Selects master-serial mode.
jumper must installed.) Factory setting. Selects boundary scan mode, external configuration data connector
jumper must removed; user-supplied XILINX cable software required.) Selects slave-serial mode, external configuration data connector
jumper must removed; user-supplied XILINX cable software required.)
MMCCMB2102UM/D User's Manual
Configuring Board Components
Table Component Configuration Settings (Continued)
Component
Memory Configuration Switch,
Position
Effect
Specifies starting address 0000_0000, default FLASH/SRAM positions, cycle waits. (One many possible configurations.) Factory setting.
Specifies starting address 8000_0000, default FLASH/SRAM positions, cycles waits. (Another many possible configurations.)
Specifies starting address 0000_0000, swapped FLASH/SRAM positions, cycle waits. (Another many possible configurations.)
Specifies starting address 8000_0000, swapped FLASH/SRAM positions, cycles waits. (Another many possible configurations.)
Pass Enable Switch,
Passes INT-bus signals directly device, without processing latching. Enables MAPI FPGA outputs configured. (One many possible configurations.) Factory setting.
MMCCMB2102UM/D User's Manual
Configuration
Table Component Configuration Settings (Continued)
Component
Pass Enable Switch, (continued)
Position
Effect
Passes INT-bus signals directly device, without processing. Latches signals from device before sending them MAPI ring. Tri-states MAPI FPGA outputs. (Another many possible configurations.) Passes INT-bus signals directly device, without processing latching. Tri-states MAPI FPGA outputs. (Another many possible configurations.)
Processes INT-bus signals before sending them device. Latches signals before sending them device. Enables MAPI FPGA outputs. (Another many possible configurations; correct configuring FPGA peripheral board.) Specifies built-in selftest, executed FLASH, upon reset. (One many possible configurations.) Factory setting.
Software Select Switch,
Specifies programmer, executed FLASH, upon reset. (Another many possible configurations.)
Specifies Picobug, executed FSRAM, upon reset. (Another many possible configurations.)
MMCCMB2102UM/D User's Manual
Configuring Board Components
Table Component Configuration Settings (Continued)
Component
Software Select Switch, (continued)
Position
Effect
Specifies user code, executed FSRAM, upon reset. (Another many possible configurations.)
MAPI Configuration Switch,
Push start configuration MAPI FPGA device.
Reset Switch,
Push reset board.
2.1.1 Setting Core FPGA Configuration Header (W6)
Jumper header specifies configuration-data source core FPGA device (location U1). diagram below shows factory configuration: installed jumper specifies on-board devices configuration source.
Alternatively, specify external source configuration data, connector remove jumper from header NOTE: Supplying configuration data from external source requires user-supplied XILINX cable user-supplied XILINX software. This action requires that jumper removed that switch specify boundary scan slave-serial configuration mode. Make sure that jumper installed switch specifies master-serial configuration mode.
MMCCMB2102UM/D User's Manual
Configuration
2.1.2 Setting Function Jumper Header (W7)
Jumper header enables disables these board functions: MAPI, DUART, FSRAM, FLASH. diagram below shows factory configuration: four jumpers enable four functions.
MAPI DUART FSRAM FLASH
disable function, remove corresponding jumper: disable FLASH memory, remove jumper from pins disable FSRAM, remove jumper from pins disable DUARTs, remove jumper from pins disable MAPI connection, remove jumper from pins
2.1.3 Setting Clock Select Jumper Header(W12)
Jumper header selects source CMB2102 clock signal. diagram below shows factory configuration: jumper between pins selects 8-megahertz canned oscillator board location
CLKSEL
Alternatively, supply external clock signal. Connect external clock signal connector J24, Reposition jumper pins
MMCCMB2102UM/D User's Manual
Configuring Board Components
2.1.4 Setting Core Configuration Mode Switch (S3)
Switch specifies configuration mode core FPGA device (U1). diagram below shows factory configuration: subswitches CMD0, CMD1, CMD2 position. (The position CMD3 subswitch irrelevant.) This configures master-serial mode.
CMD0 CMD1 CMD2 CMD3
Table explains other positions subswitches. Note that must configure jumper header appropriately each mode. Table Core Configuration Mode Switch Positions
CMD0 Subswitch CMD1 Subswitch CMD2 Subswitch Configuration Mode
Master-serial jumper must installed.) Boundary scan jumper must removed.) Slave-serial jumper must removed.)
NOTE:
Boundary scan slave-serial modes appropriate only supply configuration data from external source, connector Doing requires user-supplied XILINX cable user-supplied XILINX software.
MMCCMB2102UM/D User's Manual
Configuration
2.1.5 Setting Memory Configuration Switch (S4)
Switch selects several memory-configuration aspects. diagram below shows factory configuration: subswitches position. This configures: Addressable memory beginning with address 0x0000_0000. FLASH memory before (that having lower addresses than) FSRAM. (This unswapped position these memory blocks.) wait state clock cycles FLASH memory accesses.
HI/LO SWAP SEL1 SEL0
four subswitches control three configuration aspects: HI/LO subswitch specifies starting address memory map: specifies starting address 0x0000_0000. specifies starting address 0x8000_0000. SWAP subswitch specifies whether FLASH FSRAM starts memory map: configures unswapped position: FLASH starts memory map; FSRAM follows FLASH. configures swapped positions: FSRAM starts memory map; FLASH follows FSRAM. SEL0 SEL1 subswitches determine number cycles waits FLASH memory accesses. Table explains settings. Table Wait State Switch Positions
Cycles Waits SEL0 Subswitch SEL1 Subswitch
MMCCMB2102UM/D User's Manual
Configuring Board Components
2.1.6 Setting Pass Enable Switch (S5)
Switch controls passing methods interrupt-bus (INT-bus) signals local-bus (MLB) signals. diagram below shows factory configuration. Both IPASS MPASS subswitches directs CMB2102 pass these signals directly from MAPI ring device, without processing latching. subswitch enables MAPI FPGA outputs configured.
MPASS IPASS
NOTE:
subswitch pins connected.
INT-bus signals another subset many available MAPI connectors, subset related interrupts. IPASS subswitch specifies what FPGA device once receives these signals from MAPI ring. IPASS subswitch OFF, FPGA device passes INT-bus signals directly device, without processing. IPASS subswitch FPGA device processes INT-bus signals before sending them device.
signals subset those available MAPI connectors, subset related external connections. MPASS subswitch specifies what FPGA device once receives these signals from MAPI ring. MPASS subswitch OFF, FPGA device passes unlatched signals directly device. (Chip selects available this mode.) MPASS subswitch FPGA device latches signals before sending them device.
subswitch specifies whether MAPI FPGA outputs tri-stated. subswitch OFF, enables MAPI FPGA outputs configured. subswitch tri-states MAPI FPGA outputs.
MMCCMB2102UM/D User's Manual
Configuration
2.1.7 Setting Software Select Switch (S6)
Switch specifies software upon reset, where that software executed. diagram below shows factory configuration: GSB3 subswitch specifies execution FLASH memory; subswitches GSB2 through GSB0 specify built-in selftest.
GSB3 GSB2 GSB1 GSB0
specify execution FSRAM, GSB3 subswitch OFF. specify different software module, reposition subswitches GSB2 through GSB0 Table 2-4. Table Subswitch Settings
Software Module Built-in selftest Programmer Picobug User code GSB2 Subswitch GSB1 Subswitch GSB0 Subswitch
Making Computer-System Connections
When have configured your CMB2102, ready connect your computer system: Make sure that power disconnected. will RS232 communication with your host computer, connect RS232 cable between CMB2102 connector appropriate serial port your computer. Communication settings computer serial port must 19200 baud, bits, parity, stop bit, flow control. (Optional: your application must have higher UART addresses, connector your RS232 communication.) will OnCE-compatible emulator with your CMB2102, connect appropriate 14-lead ribbon cable between CMB2102 connector your emulator. Then appropriate cable connect your emulator your host computer.
MMCCMB2102UM/D User's Manual
Making Computer-System Connections
CMB2102 with another, compatible development board (such MMCFPGA1200, which factory ships with your CMB2102). must connect boards their MAPI rings. Hold CMB2102 directly above other board. Turn CMB2102 that right-triangle silk screen markings line Then press CMB2102 down onto other board. CMB2102 connectors through bottom board, must connect with corresponding MAPI connectors through other board. (Optional) logic analyzer with CMB2102, connect appropriate cable logic analyzer connectors: J14. cable must terminate with compatible connector, such Tektronix P6434 Hewlett-Packard E5346A. Section includes assignments cable descriptions logic analyzer connectors. (Optional) will supply external clock signal, connect cable CMB2102 connector J24. subsection 2.1.6 explains, also must position jumper between pins (Optional) will supply core FPGA configuration data from external source, must provide appropriate XILINX cable software. Connect cable CMB2102 connector follow XILINX instructions other cable connections. subsections 2.1.1 2.1.4 explain, also must remove jumper from header configure switch boundary scan slave-serial mode.) (Optional) will reconfigure memory controller, must provide appropriate Vantis in-system programming (ISP) cable software. Connect cable CMB2102 connector J12; follow Vantis instructions other cable connections using software. Make sure that your +12-volt power supply disconnected from line power. Connect power supply's cable CMB2102 connector J30. Connect power supply line power. LEDs DS9, DS10, DS11 light, confirming 5-volt, 2.5-volt, 3.3-volt power, respectively. lights briefly, during core FPGA configuration. DS12 flashes briefly, during MAPI FPGA configuration. Should power LEDs light, need replace fuse location next power connector J30. (Use GMA-1.5A fuse, compatible.) Status LEDs through light according switch setting. example, specifies programmer, DS3, DS4, while flickers rapidly. specifies Picobug, DS3, DS5, while OFF. specifies built-in selftest, status LEDs begin patterns subsection explains. This completes system connections; ready perform selftest, instructions subsection 2.3, below. ready begin debugging other development activities, instructions Section
MMCCMB2102UM/D User's Manual
Configuration
(Optional) scope observation specific interrupt signals, connectors through clip individual lines pins these connectors, appropriate connectors. MMCLAB01 logic analyzer board provides easy access MAPI-pin signals. Section gives assignments signal descriptions these connectors.)
Performing CMB2102 Selftest
Once have configured your CMB2102, perform selftest components. NOTE: open Hyperterminal, instructions subsection 3.1.1, Hyperterminal displays progress selftest. Should selftest fail, Hyperterminal indicates address which test failed.
Make sure that CMB2102 power turned disconnected. power LEDs DS9, DS10, DS11 should out. Make sure that jumper installed header Make sure that switch selects master-serial core configuration mode: CMD0, CMD1, CMD2 subswitches switch built-in selftest: subswitches Apply power. Green LEDs DS9, DS10, DS11 come confirm power. lights briefly, during core FPGA configuration. DS12 flashes briefly, during MAPI FPGA configuration. CMB2102 begins selftest: LEDs through light during test, according sequence Table 2-5. normal operation, LEDs always ON.) Table CMB2102 Selftest Sequence
(GCB0)
(GCB1)
(GCB2)
(GCB3)
MMCCMB2102UM/D User's Manual
Memory
When four LEDs this sequence, CMB2102 passed selftest. LEDs stay lit, CMB2102 failed selftest: contact Motorola customer support assistance.) Turn power. Configure switch your next development activity before restoring power CMB2102.
Memory
Table default memory your CMB2102.
MMCCMB2102UM/D User's Manual
Configuration
Table CMB2102 Default Memory
Address Range
0x0000_0000 0x003F_FFFF 0x0040_0000 0x005F_FFFF 0x0060_0000 0x0060_7FFF 0x0060_8000 0x0060_FFFF 0x0061_0000 0x0061_FFFF 0x1000_0000 0x107F_FFFF 0x1080_0000 0x10FF_FFFF 0x1100_0000 0x117F_FFFF 0x1180_0000 0x11FF_FFFF 0x1200_0000 0x127F_FFFF 0x1280_0000 0x12FF_FFFF 0x1300_0000 0x137F_FFFF 0x1380_0000 0x13FF_FFFF 0x1400_0000 0x147F_FFFF 0x1480_0000 0x14FF_FFFF 0x1500_0000 0xFFFF_FFFF
Contents
FLASH (4M)
Related Signals
FLASH_CS_b FSRAM_CS_b DUART_CS_b (ADDRESS[15]=0 selects UART DUART_CS_b (ADDRESS[15]=1 selects UART ICPP_CS_b (internal MAPI_FPGA)
Fast SRAM (2M) UART UART Interrupt controller/PIT/Port CSBAR_b[1:0]2 Chip select (8MB) Chip select (8MB) Chip select (8MB) Chip select (8MB) Chip select (8MB) Chip select (8MB) Chip select (8MB) Chip select (8MB) Chip select (8MB) Chip select (8MB)
(not defined) CS_b[0] (base address re-programmable) CS_b[1] (base address re-programmable) CS_b[2] CS_b[3] CS_b[4] CS_b[5] CS_b[6] CS_b[7] CS_b[8] CS_b[9] (not defined)
NOTES: Table lists sector (block) boundaries. Section explains individual addresses register fields this range.
MMCCMB2102UM/D User's Manual
Memory
Table FLASH Sector Boundaries
Sector (Block)
Range
0x0000_0000 0x0000_FFFF 0x0001_0000 0x0001_7FFF 0x0001_8000 0x0001_FFFF 0x0002_0000 0x0003_FFFF 0x0004_0000 0x0007_FFFF 0x0008_0000 0x000B_FFFF 0x000C_0000 0x000F_FFFF 0x0010_0000 0x0013_FFFF 0x0014_0000 0x0017_FFFF 0x0018_0000 0x001B_FFFF 0x001C_0000 0x001F_FFFF 0x0020_0000 0x0023_FFFF 0x0024_0000 0x0027_FFFF 0x0028_0000 0x002B_FFFF 0x002C_0000 0x002F_FFFF 0x0030_0000 0x0033_FFFF 0x0034_0000 0x0037_FFFF 0x0038_0000 0x003B_FFFF 0x003C_0000 0x003F_FFFF
Size (Kbytes)
Boot code Programmer
Contents
Built-in selftest Device drivers Reserved Picobug Reserved User code User code User code User code User code User code User code User code User code User code User code User code
MMCCMB2102UM/D User's Manual
Configuration
MMCCMB2102UM/D User's Manual
Debugging Embedded Code
Section Operation
This chapter explains begin using debugging tools available your MMCCMB2102 Controller Memory Board, well Motorola's SysDS Loader.
Debugging Embedded Code
With your CMB2102, Picobug monitor, standalone software. Optionally, source-level debugger with Picobug monitor. Other firms produce still additional software run, test, modify code develop embedding MMC2102 MCU. Motorola System Development Software download transfer control your code, must careful program only ranges FLASH memory SRAM that allocated user code. Programming over ranges that contain system software data storage would impair destroy usefulness software. (Subsection identifies contents memory ranges; subsection explains SysDS Loader restore system software.)
3.1.1 Using Picobug Monitor
Picobug debug monitor comes burned into FLASH memory device your CMB2102. Before start Picobug monitor, make sure that have RS232 connection between CMB2102 connector serial port your computer. start Picobug monitor, standalone debugger: switch Picobug monitor: subswitch GSB2 subswitch GSB1 OFF, subswitch GSB0 subswitch GSB3 specify execution FLASH. Apply power your CMB2102 press reset switch), then press enter key. Picobug monitor starts automatically, displaying command prompt: picobug>. Activate Hyperterminal comparable terminal-emulation program. different terminal-emulation program, must make corresponding changes commands menu selections these instructions, instructions paragraph 3.1.2.) From File menu, select Properties. This opens properties dialog box. Click Configure button dialog box. This opens configuration dialog box. configuration dialog make these communications settings: 19,200 baud, bits, parity, stop bit, flow control. Also correct communications port (for example, COM1). Click button dialog box.
MMCCMB2102UM/D User's Manual
Operation
Picobug debug monitor, merely enter commands prompt. Table explains these commands. list these commands your computer screen, enter question mark extra command command prompt. Table Picobug Commands
Command
[address]
Explanation
Breakpoint: With optional address value, sets breakpoint that address. Without address value, lists current breakpoints. With optional address value, starts code execution from that address. Without address value, starts code execution from current program-counter value. either case, execution stops when arrives breakpoint. Return: Executes code from current program-counter value return address calling routine. (Should execution arrive breakpoint before encountering return address, execution stops breakpoint.) Address: Executes code from current program-counter value specified address value. (Should execution arrive breakpoint before encountering specified address, execution stops breakpoint.) Help Displays available commands, identical command. Download: With optional address value, downloads binary image that address SRAM. Without address value, downloads SRAM S-record text file. Memory Display: With optional address1 address2 values, displays memory contents between addresses. With optional address1 value, displays contents memory bytes. With address value, defaults last address viewed. optional size value specifies format: (bytes, default), (half words), (words), (instructions). Memory Display 256: With optional address value, displays contents memory bytes, starting that address. With address value, displays contents memory bytes, starting from last address viewed. Modify Memory: With optional address value parameter values, assigns that value address location. With optional address value value parameter value, prompts value address location, then prompts value next location. stop modification, enter period instead value. With optional address value, prompts value last address viewed, then prompts value next location. stop modification, enter period instead value. optional size value, specifies format: (bytes, default), (half words), (words), (instructions).
[address]
address
[address]
[address1 [address2]] [;size]
[address]
[address [value]] [;size]
MMCCMB2102UM/D User's Manual
Debugging Embedded Code
Table Picobug Commands (Continued)
Command
nobr [address]
Explanation
Breakpoint: With optional address value, removes breakpoint from that address. Without address value, removes breakpoints. Reset: Resets peripherals. Register Display: With optional name value, displays value that register. Without name value, displays values registers. Register Modify: Assigns value parameter value name register. Trace (Step): Single steps instruction; identical command. Step (Trace): Single steps instruction; identical command. Help Displays available commands, identical command.
reset [name]
name value
3.1.2 Picobug Sample Session
This sample session begins with Picobug prompt:
picobug
contents registers, enter Register Display (rd) command without name value:
picobug>
system responds with display such this:
0041d000 80000000 ss0-ss4 bad0beef r0-r7 bad0beef r8-r15 00406024 epsr 00010000 00000400 00010050 ffffffff ffffffff ffffffff 00010000 0000000f fpsr ffffffff 00403f34 00000080 ffffffff ffffffff ffffffff 00403b24 ffffffff 7ffffff6 00000012 00403c00 00000020 00000012 00408000 000000b2
MMCCMB2102UM/D User's Manual
Operation
contents specific register, such register, enter Register Display (rd) command with name value:
picobug>
system responds with display such this:
epc: FFFFFFFF
contents specific memory location, enter Memory Display (md) command with location address. optional size value this case word) part command:
picobug> 0x0041d000
system responds with display such this:
0041D000: 710E1210
contents memory range, enter Memory Display (md) command with beginning ending addresses. optional size value this case byte) part command:
picobug> 0x0041d000 0x0041d010
system responds with display such this:
0041D000: 0041D010:
download into SRAM program executable, S-record format, enter Download (lo) command without address value:
picobug>
system waits send program executable file. open Transfer menu select Send Text File. This opens file-select dialog box. this dialog specify appropriate S-record file, then click Open button. soon download complete (this take several minutes), Picobug prompt reappears:
picobug>
contents registers, enter Register Display (rd) command again, without name value:
picobug>
MMCCMB2102UM/D User's Manual
Debugging Embedded Code
system responds with updated display, which shows that register value reflects start program just downloaded:
0041d000 80000000 ss0-ss4 bad0beef r0-r7 bad0beef r8-r15 00406024 epsr 00010000 00000400 00010050 ffffffff ffffffff ffffffff 00010000 0000000f fpsr ffffffff 00403f34 00000080 ffffffff ffffffff ffffffff 00403b24 ffffffff 7ffffff6 00000012 00403c00 00000020 00000012 00408000 000000b2
breakpoint address 0x0041D056, enter this address part Breakpoint (br) command:
picobug> 0x0041d056
Picobug prompt reappears, confirming that system breakpoint:
picobug>
list breakpoints, enter Breakpoint (br) command without address value:
picobug>
system responds with addresses breakpoints, this case only breakpoint step
0041D056
start program execution, enter command:
picobug>
this instance, breakpoint during step stops code execution. system responds with this display register values:
breakpoint!! 0041d056 80000101 ss0-ss4 bad0beef r0-r7 0041eff0 r8-r15 0041eff0 0041D056: 7F13 epsr 00010000 0041f000 00010050 jsri 0041d056 80000101 ffffffff 00010000 0000000f 0x0041d0e2 fpsr ffffffff 00403f34 00000080 ffffffff ffffffff ffffffff 00403b24 ffffffff 7ffffff6 00000012 00403c00 00000020 00000012 00000000 0041d04a
remove breakpoints, enter Breakpoint (nobr) command, without address value:
picobug> nobr
Picobug prompt reappears, confirming that system removed breakpoints:
picobug>
MMCCMB2102UM/D User's Manual
Operation
list breakpoints again, once more enter Breakpoint (br) command without address value:
picobug>
there longer breakpoints, system responds with Picobug prompt:
picobug>
continue with this example session, enter another appropriate command. example, resume program execution, enter command. your Picobug session, remove power from close terminal-emulation program.
3.1.3 Using Source-Level Debugger
source-level debugger CD-ROM that comes with your CMB2102. This software works with Picobug debug monitor provide source-level debugging your code. CMB2102 software release guide gives instructions loading software, making connections different from standalone Picobug connections.
Downloading FLASH Memory
Motorola SysDS Loader lets program code into FLASH memory, upload FLASH contents file, verify that FLASH contents match those download file, display memory contents, erase FLASH memory, erase sector FLASH memory, blank check sector FLASH memory.
3.2.1 Using SysDS Loader
Follow these steps Loader: have already installed Loader onto your computer hard disk, CMB2102 product release guide includes installation instructions. Important: Hyperterminal emulation program running, stop program. (The SysDS Loader needs same computer serial port that Hyperterminal uses.) switch Picobug monitor: GSB2 subswitch GSB1 subswitch OFF, GSB0 subswitch subswitch GSB3 specify execution FLASH. Press switch reset CMB2102.
MMCCMB2102UM/D User's Manual
Downloading FLASH Memory
Start SysDS Loader. main screen (Figure 3-1) appears.
Figure SysDS Loader Main Screen File name field FLASH/RAM page. know full pathname file programmed, enter pathname this field. know full pathname file programmed, click Browse button. This brings standard file-select dialog box: select file click button. This returns FLASH/RAM page, entering pathname File name field. your only action this Loader session will restoring system software, leave File name field blank.)
Make sure that SYSTEM field shows value CMB/EVB2102.
MMCCMB2102UM/D User's Manual
Operation
Flash area configure FLASH type (AMD29LL800), width (32), size (4MB). value Base Address field automatic, according entry SYSTEM field. (Optionally, select value <CUSTOM>, which brings Custom Address dialog box. Enter appropriate address, then click dialog button return FLASH/RAM page.) Communications area, Port field specify serial port, Speed field specify communications rate. (The default rate 19200 baud.) program FLASH memory, click Download button. software downloads file specified, progress message appears Status dialog box. Download successful message appears downloading: ready code FLASH memory. this first action this SysDS loader session, software downloads algorithm file before downloading file specified. progress message appears during downloading this algorithm file. software cannot find algorithm file, appropriate error message identifies file. Click message's button bring file-select dialog box, then this dialog specify location algorithm file. necessary, recopy file from transmittal CD-ROM. Click button resume programming FLASH memory. error message Unable Validate Flash configuration indicates some problem with programming. likely such problem that chip select base address does correspond configured chip select. Correct problem, then click again Program button.
upload FLASH memory contents file your click Upload button. This brings Upload File dialog box, Figure 3-2:
Figure Upload File Dialog
MMCCMB2102UM/D User's Manual
Downloading FLASH Memory
Enter name destination file. Optionally, click Browse button, select file standard file-select dialog box. Start Address field indicates start CMB2102 FLASH memory. default address value corresponds value SYSTEM field main screen FLASH/RAM page, enter different address, appropriate. Size Bytes field value corresponds value Size field FLASH/RAM page. system determines value Address field from Start Address Size bytes values. default Mode filed value Byte. When Upload File dialog shows appropriate values, click Save button. progress message appears during uploading. uploaded values include addresses ASCII representations.
NOTE:
verify that contents Flash memory match selected download file, click Verify button. progress message appears verification begins. Verify successful message appears verification. this first action this SysDS loader session, software downloads algorithm file before verifying FLASH. progress message appears during downloading this algorithm file. (Should software unable find algorithm file, appropriate error message appears, explained under program FLASH memory step, above.) verification fails, error message specifies location that have expected contents. recover from verification failure, downloading Flash again, replace selected download file.
MMCCMB2102UM/D User's Manual
Operation
view contents Flash memory, click Display button. This brings Display Flash/RAM display, such (Figure 3-3).
Figure Display FLASH/RAM Display this first action this SysDS loader session, software downloads algorithm file before displaying FLASH contents. progress message appears during downloading this algorithm file. (Should software unable find algorithm file, appropriate error message appears, explained under program FLASH memory step, above.) Address field shows first address value display. change display enter different address this field. Another change value display scroll bars. Mode field specify byte, half-word, word values display. When done viewing display, click Close button return main screen FLASH/RAM page.
erase FLASH memory, click Erase FLASH button. SysDS loader erases contents FLASH memory except sectors that contain system software. Erasing takes seconds. this first action this Loader session, software downloads algorithm file before erasing FLASH. progress message appears during downloading this algorithm file. (Should software unable find algorithm file, appropriate error message appears, explained under program FLASH memory step, above.) erase sector FLASH memory, click Erase Sector button. This brings Flash Sector Number dialog box. Enter number sector erased, then click button.
MMCCMB2102UM/D User's Manual
Downloading FLASH Memory
this first action this Loader session, software downloads algorithm file before erasing FLASH sector. progress message appears during downloading this algorithm file. (Should software unable find algorithm file, appropriate error message appears, explained under program FLASH memory step, above.) specify sectors that contain system software through message reminds you. Buttons message cancel erasure proceed with erasure. erase sectors through which contain system software, unless absolutely necessary. Table lists boundaries these sectors. must erase these sectors, subsequently restore factory programming clicking Restore System Software button, provided that before your SysDS loader session. Paragraph 3.2.2 gives additional information about restoring system software.
NOTE:
CAUTION:
Failure restore system software, failure correctly reset vector, during same SysDS loader session, puts into unrecoverable situation. Subsequent restoration system software require sending your CMB2102 back factory.
verify that FLASH sector blank, click Blank Check button. This brings dialog that asks sector number. Enter number sector blank checked, then click button. message tells results blank check. sector blank, erase sector different sector.) your Loader session, merely close main screen. NOTE: information about FPGA page main screen, FPGA user's manual.
3.2.2 Restoring System Software
must overwrite system-software FLASH sectors, SysDS loader restore system software, provided that before your SysDS loader session. follow these instructions: Press switch reset CMB2102. Make sure that jumper header enables FLASH, FSRAM, DUART. subswitches
MMCCMB2102UM/D User's Manual
Operation
switch Programmer: subswitches GSB2, GSB1, GSB0 Click Restore System Software button FLASH/RAM page. system software your current hard-disk directory, Loader automatically restores system software appropriate FLASH sectors. main screen reappears confirm successful programming. Should receive message that system software does exist, because software different hard-disk directory. make that directory active click again Restore System Software button.
Controlling CMB2102 LEDs
Section explained LEDs through show progress CMB2102 selftest, give other status information. Your code control these LEDs, assigning values four least-significant bits global control register (GCR): controls (GCB0). controls (GCB1). controls (GCB2). controls (GCB3).
value these bits turns corresponding LED. value these bits turns corresponding LED. example assembly routine below uses assembly code function opcode mtcr move patterns from register (r2) GCR. This this routine turns status LEDs OFF.
void change_LED(int //prototype Main() change_LED(0x0); //turn LEDs delay(time); //pause change_LED(0xF); //turn LEDs OFFLED GCB0 //assembly code function void change_LED(int asm("mtcr r2,gcr"); Move info control reg.
MMCCMB2102UM/D User's Manual
CMB2102 Design
Section Board Design FPGA Device
This section explains important relationships among components your CMB2102, explains important functions MAPI FPGA device. Additionally, this section explains Altera Max+plusII software reprogram MAPI FPGA device.
CMB2102 Design
Figure simplified diagram CMB2102 functionality. core FPGA device simulates M210 core. Most communication through MAPI FPGA device MAPI ring, local (MLB).
Control, Decode
FLASH MEMORY CONTROLLER FLASH
DUART
MAPI RING
CORE FPGA (M210 core)
MAPI FPGA: Interrupt Control Periodic Interval Timer External Interface
Figure Functionality Diagram functionality MAPI FPGA device includes interrupt controller, periodic interval timer (PIT), external interface controller. external interface controller generates off-board chip selects, conditions off-board address data signals. CMB2102 memory includes FLASH, RAM, DUART, MAPI FPGA. memory controller provides address decode such functions, generates control signals back core FPGA. Subsections 4.1.1 through 4.1.4 explain interrupt controller, periodic interval timer (PIT), external interface, port Table lists registers addresses these functions.
MMCCMB2102UM/D User's Manual
Board Design FPGA Device
Table Interrupt, PIT, Port Addresses
Function
Interrupt controller
Register
Interrupt source Normal interrupt enable Fast interrupt enable Normal interrupt pending Fast interrupt pending Interrupt control
Symbol intscr nien fien nipnd fipnd pitscr pitdr pitadr portfc_ddr portfe portf cs0bar cs1bar
Address
0x0061_1000 0x0061_1004 0x0061_1008 0x0061_100C 0x0061_1010 0x0061_1014 0x0061_1024 0x0061_1028 0x0061_102C 0x0061_1030 0x0061_1034 0x0061_1038 0x0061_1040 0x0061_1044
Periodic interval timer
Control/status register Data register Alternate data register
Port
Control data direction Edge detect enable data
Address Decode
base address base address
4.1.1 Using Interrupt Controller
MAPI FPGA device includes interrupt controller example, which Figure represents.
NIPND NIEN INTSRC FIEN FIPND FINT_b INT_b
INT_b AVEC_b VEC[6:0] FINT_b DBGCRQ_b
DBGCRQ_b
DATA BRKRQ_b
Figure Interrupt Controller Diagram
MMCCMB2102UM/D User's Manual
CMB2102 Design
interrupt controller consists priority logic block these registers: Interrupt source register (INTSRC), which consists bits, each associated with single interrupt source. Positions always forced value This means that your code force interrupt enabling interrupts these positions. Normal interrupt enable register (NIEN), 32-bit register individual masking INTSRC. Each clear NIEN masks corresponding INTSRC value: even that INTSRC set, interrupt request goes forward. Each NIEN lets corresponding INTSRC value determine request. Normal interrupt pending register (NIPND), which indicates priority normal interrupts. Fast interrupt enable register (FIEN), 32-bit register individual masking INTSRC. Each clear FIEN masks corresponding INTSRC value: even that INTSRC set, interrupt request goes forward. Each FIEN lets corresponding INTSRC value determine request. Fast interrupt pending register (FIPND), which indicates priority fast interrupts. Interrupt control register (ICR), 32-bit register that elevate fast interrupt highest-priority level, specifying servicing vector.
interrupt controller uses three priority levels: Highest priority: fast interrupts specifically elevated handled first, specified interrupt vector. Fast priority: group interrupt requests dealt with next. Fast-priority interrupts autovectored, that each already associated with interrupt vector. Normal priority: group interrupt requests dealt with last. Normal-priority interrupts also autovectored. Each peripheral-device interrupt request sets corresponding INTSRC register. interrupt controller logically ANDs INTSRC contents with those NIEN register, putting result NIPND register. This means that NIPND's bits identify pending normal interrupts. bit-wise NIPND contents becomes data INT_b signal interrupt priority logic block. Similarly, interrupt controller logically ANDs INTSRC contents with those FIEN register, putting result FIPND register. This means that FIPND's bits identify pending fast interrupts. bit-wise FIPND contents becomes data FINT_b signal priority logic block. elevates fast interrupts highest priority, specifying interrupt vector. Your code highest-priority interrupt assert DBGRQ_b signal through priority logic block CPU. Your code also have assert BRKRQ_b signal, which by-passes logic block, going directly CPU.
MMCCMB2102UM/D User's Manual
Board Design FPGA Device
Your code read interrupt registers. Your code control interrupt functionality writing NIEN, FIEN, ICR, provided that supervisor mode that 32-bit loads stores. interrupt controller autovectors interrupts (except highest-priority interrupt) asserting AVEC_b input same time asserts interrupt signal (INT_b FINT_b). interrupt handler reads interrupts signal AVEC_b signal determine interrupt vector. interrupt controller elevates highest priority request that status asserting VEC[6:0] inputs also sends fast interrupt request. Figure shows layout interrupt source register.Table lists interrupt assignments that pertain bits interrupt-controller registers. Figure shows layout interrupt control register.
IN28 IN27 IN26 IN25
Figure Interrupt Source Register Layout
Table Interrupt Source Assignments
Software Software Software INT_b[2] INT_b[1] UARTINTB UARTINTA PORTF[7] PORTF[6] PORTF[5] PORTF[4] PORTF[3] PORTF[2] PORTF[1] PORTF[0]
Active
High High High High High High Edge Edge Edge Edge Edge Edge Edge Edge
INT_b[15] INT_b[14] INT_b[13] INT_b[12] INT_b[11] INT_b[10] INT_b[9] INT_b[8] INT_b[7] INT_b[6] INT_b[5] INT_b[4] INT_b[3] Software Software Software
Active
High High High
MMCCMB2102UM/D User's Manual
CMB2102 Design
(not used)
BRKRQ ENABLE DBGRQ (not used)
Source
Vector
Figure Interrupt Control Register Layout works with other interrupt controller registers these ways: (BRKRQ) value asserts breakpoint request (that BRKRQ_b signal gets value instead value does assert breakpoint request (that BRKRQ_b signal gets value (ENABLE) value enables highest-priority interrupt. instead value interrupt controller does designate highest-priority interrupt. (DBGRQ) value interrupt controller asserts DBGRQ_b signal highest-priority interrupt. value interrupt controller asserts FINT_b VEC[6:0] signals highest-priority interrupt. values bits through specify interrupt-request source raised highest priority. values bits through specify vector assigned highest-priority interrupt.
Note necessary conditions interrupt request elevated highest priority: INTSRC register, corresponding FIEN register, ENABLE set.
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Board Design FPGA Device
4.1.2 Using Periodic Interval Timer
MAPI FPGA device includes periodic interval timer (PIT), which provide precise interrupts with minimal processor intervention. This timer either count down from modulus-latch value free-running down counter. Figure diagram this PIT.
PITCSR
STOP STEP PITIE PITIF
PITADR Count 32-bit Down Counter Control Block load counter
PIT_INT
PITDR 32-bit Modulus Latch DBUG_n
Figure Diagram NOTE: PIT, must subswitches S5-1 S5-2 OFF. Either subswitch deactivates functionality.
consists control block three registers: data register (PITDR), which contains timer modulus. Your code this modulus writing this register. Your code find modulus reading from this register. alternate data register (PITADR), which contains current counter value. Your code find current timer value reading from this register. control/status register (PITCSR), which controls timer operation. Your code control timer writing reading bits through this register.
PIT_INT output signal, which connects processor interrupt. When count reaches control block sets interrupt flag (PITIF, control/status register. This asserts PIT_INT signal, which alert processor that interrupt pending. signal remains asserted until control block your code) clears flag bit. PIT_INT signal connects int_src_reg[24] processor. set-and-forget timer, your code must reload control (RLD, control/status register. Then, your code must write appropriate modulus latch value data register. alternate data register copies modulus latch value from data register. Upon each system clock cycle, alternate data register decrements value
MMCCMB2102UM/D User's Manual
CMB2102 Design
When counter value reaches (0x0000_0000), control block sets interrupt flag (PITIF) control/status register. interrupt enable (PITIE, also set, PIT_INT interrupt-pending signal goes processor. alternate data register again copies modulus latch value from data register, counting cycle begins again. Your code change modulus latch value time, writing data register. force count immediately, your code must overwrite enable (OVW, control/status register, then write value data register.
free-running timer, your code must clear reload control (RLD, control/status register. This tells alternate address register ignore modulus latch value data register. Upon each system clock cycle, alternate data register decrements value When counter value reaches control block sets interrupt flag (PITIF) control/status register. interrupt enable (PITIE, also set, PIT_INT interrupt-pending signal goes processor. next clock cycle, alternate data register decrements value 0xFFFF_FFFF, counting cycle begins again. force count immediately, your code must overwrite enable (OVW, control/status register, then write value data register. Your code change modulus latch value time, writing data register. However, timer will ignore modulus latch value long set.
Figure shows layout control/status register. Table explains control bits control/status register.
STOP
STEP
LOAD PITIE PITIF
Figure Control/Status Register Layout
MMCCMB2102UM/D User's Manual
Board Design FPGA Device
Table Control/Status Register Values
Name
Reload Control (RLD)
Value
Effect/Meaning
After reaching 0x0000_0000, counter decrements 0xFFFF_FFFF continues counting down. After reaching 0x0000_0000, counter loads modulus latch value continues counting down. interrupt present. write this unasserts interrupt signal. write data register also clears this bit.) interrupt present. write effect.) Prevents interrupt signal from reaching interrupt controller. Allows interrupt signal reach interrupt controller. data register holds modulus latch value. When count alternate data register reaches alternate data register reads modulus latch value. alternate data register immediately reads modulus latch value from data register, regardless current count value. Counter functionality continues while debug mode. Debug mode freezes counter. None. read this always returns write effect.) Copies modulus latch value from data register alternate data register. (Hardware automatically clears this after loading.) None. read this always returns write effect.) Steps counter clock cycle. (Hardware automatically clears this after stepping. write effect counter stopped.) Starts counting. Stepping possible. Stops (freezes counter. Stepping possible.
Interrupt Flag (PITIF)
Interrupt Enable (PITIE) Overwrite Enable (OVW)
Debug Mode (DBG) Load Counter (LOAD)
Step Counter (STEP)
Stop Counter (STOP)
NOTE:
Your code step counter from step counter from modulus latch value. Setting counter value directly does cause interrupt.
4.1.3 Port Control Pins
MAPI FPGA device eight digital pins, which available control functions. These pins, edge-detect logic each pin, controlling registers make port module device.
MMCCMB2102UM/D User's Manual
CMB2102 Design
port-F registers are: Port edge control register (PORTFC): bits through address 0x0061_1030. These bits correspond, respectively, port pins through value PORTFC corresponding port falling-edge detect. value PORTFC corresponding port rising-edge detect. Figure represents this register. Port data direction register (DDR): bits through address 0x0061_1030. These bits correspond, respectively, port pins through value corresponding port input. value corresponding port output. Figure represents this register. Port edge detect register (PORTFE): bits through address 0x0061_1034. These bits correspond, respectively, port pins through value PORTFE means detection selected edge corresponding port pin. value PORTFE means that selected edge corresponding port been detected. Figure represents this register. Port data register (PORTF): bits through address 0x0061_1038. These bits correspond, respectively, port pins through data direction input, read PORTF returns current values pins; write PORTF stores data driven port pins. data direction output, read PORTF returns current value PORTF register. Figure 4-10 represents this register.
ADDRESS 0x0061_1030 PORT PORT PORT PORT PORT PORT PORT PORT
Figure Port Edge Control Register Layout
ADDRESS 0x0061_1030
Figure Port Data Direction Register Layout
MMCCMB2102UM/D User's Manual
Board Design FPGA Device
ADDRESS 0x0061_1034 PORT PORT PORT PORT PORT PORT PORT PORT
Figure Port Edge Detect Register Layout
ADDRESS 0x0061_1038 PORT PORT PORT PORT PORT PORT PORT PORT
Figure 4-10 Port Data Register Layout reset configures port pins falling-edge-detect inputs. writing PORTFC register, your code make individual pins rising-edge detect. writing register, your code make individual pins outputs. Your code read PORTFE register determine which port pins have detected their edge transitions. NOTE: Once set, PORTFE register remains until reset clears until your code writes bit. Before such clearing, subsequent changes corresponding port have effect register bit.
code read from write PORTF register control functionality port pins. data direction input, read PORTF returns current values port pins. data direction input, write PORTF stores data driven port pins. data direction output, read PORTF returns current value PORTF register.
4.1.4 Address Decoder
MAPI FPGA expose latched MAPI ring. This capability permits communication with (and programming configuration circuit MMCFPGA1200 board. This latch mode makes address, data, control signals MAPI ring behave similarly they would behave interface. configure this latch mode, CMB2102 switch subswitch
MMCCMB2102UM/D User's Manual
Configuring Your Software
Alternatively, have MAPI FPGA connect directly MAPI ring, setting switch subswitch OFF. This configures pass through mode. MAPI FPGA address decoder generate general chip-selects. default memory table (Table 2-6) lists memory addresses each chip select. possible change base address chip select writing bits through chip select base register (cs0bar, address 0x0061_1040). Similarly, possible change base address chip select writing bits through chip select base register (cs1bar, address 0x0061_1044). (The system does bits though either register.) accesses range chip select, MAPI FPGA provides (transaction acknowledge) signal memory controller.
Configuring Your Software
NOTE: steps below guidance starting Altera MAX+plusII software. Should have difficulty preparing your MAX+plusII software, phone Altera customer service assistance.
Follow steps below prepare your Altera development software with your CMB2102. Install Altera development software, Altera instructions. Obtain your Verilog authorization code, Altera instructions. registration information, this takes only hours; Altera customer service provide number.) Start Altera software. From Windows desktop, click Start, select Programs, select MAX+plusII, select MAX+plusII again. Open Options menu select Authorization Code. This brings Authorization Code dialog box. Enter your authorization code appropriate field. NOTE: Your authorization code case sensitive. Make sure correct capital lower-case letters your enter code.
Click Validate button. software verifies your authorization code, then displays your software guard number. Click button close dialog box. MAX+plusII main screen appears. Altera software, should through Altera tutorial. This completes software preparation. ready develop application suitable downloading CMB2102 device.
MMCCMB2102UM/D User's Manual
Board Design FPGA Device
Reprogramming FPGA Device
Follow steps through below, develop application suitable downloading FPGA device location U11. Most these steps typical using MAX+plusII software develop application project. These steps rigid instructions. case difficulty using MAX+plusII software, should call Altera customer service assistance. transmittal CD-ROM that contains this manual also contains example application files: symbol counter, Verilog counter, Verilog port. Windows Explorer create name folder project. Start MAX+plusII software. Open File menu select Project. From subordinate menu, select Name. This brings Project Name dialog box. Project Name dialog select newly created project folder, enter name project. (The project name should contain spaces; usually convenient give project same name folder.) Click button close dialog box. Open File menu select New. This brings dialog box. Select Text editor file, then click button. This closes dialog opens text editor window. Write Verilog code your application. (Consult Altera Verilog manuals instructions.) When your code done, leave text editor window open. Click Open Compiler Window toolbar button. software immediately compiles your code. compiler finds errors, correct them text editor window, then compile again. When compilation succeeds, your ready create default symbol. Still leaving text editor window open, open File menu select Create Default Symbol. software automatically creates graphic representation compiled code, symbol that later schematic design. Open File menu select Project. From subordinate menu, select Name. This brings Project Name dialog box. Project Name dialog select same folder selected Step Enter project name: this project will .hex file, Motorola suggests that append letter name used Step Click button close dialog box. Open File menu select New. This brings dialog box. Select graphic editor file, then click button. This closes dialog opens graphic editor window.
MMCCMB2102UM/D User's Manual
Reprogramming FPGA Device
Open Symbol menu select Enter. This brings Enter Symbol dialog box. Select symbol created Step symbol appears graphic editor window. inputs outputs symbol, then compile again. (The only errors likely this point mismatched signal names forgotten signal. Correct errors recompile.) When compilation succeeds, ready assign device. Open Assign menu select Device. This brings Device dialog box. Device Family area, select FLEX 10KA. Devices area, select EPF10K100ABC356-1. Click Device Options button, bring Individual Device Options dialog box. Individual Device Options dialog box: Device Options area. Click check these items: Release Clears Before Tri-States, Enable Chip-Wide Reset (DEV_CLRn), Enable Chip-Wide Output Enable (DEV_OE), Enable INIT_DONE Output, Low-Voltage Configuration Device, Configuration Device Pull-Up Resistor.
Find Configuration Device field: field value EPC2LC20. Elsewhere Individual Device Options dialog box, find Configuration Scheme field: field value Passive Serial (can Configuration Device). Affected Configuration Scheme area, make sure that both CLKUSR boxes have grey check marks. Make sure that only check marks those that Steps through specify, then click button return Device dialog box.
Click Device dialog button return main screen. This completes device assignment. ready assign signals pins. best give signals (wires) same names their corresponding pins. Open Assign menu select Pin/Location/Chip. This brings Pin/Location/Chip dialog box. Click Search button bring subordinate dialog that lists pins. (Click LIST button list.) listed names inputs outputs created part Step 14.) Select (highlight) pin, then click button. This returns Pin/Location/Chip dialog box; selected name will Node Name field. Chip Resource area dialog box. field, enter name FPGA pin. (This value column cross-reference table 6-5.)
MMCCMB2102UM/D User's Manual
Board Design FPGA Device
NOTE:
alternative using Search button select Pin, activating Type field. Select appropriate type from small pull-down menu, then enter name appropriate field, enter signal name Node Name field.
This completes assignment first pin. Repeat Step other signals. When done, close Pin/Location/Chip dialog box. NOTE: each finished design, Altera software creates .acf file: text file that edit. your first design, must Step each signal. subsequent designs, copy edit .acf file.
have already done configure ByteBlaster programming hardware Altera instructions. Compile your application file again. When compilation succeeds, ready create .pof file. Open MAX+plusII menu select Programmer. This brings Programmer dialog box. (You will anything this dialog box, must open this point.) Open JTAG menu select Multi-Device JTAG Chain Setup. This brings Multi-Device JTAG Chain Setup dialog box. Device Name pull-down menu select EPF10K100A, then click button. EPF10K100A name appears list center dialog box, without associated programming. Device Name pull-down menu select EPC2, then click Select Programming File button. This brings Select Programming File dialog box. Select Programming File dialog select .pof file your project. Click button return Multi-Device JTAG Chain Setup dialog box. Click button. This EPC2 name list center dialog box, showing association with selected .pof file. Click Save button. This brings subordinate dialog that lets name save listed files JTAG chain file. Click button return Multi-Device JTAG Chain Setup dialog box. Click Multi-Device JTAG Chain Setup dialog button return Programmer dialog box. This completes file creation; ready download files FPGA device.
Apply power your CMB2102. Connect ByteBlaster between CMB2102 connector parallel port your computer. Make sure that wire cable connects
MMCCMB2102UM/D User's Manual
Reprogramming FPGA Device
Click Program button Programmer dialog box. percentage indicator shows progress downloading files device CMB2102. this downloading, disconnect ByteBlaster cable from connector J19. Press CMB2102 switch transfer downloaded application FPGA device. This completes reprogramming device. close MAX+plusII software.
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Board Design FPGA Device
MMCCMB2102UM/D User's Manual
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4)
Section Connector information
This chapter consists assignments signal descriptions CMB2102 connectors.
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4)
Connectors through 2-by-50-pin connectors, CMB2102 MAPI connectors. (Connectors through bottom CMB2102, have same assignments.) diagram below shows orientation CMB2102 MAPI connectors. Figure through Figure 5-4, Table through Table 5-4, give assignments signal descriptions these connectors.
MMCCMB2102UM/D User's Manual
Connector information
P1/J1
PTJ1[100] CS_b[8] CS_b[9] PTJ1[94] VDD5V PTJ1[88] M_VEC[5] M_VEC[3] M_VEC[1] M_AVEC_b M_IPEND_b PTJ1[76] M_INT_RAW_b M_FINT_RAW_b MAPI_INT_b[6] MAPI_INT_b[4] MAPI_INT_b[2] M_FINT_b VDD3V MID[0] MAPI_INT_b[14] MAPI_INT_b[12] MID[1] MAPI_INT_b[10] MAPI_INT_b[8] PORTF[6] PORTF[4] MID[2] PORTF[2] PORTF[0] MID[3] PTJ1[32] PTJ1[30] GND1 PTJ1[24] PTJ1[22] PTJ1[20] PTJ1[18] PTJ1[16] PTJ1[14] GND1 GND2 PTJ1[8] PTJ1[6] PTJ1[4] GND2 VDD3V CS_b[4] CS_b[5] CS_b[6] CS_b[7] M_VEC[6] M_VEC[4] M_VEC[2] M_VEC[0] M_INT_b PTJ1[77] PTJ1[75] DVSP_b[0] PTJ1[69] MAPI_INT_b[7] MAPI_INT_b[5] MAPI_INT_b[3] MAPI_INT_b[1] VDD3V PTJ1[57] PTJ1[55] MAPI_INT_b[15] MAPI_INT_b[13] MAPI_INT_b[11] MAPI_INT_b[9] PORTF[7] PORTF[5] PORTF[3] PORTF[1] PTJ1[35] PTJ1[33] PTJ1[31] PTJ1[29] PTJ1[27] GND1 PTJ1[23] PTJ1[21] PTJ1[19] PTJ1[17] PTJ1[15] PTJ1[13] PTJ1[11] PTJ1[9] PTJ1[7] PTJ1[5] PTJ1[3] PTJ1[1]
Figure MAPI Connector P1/J1 Assignments
MMCCMB2102UM/D User's Manual
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4)
Table MAPI Connector P1/J1 Signal Descriptions
100, 77-75, 33-29, 24-13, 9-3, 98-95,
Mnemonic
PTJ1[x] Pass Through
Signal
VDD3V CS_b4] CS_B[9] (not exact order) VDD5V M_VEC[6] M_VEC[0] M_AVEC_b M_INT_b M_IPEND_b DVSP_b[0] M_INT_RAW_b
+3.3-volt power. CHIP SELECTS (lines 4-9) Active-low output lines that provide chip selects external devices.
87-81 68-63, 51-47
GROUND +5-volt power. EXTERNAL INTERRUPT VECTOR (lines 6-0) Signals that make interrupt vector number. EXTERNAL INTERNAL VECTOR REQUEST Signal that requests internal generation interrupt vector number. EXTERNAL NORMAL INTERRUPT Normal interrupt request signal MAPI FPGA. EXTERNAL INTERRUPT PENDING Signal indicating that MAPI FPGA interrupt pending. DEVELOPMENT SPACE Signal indicating access development space EXTERNAL NORMAL UNSYNCHRONIZED INTERRUPT Signal that requests normal unsynchronized interrupt.
M_FINT_RAW_b EXTERNAL FAST UNSYNCHRONIZED INTERRUPT Signal that requests fast unsynchronized interrupt. MAPI_INT_b[1] EXTERNAL INTERRUPTS (lines 1-15) Bidirectional interrupt lines that form external interface general-purpose module. MAPI_INT_b[15] (not exact order) M_FINT_b EXTERNAL FAST INTERRUPT Fast interrupt request signal MAPI FPGA.
45-42, 39-36
MID[0] MID[3] MAPI IDENTIFICATION CODE (lines 0-3) Signals that identify host processor board. respective values indicate CMB2102. PORTF[7] PORTF[0] GND1 GND2 PORT Edge-detect pins. GROUND Connection Ground plane. GROUND Connection Ground plane.
MMCCMB2102UM/D User's Manual
Connector information
P2/J2
PTJ2[100] PTJ2[98] PTJ2[96] PTJ2[94] PTJ2[92] PTJ2[90] PTJ2[88] GND3 VDD3V PTJ2[80] PTJ2[78] PTJ2[76] PTJ2[74] PTJ2[72] PTJ2[70] PTJ2[68] PTJ2[66] VDD3V PTJ2[60] PTJ2[58] PTJ2[56] PTJ2[54] PTJ2[52] PTJ2[50] PTJ2[48] VDD3V PTJ2[42] PTJ2[40] PTJ2[38] PTJ2[36] PTJ2[34] PTJ2[32] PTJ2[30] PTJ2[28] PTJ2[26] PTJ2[24] PTJ2[22] VDD3V GND2 PTJ2[14] PTJ2[12] PTJ2[10] PTJ2[8] PTJ2[6] PTJ2[4] PTJ2[2] GND3 PTJ2[97] PTJ2[95] PTJ2[93] PTJ2[91] PTJ2[89] PTJ2[87] GND3 PTJ2[81] VDD5V PTJ2[77] PTJ2[75] PTJ2[73] PTJ2[71] PTJ2[69] PTJ2[67] PTJ2[65] PTJ2[61] PTJ2[59] PTJ2[57] PTJ2[55] PTJ2[53] PTJ2[51] PTJ2[49] PTJ2[47] VDD5V PTJ2[41] PTJ2[39] PTJ2[37] PTJ2[35] PTJ2[33] SDCPS VDD5V PTJ2[27] PTJ2[25] PTJ2[23] PTJ2[21] PTJ2[19] GND2 PTJ2[13] PTJ2[11] PTJ2[9] PTJ2[7] PTJ2[5] PTJ2[3] GND2
Figure MAPI Connector P2/J2 Assignments
MMCCMB2102UM/D User's Manual
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4)
Table MAPI Connector P2/J2 Signal Descriptions
100, 98-87, 78-65, 61-47, 42-32, 28-21, 14-2
Mnemonic
PTJ2[x] Pass Through
Signal
GND3 VDD3V VDD5V SDCPS
GROUND Connection Ground plane. GROUND +3.3-volt power. +5-volt power. SHUT DOWN POWER SUPPLY Signal, from connected board that supplies power, disable on-board power supply. GROUND Connection Ground plane.
GND2
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Connector information
P3/J3
VDD3V PTJ3[98] PTJ3[96] PTJ3[94] PTJ3[90] M_TSIZ_b[1] M_TSIZ_b[0] DBEV_b J_TDI J_TDO PTJ3[78] IDVDD VDD5V M_TBUSY_b JD_DEBUG_b M_TC[2] M_TC[1] M_TC[0] VDD3V JD_WAKEUP_b M_D2A JD_BKREQ_b P_LPMD[0] P_LPMD[1] M_ABORT_b M_SEQ_b JD_MCU_DE_b JD_MCU_ACK_b PTJ3[40] PTJ3[38] PTJ3[36] PTJ3[34] PTJ3[32] PTJ3[30] PTJ3[28] PTJ3[26] GND4 PTJ3[22] PTJ3[20] PTJ3[18] PTJ3[16] PTJ3[14] PTJ3[12] PTJ3[10] PTJ3[8] PTJ3[6] PTJ3[4] PTJ3[2] VDD3V EXTAL PTJ3[89] J_TRST_b J_TCLK J_TMS RSTOUT_b RESET_b PTJ3[75] P_PSTAT[3] P_PSTAT[2] P_PSTAT[1] P_PSTAT[0] MID[9] MID[8] VDD3V PTJ3[57] MID[4] MAPI_BR_b MAPI_BG_b MID[5] MAPI_TSCD_b MAPI_TSCA_b PTJ3[41] PTJ3[39] MID[6] PTJ3[35] PTJ3[33] MID[7] PTJ3[29] PTJ3[27] GND4 PTJ3[21] PTJ3[19] PTJ3[17] PTJ3[15] PTJ3[13] PTJ3[11] GND4 GND3 PTJ3[5] PTJ3[3] GND3
Figure MAPI Connector P3/J3 Assignments
MMCCMB2102UM/D User's Manual
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4)
Table MAPI Connector P3/J3 Signal Descriptions
100, 41-38, 36-32, 30-26, 22-10,
Mnemonic
VDD3V PTJ3[x] +3.3-volt power Pass Through
Signal
EXTAL M_TSIZ_b[1], M_TSIZ_b[0] J_TRST_b
GROUND EXTERNAL CLOCK Off-board clock signal. TRI-STATE CONTROL Signal that puts processor tri-state mode. TRANSFER SIZE (lines Signals that indicate size external transfer. TEST RESET Active-low input signal Schmitt trigger, asynchronously initializing JTAG controller. J_TRST_b external pullup resistor. TEST CLOCK Input signal that synchronizes JTAG test logic. J_TCLK external pulldown resistor. DEBUG EVENT Open-drain, active-low input signal from external command controller, that causes enter debug mode. TEST MODE SELECT Input signal that sequences controller's state machine, sampled rising edge J_TCLK signal. J_TMS external pullup resistor. TEST DATA INPUT Serial input signal test instructions data, sampled rising edge J_TCLK signal. J_TDI external pullup resistor. TEST DATA OUTPUT Serial output signal test instructions data. Three-stateable actively driven Shift-IR Shift-DR controller states, this signal changes falling edge J_TCLK signal. RESET Active-low output signal that resets external components. Activation processor reset sources asserts this line. RESET Active-low input signal that starts system reset: reset processor most peripherals. This signal does affect debug module (which system provides J_TRST_b line). IDENTIFICATION POWER Special 3-volt power signal MAPI identification code (MID) signals. +5-volt power. PROCESSOR STATUS (lines 3-0) Output signals that provide external status indications resident core. BUSY Signal indicating that cycle progress. DEBUG MODE Output signal indicating that processor debug mode. TRANSFER CODE (lines 2-0) Signals indicating general type transfer.
J_TCLK DBEV_b J_TMS
J_TDI
J_TDO
RSTOUT_b RESET_b
IDVDD VDD5V P_PSTAT[3] P_PSTAT[0] M_TBUSY_b JD_DEBUG_b M_TC[2] M_TC[0]
MID[9] MID[4] IDENTIFICATION CODE (lines 9-4) Signals that identify host processor (not exact board. respective values (bits indicating order) CMB2102.
MMCCMB2102UM/D User's Manual
Connector information
Table MAPI Connector P3/J3 Signal Descriptions (Continued)
Mnemonic
JD_WAKEUP_b M_D2A JD_BKREQ_b MAPI_BR_b P_LPMD[0], P_LPMD[1] MAPI_BG_b M_ABORT_b MAPI_TSCD_b M_SEQ_b MAPI_TSCA_b JD_MCU_DE_b
Signal
CLOCK WAKEUP Output signal that restarts clocks (required certain designs). DATA ADDRESS Signal indicating that value data this clock cycle become address value next clock cycle. BREAKPOINT REQUEST Active-low signal that requests hardware breakpoint. MAPI REQUEST Active-low signal from alternate master, requesting ownership interface bus. PROCESSOR POWER MODE (lines Signals asserted processor upon execution doze, stop, wait instruction. MAPI GRANT Active-low output signal that grants interface-bus ownership alternate master. TRANSFER ABORT Active-low signal from processor that requested access must aborted. MAPI TRI-STATE CONTROL DATA Active-low output signal that toggles alternate master's ability drive data M_TBUSY_b signal. SEQUENTIAL ACCESS Active-low signal indicating that sequential access progress. MAPI TRI-STATE CONTROL ADDRESS Active-low output signal that toggles alternate master's ability drive address attributes. DEBUG EVENT Active-low debug-mode control line core. input signal from external command controller request that core enter debug mode. output signal acknowledges debug-mode-entry external command controller.
JD_MCU_ACK_b ACKNOWLEDGE Active-low signal indicating debug mode core. GND4 GND3 Connection Ground plane. Connection Ground plane.
MMCCMB2102UM/D User's Manual
MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4)
P4/J4
VDD5V PTJ4[98] PTJ4[94] PTJ4[92] PTJ4[90] M_OE_b M_EB_b[0] M_EB_b[1] M_EB_b[3] M_EB_b[2] MAPI_TEA_b M_ADDR[30] M_ADDR[28] M_ADDR[26] M_ADDR[24] M_ADDR[22] M_ADDR[20] M_ADDR[18] M_ADDR[16] M_ADDR[14] M_ADDR[12] M_ADDR[10] M_ADDR[8] M_ADDR[6] M_ADDR[4] M_ADDR[2] M_ADDR[0] M_DATA[30] M_DATA[28] M_DATA[26] M_DATA[24] M_DATA[22] M_DATA[20] M_DATA[18] M_DATA[16] M_DATA[14] M_DATA[12] M_DATA[10] M_DATA[8] M_DATA[6] M_DATA[4] M_DATA[2] M_DATA[0] VDD3V VDD3V CLKOUT CS_b[3] CS_b[2] CS_b[1] CS_b[0] M_RW_b M_TREQ_b MAPI_TA_b M_ADDR[31] M_ADDR[29] M_ADDR[27] M_ADDR[25] M_ADDR[23] M_ADDR[21] M_ADDR[19] M_ADDR[17] M_ADDR[15] M_ADDR[13] M_ADDR[11] M_ADDR[9] M_ADDR[7] M_ADDR[5] M_ADDR[3] M_ADDR[1] M_DATA[31] M_DATA[29] M_DATA[27] M_DATA[25] M_DATA[23] M_DATA[21] M_DATA[19] M_DATA[17] M_DATA[15] M_DATA[13] M_DATA[11] M_DATA[9] M_DATA[7] M_DATA[5] M_DATA[3] M_DATA[1] VDD3V
Figure MAPI Connector P4/J4 Assignments
MMCCMB2102UM/D User's Manual
Connector information
Table MAPI Connector P4/J4 Signal Descriptions
Mnemonic
VDD5V VDD3V PTJ4[x] +5-volt power. +3.3-volt power. Pass Through GROUND
Signal
CLKOUT CS_b[3] CS_B[0] M_OE_b M_EB_b[0], M_EB_b[1], M_EB_b[3], M_EB_b[2] M_RW_b M_TREQ_b MAPI_TEA_b MAPI_TA_b
CLOCK OUTPUT Clock signal CMB2102 provides external devices. CHIP SELECTS (lines 3-0) Active-low output lines that provide chip selects external devices. OUTPUT ENABLE Active-low signal that indicates that access read access; enables slave devices drive data bus. ENABLE BYTES Active-low outputs active during operation corresponding data bits (D31-D24 enable byte D23-D16 enable byte D7-D0 enable byte D15-D8 enable byte configure these bytes assert write cycles both read write cycles. READ/WRITE Active-low signal indicating that current access write access. TRANSMIT REQUEST Active-low signal indicating access request. processor drives this signal. TRANSFER ERROR ACKNOWLEDGE Active-low signal that indicates transfer error. source this signal external core. TRANSFER ACKNOWLEDGE Active-low signal indicating completion data transfer, either read write cycle. source this signal external core.
74-59, 56-41
M_ADDR[31] ADDRESS (lines 31-0) Output lines addressing external devices. M_ADDR[0] These lines change state only during external-memory accesses. (not exact order) M_DATA[31] M_DATA[0] (not exact order) DATA (lines 31-0) Bi-directional data lines. read (and MAPI_TA_b low), processor samples rising edge CLKOUT signal. write (and driven core), external device samples first positive edge CLKOUT signal after address presentation.
38-29, 26-17, 14-3
MMCCMB2102UM/D User's Manual
OnCE Connector (J29)
OnCE Connector (J29)
Connector J29, 2-by-7-pin connector, conveys data control signals from OnCE control block. Figure Table give assignments signal descriptions this connector.
J_TDI J_TDO J_TCLK M_RST_b P3_3V
J_TMS DBEV_b J_TRST_b
Figure OnCE Connector Assignments
Table OnCE Connector Signal Descriptions
Mnemonic
J_TDI J_TDO J_TCLK M_RST_b J_TMS P3_3V DBEV_b GROUND
Signal
DEBUG SERIAL INPUT Data command input line OnCE controller. DEBUG SERIAL OUTPUT Serial data output line from OnCE controller. DEBUG SERIAL CLOCK Serial clock input line OnCE control block. connection RESET Active-low input line OnCE controller processor, signalling reset. DEBUG MODE SELECT Input signal that tells OnCE control block advance mode state cycle mode states). OPERATING VOLTAGE Transmission line +3.3-volt operating power. DEBUG EVENT Active-low debug-mode control line OnCE controller. input signal from external command controller makes OnCE controller immediately enter debug mode. CMB2102, this input-only pin, connected directly JD_MCU_DE_b. TEST RESET Active-low input line external reset signal OnCE controller.
J_TRST_b
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Connector information
Logic Analyzer Connectors (J5, J14)
Connectors J14, 2-by-19-pin Mictor connectors, logic analyzer connectors. Figure through Figure give assignments these connectors. Table through Table give signal descriptions these connectors.
M_OE_b P_TREQ_b P_TC[2] P_TC[1] P_TC[0] P_TSIZ[1] P_TSIZ[0] P_SEQ_b P_PSTAT[3] P_PSTAT[2] P_PSTAT[1] P_PSTAT[0] M_RST_b M_BG_b P_ABORT-b P_TBUSY_b
P_TEA_b M_BR_b P_D2A DATA_DIR DVSP_b[0] DATA_EN_b LATCH_ADDR RSTOUT_b LATCH_DATA WR_b[3] WR_b[2] WR_b[1] WR_b[0] FLASH_CS_b FSRAM_CS_b DUART_CS_b IC_CS_b
Figure Logic Analyzer Connector Assignments
Table Logic Analyzer Connector Signal Descriptions
Mnemonic
M_OE_b connection
Signal
MAPI OUTPUT ENABLE Active-low signal that indicates that access read access; enables slave devices drive data bus. This signal driven from MAPI address space. TRANSFER REQUEST Active-low signal indicating access request. processor drives this signal. TRANSFER CODE (lines 2-0) Signals indicating general type transfer. TRANSFER SIZE (lines Signals that indicate size external transfer. SEQUENTIAL ACCESS Active-low signal indicating that sequential access progress. PROCESSOR STATUS (lines 3-0) Output signals that provide external status indications processor.
12-15
P_TREQ_b P_TC[2] P_TC[0] P_TSIZ[1], P_TSIZ[0] P_SEQ_b P_PSTAT[3] P_PSTAT[0]
MMCCMB2102UM/D User's Manual
Logic Analyzer Connectors (J5, J14)
Table Logic Analyzer Connector Signal Descriptions (Continued)
24-27
Mnemonic
M_RST_b M_BG_b P_ABORT_b P_TBUSY_b IC_CS_b DUART_CS_b FSRAM_CS_b FLASH_CS_b
Signal
MASTER RESET Active-low signal indicating core master reset. GRANT Active-low output signal that grants ownership alternate master. PROCESSOR ABORT Active-low signal indicating core transfer abort. TRANSFER BUSY Active-low signal indicating that access progress. processor drives this signal. CHIP SELECT Active-low signal access chip-select registers MAPI FPGA device. DUART CHIP SELECT Active-low signal access chip-select registers DUART. CHIP SELECT Active-low signal access chip-select registers FSRAM. CHIP SELECT Active-low signal access chip-select registers FLASH memory. WRITE ENABLE Active-low signals that enable byte writes. WR_b[0] enables bits WR_b[1] enables bits WR_b[2] enables bits WR_b[3] enables bits clock signal).
WR_b[0] WR_b[3]
LATCH_DATA DATA CAPTURE Signal capture CMB2102 data positive edge RSTOUT_b
RESET Active-low, reset signal from core. positive edge clock signal).
LATCH_ADDR ADDRESS CAPTURE Signal capture CMB2102 addresses DATA_EN_b DVSP0_b DATA_DIR P_D2A
M_BR_b DATA BUFFER ENABLE Active-low signal that enables data buffer. DEVELOPMENT SPACE Signal indicating access development space DATA DIRECTION Signal that controls direction data buffer. DATA ADDRESS Signal indicating that value data this clock cycle become address value next clock cycle. REQUEST Active-low signal from alternate master, requesting ownership MLB. TRANSFER ERROR ACKNOWLEDGE Active-low signal that indicates transfer error.
P_TEA_b
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Connector information
CLKOUT P_ADDR[31] P_ADDR[30] P_ADDR[29] P_ADDR[28] P_ADDR[27] P_ADDR[26] P_ADDR[25] P_ADDR[24] P_ADDR[23] P_ADDR[22] P_ADDR[21] P_ADDR[20] P_ADDR[19] P_ADDR[18 P_ADDR[17] P_ADDR[16]
P_RW_b P_ADDR[15] P_ADDR[14] P_ADDR[13] P_ADDR[12] P_ADDR[11] P_ADDR[10] P_ADDR[9] P_ADDR[8] P_ADDR[7] P_ADDR[6] P_ADDR[5] P_ADDR[4] P_ADDR[3] P_ADDR[2] P_ADDR[1] P_ADDR[0]
Figure Logic Analyzer Connector Assignments
Table Logic Analyzer Connector Signal Descriptions
4-35
Mnemonic
CLKOUT connection
Signal
CLOCK OUTPUT External clock source.
P_ADDR[31] ADDRESS Output lines 31-0, addressing external devices. These P_ADDR[0] lines change state only during external-memory accesses. (not exact order) P_RW_b READ/WRITE CONTROL Active-low core read/write control signal.
MMCCMB2102UM/D User's Manual
Logic Analyzer Connectors (J5, J14)
P_TA_b P_DATA[31] P_DATA[30] P_DATA[29] P_DATA[28] P_DATA[27] P_DATA[26] P_DATA[25] P_DATA[24] P_DATA[23] P_DATA[22] P_DATA[21] P_DATA[20] P_DATA[19] P_DATA[18] P_DATA[17] P_DATA[16]
SHS_b P_DATA[15] P_DATA[14] P_DATA[13] P_DATA[12] P_DATA[11] P_DATA[10] P_DATA[9] P_DATA[8] P_DATA[7] P_DATA[6] P_DATA[5] P_DATA[4] P_DATA[3] P_DATA[2] P_DATA[1] P_DATA[0]
Figure Logic Analyzer Connector Assignments
Table Logic Analyzer Connector Signal Descriptions
4-35
Mnemonic
P_TA_b P_DATA[31] P_DATA[0] (not exact order) SHS_b connection
Signal
TRANSMIT ACKNOWLEDGE Active-low signal that indicates data-transfer completion, either read cycle write cycle. DATA Bi-directional data lines 31-0, accessing external memory.
SHOW CYCLE STROBE Active-low signal output signal indicating that address data valid show cycles.
MMCCMB2102UM/D User's Manual
Connector information
Core FPGA Configuration Connector (J9)
Connector 2-by-13-pin connector, receives external configuration data core FPGA device, through XILINX cable. Figure Table give assignments signal descriptions this connector.
P3_3V C_PROGRAM_B D[0] D[2] D[4] D[6] C_DONE C_WRITE_B C_TCK C_TDO
C_CCLK C_INIT_B D[1] D[3] D[5] D[7] C_BUSY C_CS_B C_TMS F1_TDI
Figure Core Configuration Connector Assignments
Table Core Configuration Connector Signal Descriptions
Mnemonic
P3_3V C_PROGRAM_B C_CCLK C_INIT_B D[0] D[7]
Signal
OPERATING VOLTAGE Transmission line +3.3-volt operating power. GROUND CORE PROGRAM Input signal: asserted low, starts configuration sequence core FPGA device. CONFIGURATION CLOCK serial clock input selectRAM slave-serial modes. serial clock output master-serial mode. INITIALIZATION low, signal that configuration memory being cleared. After configuration, user line. DATA (lines 0-7) Configuration data input data lines After configuration, user lines (unless selectMAP port retained). bit-serial modes, D[0] line becomes DIN, single data input. After configuration, user line. CONFIGURATION DONE Signal that configuration complete, that startup sequence under way. CONFIGURATION BUSY Output signal that controls rate configuration-data loading. After configuration, user line (unless selectMAP port retained). WRITE ENABLE selectMAP mode, active-low write enable signal. After configuration, user line (unless selectMAP port retained).
C_DONE C_BUSY
C_WRITE_B
MMCCMB2102UM/D User's Manual
Memory Controller Connector (J12)
Table Core Configuration Connector Signal Descriptions (Continued)
Mnemonic
C_CS_B C_TCK C_TMS C_TDO
Signal
CHIP SELECT selectMAP mode, active-low chip select signal. After configuration, user line (unless selectMAP port retained) connection JTAG CLOCK JTAG scan clock signal core configuration chain. JTAG MODE CONTROL JTAG mode control signal core configuration chain. JTAG DATA OUTPUT JTAG serial data output line from core configuration chain. JTAG DATA INPUT JTAG serial data input line core configuration chain.
F1_TDI
Memory Controller Connector (J12)
Connector J12, 2-by-5-pin connector, receives reprogramming data memory-controller device, through Vantis cable. Figure 5-10 Table 5-10 give assignments signal descriptions this connector.
MC_TCK MC_TMS MC_TDI MC_TDO MC_TRST_B
P3_3V
Figure 5-10 Memory Controller Connector Assignments
Table 5-10 Memory Controller Connector Signal Descriptions
Mnemonic
MC_TCK MC_TMS MC_TDI P3_3V MC_TDO MC_TRST_B GROUND
Signal
SERIAL CLOCK JTAG serial clock signal memory controller. MODE SELECT JTAG mode select signal memory controller. JTAG SERIAL INPUT JTAG serial input line memory controller. OPERATING VOLTAGE Transmission line +3.3-volt operating power. JTAG SERIAL OUTPUT JTAG serial output line from memory controller. JTAG RESET Active-low input line memory controller. connection
MMCCMB2102UM/D User's Manual
Connector information
MAPI FPGA Configuration Connector (J19)
Connector J19, 2-by-5-pin connector, receives external configuration data MAPI FPGA device, through Altera ByteBlaster cable. Figure 5-11 Table 5-11 give assignments signal descriptions this connector.
A_TCK A_TDO A_TMS A_TDI
P3_3V
Figure 5-11 MAPI FPGA Configuration Connector Assignments
Table 5-11 MAPI FPGA Configuration Connector Signal Descriptions
Mnemonic
A_TCK A_TDO P3_3V A_TMS A_TDI
Signal
SERIAL CLOCK JTAG serial clock signal MAPI-FPGA configuration chain. GROUND JTAG SERIAL OUTPUT JTAG serial output line from MAPI FPGA. OPERATING VOLTAGE Transmission line +3.3-volt operating power. JTAG MODE SELECT JTAG mode select signal MAPI-FPGA configuration chain. connection JTAG SERIAL INPUT JTAG serial input line MAPI_FPGA configuration chain.
MMCCMB2102UM/D User's Manual
RS232 Connectors (J27, J28)
RS232 Connectors (J27, J28)
Connectors J28, RS232 connectors, have format. diagram below shows numbering these connectors. Table 5-12 lists assignments signal directions these connectors.
Table 5-12 RS232 Connector J27, Assignments
Signal
Communication Detect Transmitted Data Received Data Data Terminal Ready GROUND Data Ready Clear Send Request Send Ring Indicator
Signal Direction
NOTE:
Connector channel connector channel Accordingly, respective assignments thought CDB. Similarly, respective assignments thought TXDA TXDB, forth.
MMCCMB2102UM/D User's Manual
Connector information
MMCCMB2102UM/D User's Manual
Section Cross Reference Tables
During your application development, need trace signal from core FPGA device, through MAPI FPGA device, MAPI-ring connector. Conversely, need trace signal other direction. tables this chapter help such tracing: Table lists trace relationships core FPGA signals. Table lists trace relationships core FPGA pins Table lists trace relationships MAPI-ring signals. Table lists trace relationships MAPI-ring pins. Table lists pins MAPI FPGA device, showing their relationships pins either core FPGA device MAPI-ring connectors. Table lists pins MAPI connectors, showing their MAPI-FPGA-device signals CMB2102, their FPGA-device signals MMCFPGA1200 board.
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring
Core FPGA Signal
busy_dout cclk cs_b done d[0] d[1] d[3] d[4] d[5] d[6] d[7] gclk[2] gclk[3] init_b j_capture-dr_b j_en_tap_ctlr j_en_tdo j_gp1_regsel j_gp2_regsel
MAPI FPGA
AH15 AL13
MAPI Connectors Signal
Core Side
Ring Side
MMCCMB2102UM/D User's Manual
Cross Reference Tables
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA Signal
j_serial_out j_tclk (also connects J29-5) j_tdi (also connects J29-1) j_tdo (also connects J29-3) j_tms (also connects J29-10) j_trst_b (also connects J29-14) j_update_gp_reg_b jd_bkreq_b jd_debug_b jd_idr_b jd_mcu_ack_b jd_mcu_de_b (also connects J29-12) jd_wakeup_b m_bg_b m_br_b m_clk m_por m_rst_b m_tsca_b m_tscd_b m[0] m[1] m[2] p_abort_b (also connects U8-15) p_addr[0] p_addr[1] p_addr[2] p_addr[3] p_addr[4] p_addr[5] p_addr[6] p_addr[7] p_addr[8] p_addr[9]
MAPI FPGA
AK16 AD31 AJ15 AK17 AE30 AL16 AH28 AH29 AJ28 AA23 AF20 AD17 AE18 AF21 AF18 AE17 AD22 AE19 AD19 AF22 AF24 AE16 AD16
MAPI Connectors Signal
J3-85 J3-82 J3-80 J3-83 J3-87
Core Side
Ring Side
J3-54 J3-70 J3-42 J3-44 J3-58 MAPI_BG_B MAPI_BR_G J3-51 J3-53
MAPI_TSCA_B MAPI_TSCD_B
J3-45 J3-47
M_ABORT_B M_ADDR[0] M_ADDR[1] M_ADDR[2] M_ADDR[3] M_ADDR[4] M_ADDR[5] M_ADDR[6] M_ADDR[7] M_ADDR[8] M_ADDR[9]
J3-48 J4-42 J4-41 J4-44 J4-43 J4-46 J4-45 J4-48 J4-47 J4-50 J4-49
MMCCMB2102UM/D User's Manual
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA Signal
p_addr[10] p_addr[11] p_addr[12] p_addr[13] p_addr[14] p_addr[15] p_addr[16] p_addr[17] p_addr[18] p_addr[19] p_addr[20] p_addr[21] p_addr[22] p_addr[23] p_addr[24] p_addr[25] p_addr[26] p_addr[27] p_addr[28] p_addr[29] p_addr[30] p_addr[31] p_avec_b p_data[0] p_data[1] p_data[2] p_data[3] p_data[4] p_data[5] p_data[6] p_data[7] p_data[8] p_data[9] p_data[10] p_data[11] p_data[12] p_data[13] p_data[14] p_data[15] p_data[16]
MAPI FPGA
MAPI Connectors Signal
M_ADDR[10] M_ADDR[11] M_ADDR[12] M_ADDR[13] M_ADDR[14] M_ADDR[15] M_ADDR[16] M_ADDR[17] M_ADDR[18] M_ADDR[19] M_ADDR[20] M_ADDR[21] M_ADDR[22] M_ADDR[23] M_ADDR[24] M_ADDR{25] M_ADDR[26] M_ADDR[27] M_ADDR[28] M_ADDR[29] M_ADDR[30] M_ADDR[31] M_AVEC_B M_DATA[0] M_DATA[1] M_DATA[2] M_DATA[3] M_DATA[4] M_DATA[5] M_DATA[6] M_DATA[7] M_DATA[8] M_DATA[9] M_DATA[10] M_DATA[11] M_DATA[12] M_DATA[13] M_DATA[14] M_DATA[15] M_DATA[16]
Core Side
Ring Side
J4-52 J4-51 J4-54 J4-53 J4-56 J4-55 J4-60 J4-59 J4-62 J4-61 J4-64 J4-63 J4-66 J4-65 J4-68 J4-67 J4-70 J4-69 J4-72 J4-71 J4-74 J4-73 J1-80 J4-4 J4-3 J4-6 J4-5 J4-8 J4-7 J4-10 J4-9 J4-12 J4-11 J4-14 J4-13 J4-18 J4-17 J4-20 J4-19 J4-22
MMCCMB2102UM/D User's Manual
Cross Reference Tables
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA Signal
p_data[17] p_data[18] p_data[19] p_data[20] p_data[21] p_data[22] p_data[23] p_data[24] p_data[25] p_data[26] p_data[27] p_data[28] p_data[29] p_data[30] p_data[31] p_d2a p_fill_ir p_fint_b p_fint_raw_b p_gcb[0] p_gcb[1] p_gcb[2] p_gcb[3] p_gcb[4] p_gcb[5] p_gcb[6] p_gcb[7] p_gcb[8] p_gcb[9] p_gcb[10] p_gcb[11] p_gcb[12] p_gcb[13] p_gcb[14] p_gcb[15] p_gcb[16] p_gcb[17] p_gcb[18] p_gcb[19] p_gcb[20]
MAPI FPGA
AA29 AA30 AB29 AC29 AC30 AD29 AJ23 AK24 AF30 AH22 AH20 AK26 AL20 AF31 AH25
MAPI Connectors Signal
M_DATA[17] M_DATA[18] M_DATA[19] M_DATA[20] M_DATA[21] M_DATA[22] M_DATA[23] M_DATA[24] M_DATA[25] M_DATA[26] M_DATA[27] M_DATA[28] M_DATA[29] M_DATA[30] M_DATA[31] M_D2A M_FINT_B M_FINT_RAW_B
Core Side
Ring Side
J4-21 J4-24 J4-23 J4-26 J4-25 J4-30 J4-29 J4-32 J4-31 J4-34 J4-33 J4-36 J4-35 J4-38 J4-37 J3-36 J1-62 J1-70
MMCCMB2102UM/D User's Manual
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA Signal
p_gcb[21] p_gcb[22] p_gcb[23] p_gcb[24] p_gcb[25] p_gcb[26] p_gcb[27] p_gcb[28] p_gcb[29] p_gcb[30] p_gcb[31] p_gsb[0] p_gsb[1] p_gsb[2] p_gsb[3] p_gsb[4] p_gsb[5] p_gsb[6] p_gsb[7] p_gsb[8] p_gsb[9] p_gsb[10] p_gsb[11] p_gsb[12] p_gsb[13] p_gsb[14] p_gsb[15] p_gsb[16] p_gsb[17] p_gsb[18] p_gsb[19] p_gsb[20] p_gsb[21] p_gsb[22] p_gsb[23] p_gsb[24] p_gsb[25] p_gsb[26] p_gsb[27] p_gsb[28]
MAPI FPGA
AL26 AK18 AH26 AB28 AB31 AJ21 AK21 AJ25 AJ18 AK20 AD30 AL27 AD28 AK25
MAPI Connectors Signal
Core Side
Ring Side
MMCCMB2102UM/D User's Manual
Cross Reference Tables
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA Signal
p_gsb[29] p_gsb[30] p_gsb[31] p_int_b p_int_raw_b p_ipend_b p_lpmd[0] p_lpmd[1] p_pstat[0] p_pstat[1] p_pstat[2] p_pstat[3] p_rw_b p_seq_b p_ta_b p_tbusy_b p_tc[0] p_tc[1] p_tc[2] p_te_b p_tea_b p_treq_b p_tsiz[0] p_tsiz[1] p_vec[0] p_vec[1] p_vec[2] p_vec[3] p_vec[4] p_vec[5] p_vec[6] program_b t_lsrl_seral_out tb_dbist tb_dbist_serial_out tb_djc_tdi tb_dsp_tdo tb_dsp_tms tb_mbist tb_mbist_clk_disable_b
MAPI FPGA
AH10 AK10 AH14 AL10 AJ11 AK11 AH12 AK12 AJ14 AL12 AH13 AJ13 AK15 AA26 AB22 AC26 AB23 AB26 AB25 AB24 AA25 AA22 AF15 AE15
MAPI Connectors Signal
Core Side
Ring Side
M_INT_B M_INT_RAW_B M_IPEND_B
J1-79 J1-72 J1-78 J3-52 J3-50 J3-67 J3-69 J3-71 J3-73
M_RW_B M_SEQ_B M_TBUSY_B M_TC[0] M_TC[1] M_TC[2]
J4-81 J3-46 J3-72 J3-62 J3-64 J3-66
M_TREQ_B M_TSIZ[0] M_TSIZ[1] M_VEC[0] M_VEC[1] M_VEC[2] M_VEC[3] M_VEC[4] M_VEC[5] M_VEC[6]
J4-79 J3-86 J3-88 J1-81 J1-82 J1-83 J1-84 J1-85 J1-86 J1-87
MMCCMB2102UM/D User's Manual
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA Signal
tb_mbist_serial_out tb_mbist_tclk_disable_b tb_pram tb_prom tb_rti tb_xram tb_xrom tb_yram tb_yrom td_shift_dr_b tf_arri_b tf_arwi_b tf_bistclr tf_gp[0] tf_gp[1] tf_gp[2] tf_gp[3] tf_gp[4] tf_gp[5] tf_hi_z tf_iddq tf_mdi_mode tf_rst_bist tf_rst_hi_z tf_slv_mode tf_sof tp_clk_sel tp_clkgen_clk_disable_b tp_clkgen_clk_disable_b tp_dpath_clk_disable_b tp_dpath_tclk_disable_b tp_lsrl tp_off_bus_b tp_pie_clk_disable_b tp_pie_dpath_clk_disable_b tp_rce_clk_disable_b
MAPI FPGA
AJ17 AH17 AK14 AJ12 AH23 AJ22 AJ24 AJ26 AL19 AL22 AK27 AH18 AC28 AH19 AJ19 AK23 AE28 AJ20 AL24
MAPI Connectors Signal
Core Side
Ring Side
MMCCMB2102UM/D User's Manual
Cross Reference Tables
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA Signal
tp_rce_dpath_clk_disable_b tp_rst_scan_b tp_scan_clk_disable_b ts_chain_length[0] ts_chain_length[1] ts_scan ts_scip[0] ts_scip[18] ts_scop[0] ts_scop[1] ts_scop[2] ts_scop[3] ts_scop[4] ts_scop[5] ts_scop[6] ts_scop[7] ts_scop[8] ts_scop[9] ts_scop[10] ts_scop[11] ts_scop[12] ts_scop[13] ts_scop[14] ts_scop[15] ts_scop[16] ts_scop[17] ts_scop[18] ts_scow ts_test_en ts_wrap_hold ts_wrap_se ts_wrap_tmode[0] ts_wrap_tmode[1] write_b
MAPI FPGA
AL15 AA24
MAPI Connectors Signal
Core Side
Ring Side
MAPI_TA_B CLKUSR DATA_STRB_B DCLK
J4-77
MMCCMB2102UM/D User's Manual
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA Signal MAPI FPGA Core Side Ring Side
AC22 AC23 AC24 AD10 AD11 AD12 AD13 AD15 AD21 AD24 AD25 AE10 AE11 AE12 AE13 AE22 AE23 AE24 AF10 AF12 AF13
MAPI Connectors Signal
NICEO CONF_DONE CDATA[0] CDATA[1] CDATA[2] CDATA[4] FPGA[252] CDATA[6] CS_B[1] CS_B[4] CS_B[8] M_EB_B[3] DEV_CLRN FPGA[105] FPGA[99] FPGA[249] CDATA[5] CS_B[0] CS_B[2] CS_B[5] CS_B[7] M_EB_B[1] FPGAI[1] FPGA[101] CDATA[3] CDATA[7] CS_B[3] CS_B[6] CS_B[9] M_EB_B[0] M_EB_B[2] ADDR GCLK[0] J4-91 J1-93 J1-96 J4-86 J4-80 J4-85 J4-89 J1-95 J1-91 J4-84 J3-92 J4-87 J1-97 J1-98 J4-82
MMCCMB2102UM/D User's Manual
Cross Reference Tables
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA Signal MAPI FPGA Core Side Ring Side
AF14 AF17
MAPI Connectors Signal
FPGAI[0] FPGA[103] UART_B_INT FPGAI[2] MAPI_INT_b[6] MAPI_INT_B[3] MAPI_INT_B[14] MAPI_INT_B[13] MAPI_INT_B[10] PORTF[7] UARTA_INT MAPI_INT_B[7] MAPI_INT_B[5] MAPI_INT_B[1] MAPI_INT_B[12] MAPI_INT_B[11] MAPI_INT_B[8] PORTF[5] PORTF[3] FPGA[237] FPGA[240] MAPI_INT_B[4] MAPI_INT_B[15] MAPI_INT_B[2] MAPI_INT_B[9] PORTF[6] PORTF[4] PORTF[1] PORTF[2] PORTF[0] NCONFIG MSEL[1] MSEL[0] NTRST NSTATUS INIT_DONE M_OE_B RDYNBSY J4-88 J1-66 J1-53 J1-64 J1-47 J1-44 J1-42 J1-37 J1-38 J1-36 J1-67 J1-65 J1-61 J1-54 J1-49 J1-48 J1-43 J1-39 J1-68 J1-63 J1-56 J1-51 J1-50 J1-45
MMCCMB2102UM/D User's Manual
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA Signal MAPI FPGA Core Side Ring Side
MAPI Connectors Signal
L_ADDR_B MAPI_TEA_B J4-78
MMCCMB2102UM/D User's Manual
Cross Reference Tables
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring
Core FPGA
AA29 AA30 AB28 AB29 AB31 AC28 AC29 AC30 AD28 AD29 AD30 AD31 AE28 AE30 AF30 AF31
MAPI FPGA Core Side
MAPI Connectors Signal
M_ADDR[21] M_ADDR[22] M_DATA[26] M_DATA[27]
Signal
p_addr[21] p_addr[22] p_data[26] p_data[27] d[5] d[6] tf_gp[5] p_gsb[3] p_data[28] p_gsb[5] p_addr[23] ts_scan tb_xrom tf_rst_bist p_data[29] p_data[30] tp_pie_dpath_clk_disable_b p_addr[24] p_addr[25] j_serial_out p_gsb[20] p_data[31] p_gsb[17] jd_bkreq_b p_addr[26] p_addr[27] j_gp1_regsel tp_clkgen_tclk_disable_b jd_mcu_ack_b p_addr[28] tb_dsp_tdo j_update_gp_reg_b p_gcb[3] p_gcb[15] tb_mbist p_addr[29] p_addr[30] d[7] p_addr[31]
Ring Side
J4-63 J4-66 J4-34 J4-33
M_DATA[28] M_ADDR[23]
J4-36 J4-65
M_DATA[29] M_DATA[30] M_ADDR[24] M_ADDR[25]
J4-35 J4-38 J4-68 J4-67
AE16
M_DATA[31]
J4-37 J3-54
M_ADDR[26] M_ADDR[27]
J4-70 J4-69
AF18 M_ADDR[28]
J3-42 J4-72
M_ADDR[29] M_ADDR[30] M_ADDR[31]
J4-71 J4-74 J4-73
MMCCMB2102UM/D User's Manual
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA
AH10 AH12 AH13 AH14 AH15 AH17 AH18 AH19 AH20 AH22 AH23 AH25 AH26 AH28 AH29 AJ11 AJ12 AJ13 AJ14 AJ15 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22
MAPI FPGA Core Side Ring Side
MAPI Connectors Signal
Signal
program_b done j_tdo (also connects J29-3) p_lpmd[0] jd_mcu_de_b (also connects J29-12) p_pstat[1] p_rw_b p_tc[2] p_tsiz[0] p_ta_b j_en_tdo tb_pram tf_mdi_mode tf_rst_hi_z p_gcb[11] p_gcb[10] tf_bistclr p_gcb[18] p_gsb[1] m[0] m[1] init_b p_d2a m_rst_b j_en_tap_ctlr p_pstat[0] p_pstat[2] p_tc[0] td_shift_dr_b p_tsiz[1] p_tea_b jd_debug_b tb_mbist_tclk_disable_b p_gsb[14] tf_sof tp_dpath_tclk_disable_b p_gsb[10] tf_gp[0]
J3-80 AF15 AE17 J3-52 J3-44 J3-69 AA25 AB24 AB22 M_RW_B M_TC[2] M_TSIZ[0] J4-81 J3-66 J3-86
M_D2A
J3-36
J3-67 J3-71 AB26 AC26 AD16 M_TC[0] M_TSIZ[1] J3-62 J3-88 J3-70
MMCCMB2102UM/D User's Manual
Cross Reference Tables
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA
AJ23 AJ24 AJ25 AJ26 AJ28 AK10 AK11 AK12 AK14 AK15 AK16 AK17 AK18 AK20 AK21 AK23 AK24 AK25 AK26 AK27 AL10 AL12 AL13 AL15 AL16 AL19 AL20 AL22
MAPI FPGA Core Side Ring Side
MAPI Connectors Signal
Signal
p_gcb[0] tf_gp[1] p_gsb[12] tf_gp[2] m[2] j_tdi (also connects J29-1) p_lpmd[1] j_trst_b (also connects J29-14) tb_xram p_pstat[3] p_seq_b p_tc[1] p_te_b tb_yrom tb_djc_tdi j_tclk (also connects J29-5) jd_idr_ p_gsb[0] p_gsb[15] p_gsb[11] tp_clk_sel p_gcb[1] p_gsb[21] p_gcb[12] tf_iddq tb_yram tb_prom j_tms (also connects J29-10) j_capture_dr_b p_tbusy_b p_treq_b j_gp2_regsel tp_rst_scan_b m_clk tf_gp[3] p_gcb[14] tf_gp[4]
J3-82 AE15 J3-50 J3-87
J3-73 AA22 AB25 M_SEQ_B M_TC[1] J3-46 J3-64
J3-85
J3-83
AB23 AA26
M_TBUSY_B M_TREQ_B
J3-72 J4-79
MMCCMB2102UM/D User's Manual
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA
AL24 AL26 AL27
MAPI FPGA Core Side Ring Side
MAPI Connectors Signal
Signal
tp_lsrl p_gcb[21] p_gsb[18] p_aveb_b p_fint_raw_b p_vec[0] ts_scip[0] jd_wakeup_b gclk[2] tf_arri_b p_gcb[8] p_gsb[23] p_gcb[4] p_gsb[26] p_gcb[19] write_b p_fint_b ts_chain_length[1] p_fill_ir ts_wrap_tmode[1] p_vec[3] m_bg_b tp_off_bus_b p_ipend_b tp_rce_dpath_clk_disable_b tp_rce_clk_disable_b tp_dpath_clk_disable_b p_gsb[24] p_gcb[23] p_gsb[2] p_gcb[9] p_gsb[8] p_gcb[27] p_gcb[17] d[0] ts_chain_length[0] p_vec[1] ts_wrap_tmode[0]
AD22
M_AVEC_B M_FINT_RAW_B M_VEC[0] J3-58
J1-80 J1-70 J1-81 J3-58
M_FINT_B
J1-62
AE19
AF22
M_VEC[3] MAPI_BG_B M_IPEND_B
J1-84 J3-51 J1-78
M_VEC[1]
J1-82
MMCCMB2102UM/D User's Manual
Cross Reference Tables
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA
MAPI FPGA Core Side
AA23
MAPI Connectors Signal
M_VEC[4] M_VEC[6] M_ABORT_B
Signal
ts_wrap_se p_vec[4] p_vec[6] p_abort_b (also connects U8-15) tb_mbist_clk_disable_b tp_clkgen_clk_disable_b tp_scan_clk_disable_b p_gcb[28] p_gcb[2] p_gsb[31] p_gcb[13] p_gcb[20] p_gsb[25] p_gcb[25] ts_scop[7] p_addr[0] busy_dout cclk cs_b p_int_b p_int_raw_b p_vec[2] ts_wrap_hold p_vec[5] ts_scip[18] m_por tf_slv_mode gclk[3] tp_pie_clk_disable_b m_tscd_b p_gcb[31] p_gsb[28] p_gsb[27] p_gcb[26] p_data[[0] ts_scop[9] ts_scop[15]
Ring Side
J1-85 J1-87 J3-48
M_ADDR[0]
J4-42
M_INT_B M_INT_RAW_B M_VEC[2] M_VEC[5]
J1-79 J1-72 J1-83 J1-86
AD17
AF21
MAPI_TSCD_B
J3-47
M_DATA[0]
J4-4
MMCCMB2102UM/D User's Manual
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA
MAPI FPGA Core Side
MAPI Connectors Signal
M_ADDR[1] M_DATA[1] M_DATA[2] M_ADDR[2] M_ADDR[3] M_DATA[3] M_ADDR[4]
Signal
p_addr[1] ts_scop[6] p_data[1] p_data[[2] tf_arwi_b p_addr[2] p_addr[3] ts_scop[13] p_data[[3] p_addr[4] ts_scop[12] ts_scop[18] p_data[[4] p_data[[5] ts_scop[17] p_addr[5] p_addr[6] ts_scop[8] p_data[[6] p_data[[7] p_gsb[19] ts_scow] p_addr[7] ts_scop[3] p_gsb[29] p_data[[8] p_gsb[22] ts_scop[1] d[2] d[1] p_data[[9] p_gcb[22] p_addr[8] p_addr[9] p_data[10] p_data[11] ts_scop14] p_addr[10] ts_scop[16] ts_test_en]
Ring Side
J4-41 J4-3 J4-6 J4-44 J4-43 J4-5 J4-46
M_DATA[4] M_DATA[5] M_ADDR[5] M_ADDR[6] M_DATA[6] M_DATA[7]
J4-8 J4-7 J4-45 J4-48 J4-10 J4-9
M_ADDR[7]
J4-47
M_DATA[8]
J4-12
M_DATA[9] M_ADDR[8] M_ADDR[9] M_DATA[10] M_DATA[11] M_ADDR[10]
J4-11 J4-50 J4-49 J4-14 J4-13 J4-52
MMCCMB2102UM/D User's Manual
Cross Reference Tables
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA
MAPI FPGA Core Side
MAPI Connectors Signal
M_DATA[12] M_DATA[13]
Signal
p_gsb[30] p_data[12] p_data[13] p_gcb[30] ts_scop[10] p_addr[11] ts_scop[2] p_gcb[16] p_gsb[4] p_gcb[7] p_addr[12] p_addr[13] d[3] p_gsb[9] p_data[14] p_data[15] ts_scop[4] p_addr[14] ts_scop[0] ts_scop[5] tb_rti p_data[16] p_data[17] p_gsb[13] p_addr[15] p_addr[16] p_data18] tf_hi_z t_lsrl_serial_out p_addr[17] ts_scop[11] p_gsb[7] p_data[19] p_data[20] p_gcb[29] tb_mbist_serial_out p_addr[18] d[4] p_gcb[5] p_data[21]
Ring Side
J4-18 J4-17
M_ADDR[11]
J4-51
M_ADDR[12] M_ADDR[13]
J4-54 J4-53
M_DATA[14] M_DATA[15] M_ADDR[14]
J4-20 J4-19 J4-56
M_DATA[16] M_DATA[17] M_ADDR[15] M_ADDR[16] M_DATA[18]
J4-22 J4-21 J4-55 J4-60 J4-24
M_ADDR[17]
J4-59
M_DATA[19] M_DATA[20]
J4-23 J4-26
M_ADDR[18]
J4-62
M_DATA[21]
J4-25
MMCCMB2102UM/D User's Manual
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA
MAPI FPGA Core Side
AF20 AD19
MAPI Connectors Signal
M_DATA[22] M_ADDR[19] MAPI_TSCA_B M_DATA[23] M_DATA[24] M_ADDR[20] MAPI_BR_G
Signal
p_data[22] tb_dsp_tms p_addr[19] m_tsca_b p_gsb[16] p_data[23] p_data[24] tb_dbist_serial_out p_addr[20] m_br_b tb_dbist p_gcb[24] p_data[25] p_gsb[6] p_gcb[6]
Ring Side
AE18 AF24
J4-30 J4-61 J3-45 J4-29 J4-32 J4-64 J3-53
M_DATA[25]
J4-31
AA24 AC22 AC23 AC24 AD10 AD11 AD12 AD13 AD15 AD21 AD24 AD25
MAPI_TA_B CLKUSR DATA_STRB_B DCLK NCEO CONF_DONE CDATA[0] CDATA[1] CDATA[2] CDATA[4] FPGA[252] CDATA[6] CS_B[1] CS_B[4] CS_Bb[8] M_EB_B[3] DEV_CLRN FPGA[105] FPGA[99]
J4-77
J4-87 J1-97 J1-98 J4-82
J3-92
MMCCMB2102UM/D User's Manual
Cross Reference Tables
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA Signal MAPI FPGA Core Side Ring Side
AE10 AE11 AE12 AE13 AE22 AE23 AE24 AF10 AF12 AF13 AF14 AF17
MAPI Connectors Signal
FPGA[249] CDATA[5] CS_B[0] CS_B[2] CS_B[5] CS_B[7] M_EB_B[1] FPGAI[1] FPGA[101] CDATA[3] CDATA[7] CS_B[3] CS_B[6] CS_B[9] M_EB_B[0] M_EB_B[2] ADDR GCLK[0] FPGAI[0] FPGA[103] UARTB_INT FPGAI[2] MAPI_INT_Bb[6] MAPI_INT_B[3] MAPI_INT_B[14] MAPI_INT_B[13] MAPI_INT_B[10] PORTF[7] UARTA_INT MAPI_INT_B[7] MAPI_INT_B[5] MAPI_INT_B[1] MAPI_INT_B[12] MAPI_INT_B[11] MAPI_INT_B[8] PORTF[5] J1-67 J1-65 J1-61 J1-54 J1-49 J1-48 J1-43 J1-68 J1-63 J1-56 J1-51 J1-50 J1-45 J4-91 J1-93 J1-96 J4-86 J4-80 J4-85 J4-89 J1-95 J1-91 J4-84
MMCCMB2102UM/D User's Manual
Table Cross Reference: Core FPGA, MAPI FPGA, MAPI Ring (Continued)
Core FPGA Signal MAPI FPGA Core Side Ring Side
MAPI Connectors Signal
PORTF[3] FPGA[237] FPGA[240] MAPI_INT_B[4] MAPI_INT_B[15] MAPI_INT_B[2] MAPI_INT_B[9] PORTF[6] PORTF[4] PORTF[1] PORTF[2] PORTF[0] NCONFIG MSEL[1] MSEL[0] NTRST NSTATUS INIT_DONE M_OE_B RDYNBSY L_ADDR_B MAPI_TEA_B J4-78 J4-88 J1-66 J1-53 J1-64 J1-47 J1-44 J1-42 J1-37 J1-38 J1-36
J1-39
MMCCMB2102UM/D User's Manual
Cross Reference Tables
Table Cross Reference: MAPI Ring, MAPI FPGA, Core FPGA
MAPI Connectors Default Signal
CS_B[0] CS_B[1] CS_B[2] CS_B[3] CS_B[4] CS_B[5] CS_B[6] CS_B[7] CS_B[8] CS_B[9] MAPI_BG_B MAPI_BR_G MAPI_INT_B[1] MAPI_INT_B[2] MAPI_INT_B[3] MAPI_INT_B[4] MAPI_INT_B[5] MAPI_INT_B[6] MAPI_INT_B[7] MAPI_INT_B[8] MAPI_INT_B[9] MAPI_INT_B[10] MAPI_INT_B[11] MAPI_INT_B[12] MAPI_INT_B[13] MAPI_INT_B[14] MAPI_INT_B[15] MAPI_TA_B MAPI_TEA_B MAPI_TSCA_B MAPI_TSCD_B M_ABORT_B
MAPI FPGA Ring Side
AD10 AE10 AD11 AF22 AF24 AE18 AF21 AF20 AD17 AA23 AE19 AD19
Core FPGA Signal
J4-85 J4-87 J4-89 J4-91 J1-97 J1-95 J1-93 J1-91 J1-98 J1-96 J3-51 J3-53 J1-61 J1-64 J1-63 J1-66 J1-65 J1-68 J1-67 J1-48 J1-47 J1-50 J1-49 J1-54 J1-51 J1-56 J1-53 J4-77 J4-78 J3-45 J3-47 J3-48
Core Side
m_bg_b m_br_b
m_tsca_b m_tscd_b p_abort_b (also connects U8-15) p_addr[0] p_addr[1] p_addr[2] p_addr[3] p_addr[4]
M_ADDR[0] M_ADDR[1] M_ADDR[2] M_ADDR[3] M_ADDR[4]
J4-42 J4-41 J4-44 J4-43 J4-46
MMCCMB2102UM/D User's Manual
Table Cross Reference: MAPI Ring, MAPI FPGA, Core FPGA (Continued)
MAPI Connectors Default Signal
M_ADDR[5] M_ADDR[6] M_ADDR[7] M_ADDR[8] M_ADDR[9] M_ADDR[10] M_ADDR[11] M_ADDR[12] M_ADDR[13] M_ADDR[14] M_ADDR[15] M_ADDR[16] M_ADDR[17] M_ADDR[18] M_ADDR[19] M_ADDR[20] M_ADDR[21] M_ADDR[22] M_ADDR[23] M_ADDR
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