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Cautions
Keep safety first your circuit designs! Renesas Technology Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) nonflammable material (iii) prevention against malfunction mishap. Notes regarding these materials These materials intended reference assist customers selection Renesas Technology Corporation product best suited customer's application; they convey license under intellectual property rights, other rights, belonging Renesas Technology Corporation third party. Renesas Technology Corporation assumes responsibility damage, infringement third-party's rights, originating product data, diagrams, charts, programs, algorithms, circuit application examples contained these materials. information contained these materials, including product data, diagrams, charts, programs algorithms represents information products time publication these materials, subject change Renesas Technology Corporation without notice product improvements other reasons. therefore recommended that customers contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor latest product information before purchasing product listed herein. information described here contain technical inaccuracies typographical errors. Renesas Technology Corporation assumes responsibility damage, liability, other loss rising from these inaccuracies errors. Please also attention information published Renesas Technology Corporation various means, including Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). When using information contained these materials, including product data, diagrams, charts, programs, algorithms, please sure evaluate information total system before making final decision applicability information products. Renesas Technology Corporation assumes responsibility damage, liability other loss resulting from information contained herein. Renesas Technology Corporation semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor when considering product contained herein specific purposes, such apparatus systems transportation, vehicular, medical, aerospace, nuclear, undersea repeater use. prior written approval Renesas Technology Corporation necessary reprint reproduce whole part these materials. these products technologies subject Japanese export control restrictions, they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations Japan and/or country destination prohibited. Please contact Renesas Technology Corporation further details these materials products contained therein.
HD404889/HD404899/HD404878/ HD404868 Series
Low-Voltage Microcomputers with On-Chip Circuit
ADE-202-075D Rev. Feb. 2000 Description
HD404889, HD404899, HD404868 Series comprise low-voltage, 4-bit single-chip microcomputers with variety on-chip supporting functions that include circuit, converter, multifunctional timers, large-current pins. These devices suitable system display panel control wide range applications, including pagers, remote controllers, home appliances equipped with display. HD404878 Series comprises low-voltage, 4-bit single-chip microcomputers with on-chip converter. Each series equipped with 32.768 sub-resonator realtime clock use, providing time counting facility, variety low-power modes reduce current drain. HD4074889, HD4074899, HD4074869 ZTATmicrocomputers with on-chip PROM that drastically shortens development time ensures smooth transition from debugging mass production. (The PROM programming specifications same 27256 type.) ZTAT Zero Turn-Around Time. ZTAT trademark Hitachi, Ltd.
Features
pins (HD404889/HD404899/HD404878 Series) pins (HD404868 Series) Large-current pins (source: max.):4 Large-current pins (sink: max.): (HD404889/HD404899/HD404878 Series) (HD404868 Series) segment multiplexed pins:16 Analog input multiplexed pins: (HD404889 HD404899 Series) (HD404868 Series)
Series
Four Timer/counters 8-bit timer: (HD404889/HD404899/HD404878 Series) (HD404868 Series) 16-bit timer:1 (Can also used 8-bit timer) 8-bit input capture circuit (HD404889/HD404899/HD404878 Series) timer outputs (including out-put) event counter inputs (edge-programmable) (HD404889/HD404899/HD404878 Series) event counter input (edge-programmable) (HD404868 Series) Clock-synchronous 8-bit serial interface converter channels 8-bit (HD404889 Series) channels 10-bit (HD404899 Series) channels 10-bit (HD404868 Series) controller/driver segments commons) (HD404889/HD404899/HD404878 Series) segments commons) (HD404868 Series) On-chip oscillators Main clock (ceramic resonator, crystal resonator, external clock operation possible) Sub-clock (32.768 crystal resonator) Interrupts External: (including edge-programmable) Internal (HD404889 HD404899 Series) (HD404878 HD404868 Series) Subroutine stack levels, including interrupts Four Low-power dissipation modes Module standby (timers, serial interface, converter) System clock division software switching (1/4 1/32) Inputs return from stop mode (wakeup): Instruction execution time Min. 0.89 (fOSC MHz) Operation voltage
Cautions about operation!
Electrical properties presented data sheet mask ZTATversions will surely sufficiently satisfy standard values. However, real capabilities, operation margin, noise margin, other properties vary depending differences manufacturing processes, internal wiring patterns, etc. Therefore, requested users carry evaluation test each product actual system under same conditions operation. Memory register, data area, stack area values unstable immediately after power turned They must initialized before use.
Series
Ordering Information
HD404889 Series
Type Product Name Model Name HD404888H HD404888TE HD4048812 HD4048812H HD4048812TE HD404889 HD404889H HD404889TE HCD404889 ZTAT
(Words) 8,192
(Digits) 1,344
Package 80-pin plastic (FP-80A) 80-pin plastic TQFP (TFP-80C)
Mask HD404888
12,288
80-pin plastic (FP-80A) 80-pin plastic TQFP (TFP-80C)
16,384
80-pin plastic (FP-80A) 80-pin plastic TQFP (TFP-80C) Chip
HCD404889 HD4074889H HD4074889TE 16,384
HD4074889
80-pin plastic QFP*1 (FP-80A) 80-pin plastic TQFP (TFP-80C)
Notes: ZTATchip shipment supported. specifications shipped chips differ from those package product. Please contact sales staff details.
Series
HD404899 Series
Type Product Name Model Name HD404898H HD404898TE HD4048912 HD4048912H HD4048912TE HD404899 HD404899H HD404899TE HCD404899 ZTAT
(Words) 8,192
(Digits) 1,344
Package 80-pin plastic (FP-80A) 80-pin plastic TQFP (TFP-80C)
Mask HD404898
12,288
80-pin plastic (FP-80A) 80-pin plastic TQFP (TFP-80C)
16,384
80-pin plastic (FP-80A) 80-pin plastic TQFP (TFP-80C) Chip
HCD404899 HD4074899H HD4074899TE 16,384
HD4074899
80-pin plastic QFP*1 (FP-80A) 80-pin plastic TQFP (TFP-80C)
Notes: ZTATchip shipment supported. specifications shipped chips differ from those package product. Please contact sales staff details. planning stage.
HD404878 Series
Type Product Name Model Name HD404874H HD404874TE HD404878 HD404878H HD404878TE HCD404878 ZTAT
(Words) 4,096
(Digits)
Package 80-pin plastic (FP-80A) 80-pin plastic TQFP (TFP-80C)
Mask HD404874
8,192
80-pin plastic (FP-80A) 80-pin plastic TQFP (TFP-80C) Chip
HCD404878
HD4074889 HD4074899 used.
Notes: ZTATchip shipment supported. specifications shipped chips differ from those package product. Please contact sales staff details. planning stage.
Series
HD404868 Series
Type Product Name Model Name HD404864H HD404864S HD404868 HD404868H HD404868S HCD404868 ZTAT
(Words) 4,096
(Digits)
Package 64-pin plastic (FP-64A) 64-pin plastic DILP (DP-64S)
Mask HD404864
8,192
64-pin plastic (FP-64A) 64-pin plastic DILP (DP-64S) Chip
HCD404868 HD4074869H HD4074869S 16,384
HD4074869
64-pin plastic (FP-64A) 64-pin plastic DILP (DP-64S)
Note: planning stage
Series
List Functions
Product Name (words) (digit) Large-current pins segment multiplexed pins Analog input multiplexed pins Timer/counter HD404888 8,192 HD4048812 12,288 1,344 (max) (source, max), (sink, max) 16-bit timer: (Can also used 8-bit timer), 8-bit timer: Input capture Timer output Event input Serial interface converter circuit Interrupt sources External Internal Low-power modes Stop mode Watch mode Standby mode Subactive mode Module standby System clock division software switching Main oscillator Ceramic oscillation Crystal oscillation Sub-oscillator Crystal oscillation (PWM output possible) (edge selection possible) (8-bit synchronous) bits channels Max. (edge selection possible (32.768kHz) 0.89µs(fOSC=4.5MHz) 80-pin plastic (FP-80A) 80-pin plastic TQFP (TFP-80C) Guaranteed operation temperature(°C) Chip HD404889 HCD404889 16,384
Minimum instruction execution time Operating voltage Package
Series
Product Name (words) (digit) Large-current pins segment multiplexed pins Analog input multiplexed pins Timer/counter HD4074889 16,384PROM HD404898 8,192 1,344 (max) (source, max), (sink, max) 16-bit timer: (Can also used 8-bit timer), 8-bit timer: Input capture Timer output Event input Serial interface converter circuit Interrupt sources External Internal Low-power modes Stop mode Watch mode Standby mode Subactive mode Module standby System clock division software switching Main oscillator Ceramic oscillation Crystal oscillation Sub-oscillator Crystal oscillation bits channels (PWM output possible) (edge selection possible) (8-bit synchronous) bits channels Max. (edge selection possible (32.768kHz) 0.89µs(fOSC=4.5MHz) HD4048912 12,288 HD404899 16,384
Minimum instruction execution time Operating voltage Package Guaranteed operation temperature(°C)
80-pin plastic (FP-80A) 80-pin plastic TQFP (TFP-80C)
Series
Product Name (words) (digit) Large-current pins segment multiplexed pins Analog input multiplexed pins Timer/counter HD40C4899 16,384 HD4074899 16,384PROM 1,344 (max) (source, max), (sink, max) HD404874 4,096 HD404878 8,192
16-bit timer: (Can also used 8-bit timer), 8-bit timer: (PWM output possible) (edge selection possible) (8-bit synchronous) bits channels Max. External Internal (edge selection possible (32.768kHz) 0.89µs(fOSC=4.5MHz) Chip
Input capture Timer output Event input Serial interface converter circuit Interrupt sources
Low-power modes Stop mode Watch mode Standby mode Subactive mode Module standby System clock division software switching Main oscillator Ceramic oscillation Crystal oscillation Sub-oscillator Crystal oscillation
Minimum instruction execution time Operating voltage Package
80-pin plastic (FP-80A) 80-pin plastic TQFP (TFP-80C)
Guaranteed operation temperature(°C)
Series
Product Name (words) (digit) Large-current pins HCD404878 8,192 (max) (source, max), (sink, max) 16-bit timer: (Can also used 8-bit timer), 8-bit timer: (edge selection possible) HD404864 4,096 (max) (source, max), (sink, max) HD404868 8,192 HD4074869 16,384PROM
segment multiplexed pins Analog input multiplexed pins Timer/counter
16-bit timer: (Can also used 8-bit timer), 8-bit timer:
Input capture Timer output Event input
(PWM output possible) (edge selection possible)
Serial interface converter circuit Interrupt sources Low-power modes Stop mode Watch mode Standby mode Subactive mode Module standby System clock division software switching Main oscillator Sub-oscillator Ceramic oscillation Crystal oscillation Crystal oscillation Chip Minimum instruction execution time Operating voltage Package Guaranteed operation temperature(°C) External Internal
(8-bit synchronous) bits channels Max. Max. (edge selection possible (32.768kHz) 0.89µs(fOSC=4.5MHz) 64-pin plastic (FP-64A) 64-pin plastic DILP (DP-64S)
Series
Arrangement
HD404889/HD404899 Series COM4 COM3 COM2 COM1 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 AVcc R70/AN0 R71/AN1 R72/AN2 R73/AN3 R80/AN4 R81/AN5 AVss TEST OSC1 OCS2 RESET D0/INT0 D1/INT1
FP-80A TFP-80C (Top View)
SEG20 SEG19 SEG18 SEG17 R63/SEG16 R62/SEG15 R61/SEG14 R60/SEG13 R53/SEG12 R52/SEG11 R51/SEG10 R50/SEG9 R43/SEG8 R42/SEG7 R41/SEG6 R40/SEG5 R33/SEG4 R32/SEG3 R31/SEG2 R30/SEG1
R00/WU0 R01/WU1 R02/WU2 R03/WU3 R10/EVNB R11/EVND R12/BUZZ R13/TOB R20/TOC R21/SCK R22/SI/SO
Series
HD404878 Series COM4 COM3 COM2 COM1 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 TEST OSC1 OSC2 RESET D0/INT0 D1/INT1
FP-80A TFP-80C (Top View)
SEG20 SEG19 SEG18 SEG17 R63/SEG16 R62/SEG15 R61/SEG14 R60/SEG13 R53/SEG12 R52/SEG11 R51/SEG10 R50/SEG9 R43/SEG8 R42/SEG7 R41/SEG6 R40/SEG5 R33/SEG4 R32/SEG3 R31/SEG2 R30/SEG1
R00/WU0 R01/WU1 R02/WU2 R03/WU3 R10/EVNB R11/EVND R12/BUZZ R13/TOB R20/TOC R21/SCK R22/SI/SO
Series
COM4 COM3 COM2 COM1 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 R63/SEG16
HD404868 Series
R70/AN0 R71/AN1 R72/AN2 R73/AN3 TEST OSC1 OSC2 RESET D0/INT0 D1/INT1
FP-64A (Top View)
R62/SEG15 R61/SEG14 R60/SEG13 R53/SEG12 R52/SEG11 R51/SEG10 R50/SEG9 R43/SEG8 R42/SEG7 R41/SEG6 R40/SEG5 R33/SEG4 R32/SEG3 R31/SEG2 R30/SEG1
R00/WU0 R01/WU1 R02/WU2 R10/EVNB R12/BUZZ R13/TOB R20/TOC R21/SCK R22/SI/SO
COM1 COM2 COM3 COM4 R70/AN0 R71/AN1 R72/AN2 R73/AN3 TEST OSC1 OSC2 RESET D0/INT0 D1/INT1 R00/WU0 R01/WU1 R02/WU2
DP-64S (Top View)
SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 R63/SEG16 R62/SEG15 R61/SEG14 R60/SEG13 R53/SEG12 R52/SEG11 R51/SEG10 R50/SEG9 R43/SEG8 R42/SEG7 R41/SEG6 R40/SEG5 R33/SEG4 R32/SEG3 R31/SEG2 R30/SEG1 R22/SI/SO R21/SCK R20/TOC R13/TOB R12/BUZZ R10/EVNB
Series
Arrangement
HCD404889, HCD404899
Model Name
Model Name: HD404889 (HCD404889) HD404899 (HCD404899)
Series
Coordinates
HCD404889, HCD404899
Chip size Coordinates: Mold Chip center (X=0,Y=0) 4.63 4.77 (mm) center
Home point position: Chip center size (µm) Chip thickness: (µm)
name R70/AN0 R71/AN1 R72/AN2 R73/AN3 R80/AN4 R81/AN5 TEST OSC1 OSC2 RESETN D0/INT0N D1/INT1 R00/WU0N R01/WU1N R02/WU2N R03/WU3N R10/EVNB R11/EVND R12/BUZZ R13/TOB R20/TOC R21/SCKN R22/Si/SO
Coodinates (µm) -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -1677 -1506 -1335 -1163 -992 -821 -649 -478 -307 -135 1064 1236 1407 1588
(µm) 1779 1589 1417 1246 1074 -240 -434 -605 -776 -948 -1119 -1290 -1462 -1633 -1804 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199
name R30/SEG1 R31/SEG2 R32/SEG3 R33/SEG4 R40/SEG5 R41/SEG6 R42/SEG7 R43/SEG8 R50/SEG9 R51/SE10 R52/SEG11 R53/SEG12 R60/SEG13 R61/SEG14 R62/SEG15 R63/SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 COM1 COM2 COM3 COM4
Coodinates (µm) 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 1588 1407 1236 1064 -135 -307 -478 -649 -821 -992 -1163 -1335 -1506 -1677
(µm) -1787 -1616 -1445 -1273 -1102 -973 -759 -588 -417 -245 1126 1297 1477 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199
Series
Arrangement
HCD404878
Model Name
Model Name: HD404878 (HCD404878)
Series
Coordinates
HCD404878
Chip size Coordinates: Mold Chip center (X=0,Y=0) 4.13 4.26 (mm) center
Home point position: Chip center size (µm) Chip thickness: (µm)
name TEST OSC1 OSC2 RESETN D0/INT0N D1/INT1 R00/WU0N R01/WU1N R02/WU2N R03/WU3N R10/EVNB R11/EVND R12/BUZZ R13/TOB R20/TOC R21/SCKN R22/Si/SO R30/SEG1
Coodinates (µm) -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1654 -1488 -1322 -1155 -989 -823 -656 -490 -324 -158 1007 1173 1339 1506 1879
(µm) 1446 1280 1114 -239 -406 -572 -738 -905 -1071 -1237 -1404 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1571
name R31/SEG2 R32/SEG3 R33/SEG4 R40/SEG5 R41/SEG6 R42/SEG7 R43/SEG8 R50/SEG9 R51/SE10 R52/SEG11 R53/SEG12 R60/SEG13 R61/SEG14 R62/SEG15 R63/SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 COM1 COM2 COM3 COM4
Coodinates (µm) 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1509 1351 1192 1033 -237 -411 -570 -728 -887 -1038 -1194 -1351 -1507
(µm) -1405 -1239 -1072 -906 -740 -573 -407 -241 1087 1246 1405 1564 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943
Series
Description
HD404889/HD404899/HD404878 Series
Number Item Power supply Test Reset Oscillation Symbol TEST RESET OSC1 OSC2 Port D0-D11 FP-80A TFP-80C 17-28 Input Input Input Output Input Output Function Apply power supply voltage this pin. Connect ground. user application. Connect potential. Used reset MCU. Internal oscillator input/output pins. Connect ceramic resonator, crystal resonator, external oscillator circuit. Realtime clock oscillator input/output pins. Connect 32.768 crystal. 32.768 crystal oscillation used, leave open. pins addressed bit. large-current source pins (max. mA), largecurrent sink pins (max. mA). pins, addressed 4-bit units. External interrupt input pins Input pins used transition from stop mode active mode. Serial interface clock Serial interface receive data input Serial interface transmit data output Timer output pins Event count input pins driver power supply pins. on-chip power supply dividing resistor disconnected software. Power supply conditions are: VCCV1V 3GND. common signal pins segment signal pins converter power supply pin. Connect close possible same potential VCC. Ground AVCC. Connect close possible same potential GND. converter analog input pins Timer overflow toggle output divided system clock output Connect ground potential.
R00-R6 R70-R8 Interrupt Wakeup Serial interface INT0,INT1 WU0-WU3 Timer TOB,TOC EVNB,EVND V0-V3
29-56, 17,18 29-32 36,37 33,34 80-77
Input Input Input Output Output Input
COM1-COM4 SEG1-SEG32 converter*1
73-76 41-72
Output Output
AN0-AN Buzzer output Other BUZZ
Input Output
Notes: Applies HD404889 HD404899 series. Applies HD404878 series.
Series
HD404868 Series
Number FP-64A Item Power supply Test Reset Oscillation Symbol TEST RESET OSC1 OSC2 Port D0-D9 13-22 20-29 DP-64S Input Input Input Function Apply power supply voltage this pin. Connect ground. user application. Connect potential. Used reset MCU.
Internal oscillator input/output pins. Connect ceramic resonator, crystal resonator, external Output oscillator circuit. Input Realtime clock oscillator input/output pins. Connect 32.768 crystal. 32.768 Output crystal oscillation pinnot used, leave open. pins addressed bit. largecurrent source pins (max. mA), large-current sink pins (max. mA). pins, addressed 4-bit units.
R00-R0 R10-R6 R70-R7 Interrupt Wakeup Serial interface INT0,INT1 WU0-WU2 Timer TOB,TOC EVNB V1-V3
23-25 26-49 13,14 23-25 64-62
30-32 33-56 8-11 30-32
Input Input Input
External interrupt input pins Input pins used transition from stop mode active mode. Serial interface clock Serial interface receive data input
Output Serial interface transmit data output Output Timer output pins Input Event count input pins driver power supply pins. on-chip power supply dividing resistor disconnected software. Power supply conditions are: VCCV1V 3GND.
COM1-COM4 SEG1-SEG24 converter Buzzer output AN0-AN BUZZ
58-61 34-57
41-64 8-11
Output common signal pins Output segment signal pins Input converter analog input pins Output Timer overflow toggle output divided system clock output
Series
Block DiagramG
HD404889/HD404899 Series
RESET TEST OSC1 OSC2
HMCS400
P-MOS largecurrent buffer
Port
N-MOS largecurrent buffer
8-bit timer EVNB
8-bit timer
EVND
8-bit timer
SI/SO AVcc AVss SEG1 SEG32 COM1 COM4 BUZZ
Synchronous serial interface
Buzzer output circuit
Data
Port
circuit 32-segment common
Port
Port
converter 8-bit channels (HD404889 Series) 10-bit channels (HD404899 Series)
Port
Port
Port
Port
Port
8-bit timer
Port
INT0 INT1
External interrupt control circuit
Signal line
Series
HD404878 Series
RESET TEST OSC1 OSC2
HMCS400
P-MOS largecurrent buffer
Port
N-MOS largecurrent buffer
8-bit timer EVNB
8-bit timer
EVND
8-bit timer
SI/SO
Clock-synchronous 8-bit serial interface
SEG1 SEG32 COM1 COM4 BUZZ
Buzzer output circuit
Data
Port
circuit 32-segment common
Port
Port
Port
Port
Port
Port
Port
8-bit timer
Port
INT0 INT1
External interrupt control circuit
Signal line
Series
HD404868 Series
RESET TEST
OSC1 OSC2
HMCS400
P-MOS largecurrent buffer
Port
N-MOS largecurrent buffer
Port
INT0 INT1
External interrupt control circuit
8-bit timer Port
EVNB
8-bit timer
8-bit timer
Clock-synchronous 8-bit serial interface
Port
SI/SO
Port
converter channels 10-bit
SEG1
SEG24 COM1 COM4
Port
Port
Port
Buzzer output circuit
BUZZ
Port
circuit 24-segment common
Series
Memory
Memory memory shown figure described below. Vector address area ($0000 $000F): When reset interrupt handling performed, program executed from vector address. JMPL instruction should used branch start address reset routine interrupt routine. Zero page subroutine area ($0000 $003F):A branch made subroutine area $0000 $003F with instruction. Pattern area ($0000 $0FFF): data area $0000 $0FFF referenced pattern data with instruction. Program area ($0000 $0FFF(HD404874, HD404864)), ($0000 $1FFF (HD404888, HD404898, HD404878, HD404868, HCD404878)), ($0000 $2FFF (HD4048812, HD4048912)), ($0000 $3FFF (HD404889, HD404899, HCD404889, HCD404899, HD4074899, HD4074889, HD4074869))
Series
$0000 $000F Zero page subroutine area words) $003F HD404874/HD404864 pattern/program area (4,096 words) Vector addresses words) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $0FFF $000A $000B HD404888/HD404898/HD404878/ HD404868/HCD404878 pattern/program area (8,192 words) $1FFF $000C $000D $000E $000F JMPL instruction (Jump reset routine) JMPL instruction (Jump routine) JMPL instruction (Jump INT0 routine) JMPL instruction (Jump INT1 routine) JMPL instruction (Jump timer routine) JMPL instruction (Jump timer B/timer routine) JMPL instruction (Jump timer routine) JMPL instruction (Jump serial interface routine)
HD4048812/HD4048912 pattern/program area (12,288 words)
$2FFF HD404889/HD4074889/ HD404899/HD4074899/HD4074869/ HCD404889/HCD404899 pattern/program area (16,384 words) $3FFF
Figure Memory Memory on-chip comprising memory register area, data area, data area, stack area. addition these areas, interrupt control area, special register area, register flag area mapped onto memory space RAM-mapped register area.The memory shown figure described below. Memory register, data area, data area, stack area values unstable immediately after power turned They must initialized before use.
Series
HD404889 Series
$000 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F
Interrupt control area Speed Select Reg. (SSR) Miscellaneous Reg. (MIS) Edge Select Reg. (ESR) used Port Mode Reg.0 (PMR0) Port Mode Reg.1 (PMR1) Port Mode Reg.2 (PMR2) Port Mode Reg.3 (PMR3) Port Mode Reg.4 (PMR4) Module Standby Reg.1 (MSR1) Module Standby Reg.2 (MSR2) Timer Mode Reg.A (TMA) Timer Mode Reg.B1 (TMB1) Timer Mode Reg.B2 (TMB2) (TRBL/TWBL) Timer-B (TRBU/TWBU) Timer Mode Reg.C1 (TMC1) Timer Mode Reg.C2 (TMC2) (TRCL/TWCL) Timer-C (TRCU/TWCU) Timer Mode Reg.D1 (TMD1) Timer Mode Reg.D2 (TMD2) (TRDL/TWDL) Timer-D (TRDU/TWDU) used
RAM-mapped register area
$03F $040 $04F $050
Memory register (MR) area digits) data area digits)
$06F $070 used $08F $090
Data (464 digits) (bank
Data (464 digits) (bank
Register flag area Serial Mode Reg.1 Serial Mode Reg.2 Serial Data Reg.Lower Serial Data Reg.Upper Mode reg. used Data Reg.Lower Data Reg.Upper Control Reg. Mode Reg. Buzzer Mode Reg. used Port D0~D3 Port D4~D7 Port D8~D11 used Port Port Port Port Port Port Port Port Port used Vreg. (SMR1) (SMR2) (SRL) (SRU) (AMR) (ADRL) (ADRU) (LCR) (LMR) (BMR) (DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) (DCR8)
$25F $260
Data (304 digits)
$38F $390 used $3BF $3C0
Stack area digits) $3FF
Notes:
Read Write
$012 $013 $016 $017 $01A $01B
Timer Read Reg.B Lower Timer Read Reg.B Upper Timer Read Reg.C Lower Timer Read Reg.C Upper Timer Read Reg.D Lower Timer Read Reg.D Upper
(TRBL) (TRBU) (TRCL) (TRCU) (TRDL) (TRDU)
Timer Write Reg.B Lower Timer Write Reg.B Upper Timer Write Reg.C Lower Timer Write Reg.C Upper Timer Write Reg.D Lower Timer Write Reg.D Upper
(TWBL) (TWBU) (TWCL) (TWCU) (TWDL) (TWDU)
Read/Write *Two registers mapped onto same address ($012, $013, $016, $017, $01A, $01B).
Figure Memory
Series
HD404899 Series
$000 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F
Interrupt control area Speed Select Reg. (SSR) Miscellaneous Reg. (MIS) Edge Select Reg. (ESR) used Port Mode Reg.0 (PMR0) Port Mode Reg.1 (PMR1) Port Mode Reg.2 (PMR2) Port Mode Reg.3 (PMR3) Port Mode Reg.4 (PMR4) Module Standby Reg.1 (MSR1) Module Standby Reg.2 (MSR2) Timer Mode Reg.A (TMA) Timer Mode Reg.B1 (TMB1) Timer Mode Reg.B2 (TMB2) (TRBL/TWBL) Timer-B (TRBU/TWBU) Timer Mode Reg.C1 (TMC1) Timer Mode Reg.C2 (TMC2) (TRCL/TWCL) Timer-C (TRCU/TWCU) Timer Mode Reg.D1 (TMD1) Timer Mode Reg.D2 (TMD2) (TRDL/TWDL) Timer-D (TRDU/TWDU) used
RAM-mapped register area
$03F $040 $04F $050
Memory register (MR) area digits) data area digits)
$06F $070 used $08F $090
Data (464 digits) (bank
Data (464 digits) (bank
Register flag area Serial Mode Reg.1 Serial Mode Reg.2 Serial Data Reg.Lower Serial Data Reg.Upper Mode reg. Data Reg.Lower Data Reg.Middle Data Reg.Upper Control Reg. Mode Reg. Buzzer Mode Reg. used Port D0~D3 Port D4~D7 Port D8~D11 used Port Port Port Port Port Port Port Port Port used Vreg. (SMR1) (SMR2) (SRL) (SRU) (AMR) (ADRL) (ADRM) (ADRU) (LCR) (LMR) (BMR) (DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) (DCR8)
$25F $260
Data (304 digits)
$38F $390 used $3BF $3C0
Stack area digits)
$3FF
Notes:
Read Write
$012 $013 $016 $017 $01A $01B
Timer Read Reg.B Lower Timer Read Reg.B Upper Timer Read Reg.C Lower Timer Read Reg.C Upper Timer Read Reg.D Lower Timer Read Reg.D Upper
(TRBL) (TRBU) (TRCL) (TRCU) (TRDL) (TRDU)
Timer Write Reg.B Lower Timer Write Reg.B Upper Timer Write Reg.C Lower Timer Write Reg.C Upper Timer Write Reg.D Lower Timer Write Reg.D Upper
(TWBL) (TWBU) (TWCL) (TWCU) (TWDL) (TWDU)
Read/Write *Two registers mapped onto same address ($012, $013, $016, $017, $01A, $01B).
Figure Memory (cont)
Series
HD404878 Series
$000 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F
Interrupt control area Speed Select Reg. (SSR) Miscellaneous Reg. (MIS) Edge Select Reg. (ESR) used Port Mode Reg.0 (PMR0) Port Mode Reg.1 (PMR1) Port Mode Reg.2 (PMR2) Port Mode Reg.3 (PMR3) Port Mode Reg.4 (PMR4) Module Standby Reg.1 (MSR1) Module Standby Reg.2 (MSR2) Timer Mode Reg.A (TMA) Timer Mode Reg.B1 (TMB1) Timer Mode Reg.B2 (TMB2) (TRBL/TWBL) Timer-B (TRBU/TWBU) Timer Mode Reg.C1 (TMC1) Timer Mode Reg.C2 (TMC2) (TRCL/TWCL) Timer-C (TRCU/TWCU) Timer Mode Reg.D1 (TMD1) Timer Mode Reg.D2 (TMD2) (TRDL/TWDL) Timer-D (TRDU/TWDU) used
RAM-mapped register area
$03F $040 $04F $050
Memory register (MR) area digits) data area
$06F $070
digits) used
$08F $090
Data (768 digits)
Register flag area Serial Mode Reg.1 Serial Mode Reg.2 Serial Data Reg.Lower Serial Data Reg.Upper used Control Reg. Mode Reg. Buzzer Mode Reg. used Port D0~D3 Port D4~D7 Port D8~D11 used Port Port Port Port Port Port Port Port Port used (LCR) (LMR) (BMR) (DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) (DCR8) (SMR1) (SMR2) (SRL) (SRU)
$38F $390 used $3BF $3C0
Stack area digits)
$3FF
Notes:
Read Write
$012 $013 $016 $017 $01A $01B
Timer Read Reg.B Lower Timer Read Reg.B Upper Timer Read Reg.C Lower Timer Read Reg.C Upper Timer Read Reg.D Lower Timer Read Reg.D Upper
(TRBL) (TRBU) (TRCL) (TRCU) (TRDL) (TRDU)
Timer Write Reg.B Lower Timer Write Reg.B Upper Timer Write Reg.C Lower Timer Write Reg.C Upper Timer Write Reg.D Lower Timer Write Reg.D Upper
(TWBL) (TWBU) (TWCL) (TWCU) (TWDL) (TWDU)
Read/Write *Two registers mapped onto same address ($012, $013, $016, $017, $01A, $01B).
Figure Memory (cont)
Series
HD404868 Series
$000 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F Interrupt control area Speed Select Reg. Miscellaneous Reg. Edge Select Reg. used Port Mode Reg.0 Port Mode Reg.1 Port Mode Reg.2 Port Mode Reg.3 Port Mode Reg.4 Module Standby Reg.1 Module Standby Reg.2 Timer Mode Reg.A Timer Mode Reg.B1 Timer Mode Reg.B2 Timer Timer Mode Reg.C1 Timer Mode Reg.C2 Timer (SSR) (MIS) (ESR) (PMR0) (PMR1) (PMR2) (PMR3) (PMR4) (MSR1) (MSR2) (TMA) (TMB1) (TMB2) (TRBL/TWBL) (TRBU/TWBU) (TMC1) (TMC2) (TRCL/TWCL) (TRCU/TWCU)
RAM-mapped register area
$03F $040 Memory register (MR) area digits) $04F $050 data area digits) $067 $068 used $08F $090
Data (304 digits)
used
Register flag area (SMR1) (SMR2) (SRL) (SRU) (AMR) (ADRL) (ADRM) (ADRU) (LCR) (LMR) (BMR)
$1BF $1C0
used
$3BF $3C0
Stack area digits)
Serial Mode Reg.1 Serial Mode Reg.2 Serial Mode Reg.Lower Serial Mode Reg.Upper Mode reg. Data Reg.Lower Data Reg.Middle Data Reg.Upper Control Reg. Mode Reg. Buzzer Mode Reg. used Port D0-D3 Port D4-D7 Port D8-D9 used Port Port Port Port Port Port Port Port
(DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7)
used
$3FF
Notes:
Read Write R/W: Read/Write *Two registers mapped onto same address ($012, $013, $016, $017).
$012 $013 $016 $017
Timer Read Reg.B Lower Timer Read Reg.B Upper Timer Read Reg.C Lower Timer Read Reg.C Upper
(TRBL) (TRBU) (TRCL) (TRCU)
Timer Write Reg.B Lower Timer Write Reg.B Upper Timer Write Reg.C Lower Timer Write Reg.C Upper
(TWBL) (TWBU) (TWCL) (TWCU)
Figure Memory (cont)
Series
RAM-mapped register area ($000 $03F): Interrupt control area ($000 $003) This area consists bits used interrupt control. configuration shown figure Individual bits only accessed manipulation instructions (SEM/SEMD, REM/REMD, TM/TMD). There restrictions access certain bits. individual bits instruction restrictions shown figure Special register area ($004 $01F, $024 $03F) This area comprises mode registers data registers external interrupts, serial interface, timers, LCD, converter, etc., data control registers. configuration shown figures These registers three kinds: write-only (W), read-only (R), read/write (R/W). SEM/SEMD REM/REMD instructions used control register (LCR: $02C) third buzzer mode register (BMR3: $02E, manipulation instructions cannot used other registers. Register flag area ($020 $023) This area consists DTON WDON flags interrupt control bits. configuration shown figure Individual bits only accessed manipulation instructions (SEM/SEMD, REM/REMD, TM/TMD). There restrictions access certain bits. individual bits instruction restrictions shown figure Memory register (MR) area ($040 $04F): this data area, memory register digits (MR(0) MR(15)) also accessed registerregister instructions LAMR XMRA. configuration this area shown figure data area: $050 $06F (HD404889/HD404899/HD404878 Series) $050 $067 (HD404868 Series) This 32-digit data area stores data displayed LCD. Data written this area automatically outputed segments display data. data indicates "on" data "off" (see section circuit details). Data area: $090 $38F (HD404889/HD404899/HD404878 Series) $090 $1BF (HD404868 Series) digits from $090 $25F, bank switched according value bank register $03F) (figure bank register value must always when accessing area from $090 $25F. data area from $260 $38F addressed without bank register setting. Stack area ($3C0 $3FF): This stack area used save contents program counter (PC), status flag (ST), carry flag (CA) when subroutine call (CAL CALL instruction) interrupt handling performed. four digits used level, area used subroutine stack with maximum levels. saved data saved status information shown figure program counter restored RTNI instructions. status carry flags restored RTNI instruction, affected instruction. part area used saving used data area.
Series
address $000 IMWU*1 (WU0 interrupt mask) (INT1 interrupt mask) IMTB (Timer interrupt mask) IMAD*3 (A/D converter interrupt mask) IFWU*2 (WU0 interrupt request flag) (INT1 interrupt request flag) IFTB (Timer interrupt request flag) IFAD*3 (A/D converter interrupt request flag) (Stack pointer reset) (INT0 interrupt mask) IMTA (Timer interrupt mask) IMTC (Timer interrupt mask) (Interrupt enable flag) (INT0 interrupt request flag) IFTA (Timer interrupt request flag) IFTC (Timer interrupt request flag)
$001
$002
$003
$020
DTON (DTON flag) (Gear enable flag) IMTD*4 (Timer interrupt mask) (Serial interrupt mask)
ADSF*3 (A/D start flag) used IFTD*4 (Timer interrupt request flag) (Serial interrupt request flag)
WDON (Watchdog flag) ICEF (Input capture error flag) used
LSON (Low speed flag) ICSF (Input capture status flag) used
$021
$022
$023
used
used
Interrupt Request Flag Interrupt Mask Interrupt Enable Flag Stack Pointer
Notes: interrupt mask HD404868 Series interrupt request flag HD404868 Series Applies HD404889, HD404899, HD404868 Series. Applies HD404889, HD404899, HD404878 Series.
Figure Interrupt Control Register Flag Area Configuration
Series
Bits interrupt control area register flag area reset SEMD instruction REMD instruction, tested instruction. They affected other instructions. following restrictions apply individual bits. SEM/SEMD LSON ICSF ICEF WDON ADSF* DTON Used Allowed executed Allowed Allowed executed active mode Used subactive mode executed Allowed Allowed executed Inhibited Allowed executed Inhibited Inhibited Inhibited Allowed Allowed Inhibited executed Allowed Allowed Allowed Allowed Allowed REM/REMD TM/TMD
Notes WDON reset only stop mode clearance means reset. REMD instruction ADSF during conversion. DTON always reset state active mode. instruction used which prohibited, nonexistent bit, status flag value will undetermined. Applies HD404889, HD404899, HD404868 Series.
Figure Instruction Restrictions
Series
HD404889 Series
address
PMR0 PMR1 PMR2 PMR3 PMR4 MSR1 MSR2 TMB1 TMB2 TRBL/TWBL TRBU/TWBU TMC1 TMC2 TRCL/TWCL TRCU/TWCU TMD1 TMD2 TRDL/TWDL TRDU/TWDU
SMR1 SMR2 ADRL ADRU DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7 DCR8
$000 Interrupt control area $003 System clock frequency $004 oscillation stop setting frequency division System clock selection division ratio switching ratio selection Interrupt frame period selection used $005 Pull-up control used INT1 edge detection selection $006 used $007 used $008 D1/INT1 D0/INT0 $009 R03/WU3 R02/WU2 R01/WU1 R00/WU0 $00A R13/TOB R12/BUZZ R11/EVND R10/EVNB $00B R20/TOC R22/SI/SO R21/SCK R5/SEG9~12 R4/SEG5~8 R3/SEG1~4 $00C R6/SEG13~16 used Timer lock on/off Timer clock on/off Timer clock on/off $00D Serial clock on/off clock on/off used $00E $00F TimerA/Timer base Timer clock source selection Reload on/off Timer clock source selection $010 Timer output mode setting EVNB edge detection selection used $011 Timer register (lower) $012 Timer register (upper) $013 $014 Timer clock source selection Reload on/off Timer output mode selection used used $015 Timer register (lower) $016 Timer register (upper) $017 $018 Timer clock source selection Reload on/off used Input capture selection EVND edge detection selection $019 Timer register (lower) $01A $01B Timer register (upper) $01C used $01F $020 Register flag area $023 $024 Serial transfer clock speed selection used used R22/SI/SO PMOS control idle setting $025 Serial data register (lower) $026 $027 Serial data register (upper) Analog channel selection conversion time $028 used $029 data register (lower) $02A $02B data register (upper) Realtime clock mode Power supply dividing On-chip power supply switch Display on/off $02C display selection resistor switch Input clock selection Duty selection $02D Clock output on/off Buzzer/clock selection Buzzer/clock source selection $02E used $02F PortD3DCR PortD2DCR PortD1DCR PortD0DCR $030 PortD6DCR PorD5DCR PortD4DCR PortD7DCR $031 $032 PortD10DCR PortD9DCR PortD8DCR PortD11DCR used $033 $034 PortR02DCR PortR01DCR PortR00DCR PortR03DCR $035 PortR12DCR PortR11DCR PortR10DCR PortR13DCR $036 PortR23DCR PortR22DCR PortR21DCR PortR20DCR $037 PortR32DCR PortR31DCR PortR30DCR PortR33DCR $038 PortR42DCR PortR41DCR PortR40DCR PortR43DCR $039 PortR53DCR PortR52DCR PortR51DCR PortR50DCR $03A PortR63DCR PortR62DCR PortR61DCR PortR60DCR PortR73DCR PortR72DCR PortR71DCR PortR70DCR $03B used $03C PortR81DCR PortR80DCR $03D used $03E used $03F Bank setting used
Figure Special Function Register Area
Series
HD404899 Series
address
PMR0 PMR1 PMR2 PMR3 PMR4 MSR1 MSR2 TMB1 TMB2 TRBL/TWBL TRBU/TWBU TMC1 TMC2 TRCL/TWCL TRCU/TWCU TMD1 TMD2 TRDL/TWDL TRDU/TWDU
SMR1 SMR2 ADRL ADRM ADRU DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7 DCR8
$000 Interrupt control area $003 System clock frequency $004 oscillation stop setting frequency division System clock selection division ratio switching ratio selection Interrupt frame period selection used $005 Pull-up control used INT1 edge detection selection $006 used $007 used $008 D1/INT1 D0/INT0 $009 R03/WU3 R02/WU2 R01/WU1 R00/WU0 $00A R13/TOB R12/BUZZ R11/EVND R10/EVNB $00B R20/TOC R22/SI/SO R21/SCK R5/SEG9~12 R4/SEG5~8 R3/SEG1~4 $00C R6/SEG13~16 used Timer lock on/off Timer clock on/off Timer clock on/off $00D Serial clock on/off clock on/off used $00E $00F TimerA/Timer base Timer clock source selection Reload on/off Timer clock source selection $010 Timer output mode setting EVNB edge detection selection used $011 Timer register (lower) $012 Timer register (upper) $013 $014 Timer clock source selection Reload on/off Timer output mode selection used used $015 Timer register (lower) $016 Timer register (upper) $017 $018 Timer clock source selection Reload on/off used Input capture selection EVND edge detection selection $019 Timer register (lower) $01A $01B Timer register (upper) $01C used $01F $020 Register flag area $023 $024 Serial transfer clock speed selection used used R22/SI/SO PMOS control idle setting $025 Serial data register (lower) $026 $027 Serial data register (upper) Analog channel selection conversion time $028 data register (lower) used $029 data register (middle) $02A $02B data register (upper) Realtime clock mode Power supply dividing On-chip power supply switch Display on/off $02C display selection resistor switch Input clock selection Duty selection $02D Clock output on/off Buzzer/clock selection Buzzer/clock source selection $02E used $02F PortD3DCR PortD2DCR PortD1DCR PortD0DCR $030 PortD6DCR PorD5DCR PortD4DCR PortD7DCR $031 $032 PortD10DCR PortD9DCR PortD8DCR PortD11DCR used $033 $034 PortR02DCR PortR01DCR PortR00DCR PortR03DCR $035 PortR12DCR PortR11DCR PortR10DCR PortR13DCR $036 PortR23DCR PortR22DCR PortR21DCR PortR20DCR $037 PortR32DCR PortR31DCR PortR30DCR PortR33DCR $038 PortR42DCR PortR41DCR PortR40DCR PortR43DCR $039 PortR53DCR PortR52DCR PortR51DCR PortR50DCR $03A PortR63DCR PortR62DCR PortR61DCR PortR60DCR PortR73DCR PortR72DCR PortR71DCR PortR70DCR $03B used $03C PortR81DCR PortR80DCR $03D used $03E used $03F Bank setting used
Figure Special Function Register Area (cont)
Series
HD404878 Series
address
PMR0 PMR1 PMR2 PMR3 PMR4 MSR1 MSR2 TMB1 TMB2 TRBL/TWBL TRBU/TWBU TMC1 TMC2 TRCL/TWCL TRCU/TWCU TMD1 TMD2 TRDL/TWDL TRDU/TWDU
SMR1 SMR2
DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7 DCR8
$000 Interrupt control area $003 System clock frequency $004 oscillation stop setting frequency division System clock selection division ratio switching ratio selection Interrupt frame period selection used $005 Pull-up control used INT1 edge detection selection $006 used $007 used $008 D1/INT1 D0/INT0 $009 R03/WU3 R02/WU2 R01/WU1 R00/WU0 $00A R13/TOB R12/BUZZ R11/EVND R10/EVNB $00B R20/TOC R22/SI/SO R21/SCK R5/SEG9~12 R4/SEG5~8 R3/SEG1~4 $00C R6/SEG13~16 used Timer lock on/off Timer clock on/off Timer clock on/off $00D Serial clock on/off used $00E $00F TimerA/Timer base Timer clock source selection Reload on/off Timer clock source selection $010 Timer output mode setting EVNB edge detection selection used $011 Timer register (lower) $012 Timer register (upper) $013 $014 Timer clock source selection Reload on/off Timer output mode selection used used $015 Timer register (lower) $016 Timer register (upper) $017 $018 Timer clock source selection Reload on/off used Input capture selection EVND edge detection selection $019 Timer register (lower) $01A $01B Timer register (upper) $01C used $01F $020 Register flag area $023 $024 Serial transfer clock speed selection used used R22/SI/SO PMOS control idle setting $025 Serial data register (lower) $026 $027 Serial data register (upper) $028 $029 used $02A $02B Realtime clock mode Power supply dividing On-chip power supply switch Display on/off $02C display selection resistor switch Input clock selection Duty selection $02D Clock output on/off Buzzer/clock selection Buzzer/clock source selection $02E used $02F PortD3DCR PortD2DCR PortD1DCR PortD0DCR $030 PortD6DCR PorD5DCR PortD4DCR PortD7DCR $031 $032 PortD10DCR PortD9DCR PortD8DCR PortD11DCR used $033 $034 PortR02DCR PortR01DCR PortR00DCR PortR03DCR $035 PortR12DCR PortR11DCR PortR10DCR PortR13DCR $036 PortR23DCR PortR22DCR PortR21DCR PortR20DCR $037 PortR32DCR PortR31DCR PortR30DCR PortR33DCR $038 PortR42DCR PortR41DCR PortR40DCR PortR43DCR $039 PortR53DCR PortR52DCR PortR51DCR PortR50DCR $03A PortR63DCR PortR62DCR PortR61DCR PortR60DCR PortR73DCR PortR72DCR PortR71DCR PortR70DCR $03B used $03C PortR81DCR PortR80DCR $03D used $03E used $03F used
Figure Special Function Register Area (cont)
Series
HD404868 Series
address
PMR0 PMR1 PMR2 PMR3 PMR4 MSR1 MSR2 TMB1 TMB2 TRBL/TWBL TRBU/TWBU TMC1 TMC2 TRCL/TWCL TRCU/TWCU
SMR1 SMR2 ADRL ADRM ADRU DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7
$000 Interrupt control area $003 System clock frequency $004 oscillation stop setting frequency division System clock selection division ratio switching ratio selection Interrupt frame period selection used $005 Pull-up control used INT1 edge detection selection $006 used $007 used $008 D1/INT1 D0/INT0 $009 used R02/WU2 R01/WU1 R00/WU0 $00A R13/TOB R12/BUZZ used R10/EVNB $00B R20/TOC R22/SI/SO R21/SCK R5/SEG9~12 R4/SEG5~8 R3/SEG1~4 $00C R6/SEG13~16 used Timer lock on/off Timer clock on/off $00D Serial clock on/off clock on/off used $00E $00F TimerA/Timer base Timer clock source selection Reload on/off Timer clock source selection $010 EVNB edge detection selection Timer output mode selection used $011 Timer register (lower) $012 Timer register (upper) $013 $014 Timer clock source selection Reload on/off Timer output mode selection used used $015 Timer register (lower) $016 Timer register (upper) $017 $018 used used $019 used $01A $01B used $01C used $01F $020 Register flag area $023 $024 Serial transfer clock speed selection used used R22/SI/SO PMOS control idle setting $025 Serial data register (lower) $026 $027 Serial data register (upper) Analog channel selection conversion time $028 data register (lower) used $029 data register (middle) $02A $02B data register (upper) Realtime clock mode Power supply dividing On-chip power supply switch Display on/off $02C display selection resistor switch Input clock selection Duty selection $02D Clock output on/off Buzzer/clock selection Buzzer/clock source selection $02E used $02F PortD3DCR PortD2DCR PortD1DCR PortD0DCR $030 PortD6DCR PorD5DCR PortD4DCR PortD7DCR $031 $032 PortD8DCR used PortD9DCR used $033 $034 PortR01DCR PortR00DCR used PortR02DCR $035 PortR12DCR PortR11DCR PortR10DCR PortR13DCR $036 PortR23DCR PortR22DCR PortR21DCR PortR20DCR $037 PortR32DCR PortR31DCR PortR30DCR PortR33DCR $038 PortR42DCR PortR41DCR PortR40DCR PortR43DCR $039 PortR53DCR PortR52DCR PortR51DCR PortR50DCR $03A PortR63DCR PortR62DCR PortR61DCR PortR60DCR PortR73DCR PortR72DCR PortR71DCR PortR70DCR $03B used $03C $03D used $03E used $03F used
Figure Special Function Register Area (cont)
Series
$040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04A $04B $04C $04D $04E $04F (10) (11) (12) (13) (14) (15) Level Level Level Level Level Level Level Level Level Level Level Level Level Level Level 1,023 Level $3C0 $3FF
1020 1021 1022 1023 PC10
PC13
PC12
PC11 $3FC $3FD $3FE $3FF
Memory registers
Stack area PC13 Program counter Status flag Carry flag
Figure Configuration Memory Registers Stack Area, Stack Position
Bank register $03F) Read/Write Initial value reset name
Used Used Used
Bank area selection Bank selected Bank selected
Note: After reset, value bank register therefore bank selected. Applies HD404889 HD404899 Series.
Figure Bank Register
Series
Functional Description
Registers Flags nine registers flags operations. they shown figure described below.
Accumulator Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, (SPY) (SPX)
Carry flag
Initial value: Undefined,
(CA) (ST) (PC)
Status flag Program counter Initial value: $0000, Stack pointer Initial value: $3FF,
Initial value:
(SP)
Figure Registers Flags Accumulator register (B): accumulator register 4-bit registers used hold result operation, data transfer from memory, area, another register.
Series
register (W), register register (Y): register 2-bit register, registers 4-bit registers, used register indirect addressing. register also used port addressing. register (SPX) register (SPY): registers 4-bit registers used register register auxiliary registers, respectively. Carry flag (CA): This flag holds overflow when arithmetic/logic instruction executed. also affected SEC, REC, ROTL, ROTR instructions. contents carry flag saved stack when interrupt handling performed, restored from stack RTNI instruction (but affected instruction). Status flag (ST): This flag holds overflow when arithmetic/logic compare instruction executed, result non-zero test instruction. used branch condition BRL, CAL, CALL instructions. status flag latch-type flag, does change until next arithmetic/logic, compare, test instruction executed. After BRL, CAL, CALL instruction, status flag regardless whether instruction executed skipped. contents status flag saved stack when interrupt handling performed, restored from stack RTNI instruction (but affected instruction). Program counter (PC): This 14-bit binary counter that holds address information. Stack pointer (SP): stack pointer 10-bit register that holds address next save space stack area. stack pointer initialized $3FF reset. stack pointer decremented each time data saved, incremented each time data restored. upper bits stack pointer fixed 1111, that maximum stack levels used. There ways which stack pointer initialized $3FF: reset mentioned above, resetting with REMD instruction. Reset reset performed driving RESET low. power-on, when subactive mode, watch mode, stop mode cleared, RESET should input least provide oscillation settling time oscillator.In other cases, reset inputting RESET least instruction cycles. Table shows areas initialized reset, their initial values.
Series
Table Initial Values after Reset
Item Program counter Status flag Stack pointer Interrupt Interrupt enable flag Abbr. (PC) (ST) (SP) (IE) (IF) (IM) (PDR) Initial value $0000 $3FF Contents Program executed from start address Branching conditional branch instruction enabled Stack level interrupts disabled interrupt requests Interrupt requests masked
flags/ mask Interrupt request flag Interrupt mask Port data register Data control registers Data control registers
bits level output possible
(DCD0 bits Output buffer (high impedance) (DCR0 bits DCR80, DCR81) (PMR0) (PMR1) (PMR2) (PMR3) (PMR4) (ESR) (TMA) (TMB1) (TMB2) (TMC1) (TMC2) (TMD1) (TMD2) (PSS) (PSW) (TCA) (TCB) (TCC) (TCD) (TWBU,L) (TWCU,L) (TWDU,L) 0000 0000 0000 0000 0000 0000 -000 0000 -0-0000 -000 $000 port mode register section port mode register section port mode register section port mode register section port mode register section edge detection select register section timer mode register section timer mode register section timer mode register section timer mode register section timer mode register section timer mode register section timer mode register section
Port mode register Port mode register Port mode register Port mode register Port mode register Edge detection select register Timers Timer mode register Timer mode register Timer mode register Timer mode register Timer mode register Timer mode register Timer mode register Prescaler Prescaler Timer/counter Timer/counter Timer/counter Timer/counter Timer write register Timer write register Timer write register
Series
Table (cont) Initial Values after Reset
Item Serial interface Serial mode register Serial mode register Serial data register Octal counter converter mode register data register (HD404889 Series) data register (HD404899 Series) control register mode register registers speed flag Watchdog timer flag start flag Direct transfer flag Input capture status flag Input capture error flag Gear enable flag Others Miscellaneous register System clock select register (AMR) (ADRU,L) Abbr. (SMR1) (SMR2) (SRU,L) Initial value 0000 -0X$XX 0000 mode register section data register section data register section control register section duty/clock control register section low-power mode section timer section converter section low-power mode section timer section timer section system clock gear function low-power mode input/output sections low-power mode oscillator circuit sections timer section serial interface converter sections Buzzer mode register section Contents serial mode register section serial mode register section
(ADRU,M,L) $1FF (LCR) (LMR) (LSON) (WDON) (ADSF) (DTON) (ICSF) (ICEF) (GEF) (MIS) (SSR) 0000 0000 0-00 0000 -000 0000
Module standby register (MSR1) Module standby register (MSR2) Buzzer mode register (BMR)
Notes: state registers flags other than those listed above after reset shown table (2). Indicates invalid value, indicates that does exist.
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Table Initial Values after Reset
Item Carry flag Accumulator register register Abbr. (CA) After Stop Mode Clearance Input Retain value immediately prior entering stop mode After Other Reset Value immediately prior reset guaranteed. Must initialized program.
X/SPX register (X/SPX) Y/SPY register (Y/SPY)
Interrupts There total nine interrupt sources, comprising wakeup input external interrupts (INT0, timer/counter (timer timer timer timer interrupts, serial interface interrupt, converter interrupt. Each interrupt source provided with interrupt request flag, interrupt mask, vector address, used storing controlling interrupt requests. addition, interrupt enable flag provided control interrupts whole. interrupt sources, timers share same vector address, converter serial interface also share same vector address. Software must therefore determine which interrupt sources requesting interrupt start interrupt handling. Interrupt control bits interrupt handling: interrupt control bits mapped onto addresses $000 $003 $022 $023, accessed manipulation instructions. However, interrupt request flags (IF) cannot software. When reset, interrupt enable flag (IE) interrupt request flags (IF) initialized interrupt masks (IM) initialized Figure shows block diagram interrupt control circuit, table shows interrupt priorities vector addresses, table lists conditions executing interrupt handling each nine kinds interrupt source. When interrupt request flag interrupt mask cleared interrupt requested. interrupt enable flag this time, interrupt handling started. vector address corresponding interrupt source generated priority control circuit. interrupt handling sequence shown figure interrupt handling flowchart figure When interrupt accepted, execution previous instruction completed first cycle. second cycle, interrupt enable flag (IE) reset. second third cycles, contents carry flag, status flag, program counter saved stack. third cycle, jump made vector address instruction execution resumed from that address.
Series
each vector address area, JMPL instruction should written that branches start address interrupt routine. interrupt routine, interrupt request flag that caused interrupt handling must reset software. Table Vector Addresses Interrupt Priorities
Priority Vector Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E
Interrupt Source RESET INT0 INT1 Timer Timer Timer Serial interface, converter
Series
$000,0
Interrupt request
$000,2
(WU0 interrupt) IFWU
$000,3
IMWU Priority control circuit Vector address
$001,0
(INT0 interrupt)
$001,1
$001,2
(INT1 interrupt)
$001,3
$002,0
(Timer interrupt) IFTA
$002,1
IMTA
$002,2
(Timer interrupt) IFTB
$022,2
IFTD (Timer interrupt)
$002,3
IMTB
$022,3
IMTD
$003,0
(Timer interrupt) IFTC
$003,1
IMTC
$003,2
(A/D interrupt) IFAD
$023,2
(Serial interrupt)
$003,3
IMAD
$023,3
Figure Block Diagram Interrupt Control Circuit
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Table Interrupt Processing Activation Conditions
Interrupt Source Interrupt Control INT0 INT1 Timer Timer Timer Timer Serial
Note: Operation affected whether value
Instruction cycle
Instruction execution*
Interrupt acceptance
Save stack reset
Save stack Vector address generated
Execution JMPL instruction vector address
Execution instruction start address interrupt routine
Note: stack accessed reset after instruction executed, even 2cycle instruction.
Figure Interrupt Sequence
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Power
RESET="0"?
Interrupt request?
IE="1"? Accept interrupt
Execute instruction Reset
PC(PC)+1
IE"0" Stack(PC) Stack(CA) Stack(ST)
PC$0002
WU0~WU3 interrupt?
PC$0004
INT0 interrupt?
PC$0006
INT1 interrupt?
PC$0008
Timer interrupt?
PC$000A Timer timer interrupt? PC$000C Timer interrupt?
PC$000E (A/D, serial interrupt)
Figure Interrupt Handling Flowchart
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Interrupt enable flag (IE: $000,0): interrupt enable flag controls interrupt enabling/disabling interrupt requests shown table interrupt enable flag reset interrupt handling RTNI instruction. Table Interrupt Enable Flag (IE: $000,0)
Interrupt Enabling/Disabling Interrupts disabled Interrupts enabled
Interrupt Enable Flag(IE)
Wakeup interrupt request flag (IFWU: $000,2): wakeup interrupt request flag (IFWU) detection falling edge input active mode, subactive mode,watch mode, standby mode. stop mode, when falling edge detected wakeup pin, waits oscillation settling time, then switches active mode. wakeup interrupt request flag (IFWU) this case. Wakeup interrupt mask (IMWU: $000,3): This masks interrupt request wakeup interrupt request flag.
Edge detection select register (ESR: $006) Read/Write Initial value reset name ESR1 ESR0
ESR1
ESR0
INT1edge detect detected Falling edge detection Rising edge detection Both rising falling edge detection
Figure Edge Detection Select Register (ESR)
Series
External interrupt request flags (IF0, IF1: $001): falling edge INT0 input, rising edge, falling edge, both edges INT1 input (table Interrupt edge selection performed means edge detection select register (ESR: $006) (figure 12). Table External Interrupt Request Flags (IF0, IF1: $001)
Interrupt Request external interrupt request External interrupt request generated
External Interrupt Request Flags (IF0, IF1)
External interrupt masks (IM0, IM1: $001): These bits mask interrupt requests external interrupt request flags (table Table External Interrupt Mask (IM: $001)
Interrupt Request External interrupt request enabled External interrupt request masked (held pending)
External Interrupt Masks (IM0, IM1)
Timer interrupt request flag (IFTA: $002,0): timer interrupt request flag timer overflow output (table Table Timer Interrupt Request Flag (IFTA: $002,0)
Interrupt Request timer interrupt request Timer interrupt request generated
Timer Interrupt Request Flag(IFTA)
Timer interrupt mask (IMTA: $002,1): This masks interrupt request timer interrupt request flag (table Table Timer Interrupt Mask (IMTA: $002,1)
Interrupt Request Timer interrupt request enabled Timer interrupt request masked (held pending)
Timer Interrupt Mask (IMTA)
Series
Timer interrupt request flag (IFTB: $002,2): timer interrupt request flag timer overflow output (table Table Timer Interrupt Request Flag (IFTB: $002,2)
Interrupt Request timer interrupt request Timer interrupt request generated
Timer Interrupt Request Flag (IFTB)
Timer interrupt mask (IMTB: $002,3): This masks interrupt request timer interrupt request flag (table 10). Table Timer Interrupt Mask (IMTB: $002,3)
Interrupt Request Timer interrupt request enabled Timer interrupt request masked (held pending)
Timer Interrupt Mask (IMTB)
Timer interrupt request flag (IFTC: $003,0): timer interrupt request flag timer overflow output (table 11). Table Timer Interrupt Request Flag (IFTC: $003,0)
Interrupt Request timer interrupt request Timer interrupt request generated (held pending)
Timer Interrupt Request Flag (IFTC)
Timer interrupt mask (IMTC: $003,1): This masks interrupt request timer interrupt request flag (table 12). Table Timer Interrupt Mask (IMTC: $003,1)
Interrupt Request Timer interrupt request enabled Timer interrupt request masked (held pending)
Timer Interrupt Mask (IMTC)
Series
Timer interrupt request flag (IFTD: $022,2): (Applies HD404889, HD404899, HD404878 Series) timer interrupt request flag timer overflow output, EVND input edge when used input capture timer (table 13). Table Timer Interrupt Request Flag (IFTD: $022,2)
Interrupt Request timer interrupt request Timer interrupt request generated
Timer Interrupt Request Flag (IFTD)
Timer interrupt mask (IMTD: $022,3): (Applies HD404889, HD404899, HD404878 Series) This masks interrupt request timer interrupt request flag (table 14). Table Timer Interrupt Mask (IMTD: $022,3)
Interrupt Request Timer interrupt request enabled Timer interrupt request masked (held pending)
Timer Interrupt Mask (IMTD)
Serial interrupt request flag (IFS: $023,2): serial interrupt request flag completion serial data transfer, data transfer halted midway (table 15). Table Serial Interrupt Request Flag (IFS: $023,2)
Serial Interrupt Request Flag (IFS) Interrupt Request serial interrupt request Serial interrupt request generated
Serial interrupt mask (IMS: $023,3): This masks interrupt request serial interrupt request flag (table 16). Table Serial Interrupt Mask (IMS: $023,3)
Interrupt Request Serial interrupt request enabled Serial interrupt request masked (held pending)
Serial Interrupt Mask (IMS)
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interrupt request flag (IFAD: $003,2): (Applies HD404889, HD404899, HD404868 Series) interrupt request flag completion conversion (table 17). Table Interrupt Request Flag (IFAD: $003,2)
Interrupt Request Flag (IFAD) Interrupt Request interrupt request interrupt request generated
interrupt mask (IMAD: $003,3): (Applies HD404889, HD404899, HD404868 Series) This masks interrupt request interrupt request flag (table 18). Table Interrupt Mask (IMAD: $003,3)
Interrupt Request interrupt request enabled interrupt request masked (held pending)
Serial Interrupt Mask (IMAD)
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Operating Modes
five operating modes shown table used MCU. function each mode shown table state transition diagram among each mode figure Table Operating Modes Clock Status
Mode Name Active Activation method Standby Stop STOP instruction when TMA3 Watch STOP instruction when TMA3 Subactive*2 INT0/timer interrupt request watch mode
RESET cancellation, instruction interrupt request, input stop mode STOP/SBY instruction subactive mode (when direct transfer selected) RESET input, STOP/SBY instruction RESET input, interrupt request
Status
System oscillator Subsystem oscillator
Stopped
Stopped RESET input, INT0/timer interrupt request
Stopped RESET input, STOP/SBY instruction
Cancellation method
RESET input, input
Notes: implies operation. Operating stopping oscillator selected setting system clock select register (SSR: $004) Subactive mode optional function; specify fnction option list.
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Table
Function Timer Timer Timer Timer
Operation Low-Power Dissipation Modes
Stop Mode Retained Retained Stopped Stopped Stopped Stopped Stopped Stopped Stopped Retained
Watch mode Retained Retained Stopped Stopped Stopped Stopped Stopped
Standby Mode Retained Retained Retained
Subactive Mode*3 Stopped
Serial interface
Retained
Notes: implies operation. Transmission/Reception activated clock input external clock mode. However, interrupts stop. When clock source used. Subactive mode optional function specified function option list. Applies HD404889, HD404899, HD404878 Series. Applies HD404889, HD404899, HD404868 Series.
Series
Reset RESET input watchdog timer Stop mode (TMA3=0,SSR3=0,LSON=0) fosc Stop Active Stop Stop Stop
Reset Active mode instruction
Standby mode fosc Active Active Stop fcyc fcyc
interrupt
fosc
Active Active fcyc fcyc fcyc (TMA3=0)
STOP (TMA3=0,SSR3=1,LSON=0) instruction fosc Stop Stop Stop Stop STOP Stop instruction
fosc
Active Active Stop fcyc
instruction
(TMA3=1) fosc Active Active fcyc fcyc
Subactive mode fosc Stop Active fSUB fSUB
interrupt
STOP instruction Timer WU0~WU3 INT0 interrupt Watch mode fosc Stop Active Stop Stop fosc Stop Active Stop Stop STOP instruction Timer INT0 interrupt
fosc Main oscillator frequency Sub-oscillator frequency (for realtime clock) fcyc fOSC/32 fOSC/4 (selected software) fx/8 fSUB fx/8 fx/4 (selected software) System clock Clock realtime clock Peripheral function clock LSON speed flag DTON Direct transfer flag TMA3 Timer mode register bit3
(TMA3=1,LSON=0)
(TMA3=1,LSON=1)
Transition Condition STOP/SBY instruction STOP/SBY instruction STOP/SBY instruction STOP/SBY instruction
DTON Don't care
LSON
TMA3
Figure Status Transitions
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Active mode: active mode functions operate. this mode, operates clocks generated OSC1 OSC2 oscillator circuits. Standby mode: standby mode oscillators continue operate clocks relating instruction execution halt. result, operation stops, registers, RAM, port/R port output retain their state immediately prior entering standby mode. Interrupts, timers, serial interface, other peripheral functions continue operate. Power consumption lower than active mode halting CPU. switched standby mode executing instruction active mode. Standby mode cleared RESET input interrupt request. When standby mode cleared RESET input, reset performed. When standby mode cleared interrupt request, enters active mode executes instruction following instruction. After executing instruction, interrupt enable flag interrupt handling executed; interrupt enable flag cleared interrupt request held pending normal instruction execution continued. operation flowchart shown figure
Series
Stop mode Standby mode Watch mode
RESET=0? RESET=0?
Yes* IFTA IMTA System clock oscillator started
IFTB IMTB+
Yes* System reset IMTC Yes* Yes*
System clock oscillator started
Next Instruction execution
System clock oscillator started
Note: Only when clearing from standby mode
Next Instruction execution
Interrupts enabled
Figure Operation Flowchart
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Stop mode: stop mode, function stop except that states prior entry into stop mode retained. This mode thus lowest power consumption operating mode. stop mode, OSC1 OSC2 oscillators stop. (SSR3) system clock select register (SSR: $004) (figure used select active stopped state oscillators. switched stop mode executing STOP instruction while (TMA3) timer mode register (TMA: $00F) cleared active mode. Stop mode cleared RESET input. When stop mode cleared RESET, RESET signal should input least oscillation settling time (tRC) (see Characteristics") shown figure Then, initialized starts instruction execution from start (address program. When detects falling edge stop mode, automatically waits oscillation settling time, then switches active mode. After transition active mode, resumes program execution from instruction following STOP instruction. stop mode cleared wakeup input, data registers retain their values prior entering stop mode.
Stop mode Oscillator
Internal clock
RESET
tres STOP instruction executed least oscillation settling time (tRC))
Figure Timing Chart Clearing Stop Mode RESET Input Note: stop mode cleared wakeup input when external clock used system clock (OSC1), subclock should stopped stop mode. Watch mode: watch mode, realtime clock function (timer function using oscillators operate, other functions stop. This mode thus second lowest power consumption after stop mode, useful performing realtime clock display only. watch mode, OSC2 oscillators stop oscillators continue operate. switched watch mode executing STOP instruction while TMA3 active mode, executing STOP/SBY instruction subactive mode.
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Watch mode cleared RESET input INT0,timer interrupt request. RESET input, refer section stop mode. When watch mode cleared INT0,timer interrupt request, mode transition depends value LSON bit: enters active mode LSON enters subactive mode LSON case transition active mode, interrupt request generation delayed secure oscillation settling time: delay time timer interrupt, and, INT0 interrupt interrupt, tRC) (MIS1, MIS0) miscellaneous register (tRC tRC) MIS1 MIS0 (figures 17). Other operations when transition made same when watch mode cleared (figure 14). Subactive mode: subactive mode, OSC1 OSC2 oscillator circuits stop operates clocks generated oscillator circuits. this mode, functions other than converter operate, since operating clocks slow, power consumption lowest after watch mode. instruction processing speed selected according whether (SSR2) system clock select register (SSR: $004) cleared value SSR2 should changed only active mode. value changed subactive mode, operate incorrectly. Subactive mode cleared executing STOP/SBY instruction. transition then made either watch mode active mode according value speed flag (LSON: $020,0) direct transfer flag (DTON: $020,3). Subactive mode function option, should specified function option list. Interrupt frame: watch mode subactive mode, supplied timer WU3, INT0 acceptance circuits. Prescaler timer operate time bases, generate interrupt frame timing. Either values selected interrupt frame period, means miscellaneous register (MIS: $005) (figure 17). watch mode subactive mode, timing generation timer A,INT0 interrupts synchronized with interrupt frame. Except case active mode transition, interrupt strobe timing used interrupt request generation. Timer generates overflow interrupt requests interrupt strobe timing.
Series
Oscillation stabilization period Active mode Watch mode Active mode
Interrupt strobe INT0 Interrupt request generation Only case transition active mode Interrupt frame period Oscillation stabilization period
Note: time from fall INT0 signal until interrupt accepted active mode entered designated then will following range T+tRCTX2T+tRC (MIS1, MIS0=00) tRCTXT+tRC (MIS1, MIS0=01
Figure Interrupt Frame
Miscellaneous Register (MIS: $005) Read/Write Reset name MIS3 MIS1 MIS0
Buffer control section Input/Output, Figure
MIS1 Notes:
MIS0
Interrupt Frame Oscillation Settling Oscillator Circuit period T(ms)*1 Time tRC(ms)*1 Condition 0.24414 3.90625 3.90625 0.12207(0.24414)*2 External clock input 7.8125 Ceramic resonator 31.25 Crystal resonator used
values 32.768 crystal oscillator X1-X2 pins. This value applies only case direct transition operation.
Figure Miscellaneous Register (MIS)
Series
Direct transition from subactive active mode: direct transition made from subactive mode active mode controlling direct transfer flag (DTON: $020,3) speed flag (LSON: $020,0). procedure shown below. LSON DTON subactive mode. Execute STOP instruction. After lapse internal processing time oscillation settling time, automatically switches from subactive mode active mode (figure 18). Notes: DTON flag ($020,3) only subactive mode. always reset state active mode. condition transition time from subactive mode active mode follows: tRC.
STOP/SBY instruction execution Subactive mode (Set LSON DTON internal processing time Oscillation stabilization time Active mode
Interrupt strobe
Direct transition completion timing Interrupt frame period tRC: Oscillation settling time Direct transition time
Figure Direct Transition Timing operation sequence: operates accordance with flowchart shown figure RESET input asynchronous input, immediately enters reset state upon RESET input, regardless current state. low-power mode operation sequence, STOP/SBY instruction executed while flag cleared interrupt flag set, releasing relevant interrupt mask, STOP/SBY instruction canceled (regarded NOP) next instruction executed. Therefore, when executing STOP/SBY instruction, interrupt flags must cleared, interrupts masked, beforehand.
Series
STOP/SBY instruction
IF=1 IM=0
Standby/watch mode
Stop Mode
IE=0
Interrupt handling routine
IF=1 IM=0
WU0~WU3
Clearing Standby watch mode Hardware Execution Hardware Execution
Clearing Stop mode
(PC)+1 (PC)+1 (PC)+2
Instruction Execution
Instruction Execution
Operation Cycle
Note: figure Operation Flowchart, operation.
Figure Operating Sequence (Low-Power Mode Operation)
Series
Usage notes: watch mode subactive mode, interrupt will detected correctly INT0 high low-level period shorter than interrupt frame period. MCU's edge sensing method shown figure samples INT0 signals regular intervals, consecutive sampled values change from high low, determines that falling edge been generated. Interrupt detection errors occur since this sampling performed interrupt frame period. highlevel period INT0 signal within interrupt frame, shown figure (a), signal will point point with result that falling edge will recognized. Similarly, low-level period INT0 signal within interrupt frame, shown figure (b), signal will high point point with result that falling edge will recognized. watch mode subactive mode, therefore, ensure that high-level low-level periods INT0 signals least long interrupt frame period.
INT0 Sampling High
Figure Edge Sensing Method
High-level mode Low-level mode
INT0
INT0
Interrupt frame
Point
Point
Interrupt frame
Point High
Point High
Figure Sampling Examples
Series
Internal Oscillator Circuit
Figure shows clock pulse generator circuit. shown table ceramic oscillator crystal oscillator connected OSC1 OSC2, 32.768 crystal oscillator connected External clock operation possible system oscillator. (SSR1) system clock select register (SSR: $004) according frequency oscillator connected OSC1 OSC2 (figure 24). Note: setting system clock select register does match frequency system oscillator, subsystem using 32.768 oscillation will operate correctly.
LSON OSC2 System oscillator fOSC 1/32 fcyc Timing tcyc generation division circuit circuit* System clock selection circuit
Registers, flags
OSC1
system clock oscillator Time base clock selection circuit fSUB Timing division tsubcyc generator circuit circuit*
Peripheral functions Interrupts
TMA3
division circuit
twcyc
Timing generation circuit
Timer interrupts
Notes: division ratio selected setting system clock select register (SSR:$004).
Figure Clock Pulse Generator Circuit
Series
System Clock Gear Function
built-in system clock gear function that allows system clock divided selected software instruction execution time. Efficient power consumption achieved operating divided-by-4 rate when high-speed processing needed, divided-by-32 rate other times. Figure shows system clock conversion method. System clock conversion from division-by-4 division-by-32 performed follows. First, make division-by-32 setting (SSR0 write), then gear enable flag (GEF: $021,3). This flag used distinguish between gear conversion transition standby mode. Next, execute instruction. When gear enable flag set, standby mode entered; when this flag set, gear conversion mode entered. this case transition made standby mode duration gear conversion, after synchronization time elapsed, transition made automatically active mode. soon transition made active mode, gear enable flag reset. same procedure used conversion from division-by-32 division-by-4. Clear interrupts, then disable interrupts, before carrying gear conversion. Incorrect operation result interrupt generated during gear conversion.
Series
Division-by-32 setting (SSR0
gear enable flag Execute instruction Synchronization time Execute next instruction
Division-by-4 setting (SSR0 gear enable flag Execute instruction Synchronization time Execute next instruction
Figure System Clock Division Ratio Conversion Flowchart
Series
System clock select register (SSR: $004) Read/Write Initial value reset name SSR3* SSR2 SSR1 SSR0
System clock division ratio switch Division-by-4 (fcyc fOSC/4) Division-by-32 (fcyc fOSC/32)
System clock division ratio switch fosc=0.4-1.0MHz fosc=1.6-4.5MHz
Subsystem clock division ratio switch Subsystem clock stop setting Subsystem clock operates stop mode Subsystem clock stops stop mode fSUB=fx/8 fSUB=fx/4
Note: subsystem clock used, this must following power-on reset. (the initial value), malfunctioning occur stop mode.
Figure System Clock Select Register
Series
Table Oscillator Circuit Examples
Circuit Structure External clock operation
External oscillator Open
Circuit Constants
OSC1
OSC2
Ceramic oscillator (OSC1,
OSC1
Ceramic oscillator
Ceramic oscillator: CSA4.00MG (Murata)
OSC2
Rf=1M±20% C1=C2=30pF±20%
Crystal oscillator (OSC1,
OSC1 Crystal oscillator OSC2
Rf=1M±20% C1=C2=10-22pF±20%
Crystal: Equivalent circuit left C0=7pFmax. RS=100max.
OSC1
OSC2
Crystal oscillator (X1,
Crystal oscillator
Crystal: 32.768 kHz: MX38T (Nihon Denpa Kogyo) C1=C2=20pF±20% RS=14k C0=1.5pF
Notes: With crystal ceramic oscillator, circuit constants will differ depending resonator, stray capacitance interconnecting circuit, other factors. Suitable constants should determined consultation with resonator manufacturer. Make connections between OSC1 pins pins) external components short possible, ensure that other lines cross these lines (see layout example figure 25). When 32.768 crystal oscillation used, leave open.
Series
RESET
OSC2
OSC1
TEST
Figure Typical Layouts Crystal Ceramic Oscillator
Series
Input/Output
input/output pins D11, R80, R81) HD404889, HD404899, HD404878 Series, input/output pins R00, R01, R02, HD404868 Series. features these pins described below. four pins source large-current max.) pins. eight pins sink large-current max.) pins. pins comprise pins (D0, R22, R80, that also have peripheral function (timer, serial interface, etc.). With these pins, peripheral function setting priority over port port setting. When peripheral function setting been made pin, function input/output mode will switched automatically accordance with that setting. Selection input output pins, selection port peripheral function pins multiplexed peripheral function pins, performed program. output peripheral function pins CMOS outputs. port designated NMOS open-drain output program. reset clears peripheral function selection. since data control registers (DCD, DCR) also reset, input/output pins high-impedance state. Each built-in pull-up that turned individually program. Figure shows buffer configuration, table shows circuit configuration control program. Table shows circuit configuration each pin.
Pull-up control signal pull-up PMOS Buffer control signal DCD, MIS3
Output data NMOS Input data Input control signal
Figure Circuit Configuration
Series
Table Programmable Circuits
PMOS NMOS pull-up Note:
MIS3 (bit MIS) DCD,DCR CMOS buffer
Table Circuit Configurations Pins
Type pins Circuit Configuration Pull-up control signal Buffer control signal Output data Input data Input control signal Pull-up control signal Buffer control signal Output data MIS3 SMR22 MIS3 DCD, Pins D0-D11 0-R03 0-R13 0-R33 0-R43 0-R53 0-R63 0-R73 0-R81
Input data Input control signal Perip- pins heral function pins Pull-up control signal MIS3 control signal
Output data
Input data
Note: reset, since control registers reset, input/output pins high-impedance state peripheral function selections cleared.
Series
Table
Type Perip- Output pins heral function pins
Circuit Configurations Pins (cont)
Circuit Configuration Pull-up control signal PMOS control signal Output data MIS3 SMR22 Pins
Pull-up control signal
MIS3 TOB, TOC, BUZZ
TOB, TOC, BUZZ
Output data
Input pins
Input data
RESET
RESET
MIS3
WU0-WU3, INT0, INT1, EVNB, EVND,
WU0-WU3 etc.
MIS3
0-AN5*
input Input control signal
Notes: reset, since control registers reset, input/output pins high-impedance state peripheral function selections cleared. Applies HD404889, HD404899, HD404868 Series.
Series
Port port consists pins pins HD404868 Series) that addressed bit-by-bit. Ports source large-current pins, ports (ports HD404868 Series) sink large-current pins. port reset instructions SEDD REDD instructions. Output data stored port data register (PDR) each pin. entire port tested instruction. port output buffer turned port data control registers (DCD0 DCD2: $030 $032). registers mapped onto memory addresses (figure 27). Ports multiplexed interrupt input pins INT0 INT1, respectively. Setting interrupt pins performed bits (PMR00, PMR01) port mode register (PMR0: $008) (figure 28).
Series
Data control registers (DCD0-2 $030-$032) (DCR0-8 $034-$03C) Register Name Read/Write DCD0-DCD2 Reset name Read/Write DCR0-DCR8 Reset name DCD03-DCD23 DCR03-DCR73 bits DCD02-DCD22 DCR02-DCR72 DCD01-DCD21 DCR01-DCR81 DCD00-DCD20 DCR00-DCR80
CMOS buffer control CMOS buffer (high impedance) CMOS buffer active
Correspondence between each ports Register Name DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7 DCR8 D11* R03* D10* R81* R80*
Note: Applies HD404889, HD404899, HD404878 Series
Figure Data Control Registers (DCD, DCR)
Series
Port port consists pins pins HD404868 Series) that addressed 4-bit units. Input performed means instructions, output means instructions. Output data stored port data register (PDR) each pin. port output buffer turned port data control registers (DCR0 DCR8: $034 $03C). registers mapped onto memory addresses (figure 27). Ports multiplexed wakeup input pins WU3, respectively. Setting these pins peripheral function pins performed port mode register (PMR1: $009) (figure 29). Ports multiplexed peripheral function pins EVNB EVND, respectively. Setting these pins peripheral function pins performed bits (PMR20, PMR21) port mode register (PMR2: $00A) (figure 30). Ports multiplexed peripheral function pins BUZZ, TOB, TOC, respectively. Setting these pins peripheral function pins performed bits (PMR22, PMR23) port mode register (PMR2: $00A) (PMR30) port mode register (PMR3: $00B)(figures 31). Ports multiplexed peripheral function pins SI/SO, respectively. Setting these pins peripheral function pins performed bits (PMR31 PMR33) port mode register (PMR3: $00B) (figure 31). Ports multiplexed peripheral function pins SEG1 SEG16, respectively. Setting these pins segment pins performed every pins 4-bit units port mode register (PMR4: $00C) (figure 32). Ports also function peripheral function pins (HD404889, HD404899, HD404868 series only). Peripheral function setting these pins performed using bits (AMR1 AMR3) mode register (AMR :$028). (See Figure Converter.)
Series
Port mode register (PMR0: $008) Read/Write Initial value reset name used used PMR01 PMR00
PMR00 PMR01
D0/INT0 mode selection INT0
D1/INT1 mode selection INT1
Figure Port Mode Register (PMR0: $008)
Series
Port mode register (PMR1: $009) Read/Write Initial value reset name PMR13* PMR12 PMR11 PMR10
PMR10 PMR11 PMR12 PMR13
R00/WU0 mode selection
R01/WU1 mode selection
R02/WU2 mode selection
R03/WU3 mode selection
Note: Applies HD404889, HD404899, HD404878 Series
Figure Port Mode Register (PMR1: $009)
Series
Port mode register (PMR2: $00A) Read/Write Initial value reset name PMR23 PMR22 PMR21* PMR20
PMR20 PMR21 PMR22 PMR23
R10/EVNB mode selection EVNB
R11/EVND mode selection EVND
R12/BUZZ mode selection BUZZ
R13/TOB mode selection
Note: Applies HD404889, HD404899, HD404878 Series
Figure Port Mode Register (PMR2: $00A)
Series
Port mode register (PMR3: $00B) Read/Write Initial value reset name PMR33 PMR32 PMR31 PMR30
PMR30 PMR31 PMR33 PMR32 Don't care
R20/TOC mode selection
R21/SCK mode selection
R22/SI/SO mode selection
Figure Port Mode Register (PMR3: $00B)
Series
Port mode register (PMR4: $00C) Read/Write Initial value reset name PMR43 PMR42 PMR41 PMR40
PMR40 R3/SEG1 SEG4 mode selection PMR41 PMR42 PMR43 SEG1-4
R4/SEG5 SEG8 mode selection SEG5-8
R5/SEG9 SEG12 mode selection SEG9-12
R6/SEG13 SEG16 mode selection SEG13-16
When segment output pin, write port data register (PDR)
Figure Port Mode Register (PMR4: $00C) Pull-Up Control Program-controllable pull-ups incorporated pins. On/off control pull-ups performed (MIS3) miscellaneous register (MIS: $005) port data register (PDR) each pin, enabling pull-up turned independently each (table figure 33). Except analog input multiplexed pins, pull-up on/off setting made independent setting on-chip supporting module pin.
Series
Miscellaneous register (MIS: $005) Read/Write Initial value reset name MIS3 MIS1 MIS0
selection (See figure Operating Modes section) MIS3 pull-up control pull-ups pull-up active
Figure Miscellaneous Register (MIS:$005) Handling Pins Used User System pins that used user system left floating, they generate noise that result chip malfunctions. Therefore, potential must fixed. this case, pull pins with built-in pull-up with external resistor approximately
Series
Prescalers
following prescalers, operating conditions each prescaler shown table output supply destinations figure Timer input clocks other than external events, serial transfer clocks other than external clocks, circuit operating clock selected from prescaler outputs accordance with respective mode register. Prescaler Operation Prescaler (PSS): Prescaler 11-bit counter that system clock input. When reset, prescaler reset $000, then divides system clock. Prescaler operation stopped reset MCU, stop mode watch mode. does stop other modes. Prescaler (PSW): Prescaler counter that clock divided from input crystal oscillation) input. When reset, prescaler reset $00, then divides input clock. Prescaler also reset software. Table
Prescaler Prescaler
Prescaler Operating Conditions
Input Clock Reset Conditions Stop Conditions reset, Stop mode, Watch mode reset, Stop mode
System clock active reset, Stop mode standby modes, Subsystem clearance clock subactive mode Clock obtained division- reset, Software* by-8 32.768 oscillation subsystem clock oscillator
Prescaler
Note: bits TMA3 TMA1 timer mode register (TMA) cleared $00.
Series
Subsystem clock
Prescaler
controller driver circuit Timer Timer Timer Timer
System clock
Clock selector
Prescaler
Serial interface
Figure Prescaler Output Destinations
Series
Timers
incorporates four timers, HD404889, HD404899, HD404878 Series, three timers, HD404868 Series. Timer Free-running timer Timer Multifunctional timer Timer Multifunctional timer Timer Multifunctional timer
Timer 8-bit free-running timer. Timers 8-bit multifunctional timers; Each their have functions shown table their operating mode program. Table
Functios Clock source Prescaler Prescaler External event Timer functions Free-running Time-base Event counter Reload Watchdog Input Capture Timer outputs Toggle Note: implies available
Timer Functions
Timer Available Available Available Available Timer Available Available Available Available Available Available Available Timer Available Available Available Available Available Available Timer Available Available Available Available Available Available
Timer Timer Functions Timer following functions. Free-running timer Realtime clock time base block diagram timer shown figure
Series
32.768-kHz oscillator Wcyc Selector Internal data Selector Clock Timer counter (TCA) Overflow Wcyc Prescaler (PSW)
Timer interrupt request flag (IFTA)
Selector
1024 2048
System clock
Prescaler (PSS)
Timer mode register (TMA)
Data Clock line Signal line
Figure Timer Block Diagram Timer Operation Free-running timer operation: timer input clock selected timer mode register (TMA: $00F). Timer reset reset, counts each time input clock input. When input clock input after timer value reaches $FF, overflow output generated, timer value becomes $00. generated overflow output sets timer interrupt request flag (IFTA: $002,0). Timer continues counting after count value returns $00, that interrupt generated regularly every input clock cycles. Realtime clock time base operation: Timer used realtime clock time base setting (TMA3) timer mode register prescaler output input timer/counter interrupts generated with accurate timing using 32.768 crystal oscillator basic clock. When timer used realtime clock time base, prescaler timer/counter reset program.
Series
Timer Register Timer operation means following register. Timer mode register (TMA: $00F): Timer mode register (TMA: $00F) 4-bit write-only register. Timer operation input clock selection shown figure
Series
Timer mode register (TMA: $00F) Read/Write Initial value reset name TMA3 TMA2 TMA1 TMA0
TMA3
TMA2
TMA1
TMA0
Source prescaler
Input clock period Operating mode 2,048 tcyc 1,024 tcyc tcyc tcyc tcyc tcyc tcyc tcyc twcyc twcyc twcyc twcyc twcyc Time base mode Timer mode
Don't care Notes: twcyc 244.14 (using 32.768 crystal oscillator) Timer/counter overflow output period input clock period 256. reset selected during LCD, enters halt state (power switch off). Therefore, provide continuous reset interval must minimized program. division ratio must changed while time base mode being used, this will result error overflow period.
Used PSW, reset
Figure Timer Mode Register (TMA)
Series
Timer Timer Functions: Timer following functions. Free-running/reload timer External event counter Timer output operation (toggle output, output) block diagram timer shown figure
Timer ineterrupt
Timer clock source Timer output control logic
request flag (IFTB)
EVNB Edge detection logic
Prescaler (PSS)
Timer read register (TRBL)
Selector
Timer read register (TRBU)
System clock
Free-runnning/Reload control
÷128 ÷512 ÷2048
(TCBL)
(TCBU)
Timer write register (TWBL) (TWBU)
Timer mode register (TMB1)
Timer mode register (TMB2) Data Clock line Signal line
Figure Timer Block Diagram
Internal data
Timer counter
Overflow
Series
Timer Operation Free-running/reload timer: Free-running/reload timer operation, input clock source, prescaler division ratio selected means timer mode register (TMB1). Timer initialized value written timer write register (TWBL, TWBU) software, counts each time input clock input. When input clock input after timer value reaches $FF, overflow output generated. Timer then value timer write register reload timer function selected, free-running timer function selected, starts counting again. Overflow output sets timer interrupt request flag (IFTB). This flag reset program reset. details, figure Interrupt Control Register Flag Area Configuration, table Initial Values after Reset. External event counter operation: When external event input designated input clock, timer operates external event counter. When external event input used, 0/EVNB designated EVNB port mode register (PMR2). external event detected edge timer designated falling edge, rising edge, both falling rising edges input signal means timer mode register (TMB2). both falling rising edges selected, input signal falling rising edge interval should least 2tcyc. Timer counts each time falling edge detected signal input EVNB pin. Other operations same free-running/reload timer function. Timer output operation: With timer R13/TOB designated setting port mode register (PMR2), toggle waveform output waveform output selected timer mode register (TMB2). Toggle output: With toggle output, output level changed upon input next clock pulse after timer value reaches $FF. this function combination with reload timer allows clock signal with period output, enabling used buzzer output. output waveform shown figure (1). output: With output, variable-duty pulses output. output waveform shown figure (2), according contents timer mode register (TMB1) timer write register (TWBL, TWBU). When waveform output with (TMB13) timer mode register cleared write timer write register change duty effective from next frame, whereas waveform output with TMB13 (reload setting), next frame output immediately after timer write register write. Module standby: With timer supply system clock timer/counter halted setting module standby register (MSR1: $00D) module standby state, mode register value retained counter value guaranteed.
Series
Toggle output waveform (timer timer
Free-running timer
clock periods Reload timer
clock periods
(256 clock periods
(256 clock periods
output waveform (timer timer
TMB13 (free-running timer) TMB13 (reload timer) (256
Notes:
Counter input clock period clock input source division ratio controlled timer mode register timer mode register Value timer write register timer write register When $FF), output always fixed timer level.)
Figure Timer Output Waveforms
Series
Timer Registers Timer operation setting timer value reading/writing controlled following registers. Timer mode register (TMB1: $010) Timer mode register (TMB2: $011) Timer write register (TWBL: $012, TWBU: $013) Timer read register (TRBL: $012, TRBU: $013) Port mode register (PMR2: $00A) Module standby register (MSR1: $00D) Timer mode register (TMB1: $010): Timer mode register (TMB1) 4-bit write-only register, used select free-running/reload timer operation input clock shown figure Timer mode register (TMB1) reset reset: modification timer mode register (TMB1) becomes effective after execution instructions following timer mode register (TMB1) write instruction. program must provide timer initialization writing timer write register (TWBL, TWBU) executed after postmodification mode become effective.
Series
Timer mode register (TMB1: $010) Read/Write Initial value reset name TMB13 TMB12 TMB11 TMB10
TMB12
TMB11
TMB10
Input clock period input clock source 2,048 tcyc tcyc tcyc tcyc tcyc tcyc tcyc R10/EVNB (external event input)
TMB13
Free-running/reload timer Free-running timer Reload timer
Figure Timer Mode Register (TMB1) Timer mode register (TMB2: $011): Timer mode register (TMB2) 3-bit write-only register, used select timer output mode EVNB detected edge shown figure Timer mode register (TMB2) reset reset.
Series
Timer mode register (TMB2: $011) Read/Write Initial value reset name TMB22 TMB21 TMB20
TMB21 TMB20 TMB22
EVNB detected edge detected Falling edge detection Rising edge detection Both rising falling edge detection
Timer output waveform Toggle output output
Figure Timer Mode Register (TMB2) Timer write register (TWBL: $012, TWBU:$013): Timer write register (TWBL, TWBU) write-only register composed lower digit (TWBL) upper digit (TWBU) (figures 42). lower digit (TWBL) timer write register reset reset, while upper digit (TWBU) undetermined. Timer initialized writing timer write register (TWBL, TWBU). write data, first write lower digit (TWBL). lower digit write does change timer value. Next, write upper digit (TWBU). Timer then initialized timer write register (TWBL, TWBU) value. When writing timer write register (TWBL, TWBU) from second time onward, necessary change lower digit (TWBL) reload value, timer initialization completed upper digit write alone.
Timer write register (lower) (TWBL: $012) Read/Write Initial value reset name TWBL3 TWBL2 TWBL1 TWBL0
Figure Timer Write Register (Lower) (TWBL)
Series
Timer write register (upper) (TWBU: $013) Read/Write Initial value reset name
Undetermined Undetermined Undetermined Undetermined
TWBU3
TWBU2
TWBU1
TWBU0
Figure Timer Write Register (Upper) (TWBU) Timer read register (TRBL: $012, TRBU: $013): Timer read register (TRBL, TRBU) read-only register composed lower digit (TRBL) upper digit (TRBU) from which value upper digit timer read directly (figures 44). First, read upper digit (TRBU) timer read register current value timer upper digit read and, same time, value timer lower digit latched lower digit (TRBL) timer read register timer value obtained when upper digit (TRBU) timer read register read reading lower digit (TRBL) timer read register
Timer read register (lower) (TRBL: $012) Read/Write Initial value reset name TRBL3
Undetermined Undetermined Undetermined Undetermined
TRBL2
TRBL1
TRBL0
Figure Timer Read Register (Lower) (TRBL)
Timer read register (upper) (TRBU: $013) Read/Write Initial value reset name
Undetermined Undetermined Undetermined Undetermined
TRBU3
TRBU2
TRBU1
TRBU0
Figure Timer Read Register (Upper) (TRBU)
Series
Port mode register (PMR2: $00A): Port mode register (PMR2) write-only register used function R10/EVNB 3/TOB pins shown figure Port mode register (PMR2) reset reset.
Port mode register (PMR2: $00A) Read/Write Initial value reset name PMR23 PMR22 PMR21* PMR20
PMR20 PMR21 PMR22 PMR23
R10/EVNB mode selection EVNB
R11/EVND mode selection EVND
R12/BUZZ mode selection BUZZ
R13/TOB mode selection
Note: Applies HD404889, HD404899, HD404878 Series
Figure Port Mode Register (PMR2: $00A) Module standby register (MSR1: $00D): Module standby register (MSR1) write-only register used designate supply stopping clock timer shown figure Module standby register (MSR1) reset reset.
Series
Module standby register (MSR1: $00D) Read/Write Initial value reset name MSR12 MSR11 MSR10
MSR10 MSR11 MSR12
Timer clock supply control Supplied Stopped
Timer clock supply control Supplied Stopped
Timer clock supply control Supplied Stopped
Figure Module Standby Register (MSR1)
Series
Timer Timer Functions:Timer following functions. Free-running/reload timer Watchdog timer Timer output operation (toggle output, output) block diagram timer shown figure
Series
System reset signal Watchdog flag (WDON) Timer output control logic
Timer interrupt request flag (IFTC)
Watchdog timer control logic
System clock
Timer overflow
Timer read register (TRCL)
Timer read register (TRCU)
Prescaler (PSS) 2048
Timer counter Selector
Overflow
(TCCL)
Free-running/reload control
(TCCU)
Timer write register
(TWCL)
(TWCU)
Timer mode register (TMC1)
Timer output control Data Clock line Signal line
Timer mode register (TMC2)
Figure Timer Block Diagram
Internal data
Series
Timer Operation Free-running/reload timer: Free-running/reload timer operation, input clock source, prescaler division ratio selected means timer mode register (TMC1). Timer initialized value written timer write register (TWCL, TWCU) software, counts each time input clock input. When input clock input after timer value reaches $FF, overflow output generated. Timer then value timer write register (TWCL, TWCU) reload timer function selected, free-running timer function selected, starts counting again. Overflow output sets timer interrupt request flag (IFTC). This flag reset program reset. details, figure Interrupt Control Register Flag Area Configuration, table Initial Values after Reset. 16-bit timer operation: When timer overflow flag selected clock source, timer used 16-bit timer that counts timer clock source pulses. this case, since timer timer free-running/reload settings independent, settings should made suit purpose. Watchdog timer operation: using timer overflow output, timer used watchdog timer detecting program runaway. watchdog timer enabled when watchdog flag (WDON) generates reset when timer overflows. Usually, timer initialization performed program before timer value reaches $FF, controlling program runaway. Timer output operation: With timer R20/TOC designated setting port mode register (PMR3) toggle waveform output waveform output selected timer mode register (TMC2). Toggle output operation similar that timer toggle output. output operation similar that timer output. Module standby: operation similar that timer module standby.
Series
Timer Registers Timer operation setting timer value reading/writing controlled following registers. Timer mode register (TMC1: $014) Timer mode register (TMC2: $015) Timer write register (TWCL: $016, TWCU: $017) Timer read register (TRCL: $016, TRCU: $017) Port mode register (PMR3: $00B) Module standby register (MSR1: $00D) Timer mode register (TMC1: $014): Timer mode register (TMC1) 4-bit write-only register, used select free-running/reload timer operation, input clock, prescaler division ratio shown figure Timer mode register (TMC1) reset reset. modification timer mode register (TMC1) becomes effective after execution instructions following timer mode register (TMC1) write instruction. program must provide timer initialization writing timer write register (TWCL, TWCU) executed after postmodification mode become effective.
Series
Timer mode register (TMC1: $014) Read/Write Initial value reset name TMC13 TMC12 TMC11 TMC10
TMC12
TMC11
TMC10
Input clock period 2,048 tcyc tcyc tcyc tcyc tcyc tcyc tcyc Timer overflow
TMC13
Free-running/reload timer Free-running timer Reload timer
Figure Timer Mode Register (TMC1)
Series
Timer mode register (TMC2: $015): Timer mode register (TMC2) 1-bit write-only register, used select timer output mode shown figure Timer mode register (TMC2) reset reset.
Timer mode register (TMC2: $015) Read/Write Initial value reset name TMC22
TMC22
Timer output waveform Toggle output output
Figure Timer Mode Register (TMC2) Timer write register (TWCL: $016, TWCU: $017): Timer write register (TWCL, TWCU) write-only register composed lower digit (TWCL) upper digit (TWCU) (figures 51). Timer write register (TWCL, TWCU) operation similar that timer write register (TWBL, TWBU).
Timer write register (lower) (TWCL: $016) Read/Write Initial value reset name TWCL3 TWCL2 TWCL1 TWCL0
Figure Timer Write Register (Lower) (TWCL)
Series
Timer write register (upper) (TWCU: $017) Read/Write Initial value reset name
Undetermined Undetermined Undetermined Undetermined TWCU3 TWCU2 TWCU1 TWCU0
Figure Timer Write Register (Upper) (TWCU) Timer read register (TRCL: $016, TRCU: $017): Timer read register (TRCL, TRCU) read-only register composed lower digit (TRCL) upper digit (TRCU) from which value upper digit timer read directly (figures 53). Timer read register (TRCL, TRCU) operation similar that timer read register (TRBL, TRBU).
Timer read register (upper) (TRCL: $016) Read/Write Initial value reset name
Undetermined Undetermined Undetermined Undetermined TRCL3 TRCL2 TRCL1 TRCL0
Figure Timer Read Register (Lower) (TRCL)
Timer read register (upper) (TRCU: $017) Read/Write Initial value reset name
Undetermined Undetermined Undetermined Undetermined TRCU3 TRCU2 TRCU1 TRCU0
Figure Timer Read Register (Upper) (TRCU)
Series
Port mode register (PMR3: $00B): Port mode register (PMR3) write-only register used function R20/TOC shown figure Port mode register (PMR3) reset reset.
Port mode register (PMR3: $00B) Read/Write Initial value reset name PMR33 PMR32 PMR31 PMR30
PMR30 PMR31 PMR33 PMR32 Don't care
R20/TOC mode selection
R21/SCK mode selection
R22/SI/SO mode selection
Figure Port Mode Register (PMR3) Module standby register (MSR1: $00D): Module standby register (MSR1) write-only register used designate supply stopping clock timer shown figure Module standby register (MSR1) reset reset.
Series
Timer (HD404889/HD404899/HD404878 Series) Timer functions Timer following functions. Free-running/reload timer External event counter Input capture timer Block diagrams timer different operating modes shown figures 55-1 55-2.
Series
Timer interrupt request flag (IFTD) EVND Edge detection logic
System clock
Timer read register (TRDL)
Timer read register (TRDU)
Prescaler (PSS)
2048
Selector
(TCDL)
Free-running/ reload control
(TCDU)
Timer write register
(TWDL)
(TWDU)
Timer mode register (TMD1)
Edge detection control Data Clock line Signal line
Timer mode register (TMD2)
Figure 55-1 Timer Block Diagram (Reload Timer Event Counter Modes)
Internal data
Timer counter
Overflow
Series
Input capture status flag (ICSF) Input capture error flag (ICEF) Timer interrupt request flag (IFTD)
EVND
Edge detection logic
Read signal
System clock Timer read register (TRDL) Prescaler (PSS) ÷128 ÷512 ÷2048 Selector Timer counter (TCDL) (TCDU) Input capture timer control (TRDU)
Overflow
Time mode register (TMD1)
Timer mode register (TMD2)
Data Clock line Signal line
Figure 55-2 Timer Block Diagram (Input Capture Timer Mode)
Internal data
Series
Timer Operation Free-running/reload timer: Free-running/reload timer operation, input clock source, prescaler division ratio selected means timer mode register (TMD1). Timer initialized value written timer write register (TWDL, TWDU) software, counts each time input clock input. When input clock input after timer value reaches $FF, overflow output generated. Timer then value timer write register (TWDL, TWDU) reload timer function selected, free-running timer function selected, starts counting again. Overflow output sets timer interrupt request flag (IFTD). This flag reset program reset. details, figure Interrupt Control Register Flag Area Configuration, table Initial Values after Reset. External event counter operation: When external event input designated input clock, timer operates external event counter. When external event input used, 1/EVND designated EVND port mode register (PMR2). external event detected edge timer designated falling edge, rising edge, both falling rising edges input signal means timer mode register (TMD2). both falling rising edges selected, input signal falling rising edge interval should least 2tcyc. Timer counts each time edge selected timer mode register (TMD2) detected. Other operations same free-running/reload timer function. Input capture timer operation: input capture timer function used measure time between trigger input edges input EVND pin. trigger input edge designated falling edge, rising edge, both falling rising edges means timer mode register (TMD2). When trigger input edge detected EVND pin, current timer value stored timer read register (TRDL, TRDU), timer interrupt request flag (IFTD) input capture status flag (ICSF) set. same time, timer reset continues counting next trigger input edge input while input capture status flag (ICSF) set, timer overflows, input capture error flag (ICEF) set. input capture status flag (ICSF) input capture error flag (ICEF) reset reset writing them. When timer operate input capture timer, reset $00.
Series
Timer Registers: Timer operation setting timer value reading/writing controlled following registers. Timer mode register (TMD1: $018) Timer mode register (TMD2: $019) Timer write register (TWDL: $01A, TWDU: $01B) Timer read register (TRDL: $01A, TRDU: $01B) Port mode register (PMR2: $00A) Module standby register (MSR1: $00D) Timer mode register (TMD1: $018): Timer mode register (TMD1) 4-bit write-only register, used select free-running/reload timer operation, input clock, prescaler division ratio shown figure Timer mode register (TMD1) reset reset. modification timer mode register (TMD1) becomes effective after execution instructions following timer mode register (TMD1) write instruction. program must provide timer initialization writing timer write register (TWDL, TWDU) executed after post-modification mode become effective. When timer operate input capture timer, internal clock should input clock.
Series
Timer mode register (TMD1: $018) Read/Write Initial value reset name TMD13 TMD12 TMD11 TMD10
TMD12
TMD11
TMD10
Input clock period input clock source 2,
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