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HD404849 Series
4-Bit Single-Chip Microcomputer
Rev. Sept. 1998 Description
HD404849 series HMCS400-series microcomputers designed increase program productivity also incorporate large-capacity memory. Each microcomputer controller/driver, converter, input capture circuit, 32-kHz oscillator clock use, four low-power dissipation modes. HD404849 series includes HD404848 with 8-kword on-chip ROM, HD4048412 with 12kword on-chip ROM, HD404849 with 16-kword on-chip ROM, HD4074849 with 16-kword on-chip PROM. On-chip available PROM (ZTATmicrocomputer) version mask version. program written PROM PROM writer, which dramatically shorten system development periods smooth process from debugging mass production. PROM programming specifications same 27256. ZTATTM: Zero Turn Around Time ZTAT trademark Hitachi Ltd.
Features
pins, including nine high-current pins max.), eight pins multiplexed with segment pins, four pins multiplexed with analog input pins Four timer/counters Eight-bit input capture circuit Three timer outputs (including outputs) event counter inputs (including which detection edge programmable) Clock-synchronous 8-bit serial interface converter channels bits) Operation voltage driver segments commons) Built-in oscillators Main clock: driven ceramic oscillator, crystal oscillator, external clock. Subclock: 32.768-kHz crystal interrupt sources Four external sources, including which detection edge programmable
HD404849 Series
internal sources Subroutine stack levels, including interrupts Four low-power dissipation modes Standby mode Stop mode Watch mode Subactive mode external input transition from stop mode active mode Instruction cycle time: 0.89 (fOSC MHz) Operation voltage (subactive mode: (HD404848, HD404849) (HD4074849) operating modes mode (HD404848, HD4048412, HD404849) MCU/PROM mode (HD4074849 only)
Ordering Information
Type Mask Product Name HD404848 Model Name HD404848H HD404848FS HD404848TF HD4048412 HD4048412H HD4048412FS HD4048412TF HD404849 HD404849H HD404849FS HD404849TF ZTATHD4074849 HD4074849H HD4074849FS HD4074849TF 16,384 1,184 16,384 1,184 12,288 1,184 (words) 8,192 (digits) Package 80-pin plastic (FP-80A) 80-pin plastic (FP-80B) 80-pin plastic TQFP (TFP-80C) 80-pin plastic (FP-80A) 80-pin plastic (FP-80B) 80-pin plastic TQFP (TFP-80C) 80-pin plastic (FP-80A) 80-pin plastic (FP-80B) 80-pin plastic TQFP (TFP-80C) 80-pin plastic (FP-80A) 80-pin plastic (FP-80B) 80-pin plastic TQFP (TFP-80C)
HD404849 Series
Arrangement
R31/AN5 R30/AN4 AVCC COM4 COM3 COM2 COM1 SEG44 SEG43 SEG42 SEG41 SEG40
R32/AN6 R33/AN7 AVSS TEST OSC1 OSC2 RESET D10/STOPC
FP-80A TFP-80C (top view)
SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 R73/SEG20
R30/AN4 R31/AN5 R32/AN6 R33/AN7 AVSS TEST OSC1 OSC2 RESET D10/STOPC D11/INT0 R00/INT1
AVCC COM4 COM3 COM2 COM1 SEG44 SEG43 SEG42
D11/INT0 R00/INT1 R01/INT2 R02/INT3 R10/TOB R11/TOC R12/TOD R13/EVNB R20/EVND R21/SCK R22/SI R23/SO R60/SEG13 R61/SEG14 R62/SEG15 R63/SEG16 R70/SEG17 R71/SEG18 R72/SEG19
FP-80B (top view)
SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 R73/SEG20 R72/SEG19 R71/SEG18
R01/INT2 R02/INT3 R10/TOB R11/TOC R12/TOD R13/EVNB R20/EVND R21/SCK R22/SI R23/SO R60/SEG13 R61/SEG14 R62/SEG15 R63/SEG16 R70/SEG17
HD404849 Series
Description
Number Item Power supply Symbol Test Reset Oscillator TEST RESET FP-80A ,TFP-80C FP-80B Function Applies power voltage Connected ground Used factory testing only: Connect this Resets Input/output pins internal oscillator circuit: Connect them ceramic oscillator connect OSC1 external oscillator circuit.
Used 32.768-kHz crystal clock purposes. used, leave open.
Port D0-D
11-19
13-21
Input/output pins addressed individual bits; pins highcurrent pins that each supply Input pins addressable individual bits
D10,
24-35, 1-4, 36-43 23-26 28-30
R0-R3, 22-33, 34-41 Interrupt Stop clear Serial INT0, INT1, INT2, INT3 STOPC Timer TOB, TOC, EVNB, EVND 21-24 26-28
Input/output pins addressable 4-bit units Input pins external interrupts Input transition from stop mode active mode
Serial clock input/output Serial receive data input Serial transmit data output Timer output pins Event count input pins
HD404849 Series
Number Item Symbol FP-80A, TFP-80C FP-80B 70-72 72-74 Function Power pins driver. power supply division resistors connected disconnected controlled software. Voltage conditions are: Common signal pins Segment signal pins Power converter: Connect same potential VCC, physically close possible Ground Connect same potential GND, physically close possible Analog input pins converter
COM1- COM4 SEG13- SEG44 converter AVCC
66-69 34-65
68-71 36-67
AVSS
0-AN
75-80,
77-80,
HD404849 Series
Block Diagram
RESET TEST STOPC
System control circuit D11/ R00/ R01/ R02/ 4-bit, 1,184 4-bit
External interrupt control cricuit
Timer R10/ R13/ EVNB R11/ R12/ R20/ EVND R21/ R22/ R23/ AVCC AVSS R30/ R31/ R32/ R33/ COM1 COM2 COM3 COM4 R60/ SEG13 Timer Timer Timer Serial interface
Highcurrent pins
/STOPC /INT0
/INT1 /INT2 /INT3 /TOB /TOC /TOD /EVNB /EVND /SCK /AN4 /AN5 /AN6 /AN7
Internal address
Internal data
Internal data
converter
(10) display circuit
Instruction decoder
Program counter (14)
/SEG13 /SEG14 /SEG15 /SEG16 /SEG17 /SEG18 /SEG19 /SEG20
SEG44
8,192 10-bit, 12,288 10-bit, 16,384 10-bit
Data Signal lines
HD404849 Series
Memory
Memory memory shown figure described below. Vector Address Area ($0000-$000F): Reserved JMPL instructions that branch start addresses reset interrupt routines. After reset interrupt, program execution continues from vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved subroutines. program branches subroutine this area response instruction. Pattern Area ($0000-$0FFF): Contains data that referenced with instruction. Program Area ($0000-$1FFF: HD404848; $0000-$2FFF: HD4048412; $0000-$3FFF: HD404849, HD4074849): Used program coding.
$0000 $000F
Vector address area words) Zero-page subroutine area words)
JMPL instruction (jump RESET, STOPC routine) JMPL instruction (jump INT0 routine) JMPL instruction (jump INT1 routine) JMPL instruction (jump timer routine) JMPL instruction (jump timer routine) JMPL instruction (jump timer INT3 routine) JMPL instruction (jump timer routine) JMPL instruction (jump A/D, serial routine)
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
$003F
Pattern area (4,096 words) 4095 HD404848 program area (8,192 words) 8191 $1FFF $0FFF
HD4048412 program area (12,288 words) 12287 HD404849/ HD4074849 program area (16,384 words) 16383 $3FFF $2FFF
Figure Memory
HD404849 Series
Memory contains area consisting memory register area, data area, data area, stack area. addition, interrupt control bits area, special register area, register flag area mapped onto same memory space RAM-mapped register area outside above areas. memory shown figure described below. RAM-Mapped Register Area ($000-$03F): Interrupt Control Bits Area ($000-$003) This area used interrupt control bits (figure These bits accessed only manipulation instructions (SEM/SEMD, REM/REMD, TM/TMD). However, note that instructions used each bit. Limitations using instructions shown figure Special Function Register Area ($004-$01F, $024-$03F) This area used mode registers data registers external interrupts, serial interface, timer/counters, LCD, converter, used data control registers ports. structure shown figures These registers classified into three types: write-only (W), read-only (R), read/write (R/W). SEM, SEMD, REM, REMD instructions used control register (LCR: $01B), manipulation instructions cannot used other registers. Register Flag Area ($020-$023) This area used DTON, WDON, other register flags interrupt control bits (figure These bits accessed only manipulation instructions (SEM/SEMD, REM/REMD, TM/TMD). However, note that instructions used each bit. Limitations using instructions shown figure Memory Register (MR) Area ($040-$04F): Consisting addresses, this area (MR0-MR15) accessed register-register instructions (LAMR XMRA). structure shown figure Data Area ($05C-$07B): Used storing 32-digit data which automatically output segments display data. Data lights corresponding segment; data extinguishes Refer description details. Data Area ($090-$21F: HD404848; $090-$2EF: HD4048412, HD404849, HD4074849): digits from $090 $25F have banks, which selected setting bank register $03F). Before accessing this area, bank register required value (figure area from $260 $2EF accessed without setting bank register. Stack Area ($3C0-$3FF): Used saving contents program counter (PC), status flag (ST), carry flag (CA) subroutine call (CAL CALL instruction) interrupts. This area used 16-level nesting subroutine stack which level requires four digits. data saved save conditions shown figure program counter restored either RTNI instruction, status carry flags only restored RTNI instruction. unused space this area used data storage.
HD404849 Series
HD404848
HD4048412, HD404849, HD4074849
$000
mapped register
$000
Interrupt control bits area (PMRA) Port mode register (SMRA) Serial mode register (SRL) Serial data register lower Serial data register upper (SRU) (TMA) Timer mode register (TMB1) Timer mode register (TRBL/TWBL) Timer-B (TRBU/TWBU) (MIS) Miscellaneous register (TMC1) Timer mode register (TRCL/TWCL) Timer-C (TRCU/TWCU) Timer mode register (TMD1) (TRDL/TWDL) Timer-D (TRDU/TWDU) (TMB2) Timer mode register Timer mode register (TMC2) (TMD2) Timer mode register (AMR) mode register (ADRL) data register lower (ADRU) data register upper
used
$000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018
mapped register
Memory register digits) used display area digits) used
$040 $050 $05C $07C $090
Memory register digits)
used
$040
$050 $05C $07C $090
display area digits)
used
Data (400 digits)
Data (464 digits (bank (bank
$220
used
Data (144 digits)
used
$260 $2F0 $3C0
$3C0 Stack digits)
Stack digits)
1023
$3FF 1023
$3FF
Notes: Read only Write only R/W: Read/write
control register mode register
used
(LCR) (LMR)
$01B $01C
data area banks: bank bank
$090
output register
(LOR3)
$01F $020 $023 $024 $025 $026 $027 $028 $029
Register flag area Port mode register Port mode register Edge sense select register Edge sense select register Serial mode register System clock select register
used
Data (464 digits) (bank
Data (464 digits) (bank
(PMRB) (PMRC) (ESR1) (ESR2) (SMRB) (SSR)
$25F
registers mapped same address $00A, $00B, $00E, $00F, $011, $012)
Port Port Port used Port Port Port Port
used
(DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3)
$02C $02D $02E $030 $031 $032 $033
Port Port
used
(DCR6) (DCR7)
$036 $037
register
$03F
Timer read register lower (TRBL) Timer read register upper (TRBU)
Timer read register lower (TRCL) Timer read register upper (TRCU)
Timer read register lower (TRDL) Timer read register upper (TRDU)
Timer write register lower (TWBL) Timer write register upper (TWBU)
Timer write register lower (TWCL) Timer write register upper (TWCU)
Timer write register lower (TWDL) Timer write register upper (TWDU)
$00A $00B
$00E $00F
$011 $012
Figure Memory
HD404849 Series
(Interrupt enable flag)
$000
INT0)
INT0)
(Reset bit)
IMTA timer
IMTC timer IMAD A/D)
IFTA timer IFTC timer
INT1)
IMTB timer IMTD timer
INT1)
IFTB timer
IFTD timer
$001
$002
IFAD A/D)
$003
Interrupt control bits area
DTON (Direct transfer flag)
ADSF (A/D start flag)
IAOF (A/D current flag)
WDON (Watchdog flag)
LSON (Low speed flag) $020
RAME (RAM enable flag)
ICEF (Input capture error flag)
ICSF (Input capture status flag)
$021
INT3)
serial interface)
INT3)
serial interface)
INT2)
used
INT2)
used
$022
$023
Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer
Register flag area
Figure Configuration Interrupt Control Bits Register Flag Areas
HD404849 Series
Bits interrupt control bits area register flag area reset SEM/SEMD REM/REMD instructions, tested with TM/TMD instructions. Other instructions have effect these bits. Note following restrictions each bit. SEM/SEMD LSON IAOF ICSF ICEF RAME WDON ADSF DTON used Allowed REM/REMD Allowed TM/TMD Allowed
executed executed Allowed Allowed executed active mode Used subactive mode executed
Allowed Allowed executed Inhibited Allowed executed
Allowed Inhibited Inhibited Allowed Allowed Inhibited
Note: WDON reset reset STOPC enable stop mode cancellation. REMD instuction must executed ADSF during conversion. DTON always reset active mode. instruction executed inhibited bits non-existing bits, value cannot guaranteed.
Figure Usage Limitations Manipulation Instructions
HD404849 Series
$000 $003 PMRA $004 SMRA $005 $006 $007 $008 TMB1 $009 TRBL/TWBL $00A TRBU/TWBU $00B $00C TMC1 $00D TRCL/TWCL $00E TRCU/TWCU $00F TMD1 $010 TRDL/TWDL $011 TRDU/TWDU $012 TMB2 $013 TMC2 $014 TMD2 $015 $016 ADRL $017 ADRU $018 bit3 bit2 bit1 bit0 Interrupt control bits area used R21/ R22/SI used R23/SO Serial transmit clock speed selection Serial data register (lower digit) Serial data register (upper digit) Clock source selection (timer Clock source selection (timer Timer register (lower digit) Timer register (upper digit) PMOS control Interrupt frame period selection Clock source selection (timer Timer register (lower digit) Timer register (upper digit) Auto reload on/off Clock source selection (timer Timer register (lower digit) Timer register (upper digit) Timer output mode selection used Timer output mode selection Timer output mode selection Analog channel selection data register (lower digit) data register (upper digit) used $01B $01C input clock source selection power switch display on/off duty cycle selection used LOR3 $01F $020 $023 PMRB $024 PMRC $025 ESR1 $026 ESR2 $027 SMRB $028 $029 used R7/SEG17-20 R6/SEG13-16 used conversion period
Timer A/time base Auto reload on/off
Pull-up control Auto reload on/off
used used Input capture selection
Register flag area 2/INT3 used D11/INT0 D10/STOPC INT3 detection edge selection EVND detection edge selection used used 32-kHz oscillation stop used DCD0 $02C DCD1 $02D DCD2 $02E DCR0 $030 DCR1 $031 DCR2 $032 DCR3 $033 Port Port used Port Port Port Port Port Port used Port Port used Port Port Port Port Port Port Port 1/INT2 /INT1 R20/EVND R13/EVNB INT2 detection edge selection used used used
used Port Port Port Port Port Port Port Port used
DCR6 $036 DCR7 $037
Port Port
Port Port
Port Port
Port Port
used $03F used used used Bank selection
Notes: display division resistor switch Display on/off watch mode output level control idle states
Transmit clock source selection 32-kHz oscillation division ratio System oscillation frequency selection
Figure Special Function Register Area
HD404849 Series
Memory registers MR(0) $040 MR(1) $041 MR(2) $042 MR(3) $043 MR(4) $044 MR(5) $045 MR(6) $046 MR(7) $047 MR(8) $048 MR(9) $049 MR(10) $04A MR(11) $04B MR(12) $04C MR(13) $04D MR(14) $04E MR(15) $04F
Stack area Level Level Level Level Level Level Level Level Level Level Level Level Level Level Level 1023 Level
$3C0
1020 1021 1022
PC13
PC11 $3FC $3FD $3FE $3FF
$3FF
1023
PC13 -PC0 Program counter Status flag Carry flag
Figure Configuration Memory Registers Stack Area, Stack Position
Bank register $03F) Initial value Read/Write name
used used used
Bank area selection Bank selected Bank selected
Note: After reset, value bank register therefore bank selected.
Figure Bank Register
HD404849 Series
Functional Description
Registers Flags nine registers flags operations. They shown figure described below.
Accumulator Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, register Initial value: Undefined, (SPY) Carry Initial value: Undefined, (CA) Status Program counter Initial value: Stack pointer Initial value: $3FF, Initial value: (PC) (SP) (ST) (SPX)
Figure Registers Flags Accumulator (A), Register (B): Four-bit registers used hold results from arithmetic logic unit (ALU) transfer data between memory, I/O, other registers. Register (W), Register (X), Register (Y): Two-bit four-bit registers used indirect addressing. register also used D-port addressing.
HD404849 Series
Register (SPX), Register (SPY): Four-bit registers used supplement registers. Carry Flag (CA): One-bit flag that stores overflow generated arithmetic operation. affected SEC, REC, ROTL, ROTR instructions. carry pushed onto stack during interrupt popped from stack RTNI instruction-but instruction. Status Flag (ST): One-bit flag that latches overflow generated arithmetic compare instruction, not-zero decision from ALU, result test. used branch condition BRL, CAL, CALL instructions. contents remain unchanged until next arithmetic, compare, test instruction executed, become after BRL, CAL, CALL instruction read, regardless whether instruction executed skipped. contents pushed onto stack during interrupt popped from stack RTNI instruction-but instruction. Program Counter (PC): 14-bit binary counter that points address instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains address stack area used next. initialized $3FF reset. decremented when data pushed onto stack, incremented when data popped from stack. four bits fixed 1111, stack used levels. initialized $3FF another way: resetting with REMD instruction. Reset reset inputting low-level voltage RESET pin. power-on when stop mode cancelled, RESET must least enable oscillator stabilize. During operation, RESET must least instruction cycles. Initial values after reset listed table
HD404849 Series
Table Initial Values After Reset
Item Program counter Status flag Stack pointer Interrupt flags/mask Interrupt enable flag Interrupt request flag Interrupt mask Port data register Data control register Abbr. (PC) (ST) (SP) (IE) (IF) (IM) (PDR) (DCD0, DCD1) (DCD2) (DCR0- DCR3, DCR6, DCR7) Port mode register Port mode register Port mode register bits Detection edge select register Detection edge select register Timer/ counters, serial interface Timer mode register (PMRA) (PMRB) (PMRC3, PMRC1, PMRC0) (ESR1) (ESR2) (TMA) Initial Value $0000 $3FF Contents Indicates program execution point from start address area Enables conditional branching Stack level Inhibits interrupts Indicates there interrupt request Prevents (masks) interrupt requests
bits Enables output level bits Turns output buffer high impedance) bits
Refer description port mode register Refer description port mode register Refer description port mode register
0000 0000
Disables edge detection Disables edge detection Refer description timer mode register
Timer mode register (TMB1) Timer mode register (TMB2) Timer mode register (TMC1) Timer mode register (TMC2) Timer mode register (TMD1) Timer mode register (TMD2)
0000 0000 0000 0000
Refer description timer mode register Refer description timer mode register Refer description timer mode register Refer description timer mode register Refer description timer mode register Refer description timer mode register
HD404849 Series
Item Timer/ counters, serial interface Serial mode register Serial mode register Prescaler Prescaler Timer counter Timer counter Timer counter Timer counter Timer write register Timer write register Timer write register Octal counter mode register data register control register mode register output register registers speed flag (AMR) (ADRU, ADRL) (LCR) (LMR) (LOR3) (LSON) Abbr. (SMRA) (SMRB) (PSS) (PSW) (TCA) (TCB) (TCC) (TCD) (TWBU, TWBL) (TWCU, TWCL) (TWDU, TWDL) Initial Value 0000 $000 0000 0000 0000 0000 Refer description operating modes Refer description timer Refer description timer Refer description operating modes, I/O, serial interface Refer description operating modes oscillation circuits Refer description memory Contents Refer description serial mode register Refer description serial mode register Refer description mode register Refer description mode register Refer description control register Refer description duty-cycle/clock control register Sets R-port/LCD segment pins port mode Refer description operating modes Refer description timer Refer description converter
Watchdog timer flag (WDON) start flag current flag Direct transfer flag Input capture status flag (ADSF) (IAOF) (DTON) (ICSF)
Input capture error flag (ICEF) Others Miscellaneous register System clock select register bits Bank register (MIS) (SSR2, SSR1)
Notes: statuses other registers flags after reset shown following table. indicates invalid value. indicates that does exist.
HD404849 Series
Status After Status After Status After Cancellation Stop Cancellation Stop Other Types Modeby STOPC Input Mode Reset Reset Pre-stop-mode values guaranteed; values must initialized program Pre-MCU-reset values guaranteed; values must initialized program
Item Carry flag
Abbr. (CA)
Accumulator register register Y/SPX register Y/SPY register Serial data register data register enable flag Port mode register System clock select register
(Y/SPX) (Y/SPY) (SRL, SRU) (ADRU, Pre-stop-mode values retained (RAME) (PMRC2) (SSR3) Pre-stop-mode values retained
HD404849 Series
Interrupts interrupt sources: four external signals (INT0, INT1, INT3), four timer/counters (timers serial interface, converter. interrupt request flag (IF), interrupt mask (IM), vector address provided each interrupt source, interrupt enable flag (IE) controls entire interrupt process. Some vector addresses shared different interrupts. They timer timer converter serial interface interrupts. type request that occurred must checked beginning interrupt processing. Interrupt Control Bits Interrupt Processing: Locations $000 $003 $022 $023 reserved interrupt control bits which accessed manipulation instructions. interrupt request flag (IF) cannot software. reset initializes interrupt enable flag (IE) interrupt mask (IM) block diagram interrupt control circuit shown figure interrupt priorities vector addresses listed table interrupt processing conditions interrupt sources listed table interrupt request occurs when that point, interrupt processed. priority programmable logic array (PLA) generates vector address assigned that interrupt source. interrupt processing sequence shown figure interrupt processing flowchart shown figure After interrupt acknowledged, previous instruction completed first cycle. reset second cycle, carry, status, program counter values pushed onto stack during second third cycles, program jumps vector address execute instruction third cycle. Program JMPL instruction each vector address, branch program start address interrupt program, reset software instruction within interrupt program. Table Vector Addresses Interrupt Priorities
Reset/Interrupt RESET, STOPC* INT0 INT1 Timer Timer INT2 Timer INT3 Timer A/D, Serial Priority Vector Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E
Note: STOPC interrupt request valid only stop mode.
HD404849 Series
Interrupt enable flag 000,0 000,2 000,3 Priority control logic INT1 interrupt 001,0 001,1 001,2 IFTA 001,3 IMTA Timer interrupt 002,0 IFTB 002,1 IMTB Timer interrupt 002,2 IFTC 002,3 IMTC Timer interrupt 003,0 IFTD 003,1 IMTD interrupt 003,2 IFAD 003,3 IMAD Note: $m,n address number 023,2 Serial interrupt 023,3 022,0 INT2 interrupt 022,1 022,2 INT3 interrupt 022,3 Sequence control Push PC/CA/ST Reset Jump vector address
INT0 interrupt
Vector address
Timer interrupt
Figure Interrupt Control Circuit
HD404849 Series
Table Interrupt Processing Activation Conditions
Interrupt Source Interrupt Control IFTA IMTA INT0 INT1 Timer Timer INT2 Timer INT3 Timer Serial
IFTB IMTB IFTC IMTC IFTD IMTD IFAD IMAD
Note: Bits marked either Their values have effect operation.
Instruction cycles
Instruction execution*
Interrupt acceptance
Stacking reset Vector address generation
Execution JMPL instruction vector address
Note: stack accessed reset after instruction executed, even two-cycle instruction.
Execution instruction start address interrupt routine
Figure Interrupt Processing Sequence
HD404849 Series
Power
RESET
Interrupt request?
Reset
Execute instruction
Accept interrupt
(PC)
Stack (PC) Stack (CA) Stack (ST)
$0002
INT0 interrupt?
$0004
INT1 interrupt?
$0006
Timer interrupt?
$0008
Timer B/INT interrupt?
$000A
Timer C/INT interrupt?
$000C
Timer interrupt?
$000E
(A/D, serial interrupt)
Figure Interrupt Processing Flowchart
HD404849 Series
Interrupt Enable Flag (IE: $000, Controls entire interrupt process. reset interrupt processing RTNI instruction, listed table Table Interrupt Enable Flag (IE: $000,
Interrupt Enabled/Disabled Disabled Enabled
External Interrupts (INT0, INT1, INT2, INT3): There four external interrupt signals. External Interrupt Request Flags (IF0-IF3: $000, $001, $022): when signals input INT0 INT1 falling, when signals input INT2 INT3 rising falling, listed table INT2 INT3 interrupt edges selected detection edge select registers (ESR1, ESR2: $026, $027) shown figures Table External Interrupt Request Flags (IF0-IF3: $000, $001, $022)
IF0-IF3 Interrupt Request
Detection edge selection register (ESR1: $026) Initial value Read/Write name ESR13 ESR12 ESR11 ESR10
ESR13
ESR12
INT3 detection edge detection Falling-edge detection Rising-edge detection Double-edge detection
ESR11
ESR10
INT2 detection edge detection Falling-edge detection Rising-edge detection Double-edge detection*
Note: Both falling rising edges detected.
Figure Detection Edge Selection Register (ESR1)
HD404849 Series
Detection edge selection register (ESR2: $027) Initial value Read/Write name ESR23
ESR22 used used
ESR23
ESR22
EVND detection edge detection Falling-edge detection Rising-edge detection Double-edge detection
Note: Both falling rising edges detected.
Figure Detection Edge Selection Register (ESR2) External Interrupt Masks (IM0-IM3: $000, $001, $022): Prevent (mask) interrupt requests caused corresponding external interrupt request flags, listed table Table External Interrupt Masks (IM0-IM3: $000, $001, $022)
IM0-IM3 Interrupt Request Enabled Disabled (masked)
Timer Interrupt Request Flag (IFTA: $001, overflow output from timer listed table Table Timer Interrupt Request Flag (IFTA: $001,
IFTA Interrupt Request
Timer Interrupt Mask (IMTA: $001, Prevents (masks) interrupt request caused timer interrupt request flag, listed table
HD404849 Series
Table Timer Interrupt Mask (IMTA: $001,
IMTA Interrupt Request Enabled Disabled (masked)
Timer Interrupt Request Flag (IFTB: $002, overflow output from timer listed table Table Timer Interrupt Request Flag (IFTB: $002,
IFTB Interrupt Request
Timer Interrupt Mask (IMTB: $002, Prevents (masks) interrupt request caused timer interrupt request flag, listed table Table Timer Interrupt Mask (IMTB: $002,
IMTB Interrupt Request Enabled Disabled (masked)
Timer Interrupt Request Flag (IFTC: $002, overflow output from timer listed table Table Timer Interrupt Request Flag (IFTC: $002,
IFTC Interrupt Request
Timer Interrupt Mask (IMTC: $002, Prevents (masks) interrupt request caused timer interrupt request flag, listed table Table Timer Interrupt Mask (IMTC: $002,
IMTC Interrupt Request Enabled Disabled (masked)
HD404849 Series
Timer Interrupt Request Flag (IFTD: $003, overflow output from timer rising falling edge signals input EVND when input capture function used, listed table Table Timer Interrupt Request Flag (IFTD: $003,
IFTD Interrupt Request
Timer Interrupt Mask (IMTD: $003, Prevents (masks) interrupt request caused timer interrupt request flag, listed table Table Timer Interrupt Mask (IMTD: $003,
IMTD Interrupt Request Enabled Disabled (masked)
Serial Interrupt Request Flag (IFS: $023, when data transfer completed when data transfer suspended, listed table Table Serial Interrupt Request Flag (IFS: $023,
Interrupt Request
Serial Interrupt Mask (IMS: $023, Prevents (masks) interrupt request caused serial interrupt request flag, listed table Table Serial Interrupt Mask (IMS: $023,
Interrupt Request Enabled Disabled (masked)
Interrupt Request Flag (IFAD: $003, completion conversion, listed table
HD404849 Series
Table Interrupt Request Flag (IFAD: $003,
IFAD Interrupt Request
Interrupt Mask (IMAD: $003, Prevents (masks) interrupt request caused interrupt request flag, listed table Table Interrupt Mask (IMAD: $003,
IMAD Interrupt Request Enabled Disabled (masked)
HD404849 Series
Operating Modes
five operating modes shown table operations each mode listed tables Transitions between operating modes shown figure Table Operating Modes Clock Status
Mode Name Active Activation method Standby Stop STOP instruction when TMA3 Watch STOP instruction when TMA3 Subactive*2 INT0 timer interrupt request from watch mode
Reset instruction cancellation, interrupt request STOPC cancellation stop mode, STOP/SBY instruction subactive mode (when direct transfer selected) System oscillator RESET input, interrupt request
Status
Stopped RESET input, STOPC input stop mode
Stopped
Stopped
Subsystem oscillator Cancellation method RESET input, STOP/SBY instruction
RESET input RESET input, INT0 timer STOP/SBY instruction interrupt request
Notes: implies operation. Operating stopping oscillator selected setting system clock select register (SSR: $029). Subactive mode optional function; specify function option list.
HD404849 Series
Table Operations Low-Power Dissipation Modes
Function Timer Timer Timer Timer Serial Stop Mode Reset Retained Reset Reset Reset Reset Reset Reset Reset Reset*
Watch Mode Retained Retained Stopped Stopped Stopped Stopped* Stopped
Standby Mode Retained Retained Retained
Subactive Mode*2 Stopped
Retained
Notes: implies operation. Output pins high impedance. Subactive mode optional function specified function option list. Transmission/reception activated clock input external clock mode. However, interrupts stop. When 32-kHz clock source used.
Table Status Low-Power Dissipation Modes
Output Standby Mode, Watch Mode D0-D D10, R0-R3, Retained Stop Mode High impedance Input Active Mode, Subactive Mode Input enabled Input enabled Input enabled
Retained output peripheral High impedance functions
HD404849 Series
Reset RESET input watchdog timer
Stop mode
(TMA3 SSR3
RAME RESET1
RAME RESET2
STOPC
STOPC
Active mode STOP fOSC: CPU: CLK: PER: Oscillate Oscillate Stop fcyc fcyc Interrupt fOSC: CPU: CLK: PER: Oscillate Oscillate fcyc fcyc fcyc
(TMA3
fOSC: CPU: CLK: PER:
Stop Oscillate Stop Stop Stop
Standby mode
(TMA3 SSR3
STOP
fOSC: CPU: CLK: PER:
Stop Stop Stop Stop Stop
Watch mode
(TMA3 (TMA3 LSON
fOSC: CPU: CLK: PER:
Oscillate Oscillate Stop fcyc
Interrupt
fOSC: CPU: CLK: PER:
Oscillate Oscillate fcyc fcyc
STOP INT0, timer
fOSC: CPU: CLK: PER:
Stop Oscillate Stop Stop
Main oscillation frequency Suboscillation frequency time-base fOSC/4 fcyc: fSUB: fX/8 fX/4 (software selectable) fX/8 CPU: System clock CLK: Clock time-base PER: Clock other peripheral functions LSON: speed flag DTON: Direct transfer flag
fOSC:
Subactive mode fOSC: CPU: CLK: PER: Stop Oscillate fSUB fSUB
STOP
(TMA3 LSON
INT0, timer
fOSC: CPU: CLK: PER:
Stop Oscillate Stop Stop
Notes:
Interrupt source STOP/SBY (DTON LSON STOP/SBY (DTON LSON STOP/SBY (DTON Don't care, LSON
Figure Status Transitions
HD404849 Series
Active Mode: functions operate according clock generated system oscillator OSC1 OSC2. Standby Mode: standby mode, oscillators continue operate, clocks related instruction execution stop. Therefore, operation stops, register contents retained, port status, when output, maintained. Peripheral functions such interrupts, timers, serial interface continue operate. power dissipation this mode lower than active mode because stops. enters standby mode when instruction executed active mode. Standby mode terminated RESET input interrupt request. terminated RESET input, reset well. After interrupt request, enters active mode executes next instruction after instruction. interrupt enable flag interrupt then processed; interrupt request left pending normal instruction execution continues. flowchart operation standby mode shown figure
HD404849 Series
Stop Oscillator: Stop Suboscillator: Active/Stop Peripheral clocks: Stop other clocks: Stop Standby Watch
Oscillator: Active Peripheral clocks: Active other clocks: Stop
Oscillator: Stop Suboscillator: Active Peripheral clocks: Stop other clocks: Stop
RESET
RESET
STOPC
IFTA IMTA
IFTB IMTB
IFTC IMTC
RAME
RAME
IFTD IMTD
IFAD IMAD
(SBY only) (SBY only) (SBY only) (SBY only)
(SBY only)
Restart processor clocks
Restart processor clocks Execute next instruction
Reset
Execute next instruction
Accept interrupt
Figure Operation Flowchart Stop Mode: stop mode, operations stop data retained. Therefore, power dissipation this mode least modes. OSC1 oscillator stops. oscillator selected operate setting system clock select register (SSR: $029; operating: SSR3 stop: SSR3 (figure 26). enters stop mode STOP instruction executed active mode when timer mode register (TMA: $008) (TMA3 (figure 41). Stop mode terminated RESET input STOPC input shown figure RESET STOPC must applied least stabilize oscillation (refer Characteristics section). When restarts after stop mode cancelled, contents before entering stop mode retained,
HD404849 Series
accuracy contents accumulator, register, register, X/SPX register, Y/SPY register, carry flag, serial data register cannot guaranteed.
Stop mode Oscillator Internal clock RESET STOPC tres STOP instruction execution tres (stabilization period)
Figure Timing Stop Mode Cancellation
Watch Mode: watch mode, clock function (timer using oscillator function operate, other function operations stop. Therefore, power dissipation this mode second least stop mode, this mode convenient when only clock display used. this mode, OSC1 OSC2 oscillator stops, oscillator operates. enters watch mode STOP instruction executed active mode when TMA3 STOP instruction executed subactive mode.
Watch mode terminated RESET input timer-A/INT0 interrupt request. details RESET input, refer Stop Mode section. When terminated timer-A/INT0 interrupt request, enters active mode LSON subactive mode LSON After interrupt request generated, time required enter active mode timer interrupt, (where tRC) INT0 interrupt, shown figures Operation during mode transition same that standby mode cancellation (figure 15).
HD404849 Series
Oscillation stabilization period Active mode Watch mode Active mode
Interrupt strobe INT0 Interrupt request generation
(During transition from watch mode active mode only) Interrupt frame length Oscillation stabilization period
Figure Interrupt Frame
Miscellaneous register (MIS: $00C) Initial value Read/Write name MIS3 MIS3 MIS2 MIS2 MIS1 MIS1 MIS0 MIS0 Oscillation circuit conditions External clock input
Buffer control. Refer figure
0.24414 0.12207 0.24414
15.625 7.8125 62.5 used 31.25
Ceramic oscillator Crystal oscillator
Notes: values applied when 32.768-kHz crystal oscillator used. value applied only when direct transfer operation used.
Figure Miscellaneous Register (MIS) Subactive Mode: OSC1 OSC2 oscillator stops operates with clock generated oscillator. this mode, functions except conversion operate. However, because operating clock slows down, power dissipation reduced, next least watch mode.
HD404849 Series
instruction execution speed selected setting (SSR2) system clock select register (SSR: $029). Note that SSR2 value must changed active mode. value changed subactive mode, malfunction. When STOP instruction executed subactive mode, enters either watch active mode, depending statuses speed flag (LSON: $020, direct transfer flag (DTON: $020, Interrupt Frame: watch subactive modes, applied timer theINT0 circuit. Prescaler timer operate time-base generate timing clock interrupt frame. Three interrupt frame lengths selected setting miscellaneous register (MIS: $00C) (figure 18). watch subactive modes, timer-A/INT0 interrupt generated synchronously with interrupt frame. interrupt request generated synchronously with interrupt strobe except during transition active mode. falling edge INT0 signal input asynchronously with interrupt frame timing, regarded input synchronously with second interrupt strobe clock after falling edge. overflow interrupt request timer generated synchronously with interrupt strobe. Direct Transition from Subactive Mode Active Mode: Available controlling direct transfer flag (DTON: $020, speed flag (LSON: $020, procedures described below: LSON DTON subactive mode. Execute STOP instruction. automatically enters active mode from subactive mode after waiting internal processing time oscillation stabilization time (figure 19). Notes: DTON flag ($020, only subactive mode. always reset active mode. transition time (TD) from subactive mode active mode:
STOP/SBY instruction execution Subactive mode (Set LSON DTON Interrupt strobe Direct transfer completion timing Interrupt frame length Oscillation stabilization period internal processing period Oscillation stabilization time
Active mode
Figure Direct Transition Timing
HD404849 Series
Stop Mode Cancellation STOPC enters active mode from stop mode inputting STOPC RESET. either case, starts instruction execution from starting address (address program. However, value enable flag (RAME: $021, differs between cancellation STOPC RESET. When stop mode cancelled RESET, RAME when cancelled STOPC, RAME RESET cancel modes, STOPC valid only stop mode; STOPC input ignored other modes. Therefore, when program needs confirm that stop mode been cancelled STOPC (for example, when contents before entering stop mode used after transition active mode), execute TEST instruction enable flag (RAME) beginning program. Operation Sequence: operates sequence shown figures reset asynchronous RESET input, regardless status. low-power mode operation sequence shown figure With flag cleared interrupt flag together with interrupt mask cleared, STOP/SBY instruction executed, instruction cancelled (regarded NOP) following instruction executed. Before executing STOP/SBY instruction, make sure interrupt flags cleared interrupts masked.
Power
RESET RAME
operation cycle
Reset
Figure Operating Sequence (Power
HD404849 Series
operation cycle
Instruction execution
SBY/STOP instruction?
Stack (PC), (CA), (ST)
Low-power mode operation cycle
Next location
Vector address
Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag
Figure Operating Sequence (MCU Operation Cycle)
HD404849 Series
Low-power mode operation cycle
Standby/watch mode
Stop mode
STOPC
Hardware execution Hardware execution
RAME
Next Iocation
Next Iocation
Reset
Instruction execution
operation cycle operation, refer figure
Figure Operating Sequence (Low-Power Mode Operation) Notes Use: When watch mode subactive mode, high level period before falling edge shorter than interrupt frame, will detected. Also, level period after falling edge shorter than interrupt frame, will detected. Edge detection shown figure level signal sampled sampling clock. When this sampled value changes from high low, falling edge detected.
HD404849 Series
figure level INT0 signal sampled interrupt frame. sampled value point also point Therefore, falling edge will detected. (b), sampled value high point also high point falling edge will detected this case either. When watch mode subactive mode, keep high level level period longer than interrupt frame.
INT0
Sampling High
Figure Edge Detection
INT0
INT0
Interrupt frame
Interrupt frame
High
High
High level period
level period
Figure Sampling Example
HD404849 Series
Internal Oscillator Circuit
block diagram clock generation circuit shown figure shown table ceramic crystal oscillator connected OSC1 OSC2, 32.768-kHz oscillator connected system oscillator also operated external clock. (SSR1) system clock select register (SSR: $029) must according quency oscillator connected OSC1 OSC2 (figure 26). Note: system clock select register (SSR: $029) setting does match oscillator frequency, subsystems using 32.768-kHz oscillation will malfunction.
LSON
OSC2 OSC1
System fOSC division oscillator circuit
fcyc tcyc
Timing generator circuit
System clock selection
with ROM, RAM, registers, flags,
Peripheral function interrupt
Subsystem oscillator
fSUB Timing division tsubcyc generator circuit circuit TMA3
division circuit
tWcyc
Timing generator circuit
Time-base clock selection
Time-base interrupt
Note: division ratio selected setting system clock select register (SSR: $029).
Figure Clock Generation Circuit
HD404849 Series
System clock select register (SSR: $029) Initial value Read/Write name SSR3* SSR2 SSR1 used
SSR3
32-kHz oscillation stop Oscillation operates stop mode Oscillation stops stop mode
SSR1
System oscillation frequency selection
SSR2
32-kHz oscillation division ratio selection fSUB fX/8 fSUB fX/4
Note: SSR3 cleared only RESET input. SSR3 will cleared STOPC input during stop mode, will retain value. SSR3 will also cleared upon entering stop mode.
Figure System Clock Select Register
HD404849 Series
RESET
OSC2
OSC1
TEST
Figure Typical Layout Crystal Ceramic Oscillators
HD404849 Series
Table Oscillator Circuit Examples
Circuit Configuration External clock operation
External oscillator
Circuit Constants
Open
Ceramic oscillator (OSC1,
OSC1 Ceramic oscillator OSC2
Ceramic oscillator: CSA4.00MG (Murata)
Crystal oscillator (OSC1,OSC2)
OSC1 Crystal oscillator OSC2 OSC1 OSC2
Equivalent circuit crystal oscillator shown left.
Crystal oscillator (X1,
Crystal oscillator
Crystal: 32.768 kHz: MX38T (Nippon Denpa)
Notes: Circuit constants differ different types crystal oscillators ceramic oscillators, with stray capacitance board, consult manufacturer oscillator determine circuit parameters. wiring between OSC1 pins pins) other elements should short possible, must cross other wiring. Refer figure using 32.768-kHz crystal oscillator, leave open.
HD404849 Series
Input/Output
input/output pins (D0-D R0-R3, input pins (D10 features described below. Nine pins 0-D8) high-current input/output pins. D10, D11, R00-R0 R1-R3, input/output pins multiplexed with peripheral function pins such timers serial interface. these pins, peripheral function setting done prior port setting. Therefore, when peripheral function selected pin, function input/output selection automatically switched according setting. Input output selection input/output pins port peripheral function selection multiplexed pins software. Peripheral function output pins CMOS output pins. Only R23/SO NMOS opendrain output software. stop mode, reset, therefore peripheral function selection cancelled. data control register (DCD, DCR) also reset, input/output pins high-impedance state. Each input/output built-in pull-up MOS, which individually turned software. buffer configuration shown figure programmable circuits listed table circuit types shown table Table Programmable Circuits
MIS3 (bit MIS) DCD, CMOS buffer PMOS NMOS Pull-up
Note: indicates status.
HD404849 Series
Pull-up MIS3 PMOS DCD,
NMOS input Input control signal
Figure Buffer Configuration
HD404849 Series
Table Circuit Configurations Pins
Type Input/output pins Circuit
Pull-up control signal Buffer control signal Output data Input data Input control signal Pull-up control signal Buffer control signal MIS3 DCD,
Pins D0-D 0-R0 0-R1 0-R2 0-R3 0-R6 0-R7
MIS3 MIS2
Output data Input data Input control signal
Input pins
Input data Input control signal
D10,
Peripheral Input/ function pins output pins
Pull-up control signal
MIS3
Output data Input data
Output pins
Pull-up control signal PMOS control signal Output data
MIS3 MIS2
Pull-up control signal
MIS3
TOB, TOC,
Output data TOB, TOC,
HD404849 Series
Type Peripheral Input function pins pins
MIS3 etc.
Circuit
Input data INT0, STOPC
Pins INT0, STOPC INT1, INT2, INT3, EVNB, EVND
0-AN
input
Input control MIS3 input Input control
4-AN
Note: reset stop mode, peripheral function selections cancelled. control register reset, input/output pins enter high-impedance state.
Port: Consist nine input/output pins input pins addressed bit. 0-D8 high-current pins, input-only pins. Pins SEDD instructions, reset REDD instructions. Output data stored port data register (PDR) each pin. pins port tested instructions. on/off statuses output buffers controlled port data control registers (DCD0-DCD2: $02C-$02E) that mapped memory addresses (figure 29). Pins multiplexed with peripheral function pins STOPC INT0, respectively. peripheral function modes these pins selected bits (PMRC2, PMRC3) port mode register (PMRC: $025) (figure 34). Ports: input/output pins addressed 4-bit units. Data input these ports instructions, output from them instructions. Output data stored port data register (PDR) each pin. on/off statuses output buffers ports controlled port data control registers (DCR0-DCR3, DCR6, DCR7: $030-$033, $036, $037) that mapped memory addresses (figure 29).
HD404849 Series
Pins R00-R02 multiplexed with peripheral pins INT1-INT respectively. peripheral function modes these pins selected bits (PMRB0-PMRB2) port mode register (PMRB: $024) (figure 30). Pins R10-R12 multiplexed with peripheral pins TOB, TOC, TOD, respectively. peripheral function modes these pins selected bits (TMB20, TMB21) timer mode register (TMB2: $013), bits (TMC20-TMC22) timer mode register (TMC2: $014), bits (TMD20-TMD23) timer mode register (TMD2: $015) (figures 33). Pins multiplexed with peripheral pins EVNB EVND, respectively. peripheral function modes these pins selected bits (PMRC0, PMRC1) port mode register (PMRC: $025) (figure 34). Pins R21-R23 multiplexed with peripheral pins SCK, respectively. peripheral function modes these pins selected (SMRA3) serial mode register (SMRA: $005), bits (PMRA0, PMRA1) port mode register (PMRA: $004), shown figures Ports multiplexed with segment pins SEG13-SEG20, respectively. function modes these pins selected 4-pin units setting output register (LOR3: $01F) (figure 37).
HD404849 Series
Data control register DCD0, DCD1 Initial value Read/Write name DCD2 Initial value Read/Write name (DCD0 DCD2: $02C $02E) (DCR0 DCR7: $030 $037)
DCD03, DCD02, DCD01, DCD00, DCD13 DCD12 DCD11 DCD10
used used used DCD20
DCR0 DCR3, DCR6, DCR7 Initial value Read/Write name
DCR03- DCR02- DCR01- DCR00- DCR33 DCR32 DCR31 DCR30 DCR63- DCR62- DCR61- DCR60- DCR73 DCR72 DCR71 DCR70 CMOS Buffer On/Off Selection (high-impedance)
Bits
Correspondence between ports DCD/DCR bits Register Name DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR6 DCR7
Figure Data Control Registers (DCD, DCR)
HD404849 Series
Port mode register (PMRB: $024) Initial value Read/Write name PMRB2
used PMRB2 PMRB1 PMRB0 R02/INT3 mode selection INT3 PMRB0 PMRB1 R00/INT1 mode selection INT1 R01/INT2 mode selection INT2
Figure Port Mode Register (PMRB)
Timer mode register (TMC2: $014) Initial value Read/Write name TMC21 TMC21 TMC20 TMC20 output R11/TOC mode selection port Toggle output output output Inhibited
used TMC22 TMC22
Figure Timer Mode Register (TMC2)
HD404849 Series
Timer mode register (TMB2: $013) Initial value Read/Write name TMB20
used used TMB21
TMB21
TMB20
R10/TOB mode selection port Toggle output output output
Figure Timer Mode Register (TMB2)
Timer mode register (TMD2: $015) Initial value Read/Write name TMD23 TMD23 TMD22 TMD22 TMD21 TMD21 TMD20 TMD20 Don't care Don't care Don't care output Input capture (R12 port) R12/TOD mode selection port Toggle output output output Inhibited
Figure Timer Mode Register (TMD2)
HD404849 Series
Port mode register (PMRC: $025) Initial value Read/Write name PMRC3 PMRC2 PMRC3 PMRC0 PMRC1 PMRC0 R20/EVND mode selection EVND R13/EVNB mode selection EVNB
PMRC2 PMRC1
D11/INT0 mode selection INT0 D10/STOPC mode selection STOPC
Note: PMRC2 reset only RESET input. When STOPC input stop mode, PMRC2 reset retains value.
Figure Port Mode Register (PMRC)
Serial mode register (SMRA: $005) Initial value Read/Write name SMRA3
SMRA2 SMRA1 SMRA0 Prescaler division ratio ÷2048 ÷512 ÷128
SMRA3
R21/SCK mode selection
SMRA2
SMRA1 SMRA0
Output Output Output Output Output Output Output Input
Clock source Prescaler Prescaler Prescaler Prescaler Prescaler Prescaler System clock External clock
Figure Serial Mode Register (SMRA)
HD404849 Series
Port mode register (PMRA: $004) Initial value Read/Write name PMRA1
used used PMRA1 PMRA0 R22/SI mode selection PMRA0 R23/SO mode selection
Figure Port Mode Register (PMRA)
output register (LOR3: $01F) Initial value Read/Write name LOR32
used LOR32
LOR31 used LOR31 R6/SEG13-SEG16 mode selection SEG13-SEG16
R7/SEG17-SEG20 mode selection SEG17-SEG20
Figure Output Register (LOR3) Pull-Up Transistor Control: program-controlled pull-up transistor provided each input/output other than input-only pins on/off status these transistors controlled (MIS3) miscellaneous register (MIS: $00C), on/off status individual transistor also controlled port data register (PDR) corresponding pin-enabling on/off control that alone (table figure 38). on/off status each transistor peripheral function mode each independently.
HD404849 Series
Miscellaneous register (MIS: $00C) Initial value Read/Write name MIS3 MIS2 MIS1 MIS0 CMOS buffer on/off selection R23/SO
MIS3
Pull-up on/off selection
MIS2
MIS1
MIS0
selection. Refer figure operation modes section.
Figure Miscellaneous Register (MIS) Deal with Unused Pins: pins that needed user system (floating) must connected prevent malfunctions noise. These pins must either pulled their pull-up transistors resistors about
HD404849 Series
Prescalers
prescalers, prescaler operating conditions listed table prescalers output supply shown figure timer input clocks except external events, serial transmit clock except external clock, controller/driver operating clock selected from prescaler outputs, depending corresponding mode registers. Prescaler Operation Prescaler 11-bit counter that inputs system clock signal. After being reset $000 reset, prescaler divides system clock. Prescaler keeps counting, except watch subactive modes reset. Prescaler Five-bit counter that inputs divided input clock signal (32-kHz crystal oscillation). After being reset reset, prescaler divides input clock. Prescaler reset software. Table Prescaler Operating Conditions
Prescaler Prescaler Input Clock System clock active standby mode), subsystem clock subactive mode) 32-kHz crystal oscillation Reset Conditions reset Stop Conditions reset, stop mode, watch mode reset, stop mode
Prescaler
reset, software
Subsystem clock fX/8 Prescaler Timer Timer Timer System clock Clock selector Prescaler Timer Serial interface
fX/4 fX/8
Figure Prescaler Output Supply
HD404849 Series
Timers
four timer/counters Timer Timer Timer Timer Free-running timer Multifunction timer Multifunction timer Multifunction timer
Timer 8-bit free-running timer. Timers 8-bit multifunction timers, whose functions listed table operating modes selected software. Table Timer Functions
Functions Clock source Prescaler Prescaler External event Timer functions Free-running Time-base Event counter Reload Watchdog Input capture Timer outputs Toggle output output Note: implies available. Timer Available Available Available Available Timer Available Available Available Available Available Available Available Available Timer Available Available Available Available Available Available Available Available Timer Available Available Available Available Available Available Available Available Available Available
Timer Timer Functions: Timer following functions. Free-running timer Clock time-base block diagram timer shown figure
HD404849 Series
32.768-kHz oscillator twcyc Selector Internal data Selector Clock Timer counter (TCA) Overflow twcyc Prescaler (PSW)
Timer interrupt request flag (IFTA)
Selector
1024 2048
System clock
Prescaler (PSS)
Timer mode register (TMA)
Figure Block Diagram Timer Timer Operations: Free-running timer operation: input clock timer selected timer mode register (TMA: $008). Timer reset reset incremented each input clock. input clock applied timer after reached $FF, overflow generated, timer reset $00. overflow sets timer interrupt request flag (IFTA: $001, Timer continues incremented after reset $00, therefore generates regular interrupts every clocks. Clock time-base operation: Timer used clock time-base setting (TMA3) timer mode register (TMA: $008) prescaler output applied timer timer generates interrupts correct timing based 32.768-kHz crystal oscillation. this case, prescaler timer reset software. Registers Timer Operation: Timer operating modes following registers. Timer mode register (TMA: $008): Four-bit write-only register that selects timer operating mode input clock source shown figure
HD404849 Series
Timer mode register (TMA: $008) Initial value Read/Write name TMA3 TMA2 TMA1 TMA0
Source Input clock TMA3 TMA2 TMA1 TMA0 prescaler frequency Operating mode Don't care Inhibited reset 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc 32tWcyc 16tWcyc 8tWcyc 2tWcyc 1/2tWcyc Time-base mode Timer mode
Note: tWcyc 244.14 (when 32.768-kHz crystal oscillator used) Timer counter overflow output period (seconds) input clock period (seconds) 256. reset selected while operating, operation halts (power switch goes pins grounded). When connected display, reset periods must program minimum. division ratio must modified during time-base mode operation, otherwise overflow cycle error will occur.
Figure Timer Mode Register (TMA)
HD404849 Series
Timer Timer Functions: Timer following functions. Free-running/reload timer External event counter Timer output operation (toggle, outputs) block diagram timer shown figure
Timer interrupt request flag (IFTB) Timer output control logic
Timer read register (TRBU) Timer read register (TRBL) Clock Timer counter (TCB) Overflow
Timer output control
Selector
EVNB System clock
2048
Timer write register (TWBU) Timer write register (TWBL)
Prescaler (PSS) Free-running/ Reload control
Timer mode register (TMB1)
Timer mode register (TMB2)
Figure Block Diagram Timer
Internal data
HD404849 Series
Timer Operations: Free-running/reload timer operation: free-running/reload operation, input clock source, prescaler division ratio selected timer mode register (TMB1: $009). Timer initialized value timer write register (TWBL: $00A, TWBU: $00B) software incremented each clock input. input clock applied timer after reached $FF, overflow generated. this case, reload timer function enabled, timer initialized initial value timer write register free-running timer function enabled, timer initialized then incremented again. overflow sets timer interrupt request flag (IFTB: $002, IFTB reset software reset. Refer figure table details. External event counter operation: Timer used external event counter selecting external event input input clock source. this case, R13/EVNB must EVNB port mode register (PMRC: $025). Timer incremented each falling edge signals input EVNB. other operations basically same free-running/reload timer operation. Timer output operation: following three output modes selected timer setting timer mode register (TMB2: $013). Toggle output output selecting timer output mode, R10/TOB TOB. output from reset reset. Toggle output: When toggle output mode selected, output level inverted clock input after timer reached $FF. using this function reload timer function, clock signals output required frequency buzzer. output waveform shown figure (1). output: When output mode selected, output level pulled clock input after timer reached $FF. Note that this function must used only when output level high. output: When output mode selected, output level high clock input after timer reached $FF. Note that this function must used only when output level low.
HD404849 Series
Toggle output waveform (timers Free-running timer
clock cycles Reload timer
clock cycles
(256 clock cycles
(256 clock cycles
output waveform (timers TMC13 TMD13 (free-running timer setting) TMC13 TMD13 (reload timer setting) (256 Note: waveform always fixed when $FF. Input clock period counter (the clock source frequency division ratio controlled timer mode registers value timer write registers
Figure Timer Output Waveform Registers Timer Operation: using following registers, timer operation modes selected timer count read written. Timer mode register (TMB1: $009) Timer mode register (TMB2: $013) Timer write register (TWBL: $00A, TWBU: $00B) Timer read register (TRBL: $00A, TRBU: $00B) Port mode register (PMRC: $025)
Timer mode register (TMB1: $009): Four-bit write-only register that selects free-running/reload timer function, input clock source, prescaler division ratio shown figure reset reset.
HD404849 Series
Timer mode register (TMB1: $009) Initial value Read/Write name TMB13 TMB12 TMB11 TMB10 Input clock period input clock source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc R13/EVNB (external event input)
TMB13
Free-running/reload timer selection Free-running timer Reload timer
TMB12
TMB11
TMB10
Figure Timer Mode Register (TMB1) Writing this register valid from second instruction execution cycle after execution previous timer mode register write instruction. timer initialization writing timer write register (TWBL: $00A, TWBU: $00B) must programmed occur after mode change becomes valid. Timer mode register (TMB2: $013): Two-bit read/write register that selects timer output mode shown figure reset reset.
Timer mode register (TMB2: $013) Initial value Read/Write name TMB20 TMB21 TMB20 R10/TOB mode selection port Toggle output output output
used used TMB21
Figure Timer Mode Register (TMB2) Timer write register (TWBL: $00A, TWBU: $00B): Write-only register consisting lower digit (TWBL) upper digit (TWBU). lower digit reset reset, upper digit value cannot guaranteed. figures
HD404849 Series
Timer initialized writing timer write register (TWBL: $00A, TWBU: $00B). this case, lower digit (TWBL) must written first, writing only lower digit does change timer value. Timer initialized value timer write register same time upper digit (TWBU) written When timer write register written again lower digit value needs change, writing only upper digit initializes timer
Timer write register (lower digit) (TWBL: $00A) Initial value Read/Write name TWBL3 TWBL2 TWBL1 TWBL0
Figure Timer Write Register Lower Digit (TWBL)
Timer write register (upper digit) (TWBU: $00B) Initial value Read/Write name
Undefined Undefined Undefined Undefined TWBU3 TWBU2 TWBU1 TWBU0
Figure Timer Write Register Upper Digit (TWBU) Timer read register (TRBL: $00A, TRBU: $00B): Read-only register consisting lower digit (TRBL) upper digit (TRBU) that holds count timer upper digit. figures upper digit (TRBU) must read first. this time, count timer upper digit obtained, count timer lower digit latched lower digit (TRBL). After this, reading TRBL, count timer when TRBU read obtained.
Timer read register (lower digit) (TRBL: $00A) Initial value Read/Write name
Undefined Undefined Undefined Undefined TRBL3 TRBL2 TRBL1 TRBL0
Figure Timer Read Register Lower Digit (TRBL)
HD404849 Series
Timer read register (upper digit) (TRBU: $00B) Initial value Read/Write name
Undefined Undefined Undefined Undefined TRBU3 TRBU2 TRBU1 TRBU0
Figure Timer Read Register Upper Digit (TRBU) Port mode register (PMRC: $025): Write-only register that selects R13/EVNB function shown figure reset reset.
Port mode register (PMRC: $025) Initial value Read/Write name PMRC3 PMRC2 PMRC3
PMRC2 PMRC1 PMRC0 PMRC1 PMRC0 R20/EVND mode selection EVND R13/EVNB mode selection EVNB
D11/INT0 mode selection INT0 D10/STOPC mode selection STOPC
Figure Port Mode Register (PMRC) Timer Timer Functions: Timer following functions. Free-running/reload timer Watchdog timer Timer output operation (toggle, outputs) block diagram timer shown figure
HD404849 Series
System reset signal Watchdog flag (WDON) Watchdog timer control logic Timer interrupt request flag (IFTC)
Timer output control logic Timer read register (TRCU) Timer output control Timer read register (TRCL) Clock Timer counter (TCC) Overflow
Selector ÷128 ÷512 ÷1024 ÷2048
Timer write register (TWCU) Free-running /Reload control Timer mode register (TMC1) Timer write register (TWCL)
System clock
Prescaler (PSS)
Timer mode register (TMC2)
Figure Block Diagram Timer
Internal data
HD404849 Series
Timer Operations: Free-running/reload timer operation: free-running/reload operation, input clock source, prescaler division ratio selected timer mode register (TMC1: $00D). Timer initialized value timer write register (TWCL: $00E, TWCU: $00F) software incremented each clock input. input clock applied timer after reached $FF, overflow generated. this case, reload timer function enabled, timer initialized initial value timer write register free-running timer function enabled, timer initialized then incremented again. overflow sets timer interrupt request flag (IFTC: $002, IFTC reset software reset. Refer figure table details. Watchdog timer operation: Timer used watchdog timer detecting out-of-control program routines setting watchdog flag (WDON: $020, program routine runs control overflow generated, reset. Program runaway controlled initializing timer software before reaches $FF. Timer output operation: following four output modes selected timer setting timer mode register (TMC2: $014). Toggle output output output selecting timer output mode, R11/TOC TOC. output from reset reset. Toggle output: operation basically same that timer-B's toggle output. output: operation basically same that timer-B's output. output: operation basically same that timer-B's output. output: When output mode selected, timer provides variable-duty pulse output function. output waveform differs depending contents timer mode register (TMC1: $00D) timer write register (TWCL: $00E, TWCU: $00F). output waveform shown figure (2). Registers Timer Operation: using following registers, timer operation modes selected timer count read written. Timer mode register (TMC1: $00D) Timer mode register (TMC2: $014) Timer write register (TWCL: $00E, TWCU: $00F) Timer read register (TRCL: $00E, TRCU: $00F)
Timer mode register (TMC1: $00D): Four-bit write-only register that selects free-running/reload timer function, input clock source, prescaler division ratio shown figure reset reset.
HD404849 Series
Writing this register valid from second instruction execution cycle after execution previous timer mode register write instruction. timer initialization writing timer write register (TWCL: $00E, TWCU: $00F) must programmed occur after mode change becomes valid.
Timer mode register (TMC1: $00D) Initial value Read/Write name TMC13 TMC13 TMC12 TMC11 TMC10 TMC12 TMC11 TMC10 Input clock period 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc
Free-running/reload timer selection Free-running timer Reload timer
Figure Timer Mode Register (TMC1) Timer mode register (TMC2: $014): Three-bit read/write register that selects timer output mode shown figure reset reset.
HD404849 Series
Timer mode register (TMC2: $014) Initial value Read/Write name TMC21 TMC21 TMC20 TMC20 output R11/TOC mode selection port Toggle output output output Inhibited
used TMC22 TMC22
Figure Timer Mode Register (TMC2) Timer write register (TWCL: $00E, TWCU: $00F): Write-only register consisting lower digit (TWCL) upper digit (TWCU). figures operation timer write register basically same that timer write register (TWBL: $00A, TWBU: $00B).
Timer write register (lower digit) (TWCL: $00E) Initial value Read/Write name TWCL3 TWCL2 TWCL1 TWCL0
Figure Timer Write Register Lower Digit (TWCL)
Timer write register (upper digit) (TWCU: $00F) Initial value Read/Write name
Undefined Undefined Undefined Undefined TWCU3 TWCU2 TWCU1 TWCU0
Figure Timer Write Register Upper Digit (TWCU)
HD404849 Series
Timer read register (TRCL: $00E, TRCU: $00F): Read-only register consisting lower digit (TRCL) upper digit (TRCU) that holds count timer upper digit. figures operation timer read register basically same that timer read register (TRBL: $00A, TRBU: $00B).
Timer read register (lower digit) (TRCL: $00E) Initial value Read/Write name
Undefined Undefined Undefined Undefined TRCL3 TRCL2 TRCL1 TRCL0
Figure Timer Read Register Lower Digit (TRCL)
Timer read register (upper digit) (TRCU: $00F) Initial value Read/Write name
Undefined Undefined Undefined Undefined TRCU3 TRCU2 TRCU1 TRCU0
Figure Timer Read Register Upper Digit (TRCU) Timer Timer Functions: Timer following functions. Free-running/reload timer External event counter Timer output operation (toggle, outputs) Input capture timer
block diagram each operation mode timer shown figures 58-1 58-2.
HD404849 Series
Timer interrupt request flag (IFTD) Timer output control logic
Timer read register (TRDU)
Timer output control Timer read register (TRDL) Clock Timer counter (TCD) Overflow
Selector EVND Edge detection logic
÷2048
÷128 ÷512
Free-running/ reload control
Timer write register (TWDL)
System clock
Prescaler (PSS)
Timer mode register (TMD1) Timer mode register (TMD2) Edge detection control
Edge detection selection register (ESR2)
Figure 58-1 Block Diagram Timer Reload Timer Event Counter Mode)
Internal data
Timer write register (TWDU)
HD404849 Series
Input capture status flag (ICSF) Input capture error flag (ICEF) Error control logic Timer interrupt request flag (IFTD)
Timer read register (TRDU) Timer read register (TRDL) EVND Edge detection logic Read signal Clock Input capture timer control Internal data Timer counter (TCD) Overflow
Selector
Timer mode register (TMD1)
System clock
Prescaler (PSS) Timer mode register (TMD2) Edge detection control Edge detection selection register (ESR2)
Figure 58-2 Block Diagram Timer Input Capture Timer Mode)
÷2048
÷128 ÷512
HD404849 Series
Timer Operations: Free-running/reload timer operation: free-running/reload operation, input clock source, prescaler division ratio selected timer mode register (TMD1: $010). Timer initialized value timer write register (TWDL: $011, TWDU: $012) software incremented each clock input. input clock applied timer after reached $FF, overflow generated. this case, reload timer function enabled, timer initialized initial value timer write register free-running timer function enabled, timer initialized then incremented again. overflow sets timer interrupt request flag (IFTD: $003, IFTD reset software reset. Refer figure table details. External event counter operation: Timer used external event counter selecting external event input input clock source. this case, R20/EVND must EVND port mode register (PMRC: $025). Either falling rising edge, both falling rising edges input signals selected external event detection edge detection edge select register (ESR2: $027). When both rising falling edges detection selected, time between falling edge rising edge input signals must longer. Timer incremented each detection edge selected detection edge select register (ESR2: $027). other operations basically same free-running/reload timer operation. Timer output operation: following four output modes selected timer setting timer mode register (TMD2: $015). Toggle output output output selecting timer output mode, R12/TOD TOD. output from reset reset. Toggle output: operation basically same that timer-B's toggle output. output: operation basically same that timer-B's output. output: operation basically same that timer-B's output. output: operation basically same that timer-C's output. Input capture timer operation: input capture timer counts clock cycles between trigger edges input EVND. Either falling rising edge, both falling rising edges input signals selected trigger input edge detection edge select register (ESR2: $027). When trigger edge input EVND, count timer written timer read register (TRDL: $011, TRDU: $012), timer interrupt request flag (IFTD: $003, input capture status flag (ICSF: $021, set. Timer reset $00, then incremented again. While ICSF set, trigger input edge applied timer timer generates overflow, input capture error flag (ICEF: $021, set. ICSF ICEF reset reset writing
HD404849 Series
selecting input capture operation, 2/TOD timer reset $00. Registers Timer Operation: using following registers, timer operation modes selected timer count read written. Timer mode register (TMD1: $010) Timer mode register (TMD2: $015) Timer write register (TWDL: $011, TWDU: $012) Timer read register (TRDL: $011, TRDU: $012) Port mode register (PMRC: $025) Detection edge select register (ESR2: $027)
Timer mode register (TMD1: $010): Four-bit write-only register that selects free-running/reload timer function, input clock source, prescaler division ratio shown figure reset reset. Writing this register valid from second instruction execution cycle after execution previous timer mode register (TMD1: $010) write instruction. timer initialization writing timer write register (TWDL: $011, TWDU: $012) must programmed occur after mode change becomes valid. When selecting input capture timer operation, select internal clock input clock source.
HD404849 Series
Timer mode register (TMD1: $010) Initial value Read/Write name TMD13 TMD12 TMD11 TMD10
TMD13
Free-running/reload timer selection Free-running timer Reload timer Input clock period input clock source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc R20/EVND (external event input)
TMD12
TMD11
TMD10
Figure Timer Mode Register (TMD1) Timer mode register (TMD2: $015): Four-bit read/write register that selects timer output mode input capture operation shown figure reset reset.
HD404849 Series
Timer mode register (TMD2: $015) Initial value Read/Write name TMD23 TMD23 TMD22 TMD22 TMD21 TMD21 TMD20 TMD20 Don't care Don't care Don't care output Input capture (R12 port) R12/TOD mode selection port Toggle output output output Inhibited
Figure Timer Mode Register (TMD2) Timer write register (TWDL: $011, TWDU: $012): Write-only register consisting lower digit (TWDL) upper digit (TWDU). figures operation timer write register basically same that timer write register (TWBL: $00A, TWBU: $00B).
Timer write register (lower digit) (TWDL: $011) Initial value Read/Write name TWDL3 TWDL2 TWDL1 TWDL0
Figure Timer Write Register Lower Digit (TWDL)
Timer write register (upper digit) (TWDU: $012) Initial value Read/Write name
Undefined Undefined Undefined Undefined TWDU3 TWDU2 TWDU1 TWDU0
Figure Timer Write Register Upper Digit (TWDU)
HD404849 Series
Timer read register (TRDL: $011, TRDU: $012): Read-only register consisting lower digit (TRDL) upper digit (TRDU). figures operation timer read register basically same that timer read register (TRBL: $00A, TRBU: $00B). When input capture timer operation selected count timer read after trigger input, either lower upper digit read first.
Timer read register (lower digit) (TRDL: $011) Initial value Read/Write name
Undefined Undefined Undefined Undefined TRDL3 TRDL2 TRDL1 TRDL0
Figure Timer Read Register Lower Digit (TRDL)
Timer read register (upper digit) (TRDU: $012) Initial value Read/Write name
Undefined Undefined Undefined Undefined TRDU3 TRDU2 TRDU1 TRDU0
Figure Timer Read Register Upper Digit (TRDU) Port mode register (PMRC: $025): Write-only register that selects R20/EVND function shown figure reset reset. Detection edge select register (ESR2: $027): Write-only register that selects detection edge signals input EVND shown figure reset reset.
HD404849 Series
Detection edge register (ESR2: $027) Initial value Read/Write name ESR23 ESR23
ESR22 used used ESR22 EVND detection edge detection Falling-edge detection Rising-edge detection Double-edge detection*
Note: Both falling rising edges detected.
Figure Detection Edge Select Register (ESR2) Notes When using timer output output, note following point. From update timer write register until occurrence overflow interrupt, output differs from period duty settings, shown table output should therefore used until after overflow interrupt following update timer write register. After overflow, output will have period duty cycle.
HD404849 Series
Table Output Following Update Timer Write Register
Output Mode Free running Timer Write Register Updated during High Output
Timer write register updated value
Timer Write Register Updated during Output
Timer write register updated value
Interrupt request
Interrupt request
(255
(255
Reload
Timer write register updated value
Interrupt request
Timer write register updated value
Interrupt request
(255
(255
HD404849 Series
Serial Interface
serial interface serially transfers receives 8-bit data, includes following features. Multiple transmit clock sources External clock Internal prescaler output clock System clock Output level control idle states Five registers, octal counter also configured serial interface follows. Serial data register (SRL: $006, SRU: $007) Serial mode register (SMRA: $005) Serial mode register (SMRB: $028) Port mode register (PMRA: $004) Miscellaneous register (MIS: $00C) Octal counter (OC) Selector
block diagram serial interface shown figure
HD404849 Series
Octal counter (OC) Idle controller controller Clock Transfer control signal Serial data register (SR) Internal data Serial interrupt request flag (IFS)
Selector ÷128 ÷512 ÷2048 Serial mode register (SMRA)
System clock
Prescaler (PSS)
Selector
Serial mode register (SMRB)
Figure Block Diagram Serial Interface Serial Interface Operation Selecting Changing Operating Mode: Table lists serial interface's operating modes. select operating mode, these combinations port mode register (PMRA: $004) serial mode register (SMRA: $005) settings; change operating mode, always initialize serial interface internally writing data serial mode register Note that serial interface initialized writing data serial mode register Refer following Serial Mode Register section details. Table Serial Interface Operating Modes
SMRA PMRA Operating Mode Clock continuous output mode Transmit mode Receive mode Transmit/receive mode
HD404849 Series
Setting: R21/SCK controlled writing data serial mode register (SMRA: $005). 2/SI R23/SO pins controlled writing data port mode register (PMRA: $004). Refer following Registers Serial Interface section details. Transmit Clock Source Setting: transmit clock source writing data serial mode register (SMRA: $005) serial mode register (SMRB: $028). Refer following Registers Serial Interface section details. Data Setting: Serial data writing data serial data register (SRL: $006, SRU, $007). Receive data obtained reading contents serial data register. serial data shifted transmit clock input from output external system. output level remains unsettled until first data output after reset, until output level control idle states performed. Transfer Control: serial interface activated instruction. octal counter reset this instruction, increments rising edge transmit clock. When eighth transmit clock signal input when serial transmission/receive discontinued, octal counter reset 000, serial interrupt request flag (IFS: $023, set, transfer stops. When prescaler output selected transmit clock, transmit clock frequency selected 4tcyc 8192tcyc setting bits (SMRA0- SMRA2) serial mode register (SMRA: $005) (SMRB0) serial mode register (SMRB: $028) listed table Table Serial Transmit Clock (Prescaler Output)
SMRB SMRA Prescaler Division Ratio 2048 4096 1024 Transmit Clock Frequency 4096t 1024t 256t 8192t 2048t 512t 128t
HD404849 Series
Operating States: serial interface following operating states; transitions between them shown figure wait state Transmit clock wait state Transfer state Continuous clock output state (only internal clock mode)
wait state: serial interface enters wait state reset (00, figure 67). wait state, serial interface initialized transmit clock ignored. instruction then executed (01, 11), serial interface enters transmit clock wait state. Transmit clock wait state: Transmit clock wait state period between execution falling edge first transmit clock. transmit clock wait state, input transmit clock (02, increments octal counter, shifts serial data register, puts serial interface transfer state. However, note that clock continuous output mode selected internal clock mode, serial interface does enter transfer state enters clock continuous output state (17). serial interface enters wait state writing data serial mode register (SMRA: $005) (04, transmit clock wait state. Transfer state: Transfer state period between falling edge first clock rising edge eighth clock. transfer state, input eight clocks execution instruction sets octal counter 000, serial interface enters another state. When instruction executed (05, 15), transmit clock wait state entered. When eight clocks input, transmit clock wait state entered (03) external clock mode, wait state entered (13) internal clock mode. internal clock mode, transmit clock stops after outputting eight clocks. transfer state, writing data serial mode register (SMRA: $005) (06, initializes serial interface, wait state entered. state changes from transfer another state, serial interrupt request flag (IFS: $023, octal counter that reset 000. Clock continuous output state (only internal clock mode): Clock continuous output state entered only internal clock mode. this state, serial interface does transmit/receive data only outputs transmit clock from pin. When bits (PMRA0, PMRA1) port mode register (PMRA: $004) transmit clock wait state transmit clock input (17), serial interface enters clock continuous output state. serial mode register (SMRA: $005) written clock continuous output mode (18), wait state entered.
HD404849 Series
External clock mode
wait state (Octal counter 000, transmit clock disabled) reset
SMRA write
instruction Transmit clock
SMRA write (IFS
Transmit clock wait state (Octal counter 000)
Transfer state (Octal counter 000)
transmit clocks
instruction (IFS
Internal clock mode
wait state (Octal counter 000, transmit clock disabled)
SMRA write Clock continuous output state (PMRA
reset
SMRA write instruction
transmit clocks
SMRA write (IFS
Transmit clock
Transmit clock
Transmit clock wait state (Octal counter 000)
Transfer state (Octal counter 000)
instruction (IFS
Note: Refer Operating States section corresponding encircled numbers.
Figure Serial Interface State Transitions Output Level Control Idle States: idle states, that wait state transmit clock wait state, output level controlled setting (SMRB1) serial mode register (SMRB: $028) output level control example shown figure Note that output level cannot controlled transfer state.
Transmit clock wait state State wait state Transfer state reset Port selection PMRA write SMRA write SMRB write External clock selection Output level control idle states Data write transmission SRL, write instruction (input) Undefined External clock mode Transmit clock wait state State wait state Transfer state reset Port selection PMRA write SMRA write SMRB write Internal clock selection Output level control idle states Data write transmission SRL, write instruction (output) Undefined Internal clock mode
HD404849 Series
Transmit clock wait state wait state
Dummy write state transition Output level control idle states
Flag reset transfer completion
wait state
Output level control idle states
Flag reset transfer completion
Figure Example Serial Interface Operation Sequence
HD404849 Series
Transmit Clock Error Detection External Clock Mode): serial interface will malfunction spurious pulse caused external noise conflicts with normal transmit clock during transfer. transmit clock error this type detected shown figure more than eight transmit clocks input transfer state, eighth clock including spurious pulse noise, octal counter reaches 000, serial interrupt request flag (IFS: $023, set, transmit clock wait state entered. falling edge next normal clock signal, transfer state entered. After transfer completion processing performed reset, writing serial mode register (SMRA: $005) changes state from transfer wait. this time again, therefore error detected.
Transmit clock wait state State (input) SMRA write
HD404849 Series
Transfer completion (IFS1
Interrupts inhibited
IFS1
SM1A write
IFS1
Transmit clock error processing
Normal termination
Transmit clock error detection flowchart
Transmit clock wait state Transfer state
Transfer state
Noise Transfer state been entered transmit clock error. When SMRA written, set.
Flag because octal counter reaches
Flag reset transfer completion
Transmit clock error detection procedures
Figure Transmit Clock Error Detection
HD404849 Series
Notes Use: Initialization after writing registers: port mode register (PMRA: $004) written transmit clock wait state transfer state, serial interface must initialized writing serial mode register (SMRA: $005) again. Setting serial interrupt request flag (IFS: $023, state changed from transfer another writing serial mode register (SMRA: $005) executing instruction during first pulse transmit clock, serial interrupt request flag set. serial interrupt request flag, serial mode register write instruction execution must programmed executed after confirming that that after executing input instruction port Registers Serial Interface serial interface operation selected, serial data read written following registers. Serial Mode Register (SMRA: $005) Serial Mode Register (SMRB: $028) Serial Data Register (SRL: $006, SRU: $007) Port Mode Register (PMRA: $004) Miscellaneous Register (MIS: $00C)
Serial Mode Register (SMRA: $005): This register following functions (figure 70). 1/SCK function selection Transfer clock selection Prescaler division ratio selection Serial interface initialization
Serial mode register (SMRA: $005) 4-bit write-only register. reset reset. write signal input serial mode register (SMRA: $005) discontinues input transmit clock serial data register octal counter, octal counter reset 000. Therefore, write performed during data transfer, data transfer discontinued serial interrupt request flag (IFS: $023, set. Written data valid from second instruction execution cycle after write operation, instruction must executed least cycles after write operation.
HD404849 Series
Serial mode register (SMRA: $005) Initial value Read/Write name SMRA3
SMRA2 SMRA1 SMRA0 Prescaler division ratio Refer table
SMRA3
R21/SCK mode selection
SMRA2
SMRA1 SMRA0
Output
Clock source Prescaler
Output Input
System clock External clock
Figure Serial Mode Register (SMRA) Serial Mode Register (SMRB: $028): This register following functions (figure 71). Prescaler division ratio selection Output level control idle states Serial mode register (SMRB: $028) 2-bit write-only register. cannot written during data transfer. setting (SMRB0) this register, prescaler division ratio selected. Only (SMRB0) reset reset. (SMRB1) used control output level idle states. output level changes same time that SMRB1 written
HD404849 Series
Serial mode register (SMRB: $028) Initial value Read/Write name
Undefined
SMRB0
used used SMRB1
SMRB1
Output level control idle states level High level
SMRB0
Transmit clock division ratio Prescaler output divided Prescaler output divided
Figure Serial Mode Register (SMRB) Serial Data Register (SRL: $006, SRU: $007): serial data register configuration shown figures This register following functions. Transmission data write shift Receive data shift read Writing data this register output from pin, first, synchronously with falling edge transmit clock; data input, first, through rising edge transmit clock. Input/output timing shown figure Data cannot read written during serial data transfer. read/write occurs during transfer, accuracy resultant data cannot guaranteed.
Serial data register (lower digit) (SRL: $006) Initial value Read/Write name
Undefined Undefined Undefined Undefined
Figure Serial Data Register (SRL)
HD404849 Series
Serial data register (upper digit) (SRU: $007) Initial value Read/Write name
Undefined Undefined Undefined Undefined
Figure Serial Data Register (SRU)
Transmit clock Serial output data
Serial input data latch timing
Figure Serial Interface Input/Output Timing Port Mode Register (PMRA: $004): This register following functions (figure 75). 2/SI function selection 3/SO function selection Port mode register (PMRA: $004) 2-bit write-only register, reset reset.
Port mode register (PMRA: $004) Initial value Read/Write name
used used PMRA1 PMRA0
PMRA1
R22/SI mode selection
PMRA0
R23/SO mode selection
Figure Port Mode Register (PMRA)
HD404849 Series
Miscellaneous Register (MIS: $00C): This register following function (figure 76). 3/SO PMOS control Miscellaneous register (MIS: $00C) 4-bit write-only register reset reset.
Miscellaneous register (MIS: $00C) Initial value Read/Write name MIS3 MIS2 MIS1 MIS0
MIS3 MIS2
Pull-up on/off selection
MIS1
MIS0
tRC* 0.12207 0.24414
R23/SO PMOS on/off selection
7.8125 31.25 used
Note: Refer figure
Figure Miscellaneous Register (MIS)
HD404849 Series
Converter
built-in converter that uses successive approximations with resistor ladder. measure eight analog inputs with 8-bit resolution. shown block diagram figure converter 4-bit mode register, 4-bit plus 4-bit data register, 1-bit start flag, 1bit current flag.
Interrupt flag (IFAD)
Encoder
data register (ADRU, ADRL)
/AN4 /AN5 /AN6 /AN7 AVCC Selector mode register (AMR) COMP Reference voltage start flag (ADSF) Reference voltage control AVSS stop, watch, subactive modes) current flag (IAOF) control logic Internal data
Conversion time control
Figure Block Diagram Converter
HD404849 Series
Mode Register (AMR: $016): Four-bit write-only register which selects conversion period indicates analog input information. mode register selects conversion period, bits select channel, shown figure
mode register (AMR: $016) Initial value Read/Write name AMR3 AMR2 AMR1 AMR0
AMR3
AMR2
AMR1
Analog input selection
AMR0
Conversion time 34tcyc 67tcyc
Figure Mode Register (AMR)
HD404849 Series
Data Register (ADRL: $017, ADRU: $018): 8-bit read-only register consisting 4-bit lower digit 4-bit upper digit. This register cleared reset. data read during conversion guaranteed. After completion conversion, resultant eight-bit data held this register until start next conversion (figures 81).
ADRU: $018 ADRL: $017
RESULT
Figure Data Registers
data register (lower digit) (ADRL: $017) Initial value Read/Write name ADRL3 ADRL2 ADRL1 ADRL0
Figure Data Register Lower Digit (ADRL)
data register (upper digit) (ADRU: $018) Initial value Read/Write name ADRU3 ADRU2
ADRU1 ADRU0
Figure Data Register Upper Digit (ADRU)
HD404849 Series
Start Flag (ADSF: $020, One-bit flag that initiates conversion when completion conversion, converted data stored data register start flag cleared. Refer figure
start flag (ADSF: $020, Initial value Read/Write name DTON DTON Refer description operating modes ADSF WDON LSON WDON Refer description timers
ADSF (A/D start flag) conversion started conversion completed
LSON Refer description operating modes
Figure Start Flag (ADSF) Current Flag (IAOF: $021, setting this 1-bit flag current flowing through ladder resistor converter during standby active modes. figure
HD404849 Series
current flag (IAOF: $021, Initial value Read/Write name RAME RAME Refer description operating modes IAOF ICEF ICSF ICEF Refer description timers
IAOF (A/D current flag) Current off. Current flows.
ICSF Refer description timers
Figure Current Flag (IAOF) Note Use: SEMD instructions write data start flag (ADSF: $020, make sure that start flag written during conversion. Data read from data register (ADRL: $017, ADRU: $018) during conversion cannot guaranteed. converter does operate stop, watch, subactive modes because relies clock from OSC, which stopped these modes. During these low-power dissipation modes, current through resistor ladder decrease power input. port data register (PDR) initialized reset. this time, pull-up selected active miscellaneous register (MIS3), port will pulled VCC. When using shared port/analog input input pin, clear Otherwise, pull-up selected MIS3 selected mode register analog will remain pulled
HD404849 Series
Controller/Driver
controller driver which drive common signal pins segment pins. controller consists area which display data stored, display control register (LCR: $01B), duty-cycle/clock-control register (LMR: $01C) (figure 84). Four duty cycles clock programmable, built-in dual-port ensures that display data automatically transmitted segment signal pins without program intervention. 32-kHz oscillation clock selected clock source, even used watch mode, which system clock stops.
HD404849 Series
power switch
power control circuit
control register (LCR)
COM1
COM2
COM3
COM4
control
Display control
common driver
R60/SEG13
R61/SEG14
function control circuit
Display data
Display dual-port digits)
Duty cycle selection
segment driver
R73/SEG20
SEG21
Selector
SEG43
SEG44
input clock
mode register (LMR)
Figure Block Diagram Controller/Driver
Internal data
output register (LCR3)
HD404849 Series
Data Area Segment Data ($05C-$07B): shown figure each storage area corresponds four duty cycles. data written area corresponding certain duty cycle, automatically output corresponding segments display data.
SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 COM4 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 COM3 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 COM2 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 COM1 $05C $05D $05E $05F $060 $061 $062 $063 $064 $065 $066 $067 $068 $069 $06A $06B SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 COM4 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 COM3 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 COM2 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 COM1 $06C $06D $06E $06F $070 $071 $072 $073 $074 $075 $076 $077 $078 $079 $07A $07B
Figure Configuration Area (for Dual-Port RAM)
HD404849 Series
Control Register (LCR: $01B): Four-bit write-only register which controls blanking, on/off switching liquid-crystal display's power supply division resistor, display watch subactive modes, connection division resistor, shown figure Blank/display Blank: Segment signals turned off, regardless data setting. Display: data output segment signals. Power switch on/off Off: power switch off. power switch VCC. Watch/subactive mode display Off: watch subactive modes, common segment pins grounded liquid-crystal power switch turned off. watch subactive modes, data output segment signals. power supply division resistor switch Off: Division resistor disconnected. Division resistor connected.
display control register (LCR: $01B) Initial value Read/Write name LCR3 LCR2 LCR1 LCR0 LCR1 LCR0 Power switch on/off Blank/display Blank Display
LCR3
power supply division resistor switch Display on/off selection watch subactive modes
LCR2
Figure Control Register (LCR)
HD404849 Series
Duty-Cycle/Clock Control Register (LMR: $01C): Four-bit write-only register which selects display duty cycle clock source, shown figure dependence frame frequency duty cycle listed table
duty cycle/clock control register (LMR: $01C) Initial value Read/Write name LMR3 LMR3 LMR2 LMR2 LMR1 LMR0
Input clock source selection (32.768 duty/64: when 32.768-kHz oscillation used) (fOSC duty cycle/1024) (fOSC duty cycle/8192) (refer table Duty cycle selection duty duty duty Static
LMR1
LMR0
Figure Duty-Cycle/Clock Control Register (LMR)
HD404849 Series
Table Frame Frequencies Different Duty Cycles
Frame Frequencies Duty Cycle LMR3 Static LMR2 CL3* fOSC fOSC fOSC 390.6 48.8 24.4 CL3* 195.3 24.4 12.2 CL3* 170.7 130.2 16.3 21.3 CL3* 97.7 12.2 781.3 97.7 48.8 390.6 48.8 24.4 170.7 260.4 32.6 16.3 21.3 195.3 24.4 12.2 1953 244.1 122.1 976.6 122.1 170.7 81.4 40.7 21.3 488.3 30.5 fOSC 3906 488.3 244.1 1953 244.1 122.1 170.7 1302 162.8 81.4 21.3 976.6 122.1
Note: division ratio depends value timer mode register (TMA). Upper value: When TMA3 duty cycle/16384. Lower value: When TMA3 32.768 duty cycle/512.
Output Register (LOR3: $01F): Write-only register used specify ports pins SEG13-SEG20 4-pin units (figure 88).
HD404849 Series
output register (LOR3: $01F) Initial value Read/Write name
used LOR32
LOR31 used
LOR32
R7/SEG17-SEG20 mode selection SEG17-SEG20
LOR31
R6/SEG13-SEG16 mode selection SEG13-SEG16
Figure Output Register (LOR3) Large Liquid-Crystal Panel Drive VLCD: capacitance very large while being driven, decrease capacitance attaching external resistors parallel, shown figure size these resistors cannot simply calculated from load capacitance because matrix configuration complicates paths charge/discharge currents flowing through capacitors-the resistance will also vary with lighting conditions. This size must determined trialand-error, taking into account power dissipation device using LCD, resistance usually suitable. (Another effective method attach capacitors µF.) Always turn power switch (set before changing liquid-crystal drive voltage (VLCD).
HD404849 Series
VLCD
COM1
4-digit
SEG13 SEG44
Static drive
VLCD
COM1 COM2
8-digit
SEG13 SEG44
duty, bias drive
VLCD
COM1 COM3 SEG13 SEG44
10-digit with sign
duty, bias drive
VLCD
COM1 COM4 SEG13 SEG44
16-digit
duty, bias drive
Figure Connection Examples
HD404849 Series
Programmable (HD4074849)
HD4074849 ZTAT microcomputer with built-in PROM that programmed PROM mode. Description Mode
Mode PROM Mode Mode FP-80B Name 2/TOD 3/EVNB 0/EVND 1/SCK 2/SI 3/SO 0/SEG13 1/SEG14 2/SEG15 3/SEG16 0/SEG17 1/SEG18 2/SEG19 3/SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 PROM Mode Name
FP-80A, TFP- FP-80B Name 2/AN6 3/AN7 AVSS TEST RESET
80A, Name TFP-80C TEST RESET
D10/STOPC D11/INT0 0/INT1 1/INT2 2/INT3 0/TOB 1/TOC
HD404849 Series
Mode PROM Mode Mode FP-80B Name COM3 COM4 AVCC 0/AN4 1/AN5 PROM Mode Name FP-80A, TFP- FP-80B Name SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 COM1 COM2 80A, Name TFP-80C
Notes: I/O: Input/output pin, Input pin, Output Each O0-O4 pins; before using, each pair must connected together.
PROM Mode Functions VPP: Applies programming voltage (12.5 built-in PROM. Inputs control signal enable PROM programming verification. Inputs data output control signal verification. A0-A14: address input pins built-in PROM. O0-O4: data input pins built-in PROM. Each O0-O4 pins; before using these pins, connect each pair together. RESET, TEST: Used PROM mode. PROM mode pulling RESET low, TEST high. Other Pins: Connect pins AVCC, R73/SEG20, VCC. Connect pins AVSS GND. Leave other pins open. Programming Built-In PROM MCU's built-in PROM programmed PROM mode. PROM mode pulling RESET, low, TEST high. PROM mode, does operate, programmed
HD404849 Series
same other commercial 27256-type EPROM using standard PROM programmer 80-to28-pin socket adapter. Recommended PROM programmers socket adapters listed table Since HMCS400-series instruction bits long, HMCS400-series built-in conversion circuit enable general-purpose PROM programmer. shown figure this circuit splits each instruction into five lower bits five upper bits that read from written consecutive addresses. This means that example, kwords built-in PROM programmed general-purpose PROM programmer, 32-kbyte address space ($0000-$7FFF) must specified. Table Recommended PROM Programmers Socket Adapters
PROM Programmer Manufacturer DATA Corp. Model name 121B
AVAL Corp.
PKW-1000
Socket Adapter Package FP-80A FP-80B TFP-80C Model Name HS4849ESH01H HS4849ESF01H HS4849ESN01H Manufacturer Hitachi
Warnings Always specify addresses $0000 $7FFF when programming with PROM programmer. address $8000 higher accessed, PROM programmed verified correctly. data unused addresses $FF. Note that plastic-package version cannot erased reprogrammed. Make sure that PROM programmer, socket adapter, aligned correctly (their positions match), otherwise overcurrents damage LSI. Before starting programming, make sure that firmly fixed socket adapter socket adapter firmly fixed onto programmer. PROM programmers have voltages (VPP 12.5 Remember that Hitachi devices require 12.5 V-the 21-V setting will damage them. 12.5 Intel 27256 setting. Programming Verification built-in PROM programmed high speed without risk voltage stress damage data reliability.
HD404849 Series
Programming verification modes selected listed table memory PROM mode shown figure Table PROM Mode Selection
Mode Programming Verification Programming inhibited High High High High O0-O4 Data input Data output High impedance
$0000 $0001 $001F $0020 $007F $0080 $1FFF $2000
Lower bits Upper bits
$0000
Vector address
$000F $0010
Zero-page subroutine words)
$003F $0040
Pattern (4,096 words)
$0FFF $1000
Program (16,384 words)
$7FFF
$3FFF
Upper three bits used (fill them with 111)
Figure Memory PROM Mode
HD404849 Series
Addressing Modes
Addressing Modes three addressing modes, shown figure described below.
register register register
address
Register Indirect Addressing
word Instruction Opcode
word Instruction
address
Direct Addressing
Instruction Opcode
address
Memory Register Addressing
Figure Addressing Modes Register Indirect Addressing Mode: contents registers bits total) used address. When area from $090 $25F used, bank must selected bank register $03F). Direct Addressing Mode: direct addressing instruction consists words. first word contains opcode, contents second word bits) used address.
HD404849 Series
Memory Register Addressing Mode: memory registers (MR), which located addresses from $040 $04F, accessed with LAMR XMRA instructions. Addressing Modes Instruction four addressing modes, shown figure described below.
word instruction
[JMPL] [BRL] [CALL]
word instruction
Opcode
Program counter
PC13 PC12 PC11 PC10 Direct Addressing
Instruction
[BR]
Opcode
Program counter
PC13 PC12 PC11 PC10 Current Page Addressing
Instruction [CAL]
Opcode
Program counter
PC13 PC12 PC11 PC10
Zero Page Addressing
Instruction
[TBR]
Opcode
register
Accumulator
Program counter
PC13 PC12 PC11 PC10
Table Data Addressing
Figure Addressing Modes
HD404849 Series
Direct Addressing Mode: program branch address memory space executing JMPL, BRL, CALL instruction. Each these instructions replaces program counter bits 13-PC0) with 14-bit immediate data. Current Page Addressing Mode: pages with words page. program branch address current page executing instruction. This instruction replaces eight low-order bits program counter (PC7-PC0) with eight-bit immediate data. instruction page boundary (address 256n 255), executing that instruction transfers contents next physical page, shown figure This means that execution instruction page boundary will make program branch next page.
Instruction Opcode register Accumulator
Referenced address RA13 RA12 RA11 RA10 Address Designation data
Accumulator, register
data
Output registers
Pattern Output
Figure Instruction
HD404849 Series
256n
256n 256n
Figure Branching when Branch Destination Page Boundary Note that HMCS400-series cross macroassembler automatic paging feature pages. Zero-Page Addressing Mode: program branch zero-page subroutine area located $0000- $003F executing instruction. When instruction executed, bits immediate data placed low-order bits program counter 5-PC0), placed eight highorder bits (PC13-PC6). Table Data Addressing Mode: program branch address determined contents fourbit immediate data, accumulator, register executing instruction. Instruction: data addressed table data addressing mode referenced with instruction shown figure data lower eight bits data written accumulator register. lower eight bits data written port output registers. both bits data written accumulator register, also port output registers same time. instruction effect program counter.
HD404849 Series
Absolute Maximum Ratings
Item Supply voltage Programming voltage voltage Total permissible input current Total permissible output current Maximum input current Symbol Value -0.3 +7.0 -0.3 +14.0 -0.3 Maximum output current Operating temperature Storage temperature Topr Tstg +125 Unit Notes
Notes: Permanent damage occur these absolute maximum ratings exceeded. Normal operation must under conditions stated electrical characteristics tables. these conditions exceeded, malfunction reliability affected. Applies (VPP) HD4074849. total permissible input current total input currents simultaneously flowing from pins ground. total permissible output current total output currents simultaneously flowing from pins. maximum input current maximum current flowing from each ground. Applies R0-R3, Applies maximum output current maximum current flowing from each pin. Applies R0-3,
HD404849 Series
Electrical Characteristics
Characteristics (HD404848/HD4048412/HD404849: -20°C +75°C; HD4074849: -20°C +75°C, unless otherwise specified)
Item Input high voltage Symbol Pin(s) RESET, SCK, INT0, INT1, INT2, INT3
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