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H8S/2357 Series,
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Hardware Manual
ADE-602-146D Rev. 11/22/02 Hitachi, Ltd.
revision list viewed directly clicking title page. rivision list summarizes locations revisions additions. Details should always checked referring relevant text.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
General Precautions Handling Product
Treatment Pins Note: connect anything pins. (not connected) pins either connected internal circuitry they used test pins reduce noise. something connected pins, operation guaranteed. Treatment Unused Input Pins Note: unused input pins high level. Generally, input pins CMOS products high-impedance input pins. unused pins their open states, intermediate levels induced noise vicinity, pass-through current flows internally, malfunction occur. Processing before Initialization Note: When power first supplied, product's state undefined. states internal circuits undefined until full power supplied throughout chip level input reset pin. During period where states undefined, register settings output state each also undefined. Design your system that does malfunction because processing while this undefined state. those products which have reset function, reset immediately after power supply been turned Prohibition Access Undefined Reserved Addresses Note: Access undefined reserved addresses prohibited. undefined reserved addresses used expand functions, test registers have been allocated these addresses. access these registers; system's operation guaranteed they accessed.
Preface
This single-chip microcomputer with 32-bit H8S/2000 core, on-chip peripheral functions required system configuration. This equipped with ROM, RAM, controller, data transfer controller (DTC), programmable pulse generator (PPG), three types timers, serial communication interface (SCI), converter, converter, ports on-chip peripheral functions. This suitable embedded microcomputer high-level control systems. on-chip flash memory (F-ZTATTM*), PROM (ZTAT®*), mask that provides flexibility reprogrammed time cope with situations from early stages mass production full-scale mass production. This particularly applicable application devices with specifications that will most probably change. Note: F-ZTATis trademark Hitachi, Ltd. ZTAT® registered trademark Hitachi, Ltd. Target Users: This manual written users will using H8S/2357 Series design application systems. Members this audience expected understand fundamentals electrical circuits, logical circuits, microcomputers. Objective: This manual written explain hardware functions electrical characteristics H8S/2357 Series above audience. Refer H8S/2600 Series, H8S/2000 Series Programming Manual detailed description instruction set.
Notes reading this manual: order understand overall functions chip Read manual according contents. This manual roughly categorized into parts CPU, system control functions, peripheral functions, electrical characteristics. order understand details CPU's functions Read H8S/2600 Series, H8S/2000 Series Programming Manual. order understand details register when name known addresses, bits, initial values registers summarized Appendix Internal Register. Examples: order: left right. Related Manuals: latest versions related manuals available from site. Please ensure have latest versions documents require.
H8S/2357 Series users manuals:
Manual Title H8S/2357 Series Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual This manual ADE-602-083
Users manuals development tools:
Manual Title C/C++ Compiler, Assembler, Optimized Linkage Editor Users Manual Simulator Debugger Users Manual Hitachi Embedded Workshop Users Manual ADE-702-247 ADE-702-037 ADE-702-201
Application Note:
Manual Title Series Technical ADE-502-059
Main Revisions Additions this Edition
Item Page Revisions (See Manual Details) H8S/2396F-ZTAT H8S/2395F-ZTAT lineup deleted Deletion "Under development" planning stage" notes Package code 128pin amended FP-128FP-128B 2.6.1 Overview Table Instruction Classification 3.3.2 Model (H8S/2398 F-ZTAT Only) Explanation replaced This flash memory boot mode. details, section ROM. operation same mode Explanation replaced This flash memory boot mode. details, section ROM. operation same mode
Port Port
Total amount Types added table
3.3.3 Mode (H8S/2398 F-ZTAT Only)
3.3.8 Modes Functions Each Operating Mode Table Functions Each Mode Memory Each Operating Mode
Title amended
Mode P/C*1 P*1/C Mode P/C*1 Mode Mode P/C*1 P*1/C P/C*1 P*1/C Mode Mode P/C*1 P*1/C P*1/C Mode 10*3 P/C*1 P*1/C Mode 11*3 P*1/C Mode Mode 14*3 15*3 P/C*1 P*1/C P*1/C
Figures Memory Each Operating Mode (H8S/2396) (1), (2), Memory Each Operating Mode (H8S/2395) (1), deleted Note amended follows Only mode provided H8S/2352.
Figure Memory Each Operating Mode (H8S/2357, H8S/2352) 4.1.3 Exception Vector Table
Explanation amended 16th line follows this case, clearing BCRL enables 128-kbyte (256k-byte)* area comprising address H'000000 H'01FFFF (H'03FFFF) used.
Item 6.1.2 Block Diagram Figure Block Diagram Controller
Page
Revisions (See Manual Details) Figure amended
DRAM controller DRAMCR RTCNT RTCOR
6.3.2 Specifications Width 6.5.11 Refresh Control Figure 6-25 Refresh Timing Figure 6-26 Refresh Timing (When RCW=1, RLW=0, RLW0=1) 6.6.1 When DDS=1 Figure 6-28 DACK Output Timing when DDS=1 (Example DRAM Access) 6.6.2 When DDS=0 Figure 6-29 DACK Output Timing when DDS=0 (Example DRAM Access) 7.3.4 Control Register (DMACR)
Description amended (Incorrect) ADWCR (Collect) ABWCR
Added figures Note:
Added figures Note:
Added figure Note:
Added figure Note:
Explanation added line follows Bits 7-Reserved: read written Write these bits. Explanation added line follows 4-Reserved: read written Write this bit.
7.3.5 Band Control Register (DMABCR)
Explanation added line follows Bits 12-Reserved: read written Write these bits.
Explanation added line follows Bits 8-Reserved: read written Write these bits.
Item 7.5.2 Sequential Mode
Page
Revisions (See Manual Details) Explanation amended line follows Transfer requests (activation sources) consist converter conversion interrupts, external requests, transmission data empty reception data full interrupts, channel compare match/input capture interrupts.
7.5.3 Idle Mode
Explanation amended line follows Transfer requests (activation sources) consist converter conversion interrupts, external requests, transmission data empty reception data full interrupts, channel compare match/input capture interrupts.
7.5.4 Repeat Mode
Explanation amended line follows Transfer requests (activation sources) consist converter conversion interrupts, external requests, transmission data empty reception data full interrupts, channel compare match/input capture interrupts.
7.5.7 Block Transfer Mode
Explanation amended line follows Transfer requests (activation sources) consist converter conversion interrupts, external requests, transmission data empty reception data full interrupts, channel compare match/input capture interrupts.
8.3.12 Example Normal Mode
Explanation amended follows appropriate receive mode. enable reception data full (RXI) interrupt. Since generation receive error during reception operation will disable subsequent reception, should enabled accept receive error interrupt.
11.3.4 Non-Overlappng Pulse Output Figure 11-6 Setup Procedure Non-Overlapping Pulse Output (Example)
Figure amended
setup
Start counter Compare match next pulse output data
[10]
[11]
Item
Page
Revisions (See Manual Details) Table amended
Channel CMIA0 CMIB0 OVI0 CMIA1 Interrupt CMIB1 OVI1 Interrupt CMFA Interrupt CMFB Interrupt Interrupt CMFA Interrupt possible CMFB Possible Possible possible Possible Possible High
12.4.1 Interrupt Sources Activation Table 12-3 8-Bit Timer Interrupt Sources
12.6.6 Interrupt Module Stop Mode 13.2.3 Reset Control/Status Register (RSTCSR)
Title amended 7-Watchdog Timer Over Flag (WOVF) Explanation amended follows
WOVF Description [Clearing condition] Cleared reading RSTCSR when WOVF then writing WOVF (Initial value)
13.3.4 Timing Setting Watchdog Timer Overflow Flag (WOVF)
Note amended Note: WDTOVF function available F-ZTAT version H8S/2398, H8S/2394, H8S/2392, H8S/2390. Word amended 17th line TCSRRSTCSR 3-Multiprocessor Interrupt Enable (MPIE) Explanation amended follows
MPIE Description Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] When MPIE cleared When MPB= data received (Initial value)
13.5.5 Internal Reset Watchdog Timer Mode 14.2.6 Serial Control Register (SCR)
Multiprocessor interrupts enabled* Receive data full interrupt (RXI) requests, receive error interrupt (ERI) requests, setting RDRF, FER, ORER flags disabled until data with multiprocessor received.
16.2.2 Control/Status Register (ADCSR)
Bits 0-Channel Select (CH2 CH0) table amended
Description Single Mode (SCAN=0) (Initial value) Scan Mode (SCAN=1) AN0, AN4,
Item 18.1 Overview
Page
Revisions (See Manual Details) Explanation amended line follows H8S/2390 kbytes on-chip high-speed static RAM. on-chip connected 16-bit bus, accessing both byte data word data performed single state. Thus, highspeed transfer word data possible.
19.1 Overview
Explanation amended line follows This series kbytes flash memory, kbytes mask ROM, kbytes PROM.
19.5.2 Programming Verification Table 19-8 Characteristics PROM Mode
Note amended Notes: Input pulse level: Input rise time fall time Timing reference levels:Input: Output:
19.15.1 Features Programming/erase methods
Explanation amended follows flash memory programming time 10ms (typ.) simultaneous 128-byte programming, equivalent 78µs (typ.) byte, erase time 50ms (typ.).
19.17.1 Boot Mode Table 19-36 System Clock Frequencies which Automatic Adjustment H8S/2398 F-ZTAT Rate Possible
Explanation amended line follows Automatic Rate Adjustment: When boot mode initiated, H8S/2398 F-ZTAT chip measures period asynchronous communication data (H'00) transmitted continuously from host. Table title amended frequency amended
Host Rate 19,200 9,600 System Clock Frequency which Automatic Adjustment H8S/2398 F-ZTAT Rate Possible
19.18.2 Program-Verify Mode Figure 19-48 Program/ProgramVerify Flowchart 19.18.4 Erase-Verify Mode Figure 19-49 Erase/Erase-Verify Flowchart
(Preliminary) deleted from figure title
(Preliminary) deleted from figure title
Item 19.22.2 Socket Adapter Memory Figure 19-54 H8S/2398 F-ZTAT Socket Adapter Assignments
Page
Revisions (See Manual Details) Figure amended H8S/2398FH8S/2398 F-ZTAT Note amended should connected using capacitor 0.47µF.
Overview Flash Memory (H8S/2396, H8S/2395F-ZTAT) Flash Memory Programming Erasing Precautions 20.2.1 System Clock Control Register (SCKCR)
Sections deleted
Explanation amended 6-Reserved: This read written only should written. 5-Reserved: H8S/2357 H8S/2352, this cannot modified always read Only should written. This reserved H8S/2390, H8S/2392, H8S/2394, H8S/2398. Only should written this bit.
20.3.1 Connecting Crystal Resonator Table 20-2 Damping Resistance Value
Table amended (Incorrect) (Correct) Rd()
Table amended (Incorrect) (Correct) Rs()
20.3.2 External Clock Input Table 20-4 External Clock Input Conditions
Table amended
Item Clock pulse width level Clock high pulse width level Symbol Unit Test Conditions Figure 22-4
22.1.1 Absolute Maximum Ratings Table22-1 Absolute Maximum Ratings
-Preliminary- deleted
Item 22.1.2 Characteristics Table22-2 Characteristics
Page 824,
Revisions (See Manual Details) -Preliminary- deleted table amended
Item Current dissipation* Normal operation Sleep mode Standby mode* Analog power supply current During conversion Idle Reference current During conversion Idle standby voltage VRAM Symbol Unit Test Conditions 50°C 50°C (5.0 (5.0 0.01
(5.0 0.01
(5.0 0.01
Note amended follows values VRAM 4.5V, VIHmin=VCC 0.9, ILmax=0.3V. depends follows (normal mode) (sleep mode) 12MHz
22.1.4 Conversion Characteristic Table 22-9 Conversion Characteristic 22.3 Electrical Characteristics H8S/2398F-ZTAT
Note amended
(Preliminary) deleted from title
Item
Page
Revisions (See Manual Details) -Preliminary- deleted Note amended operating temperature ranges flash memory programming/erasing follows: Ta=0 +75°C(regular specifications), Ta=0 +85°C(wide-range specifications).
Symbol Normal operation Sleep mode Standby mode* Analog power supply current During conversion Idle Reference current During conversion Idle standby voltage VRAM Unit Test Conditions 50°C 50°C
22.3.1 Absolute Maximum Ratings Table 22-11 Absolute Maximum Ratings
22.3.2 Characteristics Table 22-12 Characteristics
855,
-Preliminary- deleted table amended
Item Current dissipation* (5.0 (5.0 0.01
(5.0 0.01
(5.0 0.01
Note amended follows values VRAM 4.5V, VIHmin=VCC 0.9, ILmax=0.3V. depends and, follows [normal mode] [sleep mode] 12MHz
22.3.4 Conversion Characteristics Table 22-19 Conversion Characteristics
Note amended
Item 22.3.6 Flash Memory Characteristics Table 22-21 Flash Memory Characteristics
Page
Revisions (See Manual Details) -Preliminary- deleted Conditions amended Ta=0 +75°C (Programming/erasing operating temperature, regular specifications), Ta=0 +85°C (Programming/erasing operating temperature, widerange specifications)
Item Programming time*1* Erase time*
Symbol NWEC (z1) (z2) (z3)
1000
Unit ms/128 bytes ms/block Times
Test Condition
Reprogramming count Programming Wait time after setting* Wait time after setting* Wait time after setting*
1000
Additional programming wait
22.6.1 Absolute Maximum Ratings Table 22-22 Absolute Maximum Ratings 22.6.2 Characteristics Table 22-23 Characteristics
-Preliminary- deleted
Table amended
Item Current dissipation* Standby mode* Symbol 0.01 20.0 Unit Test Conditions 50°C 50°C
Note amended Table 22-23 Characteristics 890, values VRAM 4.5V, VIHmin=VCC 0.9, ILmax=0.3V.
Symbol output pins Ports Unit Test Conditions 50°C 50°C
Table amended
Item Output voltage
Current dissipation*
Standby mode*
0.01
20.0
Note amended values VRAM 2.7V, VIHmin=VCC 0.9, ILmax=0.3V.
Item 22.6.2 Characteristics
Page
Revisions (See Manual Details) Table amended
Item Output voltage Symbol output pins Ports Unit Test Conditions 50°C 50°C
892, Table 22-23 Characteristics
Current dissipation*
Standby mode*
0.01
Note amended 22.6.4 Conversion Characteristics Table 22-30 Conversion Characteristics values VRAM 3.0V, VIHmin=VCC 0.9, ILmax=0.3V.
Notes amended Notes
22.6.5 Conversion Characteristics Table 22-31 Conversion Characteristics
Test Conditions amended
Test Conditions
20-pF capacitive load resistive load resistive load
22.7.2 Characteristics Table 22-33 Characteristics
Table amended
Item Current dissipation* Standby mode* Flash memory programming/ erasing Symbol 0.01 20.0 Unit Test Conditions 50°C 50°C 75°C
(5.0
Note amended Table 22-33 Characteristics 925, values VRAM 4.5V, VIHmin=VCC 0.9, ILmax=0.3V.
Symbol output pins Ports Unit Test Conditions 50°C 50°C 75°C
Table amended
Item Output voltage
Current dissipation*
Standby mode* Flash memory programming/ erasing
0.01
(3.3
Note amended values VRAM 3.0V, VIHmin=VCC 0.9, ILmax=0.3V.
Item 22.7.4 Conversion Characteristics Table 22-40 Conversion Characteristics
Page
Revisions (See Manual Details) Unit amended Notes:
22.7.5 Conversion Characteristics Table 22-41 Conversion Characteristics
Test Conditions amended
Test Conditions
20-pF capacitive load resistive load resistive load
Functions
1075, 1076
DMACR0A, DMACR0B, DMACR1A, DMACR1B amended
Full address mode DMACRA DTSZ SAID SAIDE BLKDIR BLKE
Initial value Read/Write
Reserved Only should written this bit.
Full address mode (cont) DMACRB DAID DAIDE DTF3 DTF2 DTF1 DTF0
Initial value Read/Write
Reserved Only should written this bit.
Reserved Only should written this bit.
1078
DMABCRH amended
Full address mode FAE1 FAE0 DTA1 DTA0 DMABCRH Initial value Read/Write
Reserved Only should written this bit.
Reserved Reserved Only should Only should written this bit. written this bit.
Item Functions
Page 1079
Revisions (See Manual Details) DMABCRL amended
Full address mode (cont)
DTME1
DTE1
DTME0
DTE0
Channel Data Transfer Interrupt Enable Transfer interrupt disabled Transfer interrupt enabled
DMABCRL
Initial value Read/Write
DTIE1B DTIE1A
DTIE0B DTIE0A
Channel Data Transfer Interrupt Enable Transfer suspended interrupt disabled Transfer suspended interrupt enabled
Channel Data Transfer Interrupt Enable Transfer interrupt disabled Transfer interrupt enabled
Channel Data Transfer Interrupt Enable Transfer suspended interrupt disabled Transfer suspended interrupt enabled
Channel Data Transfer Enable Data transfer disabled Data transfer enabled
Channel Data Transfer Master Enable Data transfer disabled. normal mode, cleared interrupt Data transfer enabled
Channel Data Transfer Enable Data transfer disabled Data transfer enabled
Channel Data Transfer Master Enable Data transfer disabled. normal mode, cleared interrupt Data transfer enabled
1088
SCKCR amended
PSTOP -/(R/W)
Reserved H8S/2398, H8S/2394, H8S/2392, H8S/2390. Only should written this bit. Reserved Only should written this bit.
Item Functions
Page 1144
Revisions (See Manual Details) TCSR Note added
Timer Mode Select Interval timer mode: Sends interval timer interrupt request (WOVI) when TCNT overflows Watchdog timer mode: Generates WDTOVF signal*1 when TCNT overflows*2
Notes: WDTOVF function available F-ZTAT version, H8S/2398, H8S/2394, H8S/2392, H8S/2390. details case where TCNT overflows watchdog time mode, section 13.2.3, Reset Control/Status Register(RSTCSR).
1145
TCNT Note added Note TCNT write-protected password prevent accidental overwriting. details section 13.2.4, Notes Register Access.
1146
RSTCSR Watchdog Timer Overflow Flag Clearing condition amended TCSR RSTCSR
FLMCR1 H'FFC8 (For H8S/2395 F-ZTAT) EBR1 H'FFCA, EBR2 H'FFCB (For H8S/2396 FZTAT) deleted
Port States Each Mode Table Port States Each Processing State
1211 1214
Table amended
P67/CS7 P66/CS6 P61/CS5 P60/CS4 kept kept kept kept port [DDR Input port [DDR [DDR Input port [DDR Address output [DDR Input port [DDR Address output port Address output [DDR [DDR [DDR [DDR keep [DDR [DDR keep kept [OPE [OPE keep kept
kept
kept
kept kept
kept
[DDR [DDR keep kept kept [DRAME kept [OPE [DRAME OPE= kept kept
[DDR Input port [DDR Address output port port [DRAME Input port [DRAME
PG0/CAS
kept kept
[DRAME kept [DRAME
Item Package Dimensions Figure FP-128B Package Dimension
Page 1221
Revisions (See Manual Details) Figure replaced
22.0
16.0
Unit:
*0.22 0.05 0.20 0.04 0.10 0.75
3.15
*0.17 0.05 0.15 0.04
2.70
0.75
+0.15 -0.10
0.10
0.10
Hitachi Code JEDEC JEITA Mass (reference value) FP-128B Conforms
*Dimension including plating thickness Base material dimension
Contents
Section Overview.
Overview Block Diagram. Description 1.3.1 Arrangement 1.3.2 Functions Each Operating Mode 1.3.3 Functions.
Section CPU.
Overview 2.1.1 Features 2.1.2 Differences between H8S/2600 H8S/2000 2.1.3 Differences from H8/300 CPU. 2.1.4 Differences from H8/300H CPU. Operating Modes Address Space Register Configuration 2.4.1 Overview 2.4.2 General Registers 2.4.3 Control Registers. 2.4.4 Initial Register Values Data Formats 2.5.1 General Register Data Formats 2.5.2 Memory Data Formats Instruction 2.6.1 Overview 2.6.2 Instructions Addressing Modes 2.6.3 Table Instructions Classified Function 2.6.4 Basic Instruction Formats. Addressing Modes Effective Address Calculation. 2.7.1 Addressing Mode 2.7.2 Effective Address Calculation. Processing States 2.8.1 Overview 2.8.2 Reset State 2.8.3 Exception-Handling State 2.8.4 Program Execution State 2.8.5 Bus-Released State. 2.8.6 Power-Down State
Basic Timing 2.9.1 Overview 2.9.2 On-Chip Memory (ROM, RAM) 2.9.3 On-Chip Supporting Module Access Timing. 2.9.4 External Address Space Access Timing. 2.10 Usage Note 2.10.1 Instruction
Section Operating Modes
Overview 3.1.1 Operating Mode Selection (H8S/2357 F-ZTAT Only) 3.1.2 Operating Mode Selection (ZTAT, Mask ROM, ROMless Version, H8S/2398 F-ZTAT). 3.1.3 Register Configuration Register Descriptions. 3.2.1 Mode Control Register (MDCR) 3.2.2 System Control Register (SYSCR) 3.2.3 System Control Register (SYSCR2) (F-ZTAT Version Only) Operating Mode Descriptions 3.3.1 Mode 3.3.2 Mode (H8S/2398 F-ZTAT Only) 3.3.3 Mode (H8S/2398 F-ZTAT Only) 3.3.4 Mode (On-Chip Disabled Expansion Mode) 3.3.5 Mode (On-Chip Disabled Expansion Mode) 3.3.6 Mode (On-Chip Enabled Expansion Mode) 3.3.7 Mode (Single-Chip Mode) 3.3.8 Modes 3.3.9 Mode (H8S/2357 F-ZTAT Only) 3.3.10 Mode (H8S/2357 F-ZTAT Only) 3.3.11 Modes (H8S/2357 F-ZTAT Only). 3.3.12 Mode (H8S/2357 F-ZTAT Only) 3.3.13 Mode (H8S/2357 F-ZTAT Only) Functions Each Operating Mode. Memory Each Operating Mode.
Section Exception Handling
Overview 4.1.1 Exception Handling Types Priority. 4.1.2 Exception Handling Operation. 4.1.3 Exception Vector Table Reset 4.2.1 Overview 4.2.2 Reset Types
4.2.3 Reset Sequence. 4.2.4 Interrupts after Reset 4.2.5 State On-Chip Supporting Modules after Reset Release Traces Interrupts Trap Instruction Stack Status after Exception Handling Notes Stack
Section Interrupt Controller
Overview 5.1.1 Features 5.1.2 Block Diagram 5.1.3 Configuration 5.1.4 Register Configuration Register Descriptions. 5.2.1 System Control Register (SYSCR) 5.2.2 Interrupt Priority Registers (IPRA IPRK) 5.2.3 Enable Register (IER) 5.2.4 Sense Control Registers (ISCRH, ISCRL). 5.2.5 Status Register (ISR) Interrupt Sources 5.3.1 External Interrupts. 5.3.2 Internal Interrupts. 5.3.3 Interrupt Exception Handling Vector Table. Interrupt Operation 5.4.1 Interrupt Control Modes Interrupt Operation 5.4.2 Interrupt Control Mode 5.4.3 Interrupt Control Mode 5.4.4 Interrupt Exception Handling Sequence 5.4.5 Interrupt Response Times. Usage Notes. 5.5.1 Contention between Interrupt Generation Disabling. 5.5.2 Instructions that Disable Interrupts 5.5.3 Times when Interrupts Disabled. 5.5.4 Interrupts during Execution EEPMOV Instruction DMAC Activation Interrupt 5.6.1 Overview 5.6.2 Block Diagram 5.6.3 Operation
Section Controller.125
Overview
6.1.1 Features 6.1.2 Block Diagram 6.1.3 Configuration 6.1.4 Register Configuration Register Descriptions. 6.2.1 Width Control Register (ABWCR). 6.2.2 Access State Control Register (ASTCR) 6.2.3 Wait Control Registers (WCRH, WCRL) 6.2.4 Control Register (BCRH) 6.2.5 Control Register (BCRL). 6.2.6 Memory Control Register (MCR) 6.2.7 DRAM Control Register (DRAMCR) 6.2.8 Refresh Timer/Counter (RTCNT) 6.2.9 Refresh Time Constant Register (RTCOR) Overview Control. 6.3.1 Area Partitioning 6.3.2 Specifications 6.3.3 Memory Interfaces 6.3.4 Advanced Mode 6.3.5 Chip Select Signals. Basic Interface. 6.4.1 Overview 6.4.2 Data Size Data Alignment. 6.4.3 Valid Strobes. 6.4.4 Basic Timing 6.4.5 Wait Control. DRAM Interface. 6.5.1 Overview 6.5.2 Setting DRAM Space. 6.5.3 Address Multiplexing. 6.5.4 Data 6.5.5 Pins Used DRAM Interface 6.5.6 Basic Timing 6.5.7 Precharge State Control 6.5.8 Wait Control. 6.5.9 Byte Access Control. 6.5.10 Burst Operation 6.5.11 Refresh Control DMAC Single Address Mode DRAM Interface 6.6.1 When 6.6.2 When Burst Interface 6.7.1 Overview
6.7.2 Basic Timing 6.7.3 Wait Control. Idle Cycle. 6.8.1 Operation 6.8.2 States Idle Cycle Write Data Buffer Function. 6.10 Release 6.10.1 Overview 6.10.2 Operation 6.10.3 States External Released State 6.10.4 Transition Timing. 6.10.5 Usage Note 6.11 Arbitration 6.11.1 Overview 6.11.2 Operation 6.11.3 Transfer Timing 6.11.4 External Release Usage Note 6.12 Resets Controller
Section Controller.195
Overview 7.1.1 Features 7.1.2 Block Diagram 7.1.3 Overview Functions. 7.1.4 Configuration 7.1.5 Register Configuration. Register Descriptions (Short Address Mode) 7.2.1 Memory Address Registers (MAR) 7.2.2 Address Register (IOAR). 7.2.3 Execute Transfer Count Register (ETCR) 7.2.4 Control Register (DMACR). 7.2.5 Band Control Register (DMABCR). Register Descriptions (Full Address Mode) 7.3.1 Memory Address Register (MAR). 7.3.2 Address Register (IOAR). 7.3.3 Execute Transfer Count Register (ETCR) 7.3.4 Control Register (DMACR). 7.3.5 Band Control Register (DMABCR). Register Descriptions (3). 7.4.1 Write Enable Register (DMAWER) 7.4.2 Terminal Control Register (DMATCR). 7.4.3 Module Stop Control Register (MSTPCR) Operation
Transfer Modes Sequential Mode. Idle Mode Repeat Mode Single Address Mode Normal Mode Block Transfer Mode DMAC Activation Sources Basic DMAC Cycles. DMAC Cycles (Dual Address Mode). DMAC Cycles (Single Address Mode) Write Data Buffer Function DMAC Multi-Channel Operation Relation between External Requests, Refresh Cycles, DTC, DMAC 7.5.15 Interrupts DMAC. 7.5.16 Forced Termination DMAC Operation. 7.5.17 Clearing Full Address Mode Interrupts Usage Notes.
7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.5.11 7.5.12 7.5.13 7.5.14
Section Data Transfer Controller.285
Overview 8.1.1 Features 8.1.2 Block Diagram 8.1.3 Register Configuration Register Descriptions. 8.2.1 Mode Register (MRA). 8.2.2 Mode Register (MRB). 8.2.3 Source Address Register (SAR) 8.2.4 Destination Address Register (DAR) 8.2.5 Transfer Count Register (CRA) 8.2.6 Transfer Count Register (CRB). 8.2.7 Enable Registers (DTCER) 8.2.8 Vector Register (DTVECR) 8.2.9 Module Stop Control Register (MSTPCR) Operation 8.3.1 Overview 8.3.2 Activation Sources 8.3.3 Vector Table 8.3.4 Location Register Information Address Space 8.3.5 Normal Mode 8.3.6 Repeat Mode
8.3.7 Block Transfer Mode 8.3.8 Chain Transfer. 8.3.9 Operation Timing 8.3.10 Number Execution States 8.3.11 Procedures Using DTC. 8.3.12 Examples Interrupts Usage Notes.
Section Ports .315
Overview Port 9.2.1 Overview 9.2.2 Register Configuration 9.2.3 Functions. Port 9.3.1 Overview 9.3.2 Register Configuration 9.3.3 Functions. Port 9.4.1 Overview 9.4.2 Register Configuration 9.4.3 Functions. Port 9.5.1 Overview 9.5.2 Register Configuration 9.5.3 Functions. Port 9.6.1 Overview 9.6.2 Register Configuration 9.6.3 Functions. Port 9.7.1 Overview 9.7.2 Register Configuration 9.7.3 Functions. Port 9.8.1 Overview 9.8.2 Register Configuration 9.8.3 Functions. 9.8.4 Input Pull-Up Function (On-Chip Version Only) Port 9.9.1 Overview 9.9.2 Register Configuration (On-Chip Version Only).
9.10
9.11
9.12
9.13
9.14
9.9.3 Functions. 9.9.4 Input Pull-Up Function (On-Chip Version Only) Port 9.10.1 Overview 9.10.2 Register Configuration (On-Chip Version Only). 9.10.3 Functions. 9.10.4 Input Pull-Up Function (On-Chip Version Only). Port 9.11.1 Overview 9.11.2 Register Configuration (On-Chip Version Only). 9.11.3 Functions. 9.11.4 Input Pull-Up Function (On-Chip Version Only) Port 9.12.1 Overview 9.12.2 Register Configuration 9.12.3 Functions. 9.12.4 Input Pull-Up Function (On-Chip Version Only) Port 9.13.1 Overview 9.13.2 Register Configuration 9.13.3 Functions. Port 9.14.1 Overview 9.14.2 Register Configuration 9.14.3 Functions.
Section 16-Bit Timer Pulse Unit (TPU) .399
10.1 Overview 10.1.1 Features 10.1.2 Block Diagram 10.1.3 Configuration 10.1.4 Register Configuration 10.2 Register Descriptions. 10.2.1 Timer Control Register (TCR) 10.2.2 Timer Mode Register (TMDR) 10.2.3 Timer Control Register (TIOR) 10.2.4 Timer Interrupt Enable Register (TIER) 10.2.5 Timer Status Register (TSR) 10.2.6 Timer Counter (TCNT) 10.2.7 Timer General Register (TGR) 10.2.8 Timer Start Register (TSTR). 10.2.9 Timer Synchro Register (TSYR) 10.2.10 Module Stop Control Register (MSTPCR)
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10.3 Interface Master 10.3.1 16-Bit Registers. 10.3.2 8-Bit Registers. 10.4 Operation 10.4.1 Overview 10.4.2 Basic Functions 10.4.3 Synchronous Operation 10.4.4 Buffer Operation 10.4.5 Cascaded Operation 10.4.6 Modes 10.4.7 Phase Counting Mode 10.5 Interrupts 10.5.1 Interrupt Sources Priorities. 10.5.2 DTC/DMAC Activation. 10.5.3 Converter Activation 10.6 Operation Timing 10.6.1 Input/Output Timing 10.6.2 Interrupt Signal Timing 10.7 Usage Notes.
Section Programmable Pulse Generator (PPG) .491
11.1 Overview 11.1.1 Features 11.1.2 Block Diagram 11.1.3 Configuration 11.1.4 Registers. 11.2 Register Descriptions. 11.2.1 Next Data Enable Registers (NDERH, NDERL). 11.2.2 Output Data Registers (PODRH, PODRL) 11.2.3 Next Data Registers (NDRH, NDRL). 11.2.4 Notes Access. 11.2.5 Output Control Register (PCR) 11.2.6 Output Mode Register (PMR) 11.2.7 Port Data Direction Register (P1DDR). 11.2.8 Port Data Direction Register (P2DDR). 11.2.9 Module Stop Control Register (MSTPCR) 11.3 Operation 11.3.1 Overview 11.3.2 Output Timing 11.3.3 Normal Pulse Output 11.3.4 Non-Overlapping Pulse Output 11.3.5 Inverted Pulse Output. 11.3.6 Pulse Output Triggered Input Capture
11.4 Usage Notes.
Section 8-Bit Timers.517
12.1 Overview 12.1.1 Features 12.1.2 Block Diagram 12.1.3 Configuration 12.1.4 Register Configuration 12.2 Register Descriptions. 12.2.1 Timer Counters (TCNT0, TCNT1) 12.2.2 Time Constant Registers (TCORA0, TCORA1). 12.2.3 Time Constant Registers (TCORB0, TCORB1). 12.2.4 Time Control Registers (TCR0, TCR1) 12.2.5 Timer Control/Status Registers (TCSR0, TCSR1) 12.2.6 Module Stop Control Register (MSTPCR) 12.3 Operation 12.3.1 TCNT Incrementation Timing 12.3.2 Compare Match Timing 12.3.3 Timing External RESET TCNT 12.3.4 Timing Overflow Flag (OVF) Setting 12.3.5 Operation with Cascaded Connection 12.4 Interrupts 12.4.1 Interrupt Sources Activation. 12.4.2 Converter Activation 12.5 Sample Application 12.6 Usage Notes. 12.6.1 Contention between TCNT Write Clear. 12.6.2 Contention between TCNT Write Increment 12.6.3 Contention between TCOR Write Compare Match 12.6.4 Contention between Compare Matches 12.6.5 Switching Internal Clocks TCNT Operation 12.6.6 Interrupts Module Stop Mode
Section Watchdog Timer .541
13.1 Overview 13.1.1 Features 13.1.2 Block Diagram 13.1.3 Configuration 13.1.4 Register Configuration 13.2 Register Descriptions. 13.2.1 Timer Counter (TCNT) 13.2.2 Timer Control/Status Register (TCSR) 13.2.3 Reset Control/Status Register (RSTCSR)
13.2.4 Notes Register Access. 13.3 Operation 13.3.1 Watchdog Timer Operation 13.3.2 Interval Timer Operation 13.3.3 Timing Setting Overflow Flag (OVF) 13.3.4 Timing Setting Watchdog Timer Overflow Flag (WOVF). 13.4 Interrupts 13.5 Usage Notes. 13.5.1 Contention between Timer Counter (TCNT) Write Increment. 13.5.2 Changing Value CKS2 CKS0. 13.5.3 Switching between Watchdog Timer Mode Interval Timer Mode 13.5.4 System Reset WDTOVF Signal 13.5.5 Internal Reset Watchdog Timer Mode.
Section Serial Communication Interface (SCI) .557
14.1 Overview 14.1.1 Features 14.1.2 Block Diagram 14.1.3 Configuration 14.1.4 Register Configuration 14.2 Register Descriptions. 14.2.1 Receive Shift Register (RSR). 14.2.2 Receive Data Register (RDR) 14.2.3 Transmit Shift Register (TSR) 14.2.4 Transmit Data Register (TDR). 14.2.5 Serial Mode Register (SMR). 14.2.6 Serial Control Register (SCR). 14.2.7 Serial Status Register (SSR). 14.2.8 Rate Register (BRR). 14.2.9 Smart Card Mode Register (SCMR) 14.2.10 Module Stop Control Register (MSTPCR) 14.3 Operation 14.3.1 Overview 14.3.2 Operation Asynchronous Mode 14.3.3 Multiprocessor Communication Function 14.3.4 Operation Clocked Synchronous Mode. 14.4 Interrupts 14.5 Usage Notes.
Section Smart Card Interface .621
15.1 Overview 15.1.1 Features 15.1.2 Block Diagram
15.1.3 Configuration 15.1.4 Register Configuration 15.2 Register Descriptions. 15.2.1 Smart Card Mode Register (SCMR) 15.2.2 Serial Status Register (SSR). 15.2.3 Serial Mode Register (SMR). 15.2.4 Serial Control Register (SCR). 15.3 Operation 15.3.1 Overview 15.3.2 Connections 15.3.3 Data Format. 15.3.4 Register Settings. 15.3.5 Clock 15.3.6 Data Transfer Operations 15.3.7 Operation Mode. 15.4 Usage Notes.
Section Converter .649
16.1 Overview 16.1.1 Features 16.1.2 Block Diagram 16.1.3 Configuration 16.1.4 Register Configuration 16.2 Register Descriptions. 16.2.1 Data Registers (ADDRA ADDRD) 16.2.2 Control/Status Register (ADCSR) 16.2.3 Control Register (ADCR). 16.2.4 Module Stop Control Register (MSTPCR) 16.3 Interface Master 16.4 Operation 16.4.1 Single Mode (SCAN 16.4.2 Scan Mode (SCAN 16.4.3 Input Sampling Conversion Time 16.4.4 External Trigger Input Timing 16.5 Interrupts 16.6 Usage Notes.
Section Converter .671
17.1 Overview 17.1.1 Features 17.1.2 Block Diagram 17.1.3 Configuration 17.1.4 Register Configuration
17.2 Register Descriptions. 17.2.1 Data Registers (DADR0, DADR1) 17.2.2 Control Register (DACR). 17.2.3 Module Stop Control Register (MSTPCR) 17.3 Operation
Section RAM.679
18.1 Overview 18.1.1 Block Diagram 18.1.2 Register Configuration 18.2 Register Descriptions. 18.2.1 System Control Register (SYSCR) 18.3 Operation 18.4 Usage Note
Section ROM.683
19.1 Overview 19.1.1 Block Diagram 19.1.2 Register Configuration 19.2 Register Descriptions. 19.2.1 Mode Control Register (MDCR). 19.2.2 Control Register (BCRL). 19.3 Operation 19.4 PROM Mode (H8S/2357 ZTAT) 19.4.1 PROM Mode Setting. 19.4.2 Socket Adapter Memory 19.5 Programming (H8S/2357 ZTAT) 19.5.1 Overview 19.5.2 Programming Verification. 19.5.3 Programming Precautions 19.5.4 Reliability Programmed Data 19.6 Overview Flash Memory (H8S/2357 F-ZTAT). 19.6.1 Features 19.6.2 Block Diagram 19.6.3 Flash Memory Operating Modes 19.6.4 Configuration 19.6.5 Register Configuration 19.7 Register Descriptions. 19.7.1 Flash Memory Control Register (FLMCR1). 19.7.2 Flash Memory Control Register (FLMCR2). 19.7.3 Erase Block Registers (EBR1, EBR2). 19.7.4 System Control Register (SYSCR2) 19.7.5 Emulation Register (RAMER).
xiii
19.8 On-Board Programming Modes 19.8.1 Boot Mode. 19.8.2 User Program Mode 19.9 Programming/Erasing Flash Memory 19.9.1 Program Mode. 19.9.2 Program-Verify Mode 19.9.3 Erase Mode. 19.9.4 Erase-Verify Mode. 19.10 Flash Memory Protection 19.10.1 Hardware Protection. 19.10.2 Software Protection 19.10.3 Error Protection 19.11 Flash Memory Emulation RAM. 19.11.1 Emulation RAM. 19.11.2 Overlap. 19.12 Interrupt Handling when Programming/Erasing Flash Memory. 19.13 Flash Memory Programmer Mode 19.13.1 Programmer Mode Setting 19.13.2 Socket Adapters Memory 19.13.3 Programmer Mode Operation. 19.13.4 Memory Read Mode. 19.13.5 Auto-Program Mode 19.13.6 Auto-Erase Mode 19.13.7 Status Read Mode. 19.13.8 Status Polling 19.13.9 Programmer Mode Transition Time. 19.13.10 Notes Memory Programming 19.14 Flash Memory Programming Erasing Precautions. 19.15 Overview Flash Memory (H8S/2398 F-ZTAT). 19.15.1 Features 19.15.2 Overview 19.15.3 Flash Memory Operating Modes. 19.15.4 On-Board Programming Modes. 19.15.5 Flash Memory Emulation RAM. 19.15.6 Differences between Boot Mode User Program Mode 19.15.7 Block Configuration. 19.15.8 Configuration 19.15.9 Register Configuration 19.16 Register Descriptions. 19.16.1 Flash Memory Control Register (FLMCR1). 19.16.2 Flash Memory Control Register (FLMCR2). 19.16.3 Erase Block Register (EBR1) 19.16.4 Erase Block Registers (EBR2)
19.17
19.18
19.19
19.20
19.21 19.22
19.23
19.16.5 System Control Register (SYSCR2) 19.16.6 Emulation Register (RAMER). On-Board Programming Modes 19.17.1 Boot Mode 19.17.2 User Program Mode Programming/Erasing Flash Memory 19.18.1 Program Mode. 19.18.2 Program-Verify Mode 19.18.3 Erase Mode. 19.18.4 Erase-Verify Mode. Flash Memory Protection 19.19.1 Hardware Protection. 19.19.2 Software Protection 19.19.3 Error Protection Flash Memory Emulation RAM. 19.20.1 Emulation RAM. 19.20.2 Overlap. Interrupt Handling when Programming/Erasing Flash Memory. Flash Memory Programmer Mode 19.22.1 Programmer Mode Setting 19.22.2 Socket Adapters Memory 19.22.3 Programmer Mode Operation. 19.22.4 Memory Read Mode. 19.22.5 Auto-Program Mode 19.22.6 Auto-Erase Mode 19.22.7 Status Read Mode. 19.22.8 Status Polling 19.22.9 Programmer Mode Transition Time. 19.22.10 Notes Memory Programming Flash Memory Programming Erasing Precautions.
Section Clock Pulse Generator .799
20.1 Overview 20.1.1 Block Diagram 20.1.2 Register Configuration 20.2 Register Descriptions. 20.2.1 System Clock Control Register (SCKCR) 20.3 Oscillator 20.3.1 Connecting Crystal Resonator. 20.3.2 External Clock Input 20.4 Duty Adjustment Circuit 20.5 Medium-Speed Clock Divider. 20.6 Master Clock Selection Circuit
Section Power-Down Modes .809
21.1 Overview 21.1.1 Register Configuration 21.2 Register Descriptions. 21.2.1 Standby Control Register (SBYCR) 21.2.2 System Clock Control Register (SCKCR) 21.2.3 Module Stop Control Register (MSTPCR) 21.3 Medium-Speed Mode 21.4 Sleep Mode. 21.5 Module Stop Mode 21.5.1 Module Stop Mode. 21.5.2 Usage Notes 21.6 Software Standby Mode 21.6.1 Software Standby Mode. 21.6.2 Clearing Software Standby Mode 21.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode 21.6.4 Software Standby Mode Application Example 21.6.5 Usage Notes 21.7 Hardware Standby Mode. 21.7.1 Hardware Standby Mode 21.7.2 Hardware Standby Mode Timing. 21.8 Clock Output Disabling Function.
Section Electrical Characteristics .823
22.1 Electrical Characteristics Mask Version (H8S/2398) ROMless Versions (H8S/2394, H8S/2392, H8S/2390). 22.1.1 Absolute Maximum Ratings. 22.1.2 Characteristics 22.1.3 Characteristics 22.1.4 Conversion Characteristics. 22.1.5 Conversion Characteristics. 22.2 Usage Note (Internal Voltage Step Down H8S/2398, H8S/2394, H8S/2392, H8S/2390). 22.3 Electrical Characteristics H8S/2398 F-ZTAT. 22.3.1 Absolute Maximum Ratings. 22.3.2 Characteristics 22.3.3 Characteristics 22.3.4 Conversion Characteristics. 22.3.5 Conversion Characteristics. 22.3.6 Flash Memory Characteristics 22.4 Notes 22.5 Usage Note (Internal Voltage Step Down H8S/2398 F-ZTAT)
22.6 Electrical Characteristics H8S/2357 Mask ZTAT Versions, H8S/2352 22.6.1 Absolute Maximum Ratings. 22.6.2 Characteristics 22.6.3 Characteristics 22.6.4 Conversion Characteristics. 22.6.5 Convervion Characteristics 22.7 Electrical Characteristics H8S/2357 F-ZTAT. 22.7.1 Absolute Maximum Ratings. 22.7.2 Characteristics 22.7.3 Characteristics 22.7.4 Conversion Characteristics. 22.7.5 Conversion Characteristics. 22.7.6 Flash Memory Characteristics 22.8 Usage Note
Appendix Instruction Set.943
Instruction List. Instruction Codes. Operation Code Number States Required Instruction Execution States During Instruction Execution 1000 Condition Code Modification. 1014
Appendix Internal Register 1020
Addresses. 1020 Functions 1030
Appendix Port Block Diagrams 1172
C.10 C.11 C.12 C.13 Port Block Diagram. Port Block Diagram. Port Block Diagram. Port Block Diagram. Port Block Diagram. Port Block Diagram. Port Block Diagram. Port Block Diagram Port Block Diagram Port Block Diagram. Port Block Diagram Port Block Diagram Port Block Diagram. 1172 1175 1179 1182 1183 1187 1193 1196 1197 1198 1199 1200 1208
xvii
Appendix States.1211
Port States Each Mode 1211
Appendix States Power-On.1215
When Pins Settle from Indeterminate State Power-On 1215 When Pins Settle from High-Impedance State Power-On. 1216
Appendix Timing Transition Recovery from Hardware Standby Mode .1218
Timing Transition Hardware Standby Mode 1218 Timing Recovery from Hardware Standby Mode. 1218
Appendix Product Code Lineup .1219 Appendix Package Dimensions .1220
xviii
Section Overview
Overview
H8S/2357 Series series microcomputers (MCUs: microcomputer units), built around H8S/2000 CPU, employing Hitachi's proprietary architecture, equipped with peripheral functions on-chip. H8S/2000 internal 32-bit architecture, provided with sixteen 16-bit general registers concise, optimized instruction designed high-speed operation, address 16-Mbyte linear address space. instruction upward-compatible with H8/300 H8/300H instructions object-code level, facilitating migration from H8/300, H8/300L, H8/300H Series. On-chip peripheral functions required system configuration include controller (DMAC) data transfer controller (DTC) masters, memory, 16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports. Single-power-supply flash memory (F-ZTAT*1), PROM (ZTAT*2), mask versions available, providing quick flexible response conditions from ramp-up through full-scale volume production, even applications with frequently changing specifications. features H8S/2357 Series shown table 1-1. Notes: F-ZTAT trademark Hitachi, Ltd. ZTAT trademark Hitachi, Ltd.
Table
Item
Overview
Specification General-register machine Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) High-speed operation suitable realtime control Maximum clock rate: High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 16-bit register-register multiply: 1000 16-bit register-register divide: 1000 Instruction suitable high-speed operation Sixty-five basic instructions 8/16/32-bit move/arithmetic logic instructions Unsigned/signed multiply divide instructions Powerful bit-manipulation instructions operating modes Advanced mode: 16-Mbyte address space Address space divided into areas, with specifications settable independently each area Chip select output possible each area Choice 8-bit 16-bit access space each area 2-state 3-state access space designated each area Number program wait states each area Burst directly connectable Maximum 8-Mbyte DRAM directly connectable interval timer possible) External release function Choice short address mode full address mode channels short address mode channels full address mode Transfer possible repeat mode, block transfer mode, etc. Single address mode transfer possible activated internal interrupt activated internal interrupt software Multiple transfers multiple types transfer possible activation source Transfer possible repeat mode, block transfer mode, etc. Request sent interrupt that activated
controller controller (DMAC)
Data transfer controller (DTC)
Item 16-bit timer-pulse unit (TPU) Programmable pulse generator (PPG)
Specification 6-channel 16-bit timer on-chip Pulse processing capability pins' Automatic 2-phase encoder count capability Maximum 16-bit pulse output possible with time base Output trigger selectable 4-bit groups Non-overlap margin Direct output inverse output setting possible 8-bit up-counter (external event count capability) time constant registers Two-channel connection possible Watchdog timer interval timer selectable Asynchronous mode synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: bits Input: channels High-speed conversion: minimum conversion time operation) Single scan mode selectable Sample hold circuit conversion activated external trigger timer trigger Resolution: bits Output: channels pins, input-only pins
8-bit timer channels Watchdog timer Serial communication interface (SCI) channels converter
converter ports Memory
Flash memory, PROM, Mask High-speed static Product Name H8S/2357 H8S/2352 H8S/2398 H8S/2394 H8S/2392 H8S/2390 kbytes kbytes
kbytes kbytes kbytes kbytes kbytes kbytes
Item Interrupt controller
Specification Nine external interrupt pins (NMI, IRQ0 IRQ7) internal interrupt sources Eight priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Eight operating modes (H8S/2357 F-ZTAT) External Data On-Chip Initial Value Maximum Value
Power-down state
Operating modes
Operating Mode Mode Description Advanced User program mode Advanced Boot mode Advanced On-chip disabled expansion mode On-chip enabled expansion mode Single-chip mode
Disabled bits bits Enabled bits
bits bits bits
Enabled
bits
bits
Enabled
bits
bits
Item Operating
Specification Four operating modes (H8S/2398 F-ZTAT, mask ROM, ROMless, ZTAT) modes External Data Operating On-Chip Initial Maximum Mode Mode Description Value Value Advanced On-chip disabled Disabled bits bits expansion mode On-chip disabled Disabled bits bits expansion mode On-chip enabled Enabled bits bits expansion mode Single-chip mode Enabled Notes: H8S/2398 F-ZTAT, modes indicate boot mode. details boot mode H8S/2398 F-ZTAT, refer table 19-35 section 19.17, On-Board Programming Modes. addition, details user program mode, refer also tables 19-35 section 19.17, On-Board Programming Modes. ROMless version, only modes available. Clock pulse Built-in duty correction circuit generator 120-pin plastic TQFP (TFP-120) Packages plastic (FP-128B)
Item Product lineup
Specification version Operating Supply Voltage Operating Frequency ROMless HD6412352F20 Version HD6412352TE20 version
HD6412394F20 HD6412394TE20 HD6412392F20 HD6412392TE20 HD6412390F20 HD6412390TE20
version
HD6412352F10 HD6412352TE10
HD6412352F13 HD6412352TE13
Mask Version* F-ZTAT Version* ZTAT Version Packages
HD6432357(A**)F HD6432398(A**)F HD6432357(A**)TE HD6432398(A**)TE HD64F2357F20 HD64F2357TE20 HD6472357F20 HD6472357TE20 HD64F2398F20 HD64F2398TE20
HD6432357(M**)F HD6432357(K**)F HD6432357(M**)TE HD6432357(K**)TE HD64F2357VF13 HD64F2357VTE13 HD6472357F13 HD6472357TE13 HD6472357F10 HD6472357TE10
FP-128B FP-128B FP-128B TFP-120 TFP-120 TFP-120 Notes: mask versions, (**) code. sections 22.3.6 22.7.6, Flash Memory Characteristics, flash version operating supply voltage temperature range programming/erasing.
Block Diagram
Figure shows internal block diagram H8S/2357 Series.
Port
Port
Internal data
H8S/2000
Internal address
controller
EXTAL XTAL STBY WDTOVF (FWE, VCL)*1
Port
Clock pulse generator
/A23 /IRQ7 /A22 /IRQ6 /A21 /IRQ5 /A20 /IRQ4 /A19 /A18 /A17 /A16 /A15 /A14 /A13 /A12 /A10 /SCK1 /SCK0 /RxD1 /RxD0 /TxD1 /TxD0 /TxD2 /RxD2 /SCK2 /ADTRG
Interrupt controller /HWR /LWR /LCAS/WAIT/BREQO /BACK /BREQ /CS0 /CS1 /CS2 /CS3 /CAS /CS7/IRQ3 /CS6/IRQ2 /IRQ1 /IRQ0 /TEND1 /DREQ1 /TEND0/CS5 /DREQ0/CS4
Port
Peripheral address Peripheral data
ROM*2 Port
DMAC
Port Port 8-bit timer
converter Port
Port
converter
Port
Port
Port
Vref AVCC AVSS
Port
TIOCA0 DACK0 TIOCB0 DACK1 PO10 TIOCC0 TCLKA PO11 TIOCD0 TCLKB PO12 TIOCA1 PO13 TIOCB1 TCLKC PO14 TIOCA2 PO15 TIOCB2 TCLKD
Notes: This functions WDTOVF function ZTAT, mask products, H8S/2352. H8S/2357F-ZTAT, WDTOVF function available, because this used pin. H8S/2398, H8S/2394, H8S/2392, H8S/2390, WDTOVF function available, because this used pin. ROMless version, supported.
Figure Block Diagram
TIOCA3 TIOCB3 TIOCC3 TMRI0 TIOCD3 TMCI0 TIOCA4 TMRI1 TIOCB4 TMCI1 TIOCA5 TMO0 TIOCB5 TMO1
1.3.1
Description
Arrangement
Figures show arrangement H8S/2357, H8S/2352 figures show arrangements H8S/2398, H8S/2394, H8S/2392, H8S/2390.
/RxD2 /TxD2 /BREQ /BACK /LCAS/WAIT /BREQO /LWR /HWR EXTAL XTAL STBY WDTOVF (FWE)* /PO0/TIOCA3 /PO1/TIOCB3 /PO2/TIOCC3/TMRI0 /PO3/TIOCD3/TMCI0 /PO4/TIOCA4/TMRI1 /PO5/TIOCB4/TMCI1 /PO6/TIOCA5/TMO0 /PO7/TIOCB5/TMO1 /TEND1 /DREQ1 /TEND0 /CS5
Note: This WDTOVF function ZTAT, mask ROM, ROMless versions. F-ZTAT version, WDTOVF function available, this pin.
Figure H8S/2357, H8S/2352 Arrangement (TFP-120: View)
/A10 /A11 /A12 /A13 /A14 /A15 /A16 /A17 /A18 /A19 /A20 /IRQ4 /A21 /IRQ5 /A22 /IRQ6 /A23 /IRQ7 /CS7/IRQ3 /CS6/IRQ2
SCK2 ADTRG AVCC Vref AVSS TCLKD TIOCB2 PO15 TIOCA2 PO14 TCLKC TIOCB1 PO13 TIOCA1 PO12 TCLKB TIOCD0 PO11 TCLKA TIOCC0 PO10 DACK1 TIOCB0 DACK0 TIOCA0
DREQ0 SCK1 SCK0 RxD1 RxD0 TxD1 TxD0 IRQ0 IRQ1
Note: This WDTOVF function ZTAT, mask ROM, ROMless versions. F-ZTAT version, WDTOVF function available, this pin.
Figure H8S/2357, H8S/2352 Arrangement (FP-128B: View)
/CS1 /CS0 /A10 /A11 /A12 /A13 /A14 /A15 /A16 /A17 /A18 /A19 /A20 /IRQ4 /A21 /IRQ5 /A22 /IRQ6 /A23 /IRQ7 /CS7/IRQ3 /CS6/IRQ2 /IRQ1 /IRQ0
AVCC Vref AVSS TCLKD TIOCB2 PO15 TIOCA2 PO14 TCLKC TIOCB1 PO13 TIOCA1 PO12 TCLKB TIOCD0 PO11 TCLKA TIOCC0 PO10 DACK1/ TIOCB0 DACK0/ TIOCA0 CAS/ CS3/ CS2/
/ADTRG /SCK2 /RxD2 /TxD2 /BREQ /BACK /LCAS/WAIT/BREQO /LWR /HWR EXTAL XTAL STBY WDTOVF (FWE*) /PO0/TIOCA3 /PO1/TIOCB3 /PO2/TIOCC3/TMRI0 /PO3/TIOCD3/TMCI0 /PO4/TIOCA4/TMRI1 /PO5/TIOCB4/TMCI1 /PO6/TIOCA5/TMO0 /PO7/TIOCB5/TMO1 /TEND1 /DREQ1 /TEND0/CS5 /DREQ0/CS4
SCK1 SCK0 RxD1 RxD0 TxD1 TxD0
/RxD2 /TxD2 /BREQ /BACK /LCAS/WAIT/BREQO /LWR /HWR EXTAL XTAL STBY /PO0/TIOCA3 /PO1/TIOCB3 /PO2/TIOCC3/TMRI0 /PO3/TIOCD3/TMCI0 /PO4/TIOCA4/TMRI1 /PO5/TIOCB4/TMCI1 /PO6/TIOCA5/TMO0 /PO7/TIOCB5/TMO1 /TEND1 /DREQ1 /TEND0/CS5
Figure H8S/2398, H8S/2394, H8S/2392, H8S/2390 Arrangement (FP-120: View)
/A10 /A11 /A12 /A13 /A14 /A15 /A16 /A17 /A18 /A19 /A20 /IRQ4 /A21 /IRQ5 /A22 /IRQ6 /A23 /IRQ7 /CS7/IRQ3 /CS6/IRQ2
SCK2 ADTRG/ AVCC Vref AVSS TCLKD TIOCB2 PO15 TIOCA2 PO14 TCLKC TIOCB1 PO13 TIOCA1 PO12 TCLKB TIOCD0 PO11 TCLKA TIOCC0 PO10 DACK1/ TIOCB0 DACK0/ TIOCA0 CAS/ CS3/ CS2/ CS1/ CS0/
DREQ0/ SCK1 SCK0 RxD1 RxD0 TxD1 TxD0 IRQ0 IRQ1
Figure H8S/2398, H8S/2394, H8S/2392, H8S/2390 Arrangement (FP-128B: View)
/CS1 /CS0 /A10 /A11 /A12 /A13 /A14 /A15 /A16 /A17 /A18 /A19 /A20 /IRQ4 /A21 /IRQ5 /A22 /IRQ6 /A23 /IRQ7 /CS7/IRQ3 /CS6/IRQ2 /IRQ1 /IRQ0
AVCC Vref AVSS TCLKD TIOCB2 PO15 TIOCA2 PO14 TCLKC TIOCB1 PO13 TIOCA1 PO12 TCLKB TIOCD0 PO11 TCLKA TIOCC0 PO10 DACK1/ TIOCB0 DACK0/ TIOCA0 CAS/
SCK1 SCK0 RxD1 RxD0 TxD1 TxD0
/ADTRG /SCK2 /RxD2 /TxD2 /BREQ /BACK /LCAS/WAIT/BREQO /LWR /HWR EXTAL XTAL STBY /PO0/TIOCA3 /PO1/TIOCB3 /PO2/TIOCC3/TMRI0 /PO3/TIOCD3/TMCI0 /PO4/TIOCA4/TMRI1 /PO5/TIOCB4/TMCI1 /PO6/TIOCA5/TMO0 /PO7/TIOCB5/TMO1 /TEND1 /DREQ1 /TEND0/CS5 /DREQ0/CS4
1.3.2
Functions Each Operating Mode
Table shows functions H8S/2357 Series each operating modes. Table
Functions Each Operating Mode
Name PROM Mode Flash Memory Programmer Mode (A9)*3 (A17)*3 (A18)*3
TFP-120
FP-128B
Mode IRQ5
Mode IRQ5
Mode PC0/A PC1/A PC2/A PC3/A PC4/A PC5/A PC6/A PC7/A IRQ4 IRQ5
Mode 4/IRQ4 5/IRQ5
Name PROM Mode Flash Memory Programmer Mode I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 (VCC)*3
TFP-120
FP-128B
Mode IRQ6 IRQ7 P67/IRQ3/ P66/IRQ2/ P65/IRQ1 P64/IRQ0 0/D0 1/D1 2/D2 3/D3 4/D4 5/D5 6/D6 7/D7 P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1
Mode IRQ6 IRQ7 P67/IRQ3/ P66/IRQ2/ P65/IRQ1 P64/IRQ0 0/D0 1/D1 2/D2 3/D3 4/D4 5/D5 6/D6 7/D7 P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1
Mode IRQ6 IRQ7 P67/IRQ3/ P66/IRQ2/ P65/IRQ1 P64/IRQ0 0/D0 1/D1 2/D2 3/D3 4/D4 5/D5 6/D6 7/D7 P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1
Mode 6/IRQ6 7/IRQ7 P67/IRQ3 P66/IRQ2 P65/IRQ1 P64/IRQ0 P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1
TFP120 FP128B
Name PROM Mode Flash Memory Programmer Mode (VSS)*3 (VCL)*2 (VCC)*3 XTAL
Mode P34/SCK0 P35/SCK1 P60/ DREQ0/ P61/TEND0/ P62/DREQ1 P63/TEND1
Mode P34/SCK0 P35/SCK1 P60/ DREQ0/ P61/TEND0/ P62/DREQ1 P63/TEND1
Mode P34/SCK0 P35/SCK1 P60/ DREQ0/ P61/TEND0/ P62/DREQ1 P63/TEND1
Mode P34/SCK0 P35/SCK1 P60/DREQ0 P61/TEND0 P62/DREQ1 P63/TEND1
P27/PO7/ P27/PO7/ P27/PO7/ P27/PO7/ TIOCB5/ TMO1 TIOCB5/ TMO1 TIOCB5/ TMO1 TIOCB5/ TMO1 P26/PO6/ P26/PO6/ P26/PO6/ P26/PO6/ TIOCA5/ TMO0 TIOCA5/ TMO0 TIOCA5/ TMO0 TIOCA5/ TMO0 P25/PO5/ P25/PO5/ P25/PO5/ P25/PO5/ TIOCB4/ TMCI1 TIOCB4/ TMCI1 TIOCB4/ TMCI1 TIOCB4/ TMCI1 P24/PO4/ P24/PO4/ P24/PO4/ P24/PO4/ TIOCA4/ TMRI1 TIOCA4/ TMRI1 TIOCA4/ TMRI1 TIOCA4/ TMRI1 P23/PO3/ P23/PO3/ P23/PO3/ P23/PO3/ TIOCD3/ TMCI0 TIOCD3/ TMCI0 TIOCD3/ TMCI0 TIOCD3/ TMCI0 P22/PO2/ P22/PO2/ P22/PO2/ P22/PO2/ TIOCC3/ TMRI0 TIOCC3/ TMRI0 TIOCC3/ TMRI0 TIOCC3/ TMRI0 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF (FWE)*2 (VCL)*2 STBY XTAL P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF (FWE)*2 (VCL)*2 STBY XTAL P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF (FWE)*2 (VCL)*2 STBY XTAL P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF (FWE)*2 (VCL)*2 STBY XTAL
Name PROM Mode Flash Memory Programmer Mode EXTAL
TFP-120
FP-128B
Mode EXTAL PF2/LCAS/ WAIT/ BREQO PF1/BACK PF0/BREQ P50/TxD2 P51/RxD2 P52/SCK2 P53/ADTRG Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ P47/AN7/ P17/PO15/ TIOCB2/ TCLKD
Mode EXTAL PF2/LCAS/ WAIT/ BREQO PF1/BACK PF0/BREQ P50/TxD2 P51/RxD2 P52/SCK2 P53/ADTRG Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ P47/AN7/ P17/PO15/ TIOCB2/ TCLKD
Mode EXTAL PF2/LCAS/ WAIT/ BREQO PF1/BACK PF0/BREQ P50/TxD2 P51/RxD2 P52/SCK2 P53/ADTRG Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ P47/AN7/ P17/PO15/ TIOCB2/ TCLKD
Mode EXTAL
P50/TxD2 P51/RxD2 P52/SCK2 P53/ADTRG Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ P47/AN7/ P17/PO15/ TIOCB2/ TCLKD
(NC)*3
Name PROM Mode Flash Memory Programmer Mode
TFP-120
FP-128B
Mode P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 0/CAS 1/CS3 2/CS2 3/CS1 4/CS0
Mode P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 0/CAS 1/CS3 2/CS2 3/CS1 4/CS0
Mode P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 0/CAS 1/CS3 2/CS2 3/CS1 4/CS0
Mode P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0
Notes: pins should connected left open. ROMless version, only modes available. This functions WDTOVF function ZTAT, mask products, H8S/2352. H8S/2357F-ZTAT, WDTOVF function available, because this used pin. H8S/2398, H8S/2394, H8S/2392, H8S/2390, WDTOVF function available, because this used pin. names parentheses available other than H8S/2357 F-ZTAT.
1.3.3
Functions
Table outlines functions H8S/2357 Series. Table Functions
Type Power Symbol TFP-120 FP-128B 100, Input Name Function Power supply: connection power supply. pins should connected system power supply. Ground: connection ground pins should connected system power supply
Input
Internal voltage VCL*1 step-down drop Clock XTAL
INPUT Connects external capacitor between this ground This should never connected VCC. Input Connects crystal oscillator. section Clock Pulse Generator, typical connection diagrams crystal oscillator external clock input. Connects crystal oscillator. EXTAL also input external clock. section Clock Pulse Generator, typical connection diagrams crystal oscillator external clock input.
EXTAL
Input
Output System clock: Supplies system clock external device.
Type Symbol TFP-120 FP-128B Input Name Function Mode pins: These pins operating mode. relation between settings pins operating mode shown below. These pins should changed while H8S/2357 Series operating. Operating Mode Mode Mode Mode Mode
Operating mode control
Note: ROMless version, only modes available. System control Input Reset input: When this driven low, chip reset. type reset selected according input level. power-on, input level should high. Standby: When this driven low, transition made hardware standby mode. request: Used external master issue request H8S/2357 Series.
STBY
Input
BREQ
Input
BREQO
Output request output: external request signal used when internal master accesses external space external busreleased state. Output request acknowledge: Indicates that been released external master.
BACK
Type System control Symbol FWE*
TFP-120
FP-128B Input
Name Function Flash write enable: Enables/disables flash memory programming. Nonmaskable interrupt: Requests nonmaskable interrupt. When this used, should fixed high. Interrupt request These pins request maskable interrupt.
Interrupts
Input
IRQ7 IRQ0 Address
Input
Output Address bus: These pins output address.
Data
Data bus: These pins constitute bidirectional data bus.
control
Output Chip select: Signals selecting areas 127, 128, Output Address strobe: When this low, indicates that address output address enabled. Output Read: When this low, indicates that external address space read. Output High write/write enable: strobe signal that writes external space indicates that upper half (D15 data enabled. 2CAS type DRAM write enable signal. Output write: strobe signal that writes external space indicates that lower half data enabled.
Type control Symbol TFP-120 FP-128B Name Function
Output Upper column address strobe/column address strobe: 2CAS type DRAM upper column address strobe signal. Input Wait: Requests insertion wait state cycle when accessing external 3-state address space.
WAIT
LCAS
Output Lower column address strobe: 2-CAS type DRAM lower column address strobe signal Input request These pins request DMAC activation.
controller (DMAC)
DREQ1, DREQ0 TEND1, TEND0 DACK1, DACK0
Output transfer These pins indicate DMAC data transfer. Output transfer acknowledge These DMAC single address transfer acknowledge pins. Clock input These pins input external clock. Input capture/ output compare match TGR0A TGR0D input capture input output compare output, output pins. Input capture/ output compare match TGR1A TGR1B input capture input output compare output, output pins. Input capture/ output compare match TGR2A TGR2B input capture input output compare output, output pins. Input capture/ output compare match TGR3A TGR3D input capture input output compare output, output pins.
111,
121,
16-bit timerpulse unit (TPU)
TCLKD TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1
105, 107, 115, 117, Input 109, 119,
108,
118,
TIOCA2, TIOCB2
106,
116,
TIOCA3, TIOCB3, TIOCC3, TIOCD3
Type 16-bit timerpulse unit (TPU) Symbol TIOCA4, TIOCB4 TFP-120 FP-128B Name Function Input capture/ output compare match TGR4A TGR4B input capture input output compare output, output pins. Input capture/ output compare match TGR5A TGR5B input capture input output compare output, output pins.
TIOCA5, TIOCB5
Programmable PO15 pulse generator (PPG) 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 Watchdog timer (WDT) Serial communication interface (SCI) Smart Card interface
112,
122,
Output Pulse output Pulse output pins. Output Compare match output: compare match output pins. Input Counter external clock input: Input pins external clock input counter. Counter external reset input: counter reset input pins.
Input
WDTOVF*
Output Watchdog timer overflows: counter overflows signal output watchdog timer mode. Output Transmit data (channel Data output pins. Input Receive data (channel Data input pins. Serial clock (channel Clock pins. Analog Analog input pins. conversion external trigger input: input external trigger start conversion.
TxD2, TxD1, TxD0 RxD2, RxD1, RxD0 SCK2, SCK1, SCK0
101,
converter
ADTRG
Input Input
converter
DA1,
102,
112,
Output Analog output: converter analog output pins.
Type converter converter Symbol AVCC TFP-120 FP-128B Input Name Function This power supply converter converter. When converter converter used, this should connected system power supply This ground converter converter. This should connected system power supply This reference voltage input converter converter. When converter converter used, this should connected system power supply Port 8-bit port. Input output designated each means port data direction register (P1DDR). Port 8-bit port. Input output designated each means port data direction register (P2DDR). Port 6-bit port. Input output designated each means port data direction register (P3DDR). Port 8-bit input port. Port 4-bit port. Input output designated each means port data direction register (P5DDR).
AVSS
Input
Vref
Input
ports
Input
102, 101,
Type ports Symbol TFP-120 FP-128B Name Function Port 8-bit port. Input output designated each means port data direction register (P6DDR). Port 8-bit port. Input output designated each means port data direction register (PADDR). Port 8-bit port. Input output designated each means port data direction register (PBDDR). Port 8-bit port. Input output designated each means port data direction register (PCDDR). Port 8-bit port. Input output designated each means port data direction register (PDDDR). Port 8-bit port. Input output designated each means port data direction register (PEDDR). Port 8-bit port. Input output designated each means port data direction register (PFDDR). Port 5-bit port. Input output designated each means port data direction register (PGDDR).
Notes:
Applies H8S/2398, H8S/2394, H8S/2392, H8S/2390 only. Applies H8S/2357F-ZTAT only. available F-ZTAT version, H8S/2398, H8S/2394, H8S/2392, H8S/2390. Applies On-chip version only.
Section
Overview
H8S/2000 high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 H8/300H CPUs. H8S/2000 sixteen 16-bit general registers, address 16-Mbyte (architecturally 4-Gbyte) linear address space, ideal realtime control. 2.1.1 Features
H8S/2000 following features. Upward-compatible with H8/300 H8/300H CPUs execute H8/300 H8/300H object programs General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) Sixty-five basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) @(d:32,ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, @aa:32] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8,PC) @(d:16,PC)] Memory indirect [@@aa:8] 16-Mbyte address space Program: Mbytes Data: Mbytes (architecturally 4-Gbyte)
High-speed operation frequently-used instructions execute states Maximum clock rate 8/16/32-bit register-register add/subtract 8-bit register-register multiply 8-bit register-register divide 16-bit register-register multiply 1000 16-bit register-register divide 1000 operating mode Advanced mode Power-down state Transition power-down state SLEEP instruction clock speed selection 2.1.2 Differences between H8S/2600 H8S/2000
differences between H8S/2600 H8S/2000 shown below. Register configuration register supported only H8S/2600 CPU. Basic instructions four instructions MAC, CLRMAC, LDMAC, STMAC supported only H8S/2600 CPU. Number execution states number exection states MULXU MULXS instructions.
Internal Operation Instruction MULXU Mnemonic MULXU.B MULXU.W MULXS MULXS.B MULXS.W H8S/2600 H8S/2000
There also differences address space, functions, power-down state, etc., depending product.
2.1.3
Differences from H8/300
comparison H8/300 CPU, H8S/2000 following enhancements. More general registers control registers Eight 16-bit expanded registers, 8-bit control register, have been added. Expanded address space Advanced mode supports maximum 16-Mbyte address space. Enhanced addressing addressing modes have been enhanced make effective 16-Mbyte address space. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Signed multiply divide instructions have been added. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast. 2.1.4 Differences from H8/300H
comparison H8/300H CPU, H8S/2000 following enhancements. Additional control register 8-bit control register been added. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast.
Operating Modes
H8S/2357 Series advanced operating mode. Advanced mode supports maximum 16-Mbyte total address space (architecturally maximum 16-Mbyte program area maximum Gbytes program data areas combined). mode selected mode pins microcontroller. Advanced Mode Address Space: Linear access provided 16-Mbyte maximum address space (architecturally maximum 16-Mbyte program area maximum 4-Gbyte data area, with maximum Gbytes program data areas combined). Extended Registers (En): extended registers used 16-bit registers, upper 16-bit segments 32-bit registers address registers. Instruction Set: instructions addressing modes used.
Exception Vector Table Memory Indirect Branch Addresses: advanced mode area starting H'00000000 allocated exception vector table units bits. each bits, upper bits ignored branch address stored lower bits (figure 2-1). details exception vector table, section Exception Handling.
H'00000000 Reserved Power-on reset exception vector H'00000003 H'00000004 Reserved Manual reset exception vector* H'00000007 H'00000008 Exception vector table
H'0000000B H'0000000C
(Reserved system use)
H'00000010
Reserved Exception vector
Note: Manual reset only supported H8S/2357 ZTAT.
Figure Exception Vector Table (Advanced Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. advanced mode operand 32-bit longword operand, providing 32-bit branch address. upper bits these bits reserved area that regarded H'00. Branch addresses stored area from H'00000000 H'000000FF. Note that first part this range also exception vector table.
Stack Structure: advanced mode, when program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 2-2. When invalid, pushed onto stack. details, section Exception Handling.
Reserved bits)
EXR*1 Reserved*1*3 bits)
Subroutine Branch
Exception Handling
Notes: When used stored stack. when used. Ignored when returning.
Figure Stack Structure Advanced Mode
Address Space
Figure shows memory H8S/2000 CPU. H8S/2000 provides linear access maximum 16-Mbyte (architecturally 4-Gbyte) address space advanced mode.
H'00000000
Program area
H'00FFFFFF
Data area
Cannot used H8S/2357 Series
H'FFFFFFFF Advanced Mode
Figure Memory
2.4.1
Register Configuration
Overview
internal registers shown figure 2-4. There types registers: general registers control registers.
General Registers (Rn) Extended Registers (En) (SP) Control Registers (CR) Legend EXR: CCR:
Stack pointer Program counter Extended control register Trace Interrupt mask bits Condition-code register Interrupt mask User interrupt mask bit*
Half-carry flag User Negative flag Zero flag Overflow flag Carry flag
Note: H8S/2357 Series, this cannot used interrupt mask.
Figure Registers
2.4.2
General Registers
eight 32-bit general registers. These general registers functionally alike used both address registers data registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. Figure illustrates usage general registers. usage each register selected independently.
Address registers 32-bit registers
16-bit registers registers (extended registers)
8-bit registers
registers (ER0 ER7) registers
registers (R0H R7H)
registers (R0L R7L)
Figure Usage General Registers General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Free area
(ER7)
Stack area
Figure Stack 2.4.3 Control Registers
control registers 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR). Program Counter (PC): This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word), least significant ignored. (When instruction fetched, least significant regarded Extended Control Register (EXR): This 8-bit register contains trace three interrupt mask bits I0). 7-Trace (T): Selects trace mode. When this cleared instructions executed sequence. When this trace exception generated each time instruction executed. Bits 3-Reserved: These bits reserved. They always read Bits 0-Interrupt Mask Bits I0): These bits designate interrupt mask level details, refer section Interrupt Controller. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. interrupts, including NMI, disabled three states after these instructions executed, except STC. Condition-Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags.
7-Interrupt Mask (I): Masks interrupts other than when (NMI accepted regardless setting.) hardware start exceptionhandling sequence. details, refer section Interrupt Controller. 6-User Interrupt Mask (UI): written read software using LDC, STC, ANDC, ORC, XORC instructions. With H8S/2357 Series, this cannot used interrupt mask bit. 5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise. 4-User (U): written read software using LDC, STC, ANDC, ORC, XORC instructions. 3-Negative Flag (N): Stores value most significant (sign bit) data. 2-Zero Flag (Z): indicate zero data, cleared indicate non-zero data. 1-Overflow Flag (V): when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, store value shifted carry flag also used accumulator manipulation instructions. Some instructions leave some flag bits unchanged. action each instruction flag bits, refer Appendix A.1, Instructions List. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. flags used branching conditions conditional branch (Bcc) instructions. 2.4.4 Initial Register Values
Reset exception handling loads CPU's program counter (PC) from vector table, clears trace sets interrupt mask bits other bits general registers initialized. particular, stack pointer (ER7) initialized.
stack pointer should therefore initialized MOV.L instruction executed immediately after reset. Don'tacare
Data Formats
process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data. 2.5.1 General Register Data Formats
Figure shows data formats general registers.
Data Type Register Number Data Format
1-bit data
1-bit data
Don't care
4-bit data
Upper
Lower
Don't care
4-bit data
Don't care
Upper
Lower
Byte data
Don't care Don't care
Byte data
Figure General Register Data Formats
Data Type
Register Number
Data Format
Word data
Word data Longword data
Legend ERn: General register General register General register RnH: General register RnL: General register MSB: Most significant LSB: Least significant
Figure General Register Data Formats (cont)
2.5.2
Memory Data Formats
Figure shows data formats memory. access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches.
Data Type Address 1-bit data Address Data Format
Byte data
Address
Word data
Address Address
Longword data
Address Address Address Address
Figure Memory Data Formats When used address register access stack, operand size should word size longword size.
2.6.1
Instruction
Overview
H8S/2000 types instructions. instructions classified function table 2-1. Table
Function Data transfer
Instruction Classification
Instructions POP* PUSH* LDM, SMOVFPE, MOVTPE*
Size
Types
Arithmetic operations
ADD, SUB, CMP, ADDX, SUBX, DAA, INC, ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*
Logic operations Shift manipulation Branch System control Block data transfer Total:
AND, XOR,
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* JMP, BSR, JSR,
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV
Notes: B-byte size; W-word size; L-longword size. POP.W PUSH.W identical MOV.W @SP+, MOV.W @-SP. POP.L PUSH.L identical MOV.L @SP+, MOV.L ERn, @-SP. general name conditional branch instructions. Cannot used H8S/2357 Series. Only register ER0, ER1, ER4, should used when using instruction.
2.6.2
Instructions Addressing Modes
Table indicates combinations instructions addressing modes that H8S/2600 use. Table Combinations Instructions Addressing Modes
Addressing Modes
@-ERn/@ERn+
@(d:16,ERn)
@(d:32,ERn)
@(d:8,PC)
Function
Instruction
@(d:16,PC)
@@aa:8
@aa:16
@aa:24
@aa:32
@aa:8
@ERn
Data transfer
POP, PUSH LDM, SMOVFPE, MOVTPE*1 ADD, ADDX, SUBX ADDS, SUBS INC, DAA, MULXU, DIVXU MULXS, DIVXS EXTU, EXTS TAS*2
Arithmetic operations
Logic operations
AND,
Shift manipulation Branch Bcc, JMP, System control TRAPA SLEEP ANDC, ORC, XORC Block data transfer Legend Byte Word Longword
Notes: Cannot used H8S/2357 Series. Only register ER0, ER1, ER4, should used when using instruction.
2.6.3
Table Instructions Classified Function
Table summarizes instructions each functional category. notation used table defined below.
Operation Notation (EAd) (EAs) #IMM disp :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical Logical Logical exclusive Move (logical complement) 16-, 24-, 32-bit length
Note: General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit registers (ER0 ER7).
Table
Type Data transfer
Instructions Classified Function
Instruction Size* B/W/L Function (EAs) (Ead) Moves data between general registers between general register memory, moves immediate data general register. Cannot used H8S/2357 Series. Cannot used H8S/2357 Series. @SP+ Pops register from stack. POP.W identical MOV.W @SP+, POP.L identical MOV.L @SP+, ERn. @-SP Pushes register onto stack. PUSH.W identical MOV.W @-SP. PUSH.L identical MOV.L ERn, @-SP. @SP+ (register list) Pops more general registers from stack. (register list) @-SP Pushes more general registers onto stack.
MOVFPE MOVTPE
PUSH
S
Type Arithmetic operations
Instruction
Size* B/W/L
Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from byte data general register. SUBX instruction.) #IMM Performs addition subtraction with carry borrow byte data general registers, immediate data data general register. Increments decrements general register (Byte operands incremented decremented only.) Adds subtracts value from data 32-bit register. decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4-bit data. Performs unsigned multiplication data general registers: either bits bits bits bits bits bits. Performs signed multiplication data general registers: either bits bits bits bits bits bits. Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16bit remainder.
ADDX SUBX
B/W/L
ADDS SUBS
MULXU
MULXS
DIVXU
Type Arithmetic operations
Instruction DIVXS
Size*
Function Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16bit remainder. #IMM Compares data general register with data another general register with immediate data, sets bits according result. Takes two's complement (arithmetic complement) data general register. (zero extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, padding with zeros left. (sign extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, extending sign bit. @ERd (<bit @ERd)* Tests memory contents, sets most significant (bit
B/W/L
B/W/L
EXTU
EXTS
Type Logic operations
Instruction
Size* B/W/L
Function #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical exclusive operation general register another general register immediate data. (Rd) (Rd) Takes one's complement general register contents. (shift) Performs arithmetic shift general register contents. 1-bit 2-bit shift possible. (shift) Performs logical shift general register contents. 1-bit 2-bit shift possible. (rotate) Rotates general register contents. 1-bit 2-bit rotation possible. (rotate) Rotates general register contents through carry flag. 1-bit 2-bit rotation possible.
B/W/L
B/W/L
B/W/L
Shift operations
SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
B/W/L
B/W/L
B/W/L
B/W/L
Type Bitmanipulation instructions
Instruction BSET
Size*
Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
BCLR
BNOT
BTST
BAND
BIAND
BIOR
Type Bitmanipulation instructions
Instruction BXOR
Size*
Function (<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) Exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers specified general register memory operand carry flag. (<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand. (<bit-No.> <EAd>) Transfers inverse carry flag value specified general register memory operand. number specified 3-bit immediate data.
BIXOR
BILD
BIST
Type Branch instructions
Instruction
Size*
Function Branches specified address specified condition true. branching conditions listed below. Mnemonic BRA(BT) BRN(BF) BCC(BHS) BCS(BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address. Branches subroutine specified address. Branches subroutine specified address. Returns from subroutine
Type
Instruction
Size*
Function Starts trap-instruction exception handling. Returns from exception-handling routine. Causes transition power-down state. (EAs) CCR, (EAs) Moves source operand contents immediate data EXR. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid. (EAd), (EAd) Transfers contents general register memory. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid. #IMM CCR, #IMM Logically ANDs contents with immediate data. #IMM CCR, #IMM Logically contents with immediate data. #IMM CCR, #IMM Logically exclusive-ORs contents with immediate data. Only increments program counter.
System control TRAPA instructions SLEEP
ANDC
XORC
Type Block data transfer instruction
Instruction EEPMOV.B
Size*
Function then Repeat @ER5+ @ER6+ R4L-1 Until else next; then Repeat @ER5+ @ER6+ R4-1 Until else next; Transfers data block according parameters general registers ER5, ER6. size block (bytes) ER5: starting source address ER6: starting destination address Execution next instruction begins soon transfer completed.
EEPMOV.W
Notes: Size refers operand size. Byte Word Longword Only register ER0, ER1, ER4, should used when using instruction.
2.6.4
Basic Instruction Formats
instructions consist 2-byte (1-word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Figure shows examples instruction formats.
Operation field only NOP, RTS, etc.
Operation field register fields ADD.B etc.
Operation field, register fields, effective address extension (disp) Operation field, effective address extension, condition field (disp) d:16, etc. MOV.B @(d:16, Rn), etc.
Figure Instruction Formats (Examples) Operation Field: Indicates function instruction, addressing mode, operation carried operand. operation field always includes first bits instruction. Some instructions have operation fields. Register Field: Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension: Eight, bits specifying immediate data, absolute address, displacement. Condition Field: Specifies branching condition instructions.
2.7.1
Addressing Modes Effective Address Calculation
Addressing Mode
supports eight addressing modes listed table 2-4. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except program-counter relative memory indirect. manipulation instructions register direct, register indirect, absolute addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table
Addressing Modes
Symbol @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect
Register Direct-Rn: register field instruction specifies 16-, 32-bit general register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32-bit registers. Register Indirect-@ERn: register field instruction code specifies address register (ERn) which contains address operand memory. address program instruction address, lower bits valid upper bits assumed (H'00). Register Indirect with Displacement-@(d:16, ERn) @(d:32, ERn): 16-bit 32-bit displacement contained instruction added address register (ERn) specified register field instruction, gives address memory operand. 16-bit displacement sign-extended when added.
Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn: Register indirect with post-increment-@ERn+ register field instruction code specifies address register (ERn) which contains address memory operand. After operand accessed, added address register contents stored address register. value added byte access, word transfer instruction, longword transfer instruction. word longword transfer instruction, register value should even. Register indirect with pre-decrement-@-ERn value subtracted from address register (ERn) specified register field instruction code, result becomes address memory operand. result also stored address register. value subtracted byte access, word transfer instruction, longword transfer instruction. word longword transfer instruction, register value should even. Absolute Address-@aa:8, @aa:16, @aa:24, @aa:32: instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24), bits long (@aa:32). access data, absolute address should bits (@aa:8), bits (@aa:16), bits (@aa:32) long. 8-bit absolute address, upper bits assumed (H'FFFF). 16-bit absolute address upper bits sign extension. 32-bit absolute address access entire address space. 24-bit absolute address (@aa:24) indicates address program instruction. upper bits assumed (H'00). Table indicates accessible absolute address ranges. Table Absolute Address Access Ranges
Advanced Mode bits (@aa:8) bits (@aa:16) bits (@aa:32) Program instruction address bits (@aa:24) H'FFFF00 H'FFFFFF H'000000 H'007FFF, H'FF8000 H'FFFFFF H'000000 H'FFFFFF
Absolute Address Data address
Immediate-#xx:8, #xx:16, #xx:32: instruction contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. ADDS, SUBS, INC, instructions contain immediate data implicitly. Some manipulation instructions contain 3-bit immediate data instruction code, specifying number. TRAPA instruction contains 2-bit immediate data instruction code, specifying vector address. Program-Counter Relative-@(d:8, @(d:16, PC): This mode used instructions. 8-bit 16-bit displacement contained instruction sign-extended added 24-bit contents generate branch address. Only lower bits this branch address valid; upper bits assumed (H'00). value which displacement added address first byte next instruction, possible branching range -126 +128 bytes (-63 words) -32766 +32768 bytes (-16383 +16384 words) from branch instruction. resulting value should even number. Memory Indirect-@@aa:8: This mode used instructions. instruction code contains 8-bit absolute address specifying memory operand. This memory operand contains branch address. upper bits absolute address assumed address range (H'000000 H'0000FF). Note that first part address range also exception vector area. further details, refer section Exception Handling.
Specified @aa:8
Reserved Branch address
Advanced Mode
Figure 2-10 Branch Address Specification Memory Indirect Mode
address specified word longword memory access, branch address, least significant regarded causing data accessed instruction code fetched address preceding specified address. (For further information, section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation
Table indicates effective addresses calculated each addressing mode.
Effective Address Calculation Effective Address (EA) Operand general register contents. General register contents Don't care General register contents disp Sign extension disp Don't care General register contents Don't care General register contents Don't care Operand Size Value added Byte Word Longword
Addressing Mode Instruction Format
Table
Register direct (Rn)
Register indirect (@ERn)
Register indirect with displacement @(d:16, ERn) @(d:32, ERn)
Effective Address Calculation
Register indirect with post-increment pre-decrement Register indirect with post-increment @ERn+
Register indirect with pre-decrement @-ERn
Effective Address Calculation
Addressing Mode Instruction Format
Effective Address (EA)
H'FFFF
Don't care
Absolute address
@aa:8
@aa:16
Don't care
Sign extension
@aa:24
Don't care
@aa:32
Don't care
Immediate #xx:8/#xx:16/#xx:32 Operand immediate data.
Effective Address Calculation contents Effective Address (EA) Sign extension disp
Don't care
Addressing Mode Instruction Format
Program-counter relative
@(d:8, PC)/@(d:16,
disp
Memory indirect @@aa:8
Advanced mode H'000000 Memory contents
Don't care
2.8.1
Processing States
Overview
five main processing states: reset state, exception handling state, program execution state, bus-released state, power-down state. Figure 2-11 shows diagram processing states. Figure 2-12 indicates state transitions.
Reset state on-chip supporting modules have been initialized stopped. Exception-handling state transient state which changes normal processing flow response reset, interrupt, trap instruction. Processing states Program execution state executes program instructions sequence. Bus-released state external been released response request signal from master other than CPU. Sleep mode
Power-down state operation stopped conserve power.*
Software standby mode Hardware standby mode
Note: power-down state also includes medium-speed mode, module stop mode etc.
Figure 2-11 Processing States
request request
Program execution state request request SLEEP instruction with SSBY
Bus-released state exception handling Request exception handling
SLEEP instruction with SSBY
Sleep mode
Interrupt request Exception-handling state External interrupt high Software standby mode
Reset state*1
STBY high,
Hardware standby mode*2 Power-down state
Notes: From state except hardware standby mode, transition reset state occurs whenever goes low. transition also made reset state when watchdog timer overflows. From state, transition hardware standby mode occurs when STBY goes low.
Figure 2-12 State Transitions 2.8.2 Reset State
When input goes current processing stops enters reset state. enters power-on reset state when high, manual reset* state when low. interrupts masked reset state. Reset exception handling starts when signal changes from high. reset state also entered watchdog timer overflow. details, refer section Watchdog Timer. Note: Manual reset only supported H8S/2357 ZTAT.
2.8.3
Exception-Handling State
exception-handling state transient state that occurs when alters normal processing flow reset, interrupt, trap instruction. fetches start address (vector) from exception vector table branches that address. Types Exception Handling Their Priority Exception handling performed traces, resets, interrupts, trap instructions. Table indicates types exception handling their priority. Trap instruction exception handling always accepted, program execution state. Exception handling stack structure depend interrupt control mode SYSCR. Table
Priority High
Exception Handling Types Priority
Type Exception Reset Detection Timing Synchronized with clock Start Exception Handling Exception handling starts immediately after low-to-high transition pin, when watchdog timer overflows. When trace trace starts current instruction current exception-handling sequence When interrupt requested, exception handling starts current instruction current exception-handling sequence Exception handling starts when trap (TRAPA) instruction executed*
Trace
instruction execution exception-handling sequence* instruction execution exception-handling sequence* When TRAPA instruction executed
Interrupt
Trap instruction
Notes: Traces enabled only interrupt control mode Trace exception-handling executed instruction. Interrupts detected ANDC, ORC, XORC, instructions, immediately after reset exception handling. Trap instruction exception handling always accepted, program execution state.
Reset Exception Handling After gone reset state been entered, when goes high again, reset exception handling starts. enters power-on reset state when high, manual reset* state when low. When reset exception handling starts fetches start address (vector) from exception vector table starts program execution from that address. interrupts, including NMI, disabled during reset exception handling after ends. Note Manual reset only supported H8S/2357 ZTAT. Traces Traces enabled only interrupt control mode Trace mode entered when When trace mode established, trace exception handling starts each instruction. trace exception-handling sequence, cleared trace mode cleared. Interrupt masks affected. saved stack retains value when instruction executed return from trace exception-handling routine, trace mode entered again. Trace exceptionhandling executed instruction. Trace mode entered interrupt control mode regardless state bit. Interrupt Exception Handling Trap Instruction Exception Handling When interrupt trap-instruction exception handling begins, references stack pointer (ER7) pushes program counter other control registers onto stack. Next, alters settings interrupt mask bits control registers. Then fetches start address (vector) from exception vector table program execution starts from that start address. Figure 2-13 shows stack after exception handling ends.
Advanced mode
bits)
Reserved* bits)
Interrupt control mode Note: *Ignored when returning.
Interrupt control mode
Figure 2-13 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State
this state executes program instructions sequence. 2.8.5 Bus-Released State
This state which been released response request from master other than CPU. While released, halts. There other master addition CPU: data transfer controller (DTC). further details, refer section Controller. 2.8.6 Power-Down State
power-down state includes both modes which stops operating modes which does stop. There three modes which stops operating: sleep mode, software standby mode, hardware standby mode. There also other power-down modes: medium-speed mode, module stop mode. medium-speed mode other masters operate medium-speed clock. Module stop mode permits halting operation individual modules, other than CPU. details, refer section Power-Down Modes.
Sleep Mode: transition sleep mode made SLEEP instruction executed while software standby (SSBY) standby control register (SBYCR) cleared sleep mode, operations stop immediately after execution SLEEP instruction. contents registers retained. Software Standby Mode: transition software standby mode made SLEEP instruction executed while SSBY SBYCR software standby mode, clock halt operations stop. long specified voltage supplied, contents registers on-chip retained. ports also remain their existing states. Hardware Standby Mode: transition hardware standby mode made when STBY goes low. hardware standby mode, clock halt operations stop. on-chip supporting modules reset, long specified voltage supplied, on-chip contents retained.
2.9.1
Basic Timing
Overview
driven system clock, denoted symbol period from rising edge next referred "state." memory cycle cycle consists one, two, three states. Different methods used access on-chip memory, on-chip supporting modules, external address space. 2.9.2 On-Chip Memory (ROM, RAM)
On-chip memory accessed state. data bits wide, permitting both byte word transfer instruction. Figure 2-14 shows on-chip memory access cycle. Figure 2-15 shows states.
cycle Internal address Internal read signal Internal data Internal write signal Write access Internal data Write data Read data Address
Read access
Figure 2-14 On-Chip Memory Access Cycle
cycle
Address HWR, Data
Unchanged High High High High-impedance state
Figure 2-15 States during On-Chip Memory Access
2.9.3
On-Chip Supporting Module Access Timing
on-chip supporting modules accessed states. data either bits bits wide, depending particular internal register being accessed. Figure 2-16 shows access timing on-chip supporting modules. Figure 2-17 shows states.
cycle
Internal address
Address
Internal read signal Read access Internal data Internal write signal Write access Internal data Write data
Read data
Figure 2-16 On-Chip Supporting Module Access Cycle
cycle
Address
Unchanged
HWR,
High
High
High
Data
High-impedance state
Figure 2-17 States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing
external address space accessed with 8-bit 16-bit data width two-state three-state cycle. three-state access, wait states inserted. further details, refer section Controller.
2.10
2.10.1
Usage Note
Instruction
Only register ER0, ER1, ER4, should used when using instruction. instruction generated Hitachi H8/300 Series C/C++ compilers. instruction used user-defined intrinsic function, ensure that only register ER0, ER1, ER4, used.
Section Operating Modes
3.1.1
Overview
Operating Mode Selection (H8S/2357 F-ZTAT Only)
H8S/2357 F-ZTAT eight operating modes (modes 15). These modes determined mode (MD2 MD0) flash write enable (FWE) settings. operating mode initial width selected shown table 3-1. Table lists operating modes. Table Operating Mode Selection (H8S/2357 F-ZTAT Only)
External Data On-Chip Initial Width Max. Width
Operating Operating Mode Mode Description Advanced User program mode Advanced Boot mode
Advanced On-chip disabled, Disabled bits bits expanded mode bits bits On-chip enabled, Enabled bits expanded mode Single-chip mode bits
Enabled bits
bits
Enabled bits
bits
CPU's architecture allows Gbytes address space, H8S/2357 Series actually accesses maximum Mbytes.
Modes externally expanded modes that allow access external memory peripheral devices. external expansion modes allow switching between 8-bit 16-bit modes. After program execution starts, 8-bit 16-bit address space each area, depending controller setting. 16-bit access selected area, 16-bit mode set; 8-bit access selected areas, 8-bit mode set. Note that functions each depend operating mode. Modes boot modes user program modes which flash memory programmed erased. details, section ROM. H8S/2357 F-ZTAT only used modes This means that flash write enable mode pins must select these modes. change inputs mode pins during operation. 3.1.2 Operating Mode Selection (ZTAT, Mask ROM, ROMless Version, H8S/2398 F-ZTAT)
H8S/2357 Series four operating modes (modes These modes enable selection operating mode, enabling/disabling on-chip ROM, initial width setting, setting mode pins (MD2 MD0). Table lists operating modes.
Table
Operating Mode Selection (ZTAT, Mask ROM, ROMless H8S/2398 F-ZTAT)
External Data On-Chip Initial Width Max. Width
Operating Operating Description Mode Mode
Advanced On-chip disabled, Disabled bits expanded mode bits On-chip enabled, Enabled bits expanded mode Single-chip mode
bits bits bits
Notes: H8S/2398 F-ZTAT, modes indicate boot mode. details boot mode H8S/2398 F-ZTAT version, refer table 19-35 section 19.17, On-Board Programming Modes. addition, details user program mode, refer also tables 19-35 section 19.17, On-Board Programming Modes. ROMless version, only modes available.
CPU's architecture allows Gbytes address space, H8S/2357 Series actually accesses maximum Mbytes. Modes externally expanded modes that allow access external memory peripheral devices. external expansion modes allow switching between 8-bit 16-bit modes. After program execution starts, 8-bit 16-bit address space each area, depending controller setting. 16-bit access selected area, 16-bit mode set; 8-bit access selected areas, 8-bit mode set. Note that functions each depend operating mode. H8S/2357 Series cannot used modes This means that mode pins must select modes. change inputs mode pins during operation.
3.1.3
Register Configuration
H8S/2357 Series mode control register (MDCR) that indicates inputs mode pins MD0), system control register (SYSCR) system control register (SYSCR2)*2 that control operation H8S/2357 Series. Table summarizes these registers. Table
Name Mode control register System control register System control register
Registers
Abbreviation MDCR SYSCR SYSCR2 Initial Value Undetermined H'01 H'00 Address* H'FF3B H'FF39 H'FF42
Notes: Lower bits address. SYSCR2 register only used F-ZTAT version. mask ZTAT versions, this register cannot written will return undefined value read.
3.2.1
Register Descriptions
Mode Control Register (MDCR)
MDS2 MDS1 MDS0
Initial value
Note: Determined pins MD0.
MDCR 8-bit read-only register that indicates current operating mode H8S/2357 Series. 7-Reserved: This cannot modified always read Bits 3-Reserved: These bits cannot modified always read Bits 0-Mode Select (MDS2 MDS0): These bits indicate input levels pins (the current operating mode). Bits MDS2 MDS0 correspond MD0. MDS2 MDS0 read-only bits, they cannot written mode (MD2 MD0) input levels latched into these bits when MDCR read. These latches canceled power-on reset, retained after manual reset.*
Note: Manual reset only supported H8S/2357 ZTAT. 3.2.2
System Control Register (SYSCR)
INTM1 INTM0 NMIEG RAME
Initial value
Note: H8S/2390, H8S/2392, H8S/2394, H8S/2398.
7-Reserved: Only should written this bit. 6-Reserved: This cannot modified always read Bits 4-Interrupt Control Mode (INTM1, INTM0): These bits select control mode interrupt controller. details interrupt control modes, section 5.4.1, Interrupt Control Modes Interrupt Operation.
INTM1 INTM0 Interrupt Control Mode Description Control interrupts Setting prohibited Control interrupts bits Setting prohibited (Initial value)
3-NMI Edge Select (NMIEG): Selects valid edge interrupt input.
NMIEG Description interrupt requested falling edge input interrupt requested rising edge input (Initial value)
2-Reserved: This cannot modified always read This reserved H8S/2390, H8S/2392, H8S/2394, H8S/2398. Only should written this bit. 1-Reserved: Only should written this bit. 0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized when reset status released. initialized software standby mode.
RAME
Description On-chip disabled On-chip enabled (Initial value)
3.2.3
System Control Register (SYSCR2) (F-ZTAT Version Only)
FLSHE
Initial value
SYSCR2 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 initialized H'00 reset hardware standby mode. SYSCR2 only accessed F-ZTAT version. other versions, this register cannot written will return undefined value read. Bits 4-Reserved: These bits cannot modified always read 3-Flash Memory Control Register Enable (FLSHE): Controls access flash memory control registers (FLMCR1, FLMCR2, EBR1, EBR2). details, section ROM.
FLSHE Description Flash control registers selected addresses H'FFFFC8 H'FFFFCB (Initial value) Flash control registers selected addresses H'FFFFC8 H'FFFFCB
Bits 0-Reserved: These bits cannot modified always read
3.3.1
Operating Mode Descriptions
Mode
Mode supported this LSI, must set. 3.3.2 Mode (H8S/2398 F-ZTAT Only)
This flash memory boot mode. details, section ROM. operation same mode 3.3.3 Mode (H8S/2398 F-ZTAT Only)
This flash memory boot mode. details, section ROM. operation same mode 3.3.4 Mode (On-Chip Disabled Expansion Mode)
access 16-Mbyte address space advanced mode. on-chip disabled. Ports function address bus, ports function data bus, part port carries control signals. initial mode after reset bits, with 16-bit access areas. However, note that 8-bit access designated controller areas, mode switches bits. 3.3.5 Mode (On-Chip Disabled Expansion Mode)
access 16-Mbyte address space advanced mode. on-chip disabled. Ports function address bus, ports function data bus, part port carries control signals. initial mode after reset bits, with 8-bit access areas. However, note that least area designated 16-bit access controller, mode switches bits port becomes data bus.
3.3.6
Mode (On-Chip Enabled Expansion Mode)
access 16-Mbyte address space advanced mode. on-chip enabled. Ports function input ports immediately after reset. They each output addresses setting corresponding bits data direction register (DDR) Port functions data bus, part port carries control signals. initial mode after reset bits, with 8-bit access areas. However, note that least area designated 16-bit access controller, mode switches bits port becomes data bus. 3.3.7 Mode (Single-Chip Mode)
access 16-Mbyte address space advanced mode. on-chip enabled, external addresses cannot accessed. ports available input-output ports. 3.3.8 Modes
Modes suppor
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