DSP56602 User's Manual Programmer's Reference INTRODUCTION I

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DSP56602 User's Manual Programmer's Reference INTRODUCTION I

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APPENDIX PROGRAMMER'S REFERENCE
DSP56602 User's Manual
Programmer's Reference
INTRODUCTION INSTRUCTION SUMMARY. INTERRUPT, VECTOR, ADDRESS TABLES D-14 PROGRAMMER'S SHEETS D-23
DSP56602 User's Manual
Programmer's Reference
INTRODUCTION
following pages provide reference tables programming sheets that intended simplify programming DSP56602. programming sheets provide room write value each hexadecimal value each register. programmer photocopy these sheets.
INSTRUCTION SUMMARY
following tables provide brief summary instruction DSP56602. Table D-1, Table D-2, Table provide abbreviations Table D-4, instruction summary table. complete instruction details, Appendix DSP56600 Family Manual (DSP56600FM/AD). Table Program Word Timing Symbols
Column Parallel Move Parallel Move Parallel Move Applicable Description Symbols
Instruction Clock Cycle Counts (Add cycle each symbol column) Pre-Update Long Absolute Long Immediate
Table Condition Code Register (CCR) Symbols
Symbol
Description
Scaling indicating data growth detected Limit indicating arithmetic overflow and/or data limiting Extension indicating integer portion Unnormalized indicating result unnormalized Negative indicating result
DSP56602 User's Manual
Programmer's Reference
Table Condition Code Register (CCR) Symbols (continued)
Symbol
Description
Zero indicating result equals Overflow indicating arithmetic overflow occurred result Carry indicating carry borrow occurred result
Table Condition Code Register Notation
Notation
Description
cleared according standard definition result operation affected operation always cleared operation always operation Undefined cleared according special computation definition result operation
Table Instruction Summary
Mnemonic #iiiiii,D #iii,D ADDL ADDR ADDL ADDR #iiiiii,D Syntax
DSP56602 User's Manual
Programmer's Reference
Table Instruction Summary (continued)
Mnemonic ANDI Syntax #iii,D ANDI #ii,S,D sss,S,D sss,S,D #ii,S,D BCHG BCHG #bbbb S:<aa> BCHG #bbbb S:<ea> BCHG #bbbb S:<pp> BCHG #bbbb S:<qq> BCHG #bbbb, DDDDDD BCLR BCLR #bbbb S:<pp> BCLR #bbbb S:<ea> BCLR #bbbb S:<aa> BCLR #bbbb S:<qq> BCLR #bbbb DDDDDD BRKcc BRKcc
2+U+A
2+U+A
DSP56602 User's Manual
Programmer's Reference
Table Instruction Summary (continued)
Mnemonic BScc Syntax BScc BScc BSET BSET #bbbb,S:<pp> BSET #bbbb, S:<ea> BSET #bbbb, S:<aa> BSET #bbbb DDDDDD BSET #bbbb S:<qq> BTST BTST #bbbb,S:<pp> BTST #bbb ,S:<ea> BTST #bbbb,S:<aa> BTST #bbbb DDDDDD BTST #bbbb,S:<qq> S1,S2 #iiiiii,D #iii,D CMPM CMPU DEBUG DEBUGcc CMPM S1,S2 CMPU ggg,D DEBUG DEBUGcc
2+U+A
2+U+A
DSP56602 User's Manual
Programmer's Reference
Table Instruction Summary (continued)
Mnemonic DMAC DMAC S1,S2,D (ss,su,uu) #xxx,aaaa DDDDDD,aaaa S:<ea>,aaaa S:<aa>,aaaa FOREVER ENDDO FOREVER (aaaa) ENDDO #iiiiii,D #iii,D EXTRACT EXTRACT SSS,s,D EXTRACT #iiii,s,D EXTRACTU EXTRACTU SSS,s,D EXTRACTU #iiii,s,D IFcc IFcc(.U) ILLEGAL INSERT IFcc IFcc(.U) ILLEGAL INSERT SSS,qqq,D INSERT #iiii,qqq,D Syntax
DSP56602 User's Manual
Programmer's Reference
Table Instruction Summary (continued)
Mnemonic JCLR JCLR #bbbb,S:<ea>,aaaa JCLR #bbbb,S:<pp>,aaaa JCLR #bbbb ,S:<aa>,aaaa JCLR #bbbb,DDDDDD,aaaa JCLR #bbbb, S:<qq>,aaaa JScc JScc JScc JSCLR JSCLR #bbbb,S:<pp>,aaaa JSCLR #bbbb S:<ea>,aaaa JSCLR #bbbb S:<aa>,aaaa JSCLR #bbbb, DDDDDD,aaaa JSCLR #bbbb S:<qq>,aaaa JSET JSET #bbbb S:<pp>,aaaa JSET #bbbb S:<ea>,aaaa JSET #bbbb S:<aa>,aaaa JSET #bbbb, DDDDDD,aaaa JSET #bbbb S:<qq>,aaaa Syntax
3+U+A
3+U+A
DSP56602 User's Manual
Programmer's Reference
Table Instruction Summary (continued)
Mnemonic JSSET Syntax JSSET #bbbb,S:<pp>,aaaa JSSET #bbbb,S:<ea>,aaaa JSSET #bbbb,S:<aa>,aaaa JSSET #bbbb, DDDDDD,aaaa JSSET #bbbb,S:<qq>,aaaa 0DDDDD aaaa) 0DDDDD sss,D #ii,D #ii,D sss,D LUA, 0DDDDD 01DDDD 2**s,QQ,d S1,S2,D (su,uu) MACI MACR MACRI MAXM S1,S2,D MACI #iiiiii,QQ,D MACR ±2**s,QQ,d MACRI #iiiiii,QQ,D MAXM
DSP56602 User's Manual
Programmer's Reference
Table Instruction Summary (continued)
Mnemonic MERGE MOVE Syntax MERGE SSS,D Parallel Data Move (DALU) MOVE DDDDD MOVE dddddDDDDD move MOVE S:<ea>,DDDDD MOVE S:<aa>,DDDDD MOVE S:<Rn aa>,DDDD MOVE S:<Rn aaaa>,DDDDDD MOVE Y:<ea>,YY MOVE X:<ea>,XX MOVE X:<ea> MOVE X:<ea> MOVE Y:<ea> MOVE Y:<ea> MOVE L:<ea>,LLL MOVE L:<aa>,LLL MOVE X:<ea>,XX Y:<ea>,YY MOVEC MOVEC 1DDDDD MOVEC S:<ea>,1DDDDD MOVEC S:<aa>,1DDDDD MOVEC DDDDDD, 1ddddd
1+U+A+I
1+U+A+I 1+U+A+I
1+U+A
1+U+A+I
D-10
DSP56602 User's Manual
Programmer's Reference
Table Instruction Summary (continued)
Mnemonic MOVEM Syntax MOVEM P:<ea>,DDDDDD MOVEM P:<aa>,DDDDDD MOVEP MOVEP S:<pp>,s:<ea> MOVEP S:<pp>,P:<ea> MOVEP S:<pp>,DDDDDD MOVEP X:<qq>,s:<ea> MOVEP Y:<qq>,s:<ea> MOVEP X:<qq>,DDDDDD MOVEP Y:<qq>,DDDDDD MOVEP S:<qq>,P:<ea> MPY(su,uu) MPYI MPYR MPYRI NORMF 2**s,QQ,d S1,S2,D (su,uu) MPYI #iiiiii,QQ,D MPYR 2**s,QQ,d MPYRI #iiiiii,QQ,D NORMF SSS,D #iiiiii,D #iii,D 6+U+A
2+U+A 6+U+A
2+U+A 2+U+A
6+U+A
DSP56602 User's Manual
D-11
Programmer's Reference
Table Instruction Summary (continued)
Mnemonic #xxx DDDDDD S:<ea> S:<aa> RESET STOP RESET STOP #iiiiii,D #iii,D SUBL SUBR SUBL SUBR TRAP TRAPcc TRAP TRAPcc Syntax
D-12
DSP56602 User's Manual
Programmer's Reference
Table Instruction Summary (continued)
Mnemonic WAIT S,i,L:ea WAIT Syntax
1+U+A
DSP56602 User's Manual
D-13
Programmer's Reference
INTERRUPT, VECTOR, ADDRESS TABLES
Table Interrupt Sources
Interrupt Starting Address VBA:$00 VBA:$02 VBA:$04 VBA:$06 VBA:$08 VBA:$0A VBA:$0C VBA:$0E VBA:$10 VBA:$12 VBA:$14 VBA:$16 VBA:$18 VBA:$1A VBA:$1C VBA:$1E VBA:$20 VBA:$22 VBA:$24 VBA:$26 VBA:$28 VBA:$2A VBA:$2C
Interrupt Source Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap (Reserved) (Reserved) IRQA IRQB IRQC IRQD (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Timer Compare Timer Overflow Timer Compare Timer Overflow Timer Compare
D-14
DSP56602 User's Manual
Programmer's Reference
Table Interrupt Sources (continued)
Interrupt Starting Address VBA:$2E VBA:$30 VBA:$32 VBA:$34 VBA:$36 VBA:$38 VBA:$3A VBA:$3C VBA:$3E VBA:$40 VBA:$42 VBA:$44 VBA:$46 VBA:$48 VBA:$4A VBA:$4C VBA:$4E VBA:$60 VBA:$62 VBA:$64 VBA:$66 VBA:$FE (Reserved) Interrupt Source Timer Overflow SSI0 Receive Data SSI0 Receive Data With Exception Status SSI0 Receive last slot SSI0 Transmit Data SSI0 Transmit Data with Exception Status SSI0 Transmit Last Slot (Reserved) (Reserved) SSI1 Receive Data SSI1 Receive Data With Exception Status SSI1 Receive Last Slot SSI1 Transmit Data SSI1 Transmit Data with Exception Status SSI0 Transmit Last Slot (Reserved) (Reserved) Host Receive Data Full Host Transmit Data Empty Default Host Command (Reserved)
DSP56602 User's Manual
D-15
Programmer's Reference
Table Interrupt Source Priorities within
Priority Interrupt Source Level (Nonmaskable) Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Lowest Levels (Maskable) Highest IRQA (External Interrupt) IRQB (External Interrupt) IRQC (External Interrupt) IRQD (External Interrupt) Host Command Interrupt Host Transmit Data Full Host Receive Data Empty SSI0 Data with Exception Interrupt SSI0 Data Interrupt SSI0 Receive Last Slot Interrupt SSI0 Data with Exception Interrupt SSI0 Transmit Last Slot Interrupt SSI0 Data Interrupt SSI1 Data with Exception Interrupt SSI1 Data Interrupt SSI1 Receive Last Slot Interrupt
D-16
DSP56602 User's Manual
Programmer's Reference
Table Interrupt Source Priorities within (continued)
Priority Interrupt Source SSI1 Data with Exception Interrupt SSI1 Transmit Last Slot Interrupt SSI1 Data Interrupt Timer Overflow Interrupt Timer Compare Interrupt Timer Overflow Interrupt Timer Compare Interrupt Timer Overflow Interrupt Lowest Timer Compare Interrupt
Table Internal Memory
Peripheral Address $FFFF $FFFE $FFFD $FFFC OnCE $FFFB $FFFA $FFF9 Patch $FFF8 $FFF7 $FFF6 $FFF5 BPMR $FFF4 Register Name IPR-C-Interrupt Priority Register-Core IPR-P-Interrupt Priority Register-Peripheral PCTL0-PLL Control Register PCTL1-PLL Control Register OGDBR-OnCE Register BCR-Bus Control Register IDR-ID Register PAR0-Patch Register PAR1-Patch Register PAR2-Patch Register PAR3-Patch Register BPMRG-Bus Switch Program Memory Register bits) Reset Value $0000 $0000 $0000 $0000 $0000 $001F $1602 uninitialized uninitialized uninitialized uninitialized uninitialized
DSP56602 User's Manual
D-17
Programmer's Reference
Table Internal Memory (continued)
Peripheral BPMR Address $FFF3 $FFF2 (Reserved) $FFF1 $FFF0 $FFEF $FFEE $FFED $FFEC $FFEB $FFEA $FFE9 $FFE8 $FFE7 $FFE6 $FFE5 $FFE4 $FFE3 $FFE2 $FFE1 $FFE0 $FFDF $FFDE $FFDD Register Name BPMRL-Bus Switch Program Memory Register bits) BPMRH-Bus Switch Program Memory Register High bits) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Reset Value uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized
D-18
DSP56602 User's Manual
Programmer's Reference
Table Internal Memory (continued)
Peripheral (Reserved) Address $FFDC $FFDB $FFDA $FFD9 $FFD8 $FFD7 $FFD6 $FFD5 $FFD4 $FFD3 $FFD2 $FFD1 $FFD0 $FFCF $FFCE $FFCD $FFCC $FFCB $FFCA HI08 $FFC9 $FFC8 $FFC7 $FFC6 $FFC5 $FFC4 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) HDR-HI08 Data Register HDDR-HI08 Data Direction Register HTX-HI08 Transmit Data Register HRX-HI08 Receive Data Register HBAR -HI08 Base Address Register HPCR-HI08 Port Control Register Register Name Reset Value uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized uninitialized $0000 $0000 $0000 $0000 $0000 $0000 uninitialized $0000 $0000 uninitialized $0080 $0000
DSP56602 User's Manual
D-19
Programmer's Reference
Table Internal Memory (continued)
Peripheral HI08 Address $FFC3 $FFC2 (Reserved) $FFC1 $FFC0 SSI0 $FFBF $FFBE $FFBD $FFBC $FFBB $FFBA $FFB9 $FFB8 $FFB7 $FFB6 (Reserved) $FFB5 $FFB4 $FFB3 $FFB2 $FFB1 $FFB0 SSI1 $FFAF $FFAE $FFAD $FFAC $FFAB Register Name HSR-HI08 Status Register HCR-HI08 Control Register (Reserved) (Reserved) PCRC-SSI Port Control Register PRRC-SSI GPIO Direction Register PDRC-SSI GPIO Data Register TX0-SSI Transmit Data Register TSR0-SSI Time Slot Register RX0-SSI Receive Data Register SSISR0-SSI Status Register CRC0-SSI Control Register CRB0-SSI Control Register CRA0-SSI Control Register (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) PCRD-SSI Port Control Register PRRD-SSI GPIO Direction Register PDRD-SSI GPIO Data Register TX1-SSI Transmit Data Register TSR1-SSI Time Slot Register Reset Value $0002 $0000 $0000 $0000 $0000 $0000 $0000 $0000 $0000 uninitialized $0040 $0000 $0000 $0000 $0000 $0000 $0000 $0000 $0000 $0000 $0000 $0000 $0000 $0000 $0000
D-20
DSP56602 User's Manual
Programmer's Reference
Table Internal Memory (continued)
Peripheral SSI1 Address $FFAA $FFA9 $FFA8 $FFA7 $FFA6 (Reserved) $FFA5 $FFA4 $FFA3 $FFA2 $FFA1 $FFA0 GPIO $FF9F $FF9E $FF9D Triple Timer $FF8F $FF8E $FF8D $FF8C $FF8B $FF8A $FF89 $FF88 $FF87 $FF86 $FF85 Register Name RX1-SSI Receive Data Register SSISR1-SSI Status Register CRC1-SSI Control Register CRB1-SSI Control Register CRA1-SSI Control Register (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) PCRE-GPIO Control Register PRRE-GPIO Direction Register PDRE-GPIO Data Register TCSR0-Timer Control/Status Register TLR0-Timer Load Register TCPR0-Timer Compare Register TCR0-Timer Count Register TCSR1-Timer Control/Status Register TLR1-Timer Load Register TCPR1-Timer Compare Register TCR1-Timer Count Register TCSR2-Timer Control/Status Register TLR2-Timer Load Register TCPR2-Timer Compare Register Reset Value uninitialized $0040 $0000 $0000 $0000 $0000 $0000 $0000 $0000 $0000 $0000 $0000 $0000 $0007 $0000 $0000 $0000 $0000 $0800 $0000 $0000 $0000 $0800 $0000 $0000
DSP56602 User's Manual
D-21
Programmer's Reference
Table Internal Memory (continued)
Peripheral Triple Timer Address $FF84 $FF83 $FF82 (Reserved) $FF81 $FF80 Register Name TCR2-Timer Count Register TPLR-Timer Prescaler Load Register TPCR-Timer Prescaler Count Register (Reserved) (Reserved) Reset Value $0000 $0000 uninitialized $0000 $0000
D-22
DSP56602 User's Manual
Programmer's Reference
PROGRAMMER'S SHEETS
following pages provide programmer's sheets that intended simplify programming various registers DSP56603. programmer's sheets provide room write value each hexadecimal value each register. programmer photocopy these sheets. programmer's sheets provided same order sections this document. Table lists sets programmer's sheets, registers described sheets, pages this appendix where sheets located. Table List Programmer's Sheets
Type Register JTAG Instruction Register JTAG Bypass Register JTAG Register OMR-Operating Mode Register SR-Status Register IPR-C-Interrupt Priority Register (Core) IPR-P-Interrupt Priority Register (Peripheral BCR- Control Register IDR-Identification Register PARn-Patch Registers BPMRG-Bus Switch Program Memory Register BPMRL-Bus Switch Program Memory Register BPMRH-Bus Switch Program Memory Register High PCTL0-PLL Control Register PCTL1-PLL Control Register HI08 HSR-HI08 Status Register HCR-HI08 Control Register HPCR-HI08 Port Control Register Register Page D-26 D-26 D-26 D-27 D-28 D-29 D-30 D-31 D-31 D-32 D-33 D-33 D-33 D-34 D-34 D-35 D-35 D-36
DSP56602 User's Manual
D-23
Programmer's Reference
Table List Programmer's Sheets (continued)
Type Register HI08 Register HDDR-HI08 Data Direction Register HDR-HI08 Data Register HRX-HI08 Receive Data Register HTX-HI08 Transmit Data Register HBAR-HI08 Base Address Register ICR-Interface Control Register ISR-Interface Status Register CVR-Control Vector Register IVR-Interrupt Vector Register SSI0 CRA0-SSI0 Control Register CRB0-SSI0 Control Register CRC0-SSI0 Control Register SSISR0-SSI0 Status Register RX0-SSI0 Receive Register TSR0-SSI0 Time Slot Register TX0-SSI0 Transmit Register PCRC-SSI0 Port Control Register PDRC-SSI0 Port Data Register PRRC-SSI0 Port Data Direction Register SSI1 CRA1-SSI1 Control Register CRB1-SSI1 Control Register CRC1-SSI1 Control Register SSISR1-SSI1 Status Register RX1-SSI1 Receive Register TSR1-SSI1 Time Slot Register Page D-37 D-37 D-37 D-37 D-37 D-38 D-38 D-39 D-39 D-40 D-40 D-41 D-42 D-42 D-42 D-42 D-43 D-43 D-43 D-44 D-44 D-45 D-46 D-46 D-46
D-24
DSP56602 User's Manual
Programmer's Reference
Table List Programmer's Sheets (continued)
Type Register SSI1 Register TX1-SSI1 Transmit Register PCRD-SSI1 Port Control Register PDRD-SSI1 Port Data Register PRRD-SSI1 Port Data Direction Register GPIO PCRE-GPIO Port Control Register PDRE-GPIO Port Data Register PRRE-GPIO Port Data Direction Register Timers TPLR-Timer Prescaler Load Register TPCR-Timer Prescaler Count Register Timer0 TCSR0-Timer Control/Status Register TLR0-Timer Load Register TCPR0-Timer Compare Register TCR0-Timer Count Register Timer1 TCSR1-Timer Control/Status Register TLR1-Timer Load Register TCPR1-Timer Compare Register TCR1-Timer Count Register Timer2 TCSR2-Timer Control/Status Register TLR2-Timer Load Register TCPR2-Timer Compare Register TCR2-Timer Count Register Page D-46 D-47 D-47 D-47 D-48 D-48 D-48 D-49 D-49 D-50 D-50 D-50 D-50 D-51 D-51 D-51 D-51 D-52 D-52 D-52 D-52
DSP56602 User's Manual
D-25
Programmer's Reference
Application:
Date: Programmer:
Sheet
JTAG Instruction Register Reset Read/Write
JTAG Bypass Register Reset Read/Write
JTAG Register Read Only Reset $1182201D
AA1106a
D-26
DSP56602 User's Manual
Programmer's Reference
Application:
Date: Programmer:
Sheet
Mode 0-Extended 1-Normal 2-Normal 3-Normal 4-Normal 5-Normal 6-Normal 7-Normal
Reset Vector $0400 $0800 $0800 $0800 $0800 $0800 $0800 $0800
Description Stack extension mapped memory Stack extension mapped memory Description clock cycle delay clock cycle delay Description relative instructions enabled relative instructions disabled Description External controller enabled External controller disabled
Extended Stack Underflow Flag Extended Stack Overflow Flag Extended Stack Wrap Flag
Description Stack Extension disabled Stack Extension enabled Description Address Trace disabled Address Trace enabled
Operating Mode Register (OMR) Reset $0300 Read/Write
Extended Operating Mode Register Reserved, Program
Chip Operating Mode Register
AA1106b
DSP56602 User's Manual
D-27
Programmer's Reference
Application:
Date: Programmer:
Sheet
Carry Overflow Zero Negative Unnormalized Extension Limit Scaling
Exceptions Permitted Exceptions Masked Rounding scaling Scale down-1 arithmetic right shift Scale up-1 arithmetic left shift (Reserved) None Scaling Mode
FOREVER Flag
Arithmetic Saturation Mode Convergent rounding Automatic 32-bit saturation selected Rounding Mode Convergent rounding Two's-complement rounding
Loop Flag
Status Register (SR) Reset $0300 Read/Write
Mode Register
Condition Code Register
AA1106c
D-28
DSP56602 User's Manual
Programmer's Reference
Application:
Date: Programmer:
Sheet
IAL2 IBL2 ICL2 ICL1 ICL0 IBL1 IBL0
IAL1
IAL0
IRQA Mode IRQA disabled, IRQA enabled, IRQA enabled, IRQA enabled, IRQA disabled, IRQA enabled, IRQA enabled, IRQA enabled, Trigger Mode Level-Triggered Level-Triggered Level-Triggered Level-Triggered
Trigger Mode Level-Triggered Level-Triggered Level-Triggered Level-Triggered Negative-Edge Triggered Negative-Edge Triggered Negative-Edge Triggered Negative-Edge Triggered
IRQB Mode IRQB disabled, IRQB enabled, IRQB enabled, IRQB enabled, IRQB disabled, IRQB enabled, IRQB enabled, IRQB enabled, Trigger Mode Level-Triggered Level-Triggered Level-Triggered Level-Triggered
Negative-Edge Triggered Negative-Edge Triggered Negative-Edge Triggered Negative-Edge Triggered
IRQC Mode IRQC disabled, IRQC enabled, IRQC enabled, IRQC enabled, IRQC disabled, IRQC enabled, IRQC enabled, IRQC enabled, Trigger Mode Level-Triggered Level-Triggered Level-Triggered Level-Triggered
Negative-Edge Triggered Negative-Edge Triggered Negative-Edge Triggered Negative-Edge Triggered
IDL2
IDL1
IDL0
IRQD Mode IRQD disabled, IRQD enabled, IRQD enabled, IRQD enabled, IRQD disabled, IRQD enabled, IRQD enabled, IRQD enabled,
Negative-Edge Triggered Negative-Edge Triggered Negative-Edge Triggered Negative-Edge Triggered
IDL2
IDL1
IDL0
ICL2
ICL1
ICL0
IBL2
IBL1
IBL0
IAL2
IAL1
IAL0
Interrupt Priority Register-Core (IPR-C) X:$FFFF Reset $0000
Reserved, Program
AA1106d
DSP56602 User's Manual
D-29
Programmer's Reference
Application:
Date: Programmer:
Sheet
SSI1 S1L1 S1L0 Mode Interrupts disabled Interrupts enabled, Interrupts enabled, Interrupts enabled,
HI08 HPL1 HPL0 Mode Interrupts disabled Interrupts enabled, Interrupts enabled, Interrupts enabled,
SSI0 S0L1 S0L0 Mode Interrupts disabled Interrupts enabled, Interrupts enabled, Interrupts enabled,
Timer TPL1 TPL0 Mode Interrupts disabled Interrupts enabled, Interrupts enabled, Interrupts enabled,
TPL1
TPL0
S1L1
S1L0
S0L1
S0L0
Interrupt Priority Register-Peripheral (IPR-P) X:$FFFE Reset $0000
HPL1 HPL0
Reserved, Program
AA1106e
D-30
DSP56602 User's Manual
Programmer's Reference
Application:
Date: Programmer:
Sheet
Wait state field external memory, binary encoded
Control Register (BCR) X:$FFFA Reset $001F
BMW4 BMW3 BMW2 BMW1 BMW0
Reserved, Program
Revision
Device Number
DSP56602 Identification Register (IDR) X:$FFF9 Read-Only
AA1106f
DSP56602 User's Manual
D-31
Programmer's Reference
Application:
Date: Programmer:
Sheet
Patch Register (PAR0) X:$FFF8 Reset uninitialized
Patch Register (PAR1) X:$FFF7 Reset uninitialized
Patch Register (PAR2) X:$FFF6 Reset uninitialized
Patch Register (PAR3) X:$FFF5 Reset uninitialized
AA1106g
D-32
DSP56602 User's Manual
Programmer's Reference
Application:
Date: Programmer:
Sheet
Switch Program Memory Register (BPMRG) X:$FFF4 Reset uninitialized
BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR
Switch Program Memory Register (BPMRL) X:$FFF3 Reset uninitialized
BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR
Switch Program Memory Register High (BPMRH) X:$FFF2 Reset $0000
BPMR BPMR BPMR BPMR BPMR BPMR BPMR BPMR
Reserved, Program
AA1106h
DSP56602 User's Manual
D-33
Programmer's Reference
Application:
Date: Programmer:
Sheet
Predivider Factor
with PD4-PD6 PCTL1
Multiplication Factor
Control Register (PCTL0) X:$FFFD Reset $0000
MF11 MF10
PSTP
Description disabled during Stop state operates during Stop state Description disabled enabled Description disabled during Stop state operates during Stop state
XTLD
Description XTAL output enabled XTAL output disabled (XTAL pulled high)
XTLR
Description external crystal frequency above external crystal frequency below
Predivider Factor with PD0-PD3 PCTL0
Division Factor
PSTP
Control Register (PCTL1) X:$FFFC Reset $0000
XTLD XTLR
Reserved, Program
AA1107
D-34
DSP56602 User's Manual
Programmer's Reference
Application:
Date: Programmer:
Sheet
HI08
Description Host Command Interrupt pending cleared) Host Command Interrupt pending set) HTDE
HRDF
Description register full register full Description
register empty register empty
HF0, General purpose flags. Values reflect HF0, host side.
HI08 Status Register (HSR) X:$FFC3 Reset $0002 Read-Only
HRIE HTIE HCIE Description Host Command Interrupt disabled Host Command Interrupt enabled
Description Host Receive Data Interrupt disabled Host Receive Data Interrupt enabled Description
Host Transmit Data Interrupt disabled Host Transmit Data Interrupt enabled
HF2, General purpose flags. Values reflect HF2, host side
HI08 Control Register (HCR) X:$FFC2 Reset $0000 Read/Write
HCIE HTIE HRIE
Reserved, Program
AA1108a
DSP56602 User's Manual
D-35
Programmer's Reference
Application:
Date: Programmer:
Sheet
HI08
HROD HDSP HASP HMUX HDDS HCSP Description
Description HI08 disabled HI08 enabled HAEN Description HACK configured GPIO HACK Host Acknowledge input Description HREQ/HTRQ HACK/HRRQ used GPIO HREQ/HTRQ HACK/HRRQ enabled (mode-dependent) HCSEN Description HCS/HA10 used GPIO HCS/HA10 enabled Description used GPIO enabled Description used GPIO enabled Description Disconnects pins configured GPIO Enables pins configured GPIO
HREQ open drain HREQ open drain Description Data strobe pins active Data strobe pins active high Description active active high Description HI08 uses non-multiplexed HI08 non-multiplexed Description Single strobe mode Dual strobe mode Description active active high Description HREQ HTRQ HRRQ pins) active HREQ HTRQ HRRQ pins) active high Description HACK active HACK active high
HREN
HA9EN HA8EN HGEN
HI08 Port Control Register (HPCR) X:$FFC4 Reset $0000 Read/Write
HGEN
HCSP HDDS HMUX HASP HDSP HROD
HAEN HREN
Reserved, Program
AA1108b
D-36
DSP56602 User's Manual
Programmer's Reference
Application:
Date: Programmer:
Sheet
HI08
DR12
DR11
Description used input used output
DR10
HI08 Data Direction Register (HDDR) X:$FFC8 Reset $0000 Read/Write
DR15
DR14 DR13
HI08 Data Register (HDR) X:$FFC9 Reset $0000 Read/Write
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
HI08 Receive Data Register (HRX) X:$FFC6 Reset $0000 Read-Only
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
HI08 Transmit Data Register (HTX) X:$FFC7 Reset $0000 Write-Only
Data
BA10
HI08 Base Address Register (HBAR) X:$FFC5 Reset $0080 Read/Write
Reserved, Program
AA1108c
DSP56602 User's Manual
D-37
Programmer's Reference
Application:
Date: Programmer:
Sheet
HI08
HDRQ HF0, General purpose flags, values reflect HF0, side HLEND Description Data accessed "big end" first Data accessed "little end" first TREQ RREQ
Description HREQ HACK selected selected Description HACK disabled HACK enabled Description HREQ disabled HRRQ enabled
INIT Table 7-10 page 7-25
Interface Control Register (ICR) Reset Read/Write
INIT
HDRQ TREQ RREQ
TRDY HF2, General purpose flags, values reflect HF2, side HREQ Description HREQ deasserted enabled, HREQ asserted
Description Transmit FIFO empty Transmit FIFO contains data Description register full register empty Description register empty register full
TXDE RXDF
Interface Status Register (ISR) Reset Read Only
HREQ
TRDY TXDE RXDF
Reserved, Program
AA1108d
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HI08
Description host command pending Host command pending
HV0-HV6 Equals register interrupt vector
Control Vector Register (CVR) Reset Read/Write
IV0-IV7 Contains interrupt vector MC68000 family
Interrupt Vector Register (IVR) Reset Read/Write
AA1108e
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SSI0
Description bits word bits word bits word (Reserved)
Frame Rate Divider Bits binary encoded
Prescale Modulus Bits binary encoded
Control Register (CRA0) X:$FFB6 Reset $0000 Read/Write
TLIE RLIE TEIE REIE
Description (Bit cleared) Underrun Occurred Description
Description Receive Interrupt disabled Receive Interrupt enabled Description Transmit Interrupt disabled Transmit Interrupt enabled Description Receive disabled Receive enabled Description Transmit disabled Transmit enabled Serial Output Flags
(Bit cleared) Underrun Occurred
Description (Bit cleared) Underrun Occurred
Description (Bit cleared) Underrun Occurred
Control Register (CRB0) X:$FFB7 Reset $0000 Read/Write
REIE
TEIE
RLIE
TLIE
Reserved, Program
AA1109a
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SSI0
Description Data clocked rising edge clock, latched falling edge clock Data clocked falling edge clock, latched rising edge clock Description Data shifted first Data shifted first Description clock both One-bit clock clock One-bit clock both clock One-bit clock Description Frame synch occurs with first current word Frame synch occurs with last previous word Description Positive frame synch Negative frame synch
SCKD SCD2 SCD1
Description External clock source Internal clock source Description input output Description input output Description input output Description Normal mode selected Network mode selected
SHFD
SCD0
FSL1 FSL0
Description Asynchronous mode selected Synchronous mode selected
FSL1
FSL0
SHFD
Control Register (CRC0) X:$FFB8 Reset $0000
SCKD SCD2 SCD1 SCD0
Reserved, Program
AA1109b
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SSI0
Description (Bit cleared) Overrun Occurred Description (Bit cleared) Data Register Empty Description (Bit cleared) Data Register data
Description (Bit cleared) Underrun Occurred
Description Frame Sync Frame Sync Occurred Description Frame Sync Frame Sync Occurred Serial Input Flags
Status Register (SSISR0) X:$FFB9 Reset $0040
Reserved, Program
Receive Register (RX0) X:$FFBA Read-Only
High Byte
Byte
Time Slot Register (TSR0) X:$FFBB Write-Only
Dummy Register, Written During Inactive Time Slots
Transmit Register (TX0) X:$FFBC Write-Only
High Byte
Byte
Reserved, Program
AA1109c
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SSI0
Description pins tri-stated pins enabled
Description GPIO
Port Control Register (PCRC) X:$FFBF Reset $0000 Read/Write
Description input output
Port Data Register (PDRC) X:$FFBD Reset $0000 Read/Write
Port Data Direction Register (PRRC) X:$FFBE Reset $0000 Read/Write
PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
Reserved, Program
AA1109d
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SSI1
Description bits word bits word bits word (Reserved)
Frame Rate Divider Bits binary encoded
Prescale Modulus Bits binary encoded
Control Register (CRA1) X:$FFA6 Reset $0000 Read/Write
TLIE RLIE TEIE REIE
Description (Bit cleared) Underrun Occurred Description
Description Receive Interrupt disabled Receive Interrupt enabled Description Transmit Interrupt disabled Transmit Interrupt enabled Description Receive disabled Receive enabled Description Transmit disabled Transmit enabled Serial Output Flags
(Bit cleared) Underrun Occurred
Description (Bit cleared) Underrun Occurred
Description (Bit cleared) Underrun Occurred
Control Register (CRB1) X:$FFA7 Reset $0000 Read/Write
REIE
TEIE
RLIE
TLIE
Reserved, Program
AA1110a
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SSI1
Description Data clocked rising edge clock, latched falling edge clock Data clocked falling edge clock, latched rising edge clock Description Data shifted first Data shifted first Description clock both One-bit clock clock One-bit clock both clock One-bit clock Description Frame synch occurs with first current word Frame synch occurs with last previous word Description Positive frame synch Negative frame synch
SCKD SCD2 SCD1
Description External clock source Internal clock source Description input output Description input output Description input output Description Normal mode selected Network mode selected
SHFD
SCD0
FSL1 FSL0
Description Asynchronous mode selected Synchronous mode selected
FSL1
FSL0
SHFD
Control Register (CRC1) X:$FFA8 Reset $0000
SCKD SCD2 SCD1 SCD0
Reserved, Program
AA1110b
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SSI1
Description (Bit cleared) Overrun Occurred Description (Bit cleared) Data Register Empty Description (Bit cleared) Data Register data
Description (Bit cleared) Underrun Occurred
Description Frame Sync Frame Sync Occurred Description Frame Sync Frame Sync Occurred Serial Input Flags
Status Register (SSISR1) X:$FFA9 Reset $0040
Reserved, Program
Receive Register (RX1) X:$FFAA Read-Only
High Byte
Byte
Time Slot Register (TSR1) X:$FFAB Write-Only
Dummy Register, Written During Inactive Time Slots
Transmit Register (TX1) X:$FFAC Write-Only
High Byte
Byte
Reserved, Program
AA1110c
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Sheet
SSI1
Port Control Register (PCRD) X:$FFAF Reset $0000 Read/Write
Description pins tri-stated pins enabled
Description GPIO
Description input output
Port Data Register (PDRD) X:$FFAD Reset $0000 Read/Write
Port Data Direction Register (PRRD) X:$FFAE Reset $0000 Read/Write
PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
Reserved, Program
AA1110d
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GPIO
GPIO Port Control Register (PCRE) X:$FF9F Reset $0000 Read/Write
PDCn
Port Function GPIO input GPIO output tri-stated GPIO output, open-drain
GPIO Port Direction Register (PRRE) X:$FF9E Reset $0000 Read/Write
PDC2 PDC1 PDC0
GPIO Port Data Register (PDRE) X:$FF9D Reset $0007 Read/Write
Reserved, Program
AA1111
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Timers
Prescaler Clock Source Internal Clock TIO0 TIO1 TIO2 PL0-PL13 Prescaler load value
PL13
PL12
PL11
PL10
Timer Prescaler Load Register (TPLR) X:$FF83 Reset $0000 Read/Write
PC0-PC13 Prescaler count value
PC13
PC12
PC11
PC10
Timer Prescaler Count Register (TPCR) X:$FF82 Reset uninitialized Read-Only
Reserved, Program
AA1112a
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Timer0
Description Timer free-running Timer reloads when value reached Description (bit cleared) Timer Overflow detected Description (bit cleared) Timer reached value Description Prescaler disabled Prescaler enabled
Description input output TCIE Data Input (DI)-Bit page 9-11 Data Output (DO)-Bit page 9-12 TOIE
Description Timer increments rising transitions Timer increments falling transitions
Inverter (INV)-Bit page 9-11 more information. Description Timer Compare Interrupt disabled Timer Compare Interrupt enabled Description Timer Overflow Interrupt disabled Timer Overflow Interrupt enabled
Timer Mode Control Bits Table page 9-10
Description Timer disabled Timer enabled
Timer Control/ Status Register (TCSR0) X:$FF8F Reset $0000 Read/Write Timer Load Register (TLR0) X:$FF8E Reset Uninitialized Write-Only
TCIE
TOIE
Timer Compare Register (TCPR0) X:$FF8D Reset Uninitialized Read/Write
Timer Count Register (TCR0) X:$FF8C Reset $0000 Read-Only Reserved, Program
AA1112b
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Timer1
Description Timer free-running Timer reloads when value reached Description (bit cleared) Timer Overflow detected Description (bit cleared) Timer reached value Description Prescaler disabled Prescaler enabled
Description input output TCIE Data Input (DI)-Bit page 9-11 Data Output (DO)-Bit page 9-12 TOIE
Description Timer increments rising transitions Timer increments falling transitions
Inverter (INV)-Bit page 9-11 more information. Description Timer Compare Interrupt disabled Timer Compare Interrupt enabled Description Timer Overflow Interrupt disabled Timer Overflow Interrupt enabled
Timer Mode Control Bits Table page 9-10
Description Timer disabled Timer enabled
Timer Control/ Status Register (TCSR1) X:$FF8B Reset $0800 Read/Write Timer Load Register (TLR1) X:$FF8A Reset Uninitialized Write-Only
TCIE
TOIE
Timer Compare Register (TCPR1) X:$FF89 Reset Uninitialized Read/Write
Timer Count Register (TCR1) X:$FF88 Reset $0000 Read-Only Reserved, Program
AA1112c
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Timer2
Description Timer free-running Timer reloads when value reached Description (bit cleared) Timer Overflow detected Description (bit cleared) Timer reached value Description Prescaler disabled Prescaler enabled
Description input output TCIE Data Input (DI)-Bit page 9-11 Data Output (DO)-Bit page 9-12 TOIE
Description Timer increments rising transitions Timer increments falling transitions
Inverter (INV)-Bit page 9-11 more information. Description Timer Compare Interrupt disabled Timer Compare Interrupt enabled Description Timer Overflow Interrupt disabled Timer Overflow Interrupt enabled
Timer Mode Control Bits Table page 9-10
Description Timer disabled Timer enabled
Timer Control/ Status Register (TCSR2) X:$FF87 Reset $0800 Read/Write Timer Load Register (TLR2) X:$FF86 Reset Uninitialized Write-Only
TCIE
TOIE
Timer Compare Register (TCPR2) X:$FF85 Reset Uninitialized Read/Write
Timer Count Register (TCR2) X:$FF84 Reset $0000 Read-Only Reserved, Program
AA1112d
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DSP56602 User's Manual Programmer's Reference INTRODUCTION I

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