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HM66AEB36104/HM66AEB18204 HM66AEB9404
36-Mbit SRAM 4-word Burst
ADE-203-1368 Preliminary Rev. Jan. 2003 Description
HM66AEB36104 1,048,576-word 36-bit, HM66AEB18204 2,097,152-word 18-bit, HM66AEB9404 4,194,304-word 9-bit synchronous double data rate static fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. integrates unique synchronous peripheral circuitry burst counter. input registers controlled input clock pair latched positive edge These products suitable applications which require synchronous operation, high speed, voltage, high density wide configuration. These products packaged 165-pin plastic FBGA package.
Preliminary: specifications this device subject change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specifications.
HM66AEB36104/18204/9404
Features
power supply core (VDD) power supply (VDDQ) circuitry wide output data valid window future frequency scaling Pipelined double data rate operation Common data input/output Four-tick burst reduced address frequency input clocks precise timing clock rising edges only output clocks precise flight time clock skew matching-clock data delivered together receiving device Internally self-timed write control Clock-stop capability with restart User programmable impedance output Fast clock cycle time: (333 MHz)/3.3 (300 MHz)/4.0 (250 MHz)/ (200 MHz)/6.0 (167 MHz) Simple control logic easy depth expansion JTAG boundary scan
Ordering Information
Type HM66AEB36104BP-30 HM66AEB36104BP-33 HM66AEB36104BP-40 HM66AEB36104BP-50 HM66AEB36104BP-60 HM66AEB18204BP-30 HM66AEB18204BP-33 HM66AEB18204BP-40 HM66AEB18204BP-50 HM66AEB18204BP-60 HM66AEB9404BP-30 HM66AEB9404BP-33 HM66AEB9404BP-40 HM66AEB9404BP-50 HM66AEB9404BP-60 Organization word 36-bit Cycle time Clock frequency Package Plastic FBGA 165-pin (BP-165A)
word 18-bit
word 9-bit
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Arrangement (HM66AEB36104) 165PIN-BGA
DOFF DQ27 DQ29 DQ30 DQ31 VREF DQ33 DQ35 DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQ17 DQ15 VREF DQ13 DQ12 DQ11 DQ16 DQ14 DQ10
(Top view)
Arrangement (HM66AEB18204) 165PIN-BGA
DOFF DQ12 VREF DQ15 DQ10 DQ11 DQ13 VDDQ DQ14 DQ16 DQ17 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF
(Top view)
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Arrangement (HM66AEB9404) 165PIN-BGA
DOFF VREF VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF
(Top view)
Note: Note that SA1. product does permit random start address least significant address bits. SA0, start each address.
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Descriptions
Name type Descriptions Input Synchronous address inputs: These inputs registered must meet setup hold times around rising edge Ball reserved next higher-order address input future devices. transactions operate burst-of-four words (two clock periods activity). used lowest address bits burst READ burst WRITE operations permitting random burst start address devices. These inputs ignored when device deselected once burst operation progress. Synchronous load: This input brought when cycle sequence defined. This definition includes address READ WRITE direction. transactions operate burst-of-four data (two clock periods activity). Synchronous read write Input: When low, this input designates access type (READ when high, WRITE when low) loaded address. must meet setup hold times around rising edge Synchronous byte writes: When low, these inputs cause their respective byte registered written during WRITE cycles. These signals must meet setup hold times around rising edges each rising edges comprising WRITE cycle. Byte Write Truth Table signal data relationship. Input clock: This input clock pair registers address control inputs rising edge registers data rising edge rising edge ideally degrees phase with synchronous inputs must meet setup hold times around clock rising edges. Output clock: This clock pair provides user-controlled means tuning device output data. rising edge used output timing reference second fourth output data. rising edge used output reference first third output data. Ideally, degrees phase with tied high force output reference clocks instead having provide clocks. tied high, must remain high toggled during device operation. disable: When low, this input causes bypassed stable, lowfrequency operation. Output impedance matching input: This input used tune device outputs system data impedance. output impedance where resistor from this ball ground. Alternately, this ball connected directly VDDQ, which enables minimum impedance mode. This ball cannot connected directly left unconnected. IEEE1149.1 test inputs: levels. These balls left connected JTAG function used circuit. IEEE1149.1 clock input: levels. This ball must tied JTAG function used circuit.
Input
Input
Input
Input
Input
DOFF
Input Input
Input Input
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Name type Descriptions Input/ output Synchronous data I/Os: Input data must meet setup hold times around rising edges Output data synchronized respective data clocks, respective tied high. device uses DQ8. Remaining signals device uses DQ17. Remaining signals device uses DQ35. signals read JTAG scan chain logic level applied ball site.
Output Synchronous echo clock outputs: edges these outputs tightly matched synchronous data outputs used data valid indication. These signals freely stop when tri-states. Output IEEE 1149.1 test output: level. Supply Power supply: nominal. Characteristics Operating Conditions range. Supply Power supply: Isolated output buffer supply. Nominally also permissible. Characteristics Operating Conditions range. Supply Power supply: Ground HSTL input reference voltage: Nominally VDDQ/2. Provides reference voltage input buffers. connect: These signals internally connected appear JTAG scan chain logic level applied ball sites. These signals connected ground improve package heat dissipation.
VDDQ VREF
Note:
power supply ground balls must connected proper operation device.
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Block Diagram (HM66AEB36104)
Address Registry Logic SA1' SA0' SA0'' Output SA0''' Control Logic
Burst Logic
WRITE Register
Output Register
WRITE Driver
Output Buffer Output Select
Sense Amps
Data Registry Logic
DQ0-35
Memory Array
Block Diagram (HM66AEB18204)
Address Registry Logic SA1' SA0' SA0'' Output SA0''' Control Logic
Burst Logic
WRITE Register
Output Register
WRITE Driver
Output Buffer Output Select
Sense Amps
Data Registry Logic
DQ0-17
Memory Array
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Block Diagram (HM66AEB9404)
Address Registry Logic
WRITE Register
Output Register
WRITE Driver
Output Buffer Output Select
Data Registry Logic
DQ0-8
Sense Amps
Memory Array
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Burst Sequence
Linear Burst Sequence Table (HM66AEB36104/18204)
SA1, External address internal burst address internal burst address internal burst address SA1, SA1, SA1,
Truth Table
Operation WRITE cycle Load address, input write data consecutive rising edges Data Input data Input clock Data Output QA(A+0) data Output C(t+1) clock High-Z Previous state QA(A+1) C(t+2) QA(A+2) C(t+2) QA(A+3) C(t+3) DA(A+0) K(t+1) DA(A+1) K(t+1) DA(A+2) K(t+2) DA(A+3) K(t+2)
READ cycle Load address, read data consecutive rising edges
operation) Notes:
STANDBY (Clock stopped) Stopped
high level, level, don't care, rising edge. Data inputs registered rising edges. Data outputs delivered rising edges, except high, then data outputs delivered rising edges. control inputs truth table must meet setup/hold times around rising edges (low high) control inputs registered during rising edge This device contains circuitry that will ensure outputs will high-Z during power-up. Refer state diagram timing diagrams clarification. recommended that /(K) /(C) when clock stopped. This essential, permits most rapid restart overcoming transmission line charging symmetrically. "A+0" refers address input during WRITE READ cycle. "A+1", "A+2" "A+3" refer internal burst address accordance with linear burst sequence.
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Byte Write Truth Table
(HM66AEB36104)
Operation Write Write Write Write Write Write nothing
Notes: high level, level, rising edge. Assumes WRITE cycle initiated. altered portion burst WRITE operation provided that setup hold requirements satisfied.
(HM66AEB18204)
Operation Write Write Write Write nothing
Notes: high level, level, rising edge. Assumes WRITE cycle initiated. altered portion burst WRITE operation provided that setup hold requirements satisfied.
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(HM66AEB9404)
Operation Write Write nothing
Notes: high level, level, rising edge. Assumes WRITE cycle initiated. altered portion burst WRITE operation provided that setup hold requirements satisfied.
Cycle State Diagram
Count
Count Count
WRITE DOUBLE Count Count Always
ADVANCE ADDRESS
LOAD ADDRESS Count Count
Count
READ DOUBLE Count Count Always
ADVANCE ADDRESS Supply voltage provided
Count
POWER
Notes: internally advanced accordance with burst order table. cycle terminated after burst count State machine control timing sequence controlled
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Absolute Maximum Ratings
Parameter Input voltage ball Input/output voltage Core supply voltage Output supply voltage Junction temperature Storage temperature Symbol VI/O VDDQ TSTG Rating -0.5 (2.9 max.) -0.5 VDDQ (2.9 max.) -0.5 -0.5 +125 (max) +125 Unit Notes
Notes: voltage referenced VSS. Permanent device damage occur Absolute Maximum Ratings exceeded. Functional operation should restricted Operation Conditions. Exposure higher than recommended voltages extended periods time could affect device reliability. These CMOS memory circuits have been designed meet specifications shown tables after thermal equilibrium been established. following supply voltage application sequence recommended: VSS, VDD, VDDQ, VREF then VIN. Remember, according Absolute Maximum Ratings table, VDDQ exceed 2.9V, whatever instantaneous value VDDQ.
Recommended Operating Conditions +70°C)
Parameter Power supply voltage core Power supply voltage Input reference voltage Input high voltage Input voltage Symbol VDDQ VREF (DC) (DC) 0.68 VREF -0.3 0.75 0.95 VDDQ VREF Unit Notes
Notes: Peak peak component superimposed VREF exceed VREF. VREF 0.75 (typ). Overshoot: (AC) tKHKH/2 Undershoot: (AC) -0.5 tKHKH/2 Power-up: VDDQ VDDQ During normal operation, VDDQ must exceed VDD. Control input signals have pulse widths less than tKHKL (min) operate cycle rates less than tKHKH (min).
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Characteristics +70°C,
HM66AEB36104/HM66AEB18204 HM66AEB9404 Parameter Operating supply current (READ WRITE) Symbol Unit Notes
Standby supply current (NOP)
ISB1 ISB1
Notes
inputs (except VREF) held either VIL. IOUT max, tKHKH tKHKH min. Typical values measured VDDQ +25°C, tKHKH Operating supply currents measured 100% utilization. currents valid when entering after pending READ WRITE cycles completed.
Parameter Input leakage current
Symbol (Low) VDDQ VDDQ/2 0.08 VDDQ/2 0.08
VDDQ VDDQ/2 0.08 VDDQ/2 0.08
Unit Test conditions Notes |IOH| Notes1 Notes2
Output leakage current Output high voltage
Output voltage
(Low)
Output "High" current Output "Low" current
(VDDQ/2)/(RQ/5 10%) (VDDQ/2)/(RQ/5 10%) (VDDQ/2)/(RQ/5 10%) (VDDQ/2)/(RQ/5 10%)
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Notes: Outputs impedance-controlled. |IOH| (VDDQ/2)/(RQ/5) values Outputs impedance-controlled. (VDDQ/2)/(RQ/5) values load current higher than shown values. curves available upon request. HSTL outputs meet JEDEC HSTL Class Class standards. Measured VDDQ/2 Measured VDDQ/2 Output buffer impedance programmed terminating ball through precision resistor (RQ). value five times output impedance desired. allowable range guarantee impedance matching with tolerance typical. total external capacitance ball must less than VDDQ input balls (except ball) VOUT VDDQ, output disabled. VDDQ
Capacitance +25°C, MHz,
Parameter Input capacitance Clock input capacitance Input/output capacitance (DQ) Symbol CCLK CI/O Unit Test conditions VCLK VI/O
Notes: These parameters sampled 100% tested. Parameters tested with VDDQ
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Characteristics +70°C,
Test Conditions Input waveform (Rise/fall time
1.25 0.75 0.25 Test points 0.75
Output waveform
VDDQ/2
Test points
VDDQ/2
Output load condition
0.75
VREF 16.7 SRAM
16.7
0.75
16.7
0.75
0.75
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HM66AEB36104/18204/9404
Operating Conditions
Parameter Input high voltage Input voltage Notes: Symbol (AC) (AC) VREF VREF Unit Notes
voltages referenced (GND). Overshoot: (AC) tKHKH/2 Undershoot: (AC) -0.5 tKHKH/2 Power-up: VDDQ VDDQ During normal operation, VDDQ must exceed VDD. Control input signals have pulse widths less than tKHKL (min) operate cycle rates less than tKHKH (min). maintain valid level, transitioning edge input must: Sustain constant slew rate from current level through target level, (AC) (AC). Reach least target level. After target level reached, continue maintain least target level, (DC) (DC).
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HM66AEB36104/HM66AEB18204 HM66AEB9404 Parameter Symbol 3.00 3.47 3.30 4.20 4.00 5.25 5.00 6.30 6.00 7.88 Unit Notes
Average clock tKHKH cycle time Clock phase jitter
0.20
0.20
0.20
0.20
0.20
Clock high time tKHKL Clock time tKLKH Clock clock tKH/KH Clock clock t/KHKH Clock data tKHCH clock lock time
1.20 1.20 1.35 1.35
1.30
1.32 1.32 1.49 1.49
1.45
1.60 1.60 1.80 1.80
1.80
2.00 2.00 2.20 2.20
2.30
2.40 2.40 2.70 2.70
2.80
lock 1,024 0.45
1,024 0.45
1,024 0.45
1,024 0.45
1,024 0.50
Cycle
static reset reset high output valid high output hold high echo clock valid tCHQV tCHQX tCHCQV
-0.45 0.45
-0.45 0.45
-0.45 0.45
-0.45 0.45
-0.50 0.50
high tCHCQX echo clock hold high tCQHQV output valid high tCQHQX output hold high output high-Z high output low-Z tCHQZ tCHQX1
-0.45 0.25
-0.45 0.27
-0.45 0.30
-0.45 0.35
-0.50 0.40
-0.25 0.45
-0.27 0.45
-0.30 0.45
-0.35 0.45
-0.40 0.50
-0.45
-0.45
-0.45
-0.45
-0.50
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HM66AEB36104/18204/9404
HM66AEB36104/HM66AEB18204 HM66AEB9404 Parameter Symbol 0.40 0.40 0.40 0.40 0.50 0.50 0.60 0.60 0.70 0.70 Unit Notes
Address valid tAVKH rising edge Control inputs tIVKH valid rising edge Data-in valid tDVKH rising edge rising edge tKHAX address hold rising edge tKHIX control inputs hold tKHDX rising edge data-in hold
0.28
0.30
0.35
0.40
0.50
0.40 0.40
0.40 0.40
0.50 0.50
0.60 0.60
0.70 0.70
0.28
0.30
0.35
0.40
0.50
Notes: This synchronous device. addresses, data control lines must meet specified setup hold times latching clock edges. slew rate must less than lock retention. lock time begins once input clock stable. recommended that device kept inactive during these cycles. Clock phase jitter variance from clock rising edge next expected clock rising edge. Echo clock very tightly controlled data valid data hold. design, there ±0.1 variation from echo clock data. datasheet parameters reflect tester guardbands test setup variations. Transitions measured ±100 from steady-state voltage. given voltage temperature tCHQZ less than tCHQX1 tCHQZ less than tCHQV. Remarks: This parameter sampled. Test conditions specified with output loading shown Test Conditions unless otherwise noted. Control input signals operated with pulse widths less than tKHKL (min). tied high, become references timing parameters. VDDQ +1.5
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HM66AEB36104/18204/9404
Timing Waveforms
Read Write Timing
READ (burst READ (burst WRITE (burst WRITE (burst READ (burst
tKHKH
tKHKL tKLKH
tKH/KH
t/KHKH
tIVKH tAVKH tKHAX
tKHIX
tKHDX tDVKH
tKHDX tDVKH
tKHCH
tCHCQX1 tKHCH tCHQV
tCHQX tCHQV
tCHQX tCQHQV
tCQHQX
tCHQZ
tCHCQX tCHCQV tCHCQX tCHCQV
tKHKLtKLKH tKHKH tKH/KH t/KHKH
Notes: refers output from address refers output from next internal burst address following etc. Outputs disable (high-Z) clock cycle after NOP. second cycle necessary correct device operation; however, high clock frequencies required prevent contention.
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HM66AEB36104/18204/9404
JTAG Specification
These products support limited JTAG functions IEEE standard 1149.1.
Disabling Test Access Port
possible this device without utilizing TAP. disable controller without interfering with normal operation device, must tied preclude level inputs. designed undriven input will produce response identical application logic left unconnected. they also tied through resistor. should left unconnected.
Test Access Port (TAP) Pins
Symbol assignments Description Test clock input. inputs captured rising edge outputs propagate from falling edge TCK. Test mode select. This command input controller state machine. Test data input. This input side serial registers placed between TDO. register placed between determined state controller state machine instruction that currently loaded instruction. Test data output. Output changes response falling edge TCK. This output side serial registers placed between TDO.
Note:
device does have TRST (TAP reset). Test-Logic Reset state entered while held high five rising edges TCK. controller state also reset SRAM POWER-UP.
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HM66AEB36104/18204/9404
Operating Characteristics +70°C,
Parameter Input high voltage Input voltage Input leakage current Output leakage current Output voltage Symbol VOL1 VOL2 Output high voltage VOH1 VOH2 -0.3 -5.0 -5.0 +0.5 +5.0 +5.0 Unit VDD, output disabled IOLC IOLT |IOHC| |IOHT| Conditions
Notes: voltages referenced (GND). Power-up: VDDQ +1.7 VDDQ +1.4 "EXTEST" mode "SAMPLE" mode, VDDQ nominally
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HM66AEB36104/18204/9404
Test Condition
Temperature Input timing measurement reference levels Input pulse levels Input rise/fall time Output timing measurement reference levels Test load termination supply voltage (VTT) Output load Input waveform
Test points
+70°C figures
Output waveform
Test points
Output load
External load test
Rev.0.0, Jan. 2003, page
HM66AEB36104/18204/9404
Operating Characteristics +70°C,
Parameter Test clock cycle time Test clock high pulse width Test clock pulse width Test mode select setup Test mode select hold Capture setup Capture hold valid high high invalid unknown valid Note: Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tTLQX tTLQV Unit Note
defines minimum pause transitions assure data capture.
Controller Timing Diagram
tTHTH tMVTH tTHMX tTHDX ADDRESS tTLQX tTLQV tDVTH tTHTL tTLTH
Test Access Port Registers
Register name Instruction register Bypass register register Boundary scan register Length bits bits bits Symbol [2:0] [31:0] [109:1]
Rev.0.0, Jan. 2003, page
HM66AEB36104/18204/9404
Controller Instruction
Instruction EXTEST Description EXTEST instruction allows circuitry external component package tested. Boundary scan register cells output balls used apply test vectors, while those input balls capture test results. Typically, first test vector applied using EXTEST instruction will shifted into boundary scan register using PRELOAD instruction. Thus, during Update-IR state EXTEST, output drive turned PRELOAD data driven onto output balls. IDCODE instruction causes loaded into register when controller capture-DR mode places register between balls shiftDR mode. IDCODE instruction default instruction loaded power time controller placed Test-Logic-Reset state. SAMPLE-Z instruction loaded instruction register, outputs forced inactive drive state (high-Z, except ball) boundary register connected between when controller moved shift-DR state. These instructions implemented reserved future use. these instructions. When SAMPLE instruction loaded instruction register, moving controller into capture-DR state loads data RAMs input buffers into boundary scan register. Because clock(s) independent from clock (TCK) possible attempt capture ring contents while input buffers transition (i.e., metastable state). Although allowing SAMPLE metastable input will harm device, repeatable results cannot expected. input signals must stabilized long enough meet TAPs input data capture setup plus hold time (tCS plus tCH). RAMs clock inputs need paused other operation except capturing ring contents into boundary scan register. Moving controller shift-DR state then places boundary scan register between balls. Notes
IDCODE
SAMPLE-Z
RESERVED SAMPLE (-PRELOAD)
RESERVED RESERVED BYPASS BYPASS instruction loaded instruction register when bypass register placed between TDO. This occurs when controller moved shift-DR state. This allows board level scan path shortened facilitate testing other devices scan path.
Notes: Data output register guaranteed EXTEST instruction loaded. After performing EXTEST, power-up conditions required order return part normal operation.
Rev.0.0, Jan. 2003, page
HM66AEB36104/18204/9404
Register
Part
HM66AEB36104 HM66AEB18204 HM66AEB9404
Revision number (31:29)
Type number (28:12)
00010011010001000 00010010010001000 00010000010001000
Vendor JEDEC code (11:1)
00000000111 00000000111 00000000111
Start
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Boundary Scan Order
Signal names Ball DQ11 DQ10 DQ12 DQ13 DQ14 Ball Signal names DQ10 DQ15 DQ17 DQ16 DQ27 DQ18 DQ19
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HM66AEB36104/18204/9404
Signal names Ball DOFF DQ11 DQ12 DQ13 DOFF DQ14 DQ28 DQ20 DQ29 DQ30 DQ21 DQ22 DQ31 DOFF DQ23 DQ32 Ball
Signal names INTERNAL DQ15 DQ16 DQ17 INTERNAL DQ33 DQ24 DQ25 DQ34 DQ26 DQ35 INTERNAL
Note: boundary scan mode, Clock balls referenced each other must opposite logic levels reliable operation. data synchronized respective tied high, generated with respect generated with respect
Rev.0.0, Jan. 2003, page
HM66AEB36104/18204/9404
Controller State Diagram
Test-LogicReset
Run-Test/ Idle
SelectDR-Scan Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR
SelectIR-Scan Capture-IR Shift-IR
Exit1-IR Pause-IR Exit2-IR Update-IR
Notes: value adjacent each state transition this figure represents signal present time rising edge TCK. matter what original state controller, will enter Test-Logic-Reset when held high least five rising edges TCK.
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Package Dimensions
HM66AEB36104/18204/9404BP (BP-165A)
Preliminary
Unit:
15.00 0.20
1.00
0.50 0.05
1.00
17.00 0.20
0.25
0.40 0.06
0.10
1.44 0.10
Hitachi Code JEDEC JEITA Mass (reference value)
BP-165A
Rev.0.0, Jan. 2003, page
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Disclaimer
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such failsafes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Sales Offices
Hitachi, Ltd.
Semiconductor Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109
further information write
Hitachi Semiconductor (America) Inc. East Tasman Drive Jose,CA 95134 Tel: (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Europe GmbH Electronic Components Group Dornacher D-85622 Feldkirchen Postfach 201, D-85619 Feldkirchen Germany Tel: <49> (89) 9180-0 Fax: <49> (89) Hitachi Asia Ltd. Hitachi Tower Collyer Quay #20-00 Singapore 049318 <65>-6538-6533/6538-8577 <65>-6538-6933/6538-3877 Hitachi Asia Ltd. (Taipei Branch Office) 4/F, 167, North Road Hung-Kuo Building Taipei (105), Taiwan <886>-(2)-2718-3666 <886>-(2)-2718-8180 Telex 23222 HAS-TP Hitachi Asia (Hong Kong) Ltd. Group (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Tsui, Kowloon Hong Kong <852>-2735-9218 <852>-2730-0281
Copyright Hitachi, Ltd., 2002. rights reserved. Printed Japan.
Colophon
Rev.0.0, Jan. 2003, page
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