Chip Errata MCF5102 Integrated ColdFire Processor December 1996 C
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Chip Errata MCF5102 Integrated ColdFire Processor December 1996
Contents this document intended only internal Motorola customers designing with this product. mask each part encoded into device topside markings example, following markings would indicate device from 3F94E mask, manufactured 51st week 1996: XCF5102PV20A 3F94E QEAQ9651 This errata applies following MCF5102 mask sets: Mask 3F94E 3F94E Processing Geometry 0.5u 0.5u Part Number XCF5102PV20A XCF5102PV25A
Thermal Considerations
Thermal considerations operation. Maximum Junction (Tj) Temperature cannot exceed degrees RSTI Assertion
RSTI asserted less than specified clocks, possible induce undetermined state requiring power cycle reset.
Waiter
When Waiter asserted, extra BCLK added beginning every cycle. operation WAITER mask 1F28T later will have idle clock guaranteed after every READ cycle allow additional DATA THREE-STATE time multiplexed bus. time specifications figure 10-3 User's Manual.
Low-Power Stop Mode
While CF5102 low-power stop mode, valid-to-valid interrupt level transition cause CF5102 wake from LPSTOP. order prevent recover from this condition, generate level interrupt re-assert valid interrupt. Otherwise, recover asserting reset-in (RSTI), cycling power.
MC68306 Errata 9/26/96
Copyright 1996 Motorola, Inc. rights reserved
Motorola Semiconductor Products Sector, High Performance Embedded Systems Division, Applications 6501 William Cannon Drive West, Austin, 78735-8598 Tel: (512) 891-4524 Fax: (512) 891-2943 (512) 891-4568 AESOP: pirs.aus.sps.mot.com (Login: pirs) (512) 891-3650 N/8/1/F
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