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Please contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor when considering product contained herein specific purposes, such apparatus systems transportation, vehicular, medical, aerospace, nuclear, undersea repeater use. prior written approval Renesas Technology Corporation necessary reprint reproduce whole part these materials. these products technologies subject Japanese export control restrictions, they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations Japan and/or country destination prohibited. Please contact Renesas Technology Corporation further details these materials products contained therein. HM62V16256CI Series Wide Temperature Range Version SRAM (256-kword 16-bit) ADE-203-1230C Rev. Jul. 2001 Description Hitachi HM62V16256CI Series 4-Mbit static organized 262,144-word 16-bit. HM62V16256CI Series realized higher density, higher performance power consumption employing CMOS process technology (6-transistor memory cell). offers power standby power dissipation; therefore, suitable battery backup systems. packaged standard 44-pin plastic TSOPII. Features Single supply: Fast access time: (max) Power dissipation: Active: mW/MHz (typ)(VCC mW/MHz (typ) (VCC Standby: (typ) (VCC (typ) (VCC Completely static memory. clock timing strobe required Equal access cycle times Common data input output. Three state output Battery backup operation. chip selection battery backup Temperature range: +85°C HM62V16256CI Series Ordering Information Type HM62V16256CLTTI-7 Access time Package 400-mil 44-pin plastic TSOPII (normal-bend type) (TTP-44DB) HM62V16256CI Series Arrangement 44-pin TSOP I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 (Top view) I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 Description name I/O0 I/O15 Function Address input Data input/output Chip select Chip select Write enable Output enable Lower byte select Upper byte select Power supply Ground HM62V16256CI Series Block Diagram decoder Memory matrix 2,048 2,048 I/O0 Input data control I/O15 Column Column decoder Control logic HM62V16256CI Series Operation Table I/O0 I/O7 High-Z High-Z High-Z Dout Dout High-Z High-Z High-Z I/O8 I/O15 High-Z High-Z High-Z Dout High-Z Dout High-Z High-Z Operation Standby Standby Standby Read Lower byte read Upper byte read Write Lower byte write Upper byte write Output disable Note: VIL, Absolute Maximum Ratings Parameter Power supply voltage relative Terminal voltage relative Power dissipation Storage temperature range Storage temperature range under bias Symbol Tstg Tbias Value -0.5 -0.5* 0.3* +125 Unit Notes: min: -3.0 pulse half-width Maximum voltage +4.6 Operating Conditions Parameter Supply voltage Symbol Input high voltage Input voltage Ambient temperature range Note: -0.2 -0.3 2.5/3.0 Unit Note min: -3.0 pulse half-width HM62V16256CI Series Characteristics Parameter Input leakage current Output leakage current Symbol |ILI| |ILO Typ* Unit Test conditions VI/O VIL, VIH, Others VIH/VIL, Min. cycle, duty 100%, VIL, VIH, Others VIH/VIL Cycle time duty 100%, -0.5 -100 Operating current Average operating current Standby current Standby current SB1* Output high voltage =2.2 =2.7 =2.2 0.2- Output voltage =2.2 =2.7 =2.2 Notes: Typical values V/3.0 +25°C guaranteed. This characteristic guaranteed only L-version. Capacitance +25°C, MHz) Parameter Input capacitance Input/output capacitance Note: Symbol CI/O Unit Test conditions VI/O Note This parameter sampled 100% tested. HM62V16256CI Series Characteristics +85°C, unless otherwise noted.) Test Conditions Input pulse levels: (VCC (VCC Input rise fall time: Input/output timing reference levels: (VCC Output load: figures (Including scope jig) V Dout 3070 30pF 3150 Dout 50pF RL=500 Output load (VCC Output load (VCC HM62V16256CI Series Read Cycle HM62V16256CI Parameter Read cycle time Address access time Chip select access time Symbol ACS1 ACS2 Output enable output valid Output hold from address change access time Chip select output low-Z CLZ1 CLZ2 enable low-z Output enable output low-Z Chip deselect output high-Z CHZ1 CHZ2 disable high-Z Output disable output high-Z Unit Notes HM62V16256CI Series Write Cycle HM62V16256CI Parameter Write cycle time Address valid write Chip selection write Write pulse width valid write Address setup time Write recovery time Data write time overlap Data hold from write time Output active from write Output disable output High-Z Write output high-Z Symbol Unit Notes Notes: CHZ, tOHZ tBHZ defined time which outputs achieve open circuit conditions referred output voltage levels. This parameter sampled 100% tested. given temperature voltage condition, less than both given device from device device. write occures during overlap CS1, high CS2, write begins latest transition among going low, going high, going going going low. write ends earliest transition among going high, going low, going high going high going high. measured from beginning write write. measured from later going going high write. measured from address valid beginning write. measured from earliest going high going write cycle. HM62V16256CI Series Timing Waveform Read Cycle Address tACS1 tCLZ1*2, tCHZ1 Valid address tACS2 tCLZ2*2, tCHZ2*1, tBHZ*1, tBLZ*2, tOLZ*2, Dout High impedance Valid data tOHZ*1, HM62V16256CI Series Write Cycle Clock) Address Valid address tWR*7 tCW*5 tCW*5 tWP*4 tAS*6 tWHZ*1, Valid data tOW*2 High impedance Dout HM62V16256CI Series Write Cycle Clock, VIH) Address Valid address tAS*6 tCW*5 tCW*5 tWR*7 tWP*4 Valid data High impedance Dout HM62V16256CI Series Write Cycle (LB, Clock, VIH) Address Valid address tCW*5 tCW*5 tAS*6 tWR*7 tWP*4 Valid data High impedance Dout HM62V16256CI Series Data Retention Characteristics +85°C) Parameter data retention Symbol Typ* Unit Test conditions*2 retention waveform Data retention current CCDR*1 Chip deselect data retention time Operation recovery time Notes: This characteristic guaranteed only L-version, max. +40°C. controls address buffer, buffer, buffer, buffer, buffer buffer. controls data retention mode, levels (address, CS1, I/O) high impedance state. controls data retention mode, must other input levels (address, I/O) high impedance state. Typical values +25°C guaranteed. read cycle time. HM62V16256CI Series Data Retention Timing Waveform (CS1 Controlled) (VCC Data retention mode Data Retention Timing Waveform (CS1 Controlled) (VCC Data retention mode Data Retention Timing Waveform (CS2 Controlled) (VCC Data retention mode HM62V16256CI Series Data Retention Timing Waveform (CS2 Controlled) (VCC Data retention mode Data Retention Timing Waveform (LB, Controlled) (VCC Data retention mode Data Retention Timing Waveform (LB, Controlled) (VCC Data retention mode HM62V16256CI Series Package Dimensions HM62V16256CLTTI Series (TTP-44DB) January, 2001 18.41 18.81 Unit: *0.30 0.10 0.25 0.05 0.80 0.13 0.80 11.76 0.20 *0.17 0.05 0.125 0.04 0.50 0.10 1.005 1.20 10.16 0.10 0.13 0.05 *Dimension including plating thickness Base material dimension Hitachi Code JEDEC EIAJ Mass (reference value) TTP-44DB 0.43 HM62V16256CI Series Cautions Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products. Hitachi, Ltd. Semiconductor Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109 further information write Hitachi Semiconductor (America) Inc. East Tasman Drive Jose,CA 95134 Tel: (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 585200 Hitachi Europe GmbH Electronic Components Group Dornacher D-85622 Feldkirchen Postfach 201,D-85619 Feldkirchen Germany Tel: <49> (89) 9180-0 Fax: <49> (89) Hitachi Asia Ltd. Hitachi Tower Collyer Quay #20-00 Singapore 049318 <65>-538-6533/538-8577 <65>-538-6933/538-3877 Hitachi Asia Ltd. (Taipei Branch Office) 4/F, 167, North Road Hung-Kuo Building Taipei (105), Taiwan <886>-(2)-2718-3666 <886>-(2)-2718-8180 Telex 23222 HAS-TP http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Tsui, Kowloon Hong Kong <852>-(2)-735-9218 <852>-(2)-730-0281 Copyright Hitachi, Ltd., 2001. rights reserved. Printed Japan. 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