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HD49815TF
Digital Camera Signal Processor
ADE-207-316 Edition Sep. 1999 Description
HD49815TF CMOS that been developed digital signal-processing CCD-camera digital-signal-processing systems.
Functions
CCD-sensor drive-pulse generation (TG) Digital (automatic gain control) Color signal separation circuit matrix gain gamma Color-difference matrix Enhancer setup Digital (4:2:2) Zoom control Mirror reversal Synchronization signal generator encoding (SSG) AWB, detection Two-channel 8-bit converter
Features
HD49815TF provides camera-signal processing, SSG, zoom, functions other functions single chip supports high system-integration level. conjunction with HD49323AF-01 (CDS/AGC 10-bit ADC) control microcomputer, HD49815TF forms three-chip that implement optimal CCD-camera digital-signalprocessing system. HD49815TF provides zoom function controls 256- times linear zoom. also provides half-mirror function.
HD49815TF
Features (cont)
Since HD49815TF made compatible with former product, HD49811TFA, through software, shorter development term enabled. Since software controls AWB, protocol prepared according camera shooting conditions. Programmable enables device.
System Block Diagram
HD49815TF Lens HD49323AF-01 CDS/AGC+ 10-bit Input line memory Color processing Luminance processing Microprocessor Zoom processing C-signal output Y-signal output R-Y/B-Y digital output Y-signal digital output
V.Driver
Encode
System control
(iris) control
(white balance) control
8-bit single-chip microcomputer series)
HD49815TF
Arrangement
DSP_MCK
CPREF
XSG2
XSG1
XSUB DKF_LD T_CP(TEST) TY_K SDCK EP(1) EP(2) HD_IN M_CK CBLK CSYNC SCBLK HSYNC MCK_S RESET
AD(10)
ADCK
AD(1)
AD(2)
AD(3)
AD(4)
AD(5)
AD(6)
AD(7)
AD(8)
AD(9)
ZOOM_HD CPI(1) CPI(2) CPI(3) CPI(4) CPI(5) CPI(6) CPI(7) CPI(8) CPO(1) CPO(2) CPO(3) CPO(4) CPO(5) CPO(6) CPO(7) CPO(8) YPI(1) YPI(2) YPI(3) YPI(4) YPI(5) YPI(6) YPI(7) YPI(8) YPO(1)
TFP-120
REXT Y_OUT YPO(8) YPO(7) YPO(6) YPO(5) YPO(4) YPO(3) C_OUT NRYBY YPO(2) PLL_P PLL_N DICK AVDD AVDD AVDD
(Top view)
HD49815TF
Description
Symbol XSUB DKF_LD T_CP TY_K SDCK HD_IN M_CK CBLK CSYNC SCBLK HSYNC MCK_S RESET Name shutter pulse Line input Test Title State data input State data clock State data load pulse AWB, data output window pulse window pulse Burst flag External CSYNC input Microprocessor clock VCC2 Field vertical output output Blanking pulse SYNC output blanking pulse Horizontal SYNC Identity Identity pulse VCC2 X'tal input X'tal output Line reset input output Reset Description control pulse Line input dedicated load Test (GND input) Title-killer Off) State data-setting data input State data-setting clock State data-latch pulse AWB, detection-data output Iris detection-area-setting pulse: SP-A7 output changeover Iris detection-area-setting pulse: SP-A7 output changeover Burst flag output External CSYNC input Microprocessor clock output (1/2 dividing X'tal power supply Vertical synchronization pulse Horizontal synchronization pulse Blanking pulse SYNC pulse Subcarrier blanking pulse (SECAM) Horizontal SYNC pulse (SECAM) SECAM determination pulse SECAM determination pulse power supply 2fsc oscillator input 2fsc oscillator output Line-determination-signal input dividing setting 1/2, 1/4) Reset: restore initial data settings Format ZC2R ZC2R ICZC2R ICZC2R ICZC2R ICSD OC2R VCCI GNDI ICZC2R ICZC2R ICZC2R ICZC2R ICZC2R OC2R OC2R ICZC2R VCCC GNDC
HD49815TF
Description (cont)
Symbol PLL_N PLL_P AVDD AVDD C_OUT REXT Y_OUT AVDD DICK NRYBY Name negative positive Vertical reset X'tal input X'tal output carrier frequency Analog Analog analog signal output Current buffer upper Current buffer lower Reference resister analog signal output Analog VCC2 Digital interface clock R-Y, phase output parallel output (8); parallel output parallel output parallel output parallel output parallel output parallel output parallel output parallel input (8); parallel input parallel input Description signal output signal output Vertical synchronization signal input 4fsc oscillator input 4fsc oscillator output output Analog system power supply: Analog system power supply: Chrominance-signal analog output upper current source lower current source Reference voltage input Luminance-signal analog output Analog system power supply: Digital system power supply: Digital interface clock output Color-difference signal phase clock Luminance-signal digital output Luminance-signal digital output Luminance-signal digital output Luminance-signal digital output Luminance-signal digital output Luminance-signal digital output Luminance-signal digital output Luminance-signal digital output Luminance-signal digital input Luminance-signal digital input Luminance-signal digital input Format ICSD ICZC2R GNDA VCCA GNDA VCCA GNDA GNDA VCCA GNDA VCCI GNDI ICZC2R ICZC2R OC2R OC2R OC2R OC2R OC2R OC2R OC2R OC2R
HD49815TF
Description (cont)
Symbol ZOOM_HD (10) Name parallel input parallel input parallel input parallel input parallel input (1); parallel output (8); parallel output parallel output parallel output VCC2 parallel output parallel output parallel output parallel output (1); parallel input (8); parallel input parallel input parallel input parallel input parallel input parallel input parallel input (1); Memory output Field pulse Zoom output input (10); input input input Description Luminance-signal digital input Luminance-signal digital input Luminance-signal digital input Luminance-signal digital input Luminance-signal digital input Chrominance-signal digital output Chrominance-signal digital output Chrominance-signal digital output Chrominance-signal digital output power supply Chrominance-signal digital output Chrominance-signal digital output Chrominance-signal digital output Chrominance-signal digital output Chrominance-signal digital input Chrominance-signal digital input Chrominance-signal digital input Chrominance-signal digital input Chrominance-signal digital input Chrominance-signal digital input Chrominance-signal digital input Chrominance-signal digital input Line memory control output Field pulse Horizontal synchronization signal data input data input data input data input Format OC2R OC2R OC2R OC2R VCCO GNDO OC2R OC2R OC2R OC2R ICZC2DR ICZC2R ICZC2R
HD49815TF
Description (cont)
Symbol ADCK CPREF DSP_MCK XSG1 XSG2 Name input input input input input input (1); clock Clamp reference output Microprocessor clock output VCC2 Sampling pulse Sampling pulse pulse VCC1 VCC1 Reset gate VCC2 XSG1 XSG2 Description data input data input data input data input data input data input converter clock Clamp reference pulse Microprocessor clock output: SP-A7 output changeover power supply Sampling pulse AGC/CDS Sampling pulse AGC/CDS Optical black-pulse output power supply (H1/H2 power supply) CCD-sensor horizontal drive pulse CCD-sensor horizontal drive pulse power supply power supply) CCD-sensor control reset gate power supply CCD-sensor vertical control pulse CCD-sensor vertical control pulse CCD-sensor vertical control pulse CCD-sensor vertical control pulse CCD-sensor vertical control pulse CCD-sensor vertical control pulse Format ICZC2R ICZC2R VCCO GNDO ICZC2 ICZC2 ICZC2R VCCC35 OC3R OC3R VCCC5 ZC3R VCCO ICZC2R ICZC2R ICZC2R ICZC2R ZC2R ZC2R
HD49815TF
Description Format
Format ICSD ICZC2 ICZC2DR ICZC2R OC2R OC3R ZC2R ZC3R VCCI VCCO VCCC VCCC5 VCCC35 GNDI GNDO GNDC VCCA GNDA Contents CMOS level input CMOS level input with pull-down resistor CMOS level schmitt input CMOS level input with pull-down resistor CMOS level common CMOS level common with pull-down resistor through-put control CMOS level common with through-put control CMOS level output with through-put control CMOS level output with through-put control Crystal oscillator input Crystal oscillator output Crystal oscillator input Crystal oscillator output CMOS-level three-state output CMOS-level three-state output with through-put control CMOS-level three-state output CMOS-level three-state output with through-put control Core system power supply: Puddling system power supply: Common power supply: Common power supply: Common power supply: Core system Puddling system Common Analog input Analog output Analog power supply Analog
Notes: used system output. Pins used system output. They depend voltage 109.
Block Diagram
input
detection
detection
De-Knee 1HDL
Memory control
10-bit LINE Climit PreFilter Matrix Gain Gamma correction Matrix Axis conversion Axis conversion (WB) detection Highlight enhancer Fade Base clipping
1HDL
Setup
X'tal X'tal M_CK Setup DSP_MCK Vdriver CDS/AGC etc. XSG1,2, XSUB ADCK, OBP, SP2, PBLK MCK, MCKS PLLP, PLLN, fsc, CBLK CSYNC, EP1-3 IDP, SCBLK, etc. Zoom function Digital interface Titler Microprocessor interface SDCK conversion 7.5IRE Timing generator enhancer Luminance correction Gamma correction
8-bit Y.DAC C.DAC 8-bit
HD49815TF
HD49815TF
Absolute Maximum Ratings 25°C)
Item Power supply voltage voltage operation block) voltage operation block) Output current output GND-VCC pair Allowable power dissipation Operating temperature Storage temperature With bias Without bias Symbol Vt5V Vt3V Popr Topr Tbias Tstg Ratings -0.2 +6.8 -0.2 VCC1 +0.2 -0.2 VCC2 +0.2 +125 Unit
Notes: Using this values excess absolute maximum ratings permanently damage LSI. should normally operated under conditions specified electrical characteristics. Exceeding these conditions lead incorrect operation adversely affect reliability. voltage values referenced voltage ratings also apply pins. VCC1 indicates system power supply VCC2 indicates system power supply.
HD49815TF
Electrical Characteristics (VCC1 4.75 5.25 VCC2 2.85 3.15 AVCC 2.85 3.15 25°C)
Test Conditions Item CMOS-level input voltage CMOS schmitt input voltage Output voltage Symbol VIHC VILC VOHC1 VOLC1 VOHC2 VOLC2 Input leakage current Output leakage current Pull-down current Power dissipation Popr 2.50 VCC1-0.5 VCC2-0.5 VCC2 VCC2 0.60 Unit VCC1 VCC2 -200 system system -200 system system Output Hi-Z conditions VCC2 VCC1 VCC2 AVCC Note
Analog output voltage (full scale) Analog output voltage (zero scale) Differential linearity
Vfull Vzero
0.80 -0.20 -2.0
1.00 0.00
1.20 0.20
Notes: Output voltage must measured steady state. Except pins that include pull-down resistor. Guaranteed REXT analog output load resistance 25°C. Applied pins indicated format column pin-functions table. Because cannot measured logically, tested. Because cannot measured logically, tested. VCC1, VCC2, AVCC indicate system power supply, system power supply, analog system power supply, respectively. indicates VCC1, VCC2, AVCC. voltage range (VCCC35) 2.85 5.25
HD49815TF
Crystal Oscillation Circuit
Measuring conditions oscillation frequency measured under following conditions. VCC1 VCC2 25°C MHz, MHz, MHz: Cin, Cout (±20 MHz: (±20 Cout (±20 pF), pF), Lout conditions above changed within range measuring conditions. Measuring method Under measuring conditions above, methods were tested. fmin. MHz, fmax. (applied pins fmin. MHz, fmax. (applied pins Note: oscillation start time tosc max. Measuring circuit
internal circuit Xout Dividing counter Cout Counter Lout Monitor
Note: part enclosed dotted line above circuit used when measuring MHz.
Figure Measuring Circuit
HD49815TF
Built-in Functions System Configuration
System Configuration
HD49815TF Lens HD49323AF-01 CDS/AGC+ 10-bit SP1/2 V.Driver Input line memory Color processing Luminance processing Microprocessor Zoom processing C-signal output Y-signal output R-Y/B-Y digital output Y-signal digital output
Encode
gain setting System control (iris) control
Initial setting resistor input detection data output (white balance) control
8-bit single-chip microcomputer series)
Figure System Configuration System Description following lists pixels sensors that used with HD49815TF. other pixel numbers, contact sales dept. NTSC NTSC CDS/AGC 10-bit HD49323AF-01 (manufactured Hitachi) recommended optimal CDS/AGC 10-bit HD49815TF. Since HD49323AF-01 provides correlated double sampling circuit that realizes high automatic gain control (AGC) circuit that implements programmable control 34.7 enables high-image-quality camera system when used conjunction with HD49815TF.
HD49815TF
8-bit single-chip microcomputer 8-bit single-chip microcomputer controls system. receives image detection data that HD49815TF gathering implements automatic iris control (AE), automatic white balance control (AWB), automatic focus control (AF). When setting power this microcomputer implements initial setting state data HD49815TF. details state data, "Hitachi Camera (HD49815TF) State Data". Built-in Functions Input line memory block
input 10-bit De-Knee 1HDL Memory control 1HDL color-signal processing block
luminance-signal processing block
Figure Input Line Memory Block De-knee function When CDS/AGC pre-stage external circuit uses knee circuit expand dynamic range signal, de-knee (inverse knee) circuit returns signal converted knee circuit original state. de-knee point State Data SP_A0 [1]. gain high-luminance block 1/2. function digital circuit provided. gain State Data SP_A0 from times. delay line (1HDL) function This circuit obtains horizontal efficient pixels output signal. number efficient pixels State Data SP_A0 TM_A0 [14] MCSET.
HD49815TF
Color-signal processing block
From input LINE line memory block Climit PreFilter Matrix Gain zoom function
Gamma correction Matrix
Axis conversion Axis conversion (WB)
Base clipping
Setup
luminance signal processing block
detection block
Figure Color-Signal Processing Block C-limit (complementary color clipping level) function High clipping processing performed complementary color signals independently. High clipping State Data SP_A2 complementary color signal indicates Cy), Mg), Cy), Ye). RGB-matrix block three primary colors (red, green, blue) acquired matrix multiplying arbitrary coefficients four complementary colors (Gb, taking total those results. matrix designed support minimum color moire enable free color reproduction. Arbitrary coefficients State Data SP_A2 15]. following shows formula.
State Data SP_A2
RGB-setup block black level color signals variable according coefficients matrix. value calculated formula below subtracted from color signal correct black level. subtracted value externally State Data SP_A3
Formula -[48 (Matrix data)
RGB-gain block gain value acquired control gain circuit improve white reproduction performance. prior gamma correction, changes gamma correction amount. gain State Data SP_A3 from times. (The gain from times.)
HD49815TF
gamma correction block gamma correction circuit performs gamma processing signal. State Data SP_A3 Four kinds values independently, according input-signal level, acquire optimal gamma characteristics: gamma dark reduce gain small signals improving S/N), gamma coefficient control expansion gamma curve), gamma knee decide slope large signals), gamma limit perform high-clipping processing input signal gamma circuit). matrix block luminance level changes according color temperature imaged object. State Data SP_A5 [12, luminance correction. correct luminance, create from three primary colors convert luminance signal level. matrix circuit creates level from signal. matrix State Data SP_A3 13]. axis-conversion (C-Y matrix) block (color-difference) matrix takes input signals, creates color-difference signals setting coefficients those inputs. axis-conversion (C-Y matrix) circuits State Data SP_A8 Base-clipping block Since base clipping performed color-difference signals, base-clipping circuit characteristics clipping sections near axes vector scope. This circuit State Data SP_A8 [8]. Luminance-signal-processing block
from matrix From input line memory block Gamma correction AWBdetection block Highlight enhancer zoom function
enhancer
Luminance correction
Fade
Setup
7.5IRE
Figure Luminance-Signal-Processing Block H-enhancer function H-enhancer circuit allows core level, enhancer gain, noise coefficient independently acquire optimal characteristics. This circuit State Data SP_A4 V-enhancer function V-enhancer circuit allows enhancer coefficient control gain only those signal components that exceed core level. This circuit State Data SP_A4 10].
HD49815TF
Luminance correction ratio blue levels changes according color temperature imaged object. example, object imaged color temperature, luminance level increases object appears have lower chrominance. Therefore, luminance correction circuit performs luminance-correction processing implement color depth reproduction. luminance-correction circuit State Data SP_A5 [12, 13]. setup Since clamp processes signal, black level 10-bit signal input HD49815TF fixed 48/1024. Y-setup circuit subtracts black level. However, when black level differs noise mixed analog signal, Y-setup circuit subtracts that value. Y-setup circuit State Data SP_A5 [6]. Gamma correction gamma-correction circuit implements gamma-correction processing separated signal. Four kinds values independently, according input-signal level, acquire optimal gamma characteristics: gamma input limit, gamma knee coefficient, gamma coefficient, gamma black clipping. gamma correction circuit State Data SP_A5 Highlight enhancer input-Y signal levels excess IRE, highlight enhancer implements highlight enhancer processing. This circuit State Data SP_A5 14]. Fade fade circuit amplifies luminance signal factor This circuit State Data SP_A5 [9]. Zoom, encode block, SSG, detection blocks Zoom processing R-Y, signals completed color-signal processing luminance-signal processing electronically zoomed factor 256. After clipping signals direction, zoom circuit clips these signals direction, expand these signals directions. zooming times read starting position directions State Data TM_A2 ZM_A0 Encode block This circuit encodes signals completed color-signal processing, luminance-signal processing, zoom processing NTSC/PAL TV-monitor method. that converts digital signal analog signal provided. channels: signals signals.
HD49815TF
generates signals required drive sensor (H1, SG1/2, transfer pulse), CDS/AGC control signals (SP1 SP2). addition, generates signals synchronize with monitor (the Sync signal). drive timing generated signals differs according manufacturer specifications sensor. Setting state data enables setting timing. state data TM_A0, AWB- AE-detection blocks HD49815TF provides automatic white-balance (AWB) automatic-iris (AE) detection circuits that indispensable camera. AWB-detection block takes color-difference signals completed colorsignal processing, converts MG-G axes. converted signals sent circuits white detection obtain white signal components only, white-color difference value detected. 8-bit single-chip microcomputer acquires this detection data, controls gains produce true white. State Data detection AWB_A0 AE-detection block divides output signal converted digital 10-bit arbitrary areas, performs integration processing. This function enables detection lighting level image signal. 8-bit single-chip microcomputer acquires this detection data, controls accumulation amount (the shutter) sensor iris motor lens maintain proper lighting. State Data detection AE_A0
HD49815TF
Microcomputer Interface Specifications
Write format (Pin SDCK (Pin
(Pin
byte Data byte) STD3-STH2-STD1 Read format (Pin SDCK (Pin
Address STAL STAH
Function address (write address)
(Pin
STAL (Pin
Hi-Z
byte byte Function address STAH
Hi-Z
Data byte) Notes: Synchronous serial transfer (The microcomputer serial port used.) Transfer frequency: 3.58 lower Data address handled byte unit. clock load pulse used common read/write.
HD49815TF
Data Transfer Specification
data transfer between HD49815TF microcomputer, types write, read) available. following table shows relationship between function block transfer specifications. next page, details transfer specifications described.
Function Block Signal processing Transfer Mode Transfer Specifications Iris White balance ZOOM Note: Related Address SP_A0, TM_A3, TM_A0 TMR_A0 AE_A0 AE_A8 AWB_A0 AWB_A8 AF_A0 AF_A8 ZM_A0
Transfer specifications Type Normal transfer from microcomputer Type Transfer using pulse (synchronous with reset signal (used synchronous pulse DSP) sent from microcomputer latch Note: This cannot during standby mode. Type Data transfer from microcomputer Type Data transfer from microcomputer
HD49815TF
Type
Transfer specification (Pin SDCK (Pin more more more Pulse Timing Conditions
Type
Transfer specification (Pin SDCK (Pin Pulse Timing Conditions 270,000 pixels more more more more more more Sensor clock
410,000 pixels more more more
Type
Transfer specification (Pin SDCK (Pin Pulse Timing Conditions more more more read white balance data read data within period from start blanking.
Type
Transfer specification (Pin SDCK (Pin Pulse Timing Conditions more more 270,000 pixels more 410,000 pixels 2.99 more
more Sensor clock
HD49815TF
Note: Function addresses following table shows function addresses each function block (during state data transfer) data transferred from microcomputer.
Table Function Addresses each Function Block State Data
List Data Transferred
Function Address STAH STAL STD1 STD2 Signal processing (Setting example) Function Address STAH STAL STD1 STD2 write (Setting example) Function Address read Data read automatic phase adjustment SP1, SP2, Function Address ADATA STAH STAL STD1 STD2 STAH STAL STD1 STD2 Function Address ADATA Function Address STAH STAL Read area setting STAL bits) Function Address ADATA STAH STAL STD1 STD2 Function Address ADATA STAH STAL STD1 Window setting white balance detection axis phase setting Function Address White balance read Function Address ADATA STAH STAL bandwidth selection Base-clip quantity setting, etc. STAH STAL STD1 Function Address ADATA Setting integration display gate Function Address fetch address (read_cycle) Header Data Data Data ZOOM Data Data Data
Remarks
This example related SP-A0[9]. This example related TM-A0 [14].
This example related IRIS peak detection area. This example related window count
This example related offset R-B. This example related count
This example related bandwidth selection. This example related differential gate V-end.
Note: ZOOM, transfer total seven bytes required header data
HD49815TF
Digital Interface Timing
output specification timing digital interface output R-Y, B-Y) NRYBY
DICK
output timing R-Y0 B-Y0 R-Y2 B-Y1 R-Y4 B-Y4
Detailed specifications digital interface timing X'tal nsec DICK output nsec CPO, nsec CPI, nsec
NRYBY (Reference) NRYBY DICK CPO, CPI,
nsec
R-Y/B-Y determination pulse Clock dedicated digital interface (The clock generated from external X'tal.) Digital interface output terminal Digital interface input terminal
HD49815TF
Package Dimensions
Unit:
16.0 16.0
*0.17 0.05 0.15 0.04
*0.17 0.05 0.15 0.04 1.20
1.00
0.07
0.10
0.10 0.10
*Dimension including plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TFP-120 Conforms
HD49815TF
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such failsafes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
NorthAmerica http:semiconductor.hitachi.com/ Europe Asia (Singapore) Asia (Taiwan) Asia (HongKong) Japan further information write
Hitachi Semiconductor (America) Inc. East Tasman Drive, Jose,CA 95134 Tel: (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9180-0 Fax: <49> (89) Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office Hung Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> 2718-3666 Fax: <886> 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Tsui, Kowloon, Hong Kong Tel: <852> 9218 Fax: <852> 0281 Telex: 40815 HITEC
Copyright Hitachi, Ltd., 1999. rights reserved. Printed Japan.

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