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Hitachi SuperHRISC engine
SH7014, SH7016, SH7017F-ZTATHardware Manual
ADE-602-128C Rev. 3/13/03 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
SH7014/16/17 CMOS single-chip microprocessors integrate Hitachi-original architecture, high-speed with peripheral functions required system configuration. RISC-type instruction set. Most instructions executed clock cycle, which greatly improves instruction execution speed. addition, 32-bit internal-bus architecture enhances data processing power. With this CPU, become possible assemble cost, high performance/high-functioning systems, even applications that were previously impossible with microprocessors, such real-time control, which demands high speeds. particular, this 1-kbyte on-chip cache, which allows improvement performance during external memory access. addition, this includes on-chip peripheral functions necessary system configuration, such large-capacity (except SH7014, which ROMless) RAM, timers, serial communication interface (SCI), converter, interrupt controller, ports. Memory peripheral LSIs connected efficiently with external memory access support function. This greatly reduces system cost. This F-ZTATversion with on-chip flash memory mask version. These versions enable users respond quickly flexibly changing application specifications, growing production volumes, other conditions. This hardware manual covers SH7014/16/17/. detailed description instructions, refer programming manual. Related Manuals SH7014/16/17 instruction execution: SH-1/SH-2/SH-DSP Programming Manual information development systems, please contact Hitachi sales representative.
Contents
Section
SH7014/16/17 Overview SH7014/16/17 Overview. 1.1.1 SH7014/16/17 Series Features Block Diagram. Arrangement Functions. 1.3.1 Arrangment 1.3.2 Arrangement Mode 1.3.3 Functions. CPU. Register Configuration. 2.1.1 General Registers (Rn). 2.1.2 Control Registers. 2.1.3 System Registers 2.1.4 Initial Values Registers Data Formats 2.2.1 Data Format Registers. 2.2.2 Data Format Memory. 2.2.3 Immediate Data Format Instruction Features 2.3.1 RISC-Type Instruction Set. 2.3.2 Addressing Modes. 2.3.3 Instruction Format Instruction Classification Processing States 2.5.1 State Transitions. 2.5.2 Power-Down State Operating Modes Operating Modes, Types, Selection. Explanation Operating Modes. Configuration Clock Pulse Generator (CPG). Overview 4.1.1 Block Diagram Oscillator 4.2.1 Connecting Crystal Oscillator 4.2.2 External Clock Input Method.
Section
Section
Section
4.2.3
Prescaler
Section
Exception Processing Overview 5.1.1 Types Exception Processing Priority 5.1.2 Exception Processing Operations. 5.1.3 Exception Processing Vector Table Resets. 5.2.1 Power-on Reset Address Errors. 5.3.1 Address Error Exception Processing. Interrupts 5.4.1 Interrupt Priority Level. 5.4.2 Interrupt Exception Processing Exceptions Triggered Instructions 5.5.1 Trap Instructions 5.5.2 Illegal Slot Instructions 5.5.3 General Illegal Instructions When Exception Sources Accepted. 5.6.1 Immediately after Delayed Branch Instruction 5.6.2 Immediately after Interrupt-Disabled Instruction. Stack Status after Exception Processing Ends. Notes 5.8.1 Value Stack Pointer (SP) 5.8.2 Value Vector Base Register (VBR) 5.8.3 Address Errors Caused Stacking Address Error Exception Processing Interrupt Controller (INTC). Overview 6.1.1 Features 6.1.2 Block Diagram 6.1.3 Configuration 6.1.4 Register Configuration Interrupt Sources 6.2.1 Interrupts 6.2.2 Interrupts 6.2.3 On-Chip Peripheral Module Interrupts 6.2.4 Interrupt Exception Vectors Priority Rankings Description Registers 6.3.1 Interrupt Priority Registers (IPRA-IPRH) 6.3.2 Interrupt Control Register (ICR) 6.3.3 Status Register (ISR) Interrupt Operation
Section
6.4.1 Interrupt Sequence 6.4.2 Stack after Interrupt Exception Processing Interrupt Response Time Data Transfer with Interrupt Request Signals 6.6.1 Handling DMAC Activating Sources Interrupt Sources 6.6.2 Treating Interrupt Sources DMAC Activating Sources
Section
Cache Memory (CAC) Overview 7.1.1 Features 7.1.2 Block Diagram 7.1.3 Register Configuration Register Explanation 7.2.1 Cache Control Register (CCR). Address Array Data Array 7.3.1 Cache Address Array Read/Write Space 7.3.2 Cache Data Array Read/Write Space. Cautions Use. 7.4.1 Cache Initialization 7.4.2 Forced Access Address Array Data Array 7.4.3 Cache Miss Penalty Cache Fill Timing. 7.4.4 Cache after Cache Miss
Section
State Controller (BSC) Overview 8.1.1 Features 8.1.2 Block Diagram 8.1.3 Configuration 8.1.4 Register Configuration 8.1.5 Address Description Registers 8.2.1 Control Register (BCR1) 8.2.2 Control Register (BCR2) 8.2.3 Wait Control Register (WCR1). 8.2.4 Wait Control Register (WCR2). 8.2.5 DRAM Area Control Register (DCR) 8.2.6 Refresh Timer Control/Status Register (RTCSR) 8.2.7 Refresh Timer Counter (RTCNT) 8.2.8 Refresh Time Constant Register (RTCOR) Accessing Ordinary Space. 8.3.1 Basic Timing 8.3.2 Wait State Control. 8.3.3 Assert Period Extension
DRAM Access. 8.4.1 DRAM Direct Connection 8.4.2 Basic Timing 8.4.3 Wait State Control. 8.4.4 Burst Operation 8.4.5 Refresh Timing. Address/Data Multiplex Space Access 8.5.1 Basic Timing 8.5.2 Wait State Control. 8.5.3 Assertion Extension Waits between Access Cycles 8.6.1 Prevention Data Conflicts. 8.6.2 Simplification Cycle Start Detection Arbitration Memory Connection Examples On-chip Peripheral Register Access 8.10 Operation when Program External Memory.
Section
Direct Memory Access Controller (DMAC) Overview 9.1.1 Features 9.1.2 Block Diagram 9.1.3 Configuration 9.1.4 Register Configuration Register Descriptions. 9.2.1 Source Address Registers (SAR0, SAR1) 9.2.2 Destination Address Registers (DAR0, DAR1) 9.2.3 Transfer Count Registers (DMATCR0, DMATCR1) 9.2.4 Channel Control Registers (CHCR0, CHCR1). 9.2.5 DMAC Operation Register (DMAOR) Operation. 9.3.1 Transfer Flow. 9.3.2 Transfer Requests. 9.3.3 Channel Priority 9.3.4 Transfer Types 9.3.5 Address Modes. 9.3.6 Dual Address Mode 9.3.7 Modes. 9.3.8 Relationship between Request Modes Modes Transfer Category. 9.3.9 Mode Channel Priority Order. 9.3.10 Number Cycle States DREQ Sample Timing. 9.3.11 Transfer Ending Conditions.
9.3.12 DMAC Access from Examples Use. 9.4.1 Example Transfer between On-Chip External Memory. 9.4.2 Example Transfer between External External Device with DACK Cautions Use.
Section Multifunction Timer Pulse Unit (MTU)
10.1 Overview 10.1.1 Features 10.1.2 Block Diagram 10.1.3 Configuration 10.1.4 Register Configuration 10.2 Register Descriptions. 10.2.1 Timer Control Register (TCR) 10.2.2 Timer Mode Register (TMDR) 10.2.3 Timer Control Register (TIOR) 10.2.4 Timer Interrupt Enable Register (TIER) 10.2.5 Timer Status Register (TSR) 10.2.6 Timer Counters (TCNT). 10.2.7 Timer General Register (TGR) 10.2.8 Timer Start Register (TSTR). 10.2.9 Timer Synchro Register (TSYR) 10.3 Master Interface 10.3.1 16-Bit Registers. 10.3.2 8-Bit Registers. 10.4 Operation 10.4.1 Overview 10.4.2 Basic Functions 10.4.3 Synchronous Operation 10.4.4 Buffer Operation 10.4.5 Cascade Connection Mode. 10.4.6 Mode 10.4.7 Phase Counting Mode 10.5 Interrupts 10.5.1 Interrupt Sources Priority Ranking 10.5.2 DMAC Activation 10.5.3 Converter Activation 10.6 Operation Timing 10.6.1 Input/Output Timing 10.6.2 Interrupt Signal Timing 10.7 Notes Precautions 10.7.1 Input Clock Limitations
10.7.2 Note Cycle Setting 10.7.3 Contention between TCNT Write Clear. 10.7.4 Contention between TCNT Write Increment 10.7.5 Contention between Buffer Register Write Compare Match 10.7.6 Contention between Read Input Capture. 10.7.7 Contention between Write Input Capture. 10.7.8 Contention between Buffer Register Write Input Capture 10.7.9 Contention between Write Compare Match. 10.7.10 TCNT2 Write Overflow/Underflow Contention Cascade Connection 10.7.11 Contention between Overflow/Underflow Counter Clearing 10.7.12 Contention between TCNT Write Overflow/Underflow. 10.7.13 Cautions Carrying Buffer Operation Channel Mode 10.8 Output Initialization 10.8.1 Operating Modes 10.8.2 Reset Start Operation 10.8.3 Operation Case Re-Setting Error during Operation, Etc. 10.8.4 Overview Initialization Procedures Mode Transitions Case Error during Operation, etc.
Section Watchdog Timer (WDT)
11.1 Overview 11.1.1 Features 11.1.2 Block Diagram 11.1.3 Configuration 11.1.4 Register Configuration 11.2 Register Descriptions. 11.2.1 Timer Counter (TCNT) 11.2.2 Timer Control/Status Register (TCSR) 11.2.3 Reset Control/Status Register (RSTCSR) 11.2.4 Register Access 11.3 Operation 11.3.1 Watchdog Timer Mode 11.3.2 Interval Timer Mode 11.3.3 Clearing Standby Mode. 11.3.4 Timing Setting Overflow Flag (OVF) 11.3.5 Timing Setting Watchdog Timer Overflow Flag (WOVF) 11.4 Notes 11.4.1 TCNT Write Increment Contention. 11.4.2 Changing CKS2 CKS0 Values. 11.4.3 Changing between Watchdog Timer/Interval Timer Modes 11.4.4 System Reset with WDTOVF 11.4.5 Internal Reset with Watchdog Timer
Section Serial Communication Interface (SCI)
12.1 Overview 12.1.1 Features 12.1.2 Block Diagram 12.1.3 Configuration 12.1.4 Register Configuration. 12.2 Register Descriptions. 12.2.1 Receive Shift Register (RSR). 12.2.2 Receive Data Register (RDR) 12.2.3 Transmit Shift Register (TSR) 12.2.4 Transmit Data Register (TDR). 12.2.5 Serial Mode Register (SMR). 12.2.6 Serial Control Register (SCR). 12.2.7 Serial Status Register (SSR). 12.2.8 Rate Register (BRR). 12.3 Operation 12.3.1 Overview 12.3.2 Operation Asynchronous Mode 12.3.3 Multiprocessor Communication. 12.3.4 Clock Synchronous Operation 12.4 Interrupt Sources DMAC. 12.5 Notes 12.5.1 Write TDRE Flags 12.5.2 Simultaneous Multiple Receive Errors 12.5.3 Break Detection Processing. 12.5.4 Sending Break Signal 12.5.5 Receive Error Flags Transmitter Operation (Clock Synchronous Mode Only) 12.5.6 Receive Data Sampling Timing Receive Margin Asynchronous Mode 12.5.7 Constraints DMAC 12.5.8 Cautions Clock Synchronous External Clock Mode 12.5.9 Caution Clock Synchronous Internal Clock Mode.
Section High Speed Converter -SH7014-
13.1 Overview 13.1.1 Features 13.1.2 Block Diagram 13.1.3 Configuration 13.1.4 Register Configuration 13.2 Register Descriptions. 13.2.1 Data Registers (ADDRA-ADDRH). 13.2.2 Control/Status Register (ADCSR)
13.2.3 Control Register (ADCR). 13.3 Master Interface 13.4 Operation 13.4.1 Select-Single Mode 13.4.2 Select-Scan Mode. 13.4.3 Group-Single Mode. 13.4.4 Group-Scan Mode 13.4.5 Buffer Operation 13.4.6 Simultaneous Sampling Operation. 13.4.7 Conversion Start Modes. 13.4.8 Conversion Time 13.5 Interrupts 13.6 Notes 13.6.1 Analog Input Voltage Range. 13.6.2 AVCC, AVSS Input Voltages 13.6.3 Input Ports 13.6.4 Conversion Start Modes. 13.6.5 Conversion Termination. 13.6.6 Handling Analog Input Pins
Section Mid-Speed Converter -SH7016, SH7017-.
14.1 Overview 14.1.1 Features 14.1.2 Block Diagram 14.1.3 Configuration 14.1.4 Register Configuration 14.2 Register Descriptions. 14.2.1 Data Register (ADDRA ADDRD). 14.2.2 Control/Status Register (ADCSR) 14.2.3 Control Register (ADCR). 14.3 Interface with 14.4 Operation 14.4.1 Single Mode (SCAN=0). 14.4.2 Scan Mode (SCAN=1) 14.4.3 Input Sampling Conversion Time 14.4.4 Trigger Input Timing. 14.5 Interrupt 14.6 Conversion Precision Definitions. 14.7 Usage Notes. 14.7.1 Analog Voltage Settings. 14.7.2 Handling Analog Input Pins.
viii
Section Compare Match Timer (CMT)
15.1 Overview 15.1.1 Features 15.1.2 Block Diagram 15.1.3 Register Configuration 15.2 Register Descriptions. 15.2.1 Compare Match Timer Start Register (CMSTR) 15.2.2 Compare Match Timer Control/Status Register (CMCSR) 15.2.3 Compare Match Timer Counter (CMCNT) 15.2.4 Compare Match Timer Constant Register (CMCOR) 15.3 Operation 15.3.1 Period Count Operation 15.3.2 CMCNT Count Timing 15.4 Interrupts 15.4.1 Interrupt Sources Activation. 15.4.2 Compare Match Flag Timing. 15.4.3 Compare Match Flag Clear Timing 15.5 Notes 15.5.1 Contention between CMCNT Write Compare Match. 15.5.2 Contention between CMCNT Word Write Incrementation. 15.5.3 Contention between CMCNT Byte Write Incrementation
Section Function Controller
16.1 Overview 16.2 Register Configuration 16.3 Register Descriptions. 16.3.1 Port Register (PAIORL) 16.3.2 Port Control Registers (PACRL1 PACRL2) 16.3.3 Port Register (PBIOR) 16.3.4 Port Control Registers (PBCR1 PBCR2). 16.3.5 Port Register (PCIOR) -SH7016, SH7017- 16.3.6 Port Control Register (PCCR) -SH7016, SH7017-. 16.3.7 Port Register (PDIORL) -SH7016, SH7017- 16.3.8 Port Control Register (PDCRL) -SH7016, SH7017-. 16.3.9 Port Register (PEIOR) 16.3.10 Port Control Registers (PECR1 PECR2)
Section Ports (I/O)
17.1 Overview 17.2 Port 17.2.1 Register Configuration 17.2.2 Port Data Register (PADRL) 17.3 Port
17.4
17.5
17.6
17.7
17.3.1 Register Configuration 17.3.2 Port Data Register (PBDR). Port -SH7016, SH7017- 17.4.1 Register Configuration 17.4.2 Port Data Register (PCDR). Port -SH7016, SH7017- 17.5.1 Register Configuration 17.5.2 Port Data Register (PDDRL) Port 17.6.1 Register Configuration 17.6.2 Port Data Register (PEDR). Port 17.7.1 Register Configuration 17.7.2 Port Data Register (PFDR)
Section Flash Memory (F-ZTAT)
18.1 Features 18.2 Overview 18.2.1 Block Diagram 18.2.2 Mode Transitions 18.2.3 On-Board Programming Modes. 18.2.4 Flash Memory Emulation RAM. 18.2.5 Differences between Boot Mode User Program Mode 18.2.6 Block Configuration. 18.3 Configuration 18.4 Register Configuration 18.5 Register Descriptions. 18.5.1 Flash Memory Control Register (FLMCR1). 18.5.2 Flash Memory Control Register (FLMCR2). 18.5.3 Erase Block Register (EBR1) 18.5.4 Emulation Register (RAMER). 18.6 On-Board Programming Modes 18.6.1 Boot Mode. 18.6.2 User Program Mode 18.7 Programming/Erasing Flash Memory 18.7.1 Program Mode. 18.7.2 Program-Verify Mode 18.7.3 Erase Mode. 18.7.4 Erase-Verify Mode. 18.8 Protection. 18.8.1 Hardware Protection. 18.8.2 Software Protection 18.8.3 Error Protection
18.9 Flash Memory Emulation RAM. 18.10 Note Flash Memory Programming/Erasing 18.11 Flash Memory Programmer Mode 18.11.1 Socket Adapter Correspondence Diagram. 18.11.2 Programmer Mode Operation. 18.11.3 Memory Read Mode. 18.11.4 Auto-Program Mode 18.11.5 Auto-Erase Mode 18.11.6 Status Read Mode. 18.11.7 Status Polling 18.11.8 Programmer Mode Transition Time. 18.11.9 Notes Memory Programming.
Section Mask
19.1 Overview
Section
20.1 Overview
Section Power-Down State
21.1 Overview 21.1.1 Power-Down States 21.1.2 Related Register 21.2 Standby Control Register (SBYCR) 21.3 Sleep Mode. 21.3.1 Transition Sleep Mode 21.3.2 Canceling Sleep Mode 21.4 Standby Mode 21.4.1 Transition Standby Mode. 21.4.2 Canceling Standby Mode 21.4.3 Standby Mode Application Example
Section Electrical Characteristics 28.7 MHz)
22.1 Absolute Maximum Ratings. 22.2 Characteristics. 22.3 Characteristics. 22.3.1 Clock Timing 22.3.2 Control Signal Timing 22.3.3 Timing. 22.3.4 Direct Memory Access Controller Timing. 22.3.5 Multifunction Timer Pulse Unit Timing 22.3.6 Port Timing 22.3.7 Watchdog Timer Timing
22.3.8 Serial Communication Interface Timing. 22.3.9 High Speed Converter Timing SH7014- 22.3.10 Mid-speed Converter Timing -SH7016, SH7017-. 22.3.11 Measuring Conditions Characteristics 22.4 Converter Characteristics
Appendix On-Chip Supporting Module Registers
Addresses.
Appendix Port Block Diagrams Appendix States. Appendix Notes when Converting F-ZTAT Application Software Mask-ROM Versions Appendix Appendix Product Code Lineup. Package Dimensions
Section SH7014/16/17 Overview
SH7014/16/17 Overview
SH7014/16/17 CMOS single-chip microprocessors integrate Hitachi-original architecture, high-speed with peripheral functions required system configuration. RISC-type instruction set. Most instructions executed clock cycle, which greatly improves instruction execution speed. addition, 32-bit internal-bus architecture enhances data processing power. With this CPU, become possible assemble cost, high performance/high-functioning systems, even applications that were previously impossible with microprocessors, such real-time control, which demands high speeds. particular, SH7040 series 1-kbyte on-chip cache, which allows improvement performance during external memory access. addition, this includes on-chip peripheral functions necessary system configuration, such large-capacity (except SH7014, which ROMless) RAM, timers, serial communication interface (SCI), converter, interrupt controller, ports. Memory peripheral LSIs connected efficiently with external memory access support function. This greatly reduces system cost. This F-ZTATTM* version with on-chip flash memory mask version. These versions enable users respond quickly flexibly changing application specifications, growing production volumes, other conditions. Notes: 1.1.1 CPU: Original Hitachi architecture 32-bit internal data General-register machine Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers RISC-type instruction Instruction length: 16-bit fixed length improved code efficiency Load-store architecture (basic operations executed between registers) Delayed branch instructions reduce pipeline disruption during branch Instruction based language
F-ZTAT (Flexible ZTAT) trademark Hitachi, Ltd. SH7014/16/17 Series Features
Instruction execution time: instruction/cycle ns/instruction 28.7-MHz operation) Address space: Architecture supports Gbytes On-chip multiplier: multiplication operations bits bits bits) multiplication/accumulation operations bits bits bits bits) executed four cycles Five-stage pipeline Cache Memory: 1-kbyte instruction cache Caching instruction codes relative read data 4-byte line length longword: instruction lengths) entry cache tags Direct method On-chip ROM/RAM, on-chip areas objects cache Used common with on-chip RAM; kbytes on-chip used address array/data array when cache enabled
Interrupt Controller (INTC): Seven external interrupt pins (NMI, IRQ6) Twenty-eight internal interrupt sources Sixteen programmable priority levels State Controller (BSC): Supports external extended memory access 8-bit, 16-bit external data Memory address space divided into five areas (four areas SRAM space, area DRAM space) with following settable features: Number wait cycles Outputs chip-select signals each area During DRAM space access: Outputs signals DRAM generate precharge time assurance cycle DRAM burst access function Supports high-speed access mode DRAM DRAM refresh function Programmable refresh interval Supports CAS-before-RAS refresh self-refresh modes Wait cycles inserted using external WAIT signal
Address data multiplex devices accessed Note: release Direct Memory Access Controller (DMAC) Channels): Supports cycle-steal burst transfers Supports single address mode dual address mode transfers Priority order: fixed channel channel Transfer counter: bits Transfer request sources: external DREQ input, auto-request, on-chip supporting modules Address space: Gbytes Choice 16-, 32-bit transfer data size
Multifunction Timer/Pulse Unit (MTU) Channels): Maximum types waveform output maximum types pulse processing possible based 16-bit timer, channels dual-use output compare/input capture registers independent comparators types counter input clock Input capture function Pulse output mode shot, toggle, Phase calculation mode 2-phase encoder calculation processing Compare Match Timer (CMT) (Two Channels): 16-bit free-running counter compare register Generates interrupt request upon compare match Watchdog Timer (WDT) (One Channel): Watchdog timer interval timer Count overflow generate internal reset, external signal, interrupt
Serial Communication Interface (SCI) (Two Channels): (Per Channel): Asynchronous clock-synchronous mode selectable transmit receive simultaneously (full duplex) On-chip dedicated baud rate generator Multiprocessor communication function
Ports: SH7014 Input/output: Input: Total: SH7016/17 Input/output: Input: Total: Converter: bits channels SH7014 high-speed converter, while SH7016 SH7017 have mid-speed converter. On-Chip Memory: SH7014: ROMless SH7016: kbytes (mask ROM) SH7017: kbytes (flash ROM) RAM: SH7014/16: kbytes kbyte when cache used) SH7017: kbytes kbytes when cache used) Operating Modes: Operating modes Non-extended mode (SH7014/16/17) Extended mode (SH7016/17) Single-chip mode (SH7016/17) Processing states
Program execution state Exception processing state Power-down modes Sleep mode Software standby mode Clock Pulse Generator (CPG): On-chip clock pulse generator On-chip clock-doubling circuit Product Lineup:
Product Code HD6417014F28 On-Chip ROMless On-Chip Precision Frequency/ Voltage Temperature Package
28.7 MHz/5 +75°C FP-112 (high-speed A/D) 28.7 MHz/5 +75°C FP-112 (high-speed A/D) 28.7 MHz/5 +75°C FP-112 (mid-speed A/D) 4LSB 28.7 MHz/5 +75°C FP-112 (mid-speed A/D)
HD6417014RF28 ROMless HD6437016F28 HD64F7017F28
mask flash memory
Block Diagram
Figure block diagram SH7014. Figure block diagram SH7016/17.
PA15/CK PA9/TCLKD/IRQ3 PA8/TCLKC/IRQ2 PA7/TCLKB/CS3 PA6/TCLKA/CS2 PA5/SCK1/DREQ1/IRQ1 PA4/TXD1 PA3/RXD1 PA2/SCK0/DREQ0/IRQ0 PA1/TXD0 PA0/RXD0 WDTOVF EXTAL XTAL PLLCAP PLLVSS
AVCC AVSS
PLLVCC
kB)/ cache ,,,, ,,,, ,,,, ,,,, ,,,, ,,,,,,,, ,,,, ,,,,,,,, ,,,,,,,,, ,,,,,,,, ,,,,, ,,,,,,,,, Direct memory ,,,,,,,,,access controller Interrupt state controller ,,,,, ,,,, controller ,,,, ,,,,, ,,,, ,,,,, Serial Multifunction timer/ ,,,, cation interface ,,,, pulse unit ,,,, channels) ,,,, ,,,, ,,,, Compare match ,,,,timer channels) converter ,,,, timer ,,,, ,,,, ,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,,
PB9/IRQ7/A21 PB8/IRQ6/A20/WAIT PB7/A19 PB6/A18 PB5/IRQ3/RDWR PB4/IRQ2/CASH PB3/IRQ1/CASL PB2/IRQ0/RAS
,,,,,: Peripheral data ,,,,, ,,,,, Internal address ,,,,,: Internal upper data ,,,,, ,,,,, ,,,,,: Internal lower data
Peripheral address
Figure Block Diagram SH7014
PE15/DACK1 PE14/DACK0/AH PE13 PE12 PE11 PE10 PE7/TIOC2B PE6/TIOC2A PE5/TIOC1B PE4/TIOC1A PE3/TIOC0D/DRAK1 PE2/TIOC0C/DREQ1 PE1/TIOC0B/DRAK0 PE0/TIOC0A/DREQ0
PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0
PA5/SCK1/DREQ1/IRQ1
PA2/SCK0/DREQ0/IRQ0
PA9/TCLKD/IRQ3
PA8/TCLKC/IRQ2
PB8/IRQ6/A20/WAIT
PA7/TCLKB/CS3
PA6/TCLKA/CS2
PB5/IRQ3/RDWR
PB4/IRQ2/CASH
PB3/IRQ1/CASL
PA13/WRH
PA12/WRL
PA3/RXD1
PA0/RXD0
PA4/TXD1
PA1/TXD0
PA11/CS1
PA10/CS0
PA14/RD
PA15/CK
PB2/IRQ0/RAS
PB9/IRQ7/A21
PB7/A19
PB6/A18
PB1/A17
WDTOVF EXTAL XTAL PLLVcc PLLCAP PLLVss Vcc/FWP* AVcc AVss
Note: SH7016, SH7017.
,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,,
Flash (128 kB)/ mask kB/3 kB)/ cache Direct memory access controller Interrupt controller state controller Serial communication interface channels)
Multifunction timer/ pulse unit
PB0/A16
PC15/A15 PC14/A14 PC13/A13 PC12/A12 PC11/A11 PC10/A10 PC9/A9 PC8/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD15/D15 PD14/D14 PD13/D13 PD12/D12 PD11/D11 PD10/D10 PD9/D9 PD8/D8 PD7/D7 PD6/D6 PD5/D5 PD4/D4 PD3/D3 PD2/D2 PD1/D1 PD0/D0
Compare match timer channels)
converter
Watchdog timer
PE15/DACK1 PE14/DACK0/AH
PE3/TIOC0D/DRAK1
PE1/TIOC0B/DRAK0
PE2/TIOC0C/DREQ1
PE0/TIOC0A/DREQ0
PE7/TIOC2B
PE6/TIOC2A
PE5/TIOC1B
PE4/TIOC1A
PE13
PE12
PE11
PE10
PF7/AN7
PF6/AN6
PF5/AN5
PF4/AN4
PF3/AN3
PF2/AN2
PF1/AN1
PF0/AN0
Peripheral address Peripheral data Internal address Internal upper data Internal lower data
Figure Block Diagram SH7016, SH7017
1.3.1
Arrangement Functions
Arrangment
Figure shows arrangement SH7014 (top view).
PA15/CK PLLVSS PLLCAP PLLVCC EXTAL XTAL
Figure SH7014 Arrangement (QFP-112 View)
PE14/DACK0/AH PE15/DACK1 PB2/IRQ0/RAS PB3/IRQ1/CASL PB4/IRQ2/CASH PB5/IRQ3/RDWR
PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 AVSS PF6/AN6 PF7/AN7 AVCC PE5/TIOC1B PE6/TIOC2A PE7/TIOC2B PE10 PE11 PE12 PB13
QFP-112
PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PA6/TCLKA/CS2 PA7/TCLKB/CS3 PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 WDTOVF PB9/IRQ7/A21 PB8/IRQ6/A20/WAIT PB7/A19 PB6/A18
Figure shows arrangement 144-pin arrangement.
PD10/D10 PD11/D11 Vcc/FWP* PA15/CK
PLLCAP
PD0/D0
PD1/D1
PD2/D2
PD3/D3
PD4/D4
PD5/D5
PD6/D6
PD7/D7
PD8/D8
PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 AVss PF6/AN6 PF7/AN7 AVcc PE5/TIOC1B PE6/TIOC2A PE7/TIOC2B PE10 PE11 PE12 PE13
PD9/D9
PLLVss
PLLVcc
EXTAL
XTAL
PD12/D12 PD13/D13 PD14/D14 PD15/D15 PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PA6/TCLKA/CS2 PA7/TCLKB/CS3 PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 PA10/CS0 PA11/CS1 PA12/WRL PA13/WRH WDTOVF PA14/RD PB9/IRQ7/A21 PB8/IRQ6/A20/WAIT PB7/A19 PB6/A18
QFP-112
PE14/DACK0/AH
PE15/DACK1
PB4/IRQ2/CASH
Note: SH7016, SH7017.
Figure SH7016, SH7017 Arrangement (QFP-112 View)
PB5/IRQ3/RDWR
PB2/IRQ0/RAS
PB3/IRQ1/CASL
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
PC5/A5
PC6/A6
PC7/A7
PC8/A8
PC9/A9
PB0/A16
PC10/A10
PC11/A11
PC12/A12
PC13/A13
PC14/A14
PC15A15
PB1/A17
1.3.2 Table
Arrangement Mode Arrangement Mode SH7017F (QFP-112 Pin)
Mode PE14/DACK0/AH PE15/DACK1 PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 PC15/A15 PB0/A16 PB1/A17 PB2/IRQ0/RAS PB3/IRQ1/CASL PB4/IRQ2/CASH PB5/IRQ3/RDWR Programmer Mode
Table
Arrangement Mode SH7017F (QFP-112 Pin) (cont)
Mode PB6/A18 PB7/A19 PB8/IRQ6/A20/WAIT PB9/IRQ7/A21 PA14/RD WDTOVF PA13/WRH PA12/WRL PA11/CS1 PA10/CS0 PA9/TCLKD/IRQ3 PA8/TCLKC/IRQ2 PA7/TCLKB/CS3 PA6/TCLKA/CS2 PA5/SCK1/DREQ1/IRQ1 PA4/TXD1 /RXD1 PA2/SCK0/DREQ0/IRQ0 PA1/TXD0 PA0/RXD0 PD15/D15 PD14/D14 PD13/D13 PD12/D12 PD11/D11 PD10/D10 Programmer Mode
Table
Arrangement Mode SH7017F (QFP-112 Pin) (cont)
Mode PD9/D9 PD8/D8 PD7/D7 PD6/D6 PD5/D5 PD4/D4 PD3/D3 PD2/D2 PD1/D1 PD0/D0 XTAL EXTAL (FWP) PLLVCC PLLCAP PLLVSS PA15/CK PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 Programmer Mode XTAL EXTAL PLLVCC PLLCAP PLLVSS
Table
Arrangement Mode SH7017F (QFP-112 Pin) (cont)
Mode PE4/TIOC1A PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 AVSS PF6/AN6 PF7/AN7 AVCC PE5/TIOC1B PE6/TIOC2A PE7/TIOC2B PE10 PE11 PE12 PE13 Programmer Mode
1.3.3
Functions
Table lists functions. Table Functions
Symbol Name Supply Function Connects power supply. Connect pins system supply. operation will occur there open pins. Ground Connects ground. Connect pins system ground. operation will occur there open pins. Clock PLLVCC PLLVSS PLLCAP EXTAL supply ground capacitance External clock On-chip oscillator supply. On-chip oscillator ground. On-chip oscillator external capacitance connection pin. Connect crystal oscillator. Also, external clock input EXTAL pin. Connect crystal oscillator. Supplies system clock peripheral devices. Power-on reset when Overflow output signal from Determines operating mode. change input value during operation. Protects flash memory from being written deleted. Non-maskable interrupt request pin. Enables selection whether accept rising falling edge.
Classification Power supply
XTAL System control WDTOVF Operating mode MD0-MD3 control Interrupts
Crystal System clock Power-on reset Watchdog timer overflow Mode
Flash memory write protect Non-maskable interrupt
IRQ0-IRQ3, IRQ6, IRQ7 Address A0-A21
Interrupt requests Maskable interrupt request pins. 0-3, Allows selection level input edge input. Address Outputs addresses.
Table
Functions (cont)
Symbol D0-D15 Name Data Function 16-bit (QFP-112 version) 32-bit (QFP-144 version) bidirectional data bus. Chip select signals external memory devices. Indicates reading from external device. Indicates writing upper bits (15- external data. Indicates writing lower bits (7-0) external data. Input causes insertion wait cycles into cycle during external space access. Timing signal DRAM address strobe. Timing signal DRAM column address strobe. Output when upper bits data accessed. CASL Lower column address strobe Timing signal DRAM column address strobe. Output when lower bits data accessed. RDWR DRAM read/write Address hold DRAM write strobe signal. Address hold timing signal devices using address/data multiplex bus. Input pins external clocks counter.
Classification Data
control
WAIT
Chip selects Read Upper write Lower write Wait
CASH
address strobe Upper column address strobe
control multifunction timer/pulse unit
TCLKA TCLKB TCLKC TCLKD TIOC0A TIOC0B TIOC0C TIOC0D
timer clock input
input capture/output compare (channel
Channel input capture input/output compare output/PWM output pins.
Table
Functions (cont)
Symbol TIOC1A TIOC1B Name input capture/output compare (channel input capture/output compare (channel transfer request (channels DREQ request acknowledgment (channels transfer strobe (channels Transmit data (channels Receive data (channels Serial clock (channels Analog supply Analog ground Analog input General purpose port Function Channel input capture input/output compare output/PWM output pins.
Classification control multifunction timer/pulse unit (cont)
TIOC2A TIOC2B
Channel input capture input/output compare output/PWM output pins.
Direct memory access controller (DMAC)
DREQ0 DREQ1
Input external requests transfer.
DRAK0 DRAK1 DACK0 DACK1 Serial communication interface (SCI) TxD0 TxD1 RxD0 RxD1 SCK0 SCK1 Converter AVCC AVSS ports PA9, PA15 (SH7014) PA15 (SH7016/17) (SH7014) (SH7016/17)
Output input sampling acknowledgment external transfer requests. Output strobe external external transfer requests. SCI0, SCI1 transmit data output pins.
SCI0, SCI1 receive data input pins. SCI0, SCI1 clock input/output pins. Analog supply; connected Analog supply; connected Analog signal input pins. General purpose input/output port pins. Each designated input/output.
General purpose port
General purpose input/output port pins. Each designated input/output.
Table
Functions (cont)
Symbol Name General purpose port Function General purpose input/output port pins. Each designated input/output. PD15 (SH7016/17) General purpose port General purpose input/output port pins. Each designated input/output. PE15 General purpose port General purpose input/output port pins. Each designated input/output. General purpose port General purpose input port pins.
Classification ports
PC15 (SH7016/17)
Usage Notes Unused input pins should pulled pulled down. WDTOVF should pulled down SH7017 F-ZTAT version. However, necessary pull this down, resistance higher should used.
Section
Register Configuration
register consists sixteen 32-bit general registers, three 32-bit control registers four 32-bit system registers. 2.1.1 General Registers (Rn)
sixteen 32-bit general registers (Rn) numbered R0-R15. General registers used data processing address calculation. also used index register. Several instructions have fixed their only usable register. used hardware stack pointer (SP). Saving recovering status register (SR) program counter (PC) exception processing accomplished referencing stack using R15. Figure shows general registers.
R0*1 R15, (hardware stack pointer)*2 Notes: functions index register indirect indexed register addressing mode indirect indexed addressing mode. some instructions, functions fixed source register destination register. functions hardware stack pointer (SP) during exception processing.
Figure General Registers
2.1.2
Control Registers
32-bit control registers consist 32-bit status register (SR), global base register (GBR), vector base register (VBR). status register indicates processing states. global base register functions base address indirect addressing mode transfer data registers on-chip peripheral modules. vector base register functions base address exception processing vector area (including interrupts). Figure shows control register.
Status register bit: MOVT, CMP/cond, TAS, TST, (BT/S), (BF/S), SETT, CLRT instructions indicate true false (0). ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S, DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, ROTCL instructions also indicate carry/borrow overflow/underflow. bit: Used instruction. Reserved bits. This always read write value should always Bits I0-I3: Interrupt mask bits. bits: Used DIV0U, DIV0S, DIV1 instructions. Reserved bits. read. Write only. Global base register (GBR): Indicates base address indirect addressing mode. indirect addressing mode used data transfer on-chip peripheral modules register areas logic operations. Vector base register (VBR): Stores base address exception processing vector area.
Figure Control Registers
2.1.3
System Registers
System registers consist four 32-bit registers: high multiply accumulate registers (MACH MACL), procedure register (PR), program counter (PC). multiply accumulate registers store results multiply accumulate operations. procedure register stores return address from subroutine procedure. program counter stores program addresses control flow processing. Figure shows system register.
MACH MACL
Multiply accumulate (MAC) registers high (MACH, MACL): Stores results multiply accumulate operations. Procedure register (PR): Stores return address from subroutine procedure. Program counter (PC): Indicates fourth byte (second instruction) after current instruction.
Figure System Registers 2.1.4 Initial Values Registers
Table lists values registers after reset. Table Initial Values Registers
Register R0-R14 (SP) Control registers System registers MACH, MACL, Initial Value Undefined Value stack pointer vector address table Bits I3-I0 1111 (H'F), reserved bits other bits undefined Undefined H'00000000 Undefined Value program counter vector address table
Classification General registers
2.2.1
Data Formats
Data Format Registers
Register operands always longwords bits). When memory operand only byte bits) word bits), sign-extended into longword when loaded into register (figure 2.4).
Longword
Figure Longword Operand 2.2.2 Data Format Memory
Memory data formats classified into bytes, words, longwords. Byte data accessed from address, address error will occur access word data starting from address other than longword data starting from address other than such cases, data accessed cannot guaranteed. hardware stack area, referred hardware stack pointer (SP, R15), uses only longword data starting from address because this area holds program counter status register (figure 2.5).
Address Address Byte Address Address Byte Word Longword Byte Address Byte Word
Address
Figure Byte, Word, Longword Alignment 2.2.3 Immediate Data Format
Byte (8-bit) immediate data resides instruction code. Immediate data accessed MOV, ADD, CMP/EQ instructions sign-extended handled registers longword data. Immediate data accessed TST, AND, instructions zero-extended handled longword data. Consequently, instructions with immediate data always clear upper bits destination register.
Word longword immediate data located instruction code, instead stored memory table. immediate data transfer instruction (MOV) accesses memory table using relative addressing mode with displacement.
2.3.1
Instruction Features
RISC-Type Instruction
instructions RISC type. This section details their functions. 16-Bit Fixed Length: instructions bits long, increasing program code efficiency. Instruction Cycle: microprocessor execute basic instructions cycle using pipeline system. Instructions executed 28.7 MHz. Data Length: Longword standard data length operations. Memory accessed bytes, words, longwords. Byte word data accessed from memory sign-extended handled longword data. Immediate data sign-extended arithmetic operations zeroextended logic operations. also handled longword data (table 2.2). Table Sign Extension Word Data
Description Data sign-extended bits, becomes H'00001234. next operated upon instruction. Example Conventional ADD.W #H'1234,R0
SH7014/16/17 MOV.W @(disp,PC),R1 R1,R0 .DATA.W H'1234
Note: @(disp, accesses immediate data.
Load-Store Architecture: Basic operations executed between registers. operations that involve memory access, data loaded registers executed (load-store architecture). Instructions such that manipulate bits, however, executed directly memory. Delayed Branch Instructions: Unconditional branch instructions delayed. Executing instruction that follows branch instruction then branching reduces pipeline disruption during branching (table 2.3). There types conditional branch instructions: delayed branch instructions ordinary branch instructions.
Table
Delayed Branch Instructions
Description Executes before branching TRGET Example Conventional ADD.W R1,R0 TRGET
SH7014/16/17 TRGET R1,R0
Multiplication/Accumulation Operation: 16-bit 16-bit 32-bit multiplication operations executed cycles. 16-bit 16-bit 64-bit 64-bit multiplication/accumulation operations executed three cycles. 32-bit 32-bit 64-bit 32-bit 32-bit 64bit 64-bit multiplication/accumulation operations executed four cycles. Bit: status register changes according result comparison, turn condition (true/false) that determines program will branch. number instructions that change kept minimum improve processing speed (table 2.4). Table
Description when program branches TRGET0 when TRGET1 when Example Conventional CMP.W R1,R0 TRGET0 TRGET1 #1,R0 TRGET
SH7014/16/17 CMP/GE CMP/EQ R1,R0 TRGET0 TRGET1 #1,R0 #0,R0 TRGET
changed ADD. SUB.W when program branches
Immediate Data: Byte (8-bit) immediate data resides instruction code. Word longword immediate data input instruction codes stored memory table. immediate data transfer instruction (MOV) accesses memory table using relative addressing mode with displacement (table 2.5).
Table
Immediate Data Accessing
SH7014/16/17 MOV.W #H'12,R0 @(disp,PC),R0 .DATA.W H'1234 @(disp,PC),R0 .DATA.L H'12345678 MOV.L #H'12345678,R0 Example Conventional MOV.B MOV.W #H'12,R0 #H'1234,R0
Classification 8-bit immediate 16-bit immediate
32-bit immediate
MOV.L
Note: @(disp, accesses immediate data.
Absolute Address: When data accessed absolute address, value already absolute address placed memory table. Loading immediate data when instruction executed transfers that value register data accessed indirect register addressing mode (table 2.6). Table Absolute Address Accessing
SH7014/16/17 MOV.L MOV.B @(disp,PC),R1 @R1,R0 .DATA.L H'12345678 Note: @(disp,PC) accesses immediate data. Example Conventional MOV.B @H'12345678,R0
Classification Absolute address
16-Bit/32-Bit Displacement: When data accessed 16-bit 32-bit displacement, preexisting displacement value placed memory table. Loading immediate data when instruction executed transfers that value register data accessed indirect indexed register addressing mode (table 2.7). Table Displacement Accessing
SH7014/16/17 MOV.W MOV.W @(disp,PC),R0 @(R0,R1),R2 .DATA.W H'1234 Note: @(disp,PC) accesses immediate data. Example Conventional MOV.W @(H'1234,R1),R2
Classification 16-bit displacement
2.3.2
Addressing Modes
Table describes addressing modes effective address calculation. Table
Addressing Mode Direct register addressing Indirect register addressing Post-increment indirect register addressing
Addressing Modes Effective Addresses
Instruction Format Effective Addresses Calculation effective address register (The operand contents register Rn.) effective address content register @Rn+ (After instruction executes) Byte: Word: Longword: Byte: Word: Longword: (Instruction executed with after calculation) Equation
effective address content register constant added content after instruction executed. added byte operation, word operation, longword operation. 1/2/4 1/2/4
Pre-decrement indirect register addressing
@-Rn
effective address value obtained subtracting constant from subtracted byte operation, word operation, longword operation. 1/2/4 1/2/4 1/2/4
Table
Addressing Mode
Addressing Modes Effective Addresses (cont)
Instruction Format Effective Addresses Calculation @(disp:4, effective address plus 4-bit displacement (disp). value disp zeroextended, remains same byte operation, doubled word operation, quadrupled longword operation. disp (zero-extended) 1/2/4 disp 1/2/4 Equation Byte: disp Word: disp Longword: disp
Indirect register addressing with displacement
Indirect indexed @(R0, register addressing
effective address value plus
Indirect addressing with displacement
@(disp:8, GBR)
effective address value plus 8-bit displacement (disp). value disp zeroextended, remains same byte operation, doubled word operation, quadrupled longword operation. disp (zero-extended) 1/2/4 disp 1/2/4
Byte: disp Word: disp Longword: disp
Table
Addressing Mode
Addressing Modes Effective Addresses (cont)
Instruction Format Effective Addresses Calculation Equation
Indirect indexed @(R0, GBR) effective address value plus addressing relative addressing with displacement @(disp:8, effective address value plus 8-bit displacement (disp). value disp zeroextended, doubled word operation, quadrupled longword operation. longword operation, lowest bits value masked. H'FFFFFFFC disp (zero-extended) (for longword) disp H'FFFFFFFC disp
Word: disp Longword: H'FFFFFFFC disp
Table
Addressing Mode relative addressing
Addressing Modes Effective Addresses (cont)
Instruction Format Effective Addresses Calculation disp:8 effective address value sign-extended with 8-bit displacement (disp), doubled, added value. disp (sign-extended) disp:12 effective address value sign-extended with 12-bit displacement (disp), doubled, added value. disp (sign-extended) effective address register value plus disp disp disp Equation disp
Immediate addressing
#imm:8 #imm:8 #imm:8
8-bit immediate data (imm) TST, AND, instructions zero-extended. 8-bit immediate data (imm) MOV, ADD, CMP/EQ instructions sign-extended. 8-bit immediate data (imm) TRAPA instruction zero-extended quadrupled.
2.3.3
Instruction Format
Table lists instruction formats source operand destination operand. meaning operand depends instruction code. symbols used follows: xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement
Table
Instruction Formats
Source Operand xxxx xxxx xxxx nnnn: Direct register nnnn: Direct register MOVT Destination Operand Example
Instruction Formats format xxxx format
xxxx nnnn xxxx xxxx
Control register system register Control register system register
MACH,Rn
nnnn: Indirect pre- STC.L decrement register Control register system register Control register system register LDC.L
SR,@-Rn
format xxxx mmmm xxxx xxxx
mmmm: Direct register mmmm: Indirect post-increment register mmmm: Direct register mmmm: relative using
Rm,SR @Rm+,SR
BRAF
Table
Instruction Formats (cont)
Source Operand Destination Operand mmmm: Direct register nnnn mmmm xxxx mmmm: Direct register mmmm: Indirect post-increment register (multiply/ accumulate) nnnn*: Indirect post-increment register (multiply/ accumulate) mmmm: Indirect post-increment register mmmm: Direct register mmmm: Direct register nnnn: Direct register nnnn: Indirect predecrement register nnnn: Indirect indexed register (Direct register) MOV.L @Rm+,Rn nnnn: Direct register nnnn: Indirect register MACH, MACL Example MOV.L Rm,Rn Rm,@Rn
Instruction Formats format xxxx
MAC.W @Rm+,@Rn+
MOV.L
Rm,@-Rn
MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rm),R0
format xxxx format xxxx xxxx nnnn dddd format xxxx nnnn mmmm dddd xxxx mmmm dddd
mmmmdddd: indirect register with displacement (Direct register)
nnnndddd: Indirect register with displacement nnnndddd: Indirect register with displacement nnnn: Direct register
MOV.B R0,@(disp,Rn)
mmmm: Direct register
MOV.L Rm,@(disp,Rn)
mmmmdddd: Indirect register with displacement
MOV.L @(disp,Rm),Rn
Note: multiply/accumulate instructions, nnnn source register.
Table
Instruction Formats (cont)
Source Operand Destination Operand dddddddd: Indirect with displacement R0(Direct register) dddddddd: relative with displacement dddddddd: relative Example
Instruction Formats format xxxx xxxx dddd dddd
(Direct register) MOV.L @(disp,GBR),R0
dddddddd: Indirect with displacement
MOV.L R0,@(disp,GBR)
(Direct register) MOVA @(disp,PC),R0 label label
format xxxx dddd dddd dddd format xxxx format xxxx xxxx iiii iiii nnnn dddd dddd
dddddddddddd: relative
(label disp nnnn: Direct register MOV.L @(disp,PC),Rn
dddddddd: relative with displacement iiiiiiii: Immediate iiiiiiii: Immediate
Indirect indexed
AND.B #imm,@(R0,GBR) #imm,R0
(Direct register)
iiiiiiii: Immediate format xxxx nnnn iiii iiii iiiiiiii: Immediate
nnnn: Direct register
TRAPA
#imm #imm,Rn
Instruction Classification
Table 2.10 Classification Instructions
Operation Classification Types Code Function Data transfer Instructions
Data transfer, immediate data transfer, peripheral module data transfer, structure data transfer Effective address transfer transfer Swap upper lower bytes Extraction middle registers connected Binary addition Binary addition with carry Binary addition with overflow check
MOVA MOVT SWAP XTRCT Arithmetic operations ADDC ADDV
CMP/cond Comparison DIV1 DIV0S DIV0U DMULS DMULU EXTS EXTU MULS MULU NEGC SUBC SUBV Division Initialization signed division Initialization unsigned division Signed double-length multiplication Unsigned double-length multiplication Decrement test Sign extension Zero extension Multiply/accumulate, double-length multiply/accumulate operation Double-length multiply operation Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow
Table 2.10 Classification Instructions (cont)
Operation Classification Types Code Function Logic operations Shift ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch BRAF BSRF Logical inversion Logical Memory test Logical Exclusive One-bit left rotation One-bit right rotation One-bit left rotation with One-bit right rotation with One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Conditional branch, conditional branch with delay (Branch when Conditional branch, conditional branch with delay (Branch when Unconditional branch Unconditional branch Branch subroutine procedure Branch subroutine procedure Unconditional branch Branch subroutine procedure Return from subroutine procedure Instructions
Table 2.10 Classification Instructions (cont)
Operation Classification Types Code Function System control CLRT CLRMAC SETT SLEEP TRAPA Total: clear register clear Load control register Load system register operation Return from exception processing Shift into power-down mode Storing control register data Storing system register data Trap exception handling Instructions
Table 2.11 shows format used tables 2.12 2.17, which list instruction codes, operation, execution states order classification.
Table 2.11 Instruction Code Format
Item Instruction Format OP.Sz SRC,DEST Explanation Operation code Size byte, word, longword) SRC: Source DEST: Destination Source register Destination register imm: Immediate data disp: Displacement* mmmm: Source register nnnn: Destination register 0000: 0001: 1111: iiii: Immediate data dddd: Displacement Direction transfer Memory operand Flag bits Logical each Logical each Exclusive each Logical each n-bit left shift n-bit right shift Value when wait states inserted*2 Value after instruction executed. em-dash column means change.
Instruction code
Operation
(xx) M/Q/T
Execution cycles
Notes: Depending operand size, displacement scaled details, SH-1/SH-2/SH-DSP Programming Manual. Instruction execution cycles: execution cycles shown table minimums. actual number cycles increased when contention occurs between instruction fetches data access, when destination register load instruction (memory register) register used next instruction same.
Table 2.12 Data Transfer Instructions
Execution Cycles
Instruction #imm,Rn
Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100
Operation #imm Sign extension (disp Sign extension (disp (Rn) (Rn) (Rn) (Rm) Sign extension (Rm) Sign extension (Rm) Rn-1 (Rn) Rn-2 (Rn) Rn-4 (Rn) (Rm) Sign extension Rn,Rm (Rm) Sign extension Rn,Rm (Rm) Rn,Rm (disp (disp (disp (disp Sign extension (disp Sign extension (disp
MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn Rm,Rn
MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@-Rn MOV.W Rm,@-Rn MOV.L Rm,@-Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn MOV.B R0,@(disp,Rn) MOV.W R0,@(disp,Rn) MOV.L Rm,@(disp,Rn) MOV.B @(disp,Rm),R0 MOV.W @(disp,Rm),R0 MOV.L @(disp,Rm),Rn MOV.B Rm,@(R0,Rn)
Table 2.12 Data Transfer Instructions (cont)
Execution Cycles
Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) @(disp,GBR),R0 @(disp,GBR),R0 @(disp,GBR),R0 @(disp,PC),R0
Instruction Code 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd 11000101dddddddd 11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101
Operation Sign extension Sign extension (disp GBR) (disp GBR) (disp GBR) (disp GBR) Sign extension (disp GBR) Sign extension (disp GBR) disp
SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn
Swap bottom bytes Swap consecutive words Middle bits
Table 2.13 Arithmetic Operation Instructions
Execution Cycles
Instruction ADDC ADDV CMP/EQ CMP/EQ CMP/HS CMP/GE CMP/HI CMP/GT CMP/PL CMP/PZ Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn
Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010101 0100nnnn00010001 0010nnnnmmmm1100
Operation Carry Overflow imm,
Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result
RnRm with unsigned data, with signed data, with unsigned data, with signed data, have equivalent byte, Single-step division (Rn/Rm) M/Q/T
CMP/STR Rm,Rn
DIV1 DIV0S DIV0U
Rm,Rn Rm,Rn
0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001
Table 2.13 Arithmetic Operation Instructions (cont)
Execution Cycles
Instruction DMULS.L Rm,Rn
Instruction Code 0011nnnnmmmm1101
Operation Signed operation MACH, MACL Unsigned operation MACH, MACL
DMULU.L Rm,Rn
0011nnnnmmmm0101
0100nnnn00010000
when When nonzero, byte signextended word signextended byte zeroextended word zeroextended Signed operation (Rn) (Rm) Signed operation (Rn) (Rm) MACL, Signed operation Unsigned operation 0-Rm 0-Rm-T Borrow 3/(2 3/(2)*
Comparison result
EXTS.B EXTS.W EXTU.B EXTU.W MAC.L
Rm,Rn Rm,Rn Rm,Rn Rm,Rn @Rm+,@Rn+
0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111
MAC.W
@Rm+,@Rn+
0100nnnnmmmm1111
MUL.L MULS.W
Rm,Rn Rm,Rn
0000nnnnmmmm0111 0010nnnnmmmm1111
MULU.W
Rm,Rn
0010nnnnmmmm1110
NEGC
Rm,Rn Rm,Rn
0110nnnnmmmm1011 0110nnnnmmmm1010
Borrow
Table 2.13 Arithmetic Operation Instructions (cont)
Execution Cycles
Instruction SUBC SUBV Rm,Rn Rm,Rn Rm,Rn
Instruction Code 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011
Operation Rn-Rm Rn-Rm-T Borrow Rn-Rm Underflow
Borrow Overflow
Note: normal minimum number execution cycles. (The number parentheses number cycles when there contention with following instructions.)
Table 2.14 Logic Operation Instructions
Execution Cycles
Instruction Rm,Rn #imm,R0
Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 0010nnnnmmmm1000 11001000iiiiiiii 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii
Operation GBR) GBR) GBR) GBR) (Rn) (Rn)* result imm; result GBR) imm; result GBR) GBR)
Test result Test result Test result Test result
AND.B #imm,@(R0,GBR) OR.B Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR)
TAS.B Rm,Rn #imm,R0
TST.B #imm,@(R0,GBR) Rm,Rn #imm,R0
XOR.B #imm,@(R0,GBR)
Note: on-chip DMAC cycles inserted between read write cycles instruction execution.
Table 2.15 Shift Instructions
Execution Cycles
Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16
Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001
Operation Rn<<2 Rn>>2 Rn<<8 Rn>>8 Rn<<16 Rn>>16
Table 2.16 Branch Instructions
Instruction label Instruction Code 10001011dddddddd 10001111dddddddd 10001001dddddddd 10001101dddddddd 1010dddddddddddd 0000mmmm00100011 1011dddddddddddd 0000mmmm00000011 0100mmmm00101011 0100mmmm00001011 0000000000001011 Operation disp Delayed branch, disp disp Delayed branch, disp Delayed branch, disp Delayed branch, Delayed branch, disp Delayed branch, Delayed branch, Delayed branch, Delayed branch, Exec. Cycles 3/1* 3/1* 3/1* 2/1*
BF/S label label
BT/S label label
BRAF label
BSRF
Note: state when does branch.
Table 2.17 System Control Instructions
Instruction CLRT CLRMAC Rm,SR Rm,GBR Rm,VBR Instruction Code 0000000000001000 0000000000101000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000000000101011 0000000000011000 0000000000011011 SR,Rn GBR,Rn VBR,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 Operation MACH, MACL (Rm) (Rm) GBR, (Rm) VBR, MACH MACL (Rm) MACL, (Rm) operation Delayed branch, stack area PC/SR Sleep Rn-4 (Rn) Rn-4 (Rn) Rn-4 (Rn) MACH MACL Exec. Cycles
LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR Rm,MACH Rm,MACL Rm,PR
LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR SETT SLEEP STC.L STC.L STC.L
(Rm) MACH,
Table 2.17 System Control Instructions (cont)
Instruction STS.L STS.L STS.L TRAPA MACH,@-Rn MACL,@-Rn PR,@-Rn #imm Instruction Code 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Operation Rn-4 MACH (Rn) Rn-4 MACL (Rn) Rn-4 (Rn) PC/SR stack area, (imm) Exec. Cycles
Note: number execution cycles before chip enters sleep mode: execution cycles shown table minimums. actual number cycles increased when contention occurs between instruction fetches data access, when destination register load instruction (memory register) register used next instruction same.
2.5.1
Processing States
State Transitions
four processing states: reset, exception processing, program execution powerdown. Figure shows transitions between states.
From state when
Power-on reset state
Reset states
Exception processing state When interrupt source address error occurs Exception processing source occurs Exception processing ends
interrupt source occurs
Program execution state cleared SLEEP instruction SLEEP instruction
Sleep mode
Standby mode
Power-down state
Figure Transitions between Processing States Reset State: resets reset state. When level goes low, power-on reset results. Exception Processing State: exception processing state transient state that occurs when exception processing sources such resets interrupts alter CPU's processing state flow.
reset, initial values program counter (PC) (execution start address) stack pointer (SP) fetched from exception processing vector table stored; then branches execution start address execution program begins. interrupt, stack pointer (SP) accessed program counter (PC) status register (SR) saved stack area. exception service routine start address fetched from exception processing vector table; then branches that address program starts executing, thereby entering program execution state. Program Execution State: program execution state, sequentially executes program. Power-Down State: power-down state, operation halts power consumption declines. SLEEP instruction places power-down state. This state modes: sleep mode standby mode. 2.5.2 Power-Down State
Besides ordinary program execution states, also power-down state which operation halts, lowering power consumption. There power-down state modes: sleep mode standby mode. Sleep Mode: When standby standby control register SBYCR) cleared SLEEP instruction executed, moves from program execution state sleep mode. sleep mode, halts contents internal registers data on-chip cache on-chip RAM) maintained. on-chip peripheral modules other than halt sleep mode. return from sleep mode, power-on reset, interrupt, address error; returns ordinary program execution state through exception processing state. Standby Mode: enter standby mode, standby standby control register SBYCR) execute SLEEP instruction. standby mode, CPU, on-chip peripheral module, oscillator functions halted. However, when entering standby mode, master enable DMAC should multiplication-related instructions being executed time entry into standby mode, values MACH MACL will become undefined. return from standby mode, power-on reset interrupt. resets, returns ordinary program execution state through exception processing state when placed reset state duration oscillator stabilization time. interrupts, returns ordinary program execution state through exception processing state after oscillator stabilization time elapsed. this mode, power consumption drops markedly, since oscillator stops (table 2.18).
Table 2.18 Power-Down State
State On-Chip Cache On-Chip On-Chip Port Peripheral Transition Pins Mode Conditions Clock Modules Registers Sleep Execute SLEEP instruction with cleared SBYCR Halt Stand- Execute SLEEP instruction with SBYCR Halt Held Held Held
Canceling Interrupt address error Power-on reset interrupt Power-on reset
Halt
Halt initialize*
Held
Held
Held Hi-Z (selectable)
Note: Differs depending peripheral module pin.
Section Operating Modes
Operating Modes, Types, Selection
This five operating modes three clock modes, determined setting mode pins (MD3-MD0). change mode settings during operation (while power on). Table indicates setting method operating mode. Table Operating Mode Setting
On-Chip Active Active Active Active Active
Setting Mode Mode MD3*1 MD2*1 Name
Area 8-bit space 16-bit space 8/16-bit space*2 8/16-bit space*2
mode mode mode Single chip mode Boot mode*
User programming mode*3
Active
8/16-bit space*2
Flash programmer mode*3
Active
Notes:
pins select clock mode modes (table 3.2). BCR2 BSC. Only F-ZTAT. Only SH7016, SH7017.
Table indicates setting method clock mode. Table
Clock Mode Setting
Clock Mode Reserved
Explanation Operating Modes
Table describes operating modes. Table
Mode (MCU) Mode (MCU) Mode (MCU) Mode Mode (single chip mode) Clock mode
Operating Modes
Description area becomes external memory space with 8-bit width. area becomes external memory space with 16-bit width. on-chip becomes effective. width on-chip space bit. port used, external addresses employed. input waveform frequency used doubled quadrupled internal clock modes
Configuration
Table describes function each operating mode related pin. Table
Name XTAL EXTAL PLLCAP
Operating Mode Function
Input/Output Input Input Input Input Input Input Input Function Connects crystal oscillator Connects crystal oscillator, used external clock input Connects capacitor circuit operation Designates operating mode through level applied this Designates operating mode through level applied this Designates clock mode through level applied this Designates clock mode through level applied this
Section Clock Pulse Generator (CPG)
Overview
This on-chip clock pulse generator (CPG) that generates system clock well internal clock /8192). consists oscillator, PLL, prescaler. 4.1.1 Block Diagram
block diagram clock pulse generator shown figure 4.1.
PLLCAP EXTAL Oscillator XTAL circuit
Prescaler Clock mode control circuitry /8192 Within
Figure Block Diagram Clock Pulse Generator
Oscillator
Clock pulses supplied from connected crystal resonator external clock. 4.2.1 Connecting Crystal Oscillator
Circuit Configuration: crystal oscillator connected shown figure 4.2. damping resistance (Rd) listed table 4.1. 4-10 crystal oscillator (consult your dealer concerning compatibility crystal oscillator LSI).
EXTAL 4-10 XTAL
18-22 (Recommended value)
Figure Connection Crystal Oscillator (Example) Table Damping Resistance Values (Recommended Values)
Frequency (MHz) Parameter
Crystal Oscillator: Figure shows equivalent circuit crystal oscillator. crystal oscillator with characteristics listed table 4.2.
EXTAL XTAL
Figure Crystal Oscillator Equivalent Circuit Table Crystal Oscillator Parameters
Frequency (MHz) Parameter (pF)
Notes Board Design: When connecting crystal oscillator, observe following precautions: prevent induction from interfering with correct oscillation, route signal lines near oscillator circuitry. When designing board, place crystal oscillator load capacitors close possible XTAL EXTAL pins. Figures show precautions regarding oscillator block board settings.
Crossing signal lines prohibited
XTAL
EXTAL
Figure Cautions Oscillator Circuit System Board Design External circuitry such that shown figure recommended around PLL.
PLLCAP
PLLVCC CPB: PLLVSS laminated ceramic capacitors (Recommended values)
Figure Cautions Oscillator Circuit
Place oscillation stabilization capacitor resistor near pin, ensure that these lines cross other signal lines. Supply ground from VSS. Also, separate other pins, from board power supply source, sure insert bypass capacitors close pins. 4.2.2 External Clock Input Method
Figure shows example external clock input connection. this case, make external clock high level stop when standby mode. During operation, make external input clock frequency 4-10 MHz. When leaving XTAL open, make sure parasitic capacitance less than Even when inputting external clock, sure delay until after oscillation stabilization time (upon power-on) after release from standby, order ensure stabilization time.
EXTAL XTAL Open
External clock input 4-10
Figure Example External Clock Connection 4.2.3 Prescaler
prescaler divides system clock generate internal clock /8192) supply peripheral modules.
Section Exception Processing
5.1.1
Overview
Types Exception Processing Priority
Exception processing started four sources: resets, address errors, interrupts instructions have priority shown table 5.1. When several exception processing sources occur once, they processed according priority shown. Table
Exception Reset Address error Interrupt
Types Exception Processing Priority Order
Source Power-on reset address error DMAC address error User break On-chip peripheral modules: Direct memory access controller (DMAC) Multifunction timer/pulse unit (MTU) Serial communication interface (SCI) converter (A/D) Compare match timer (CMT) Watchdog timer (WDT) state controller (BSC) Priority High
Instructions Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Illegal slot instructions (undefined code placed directly after delay branch instruction* instructions that rewrite PC*2) Notes: Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. Instructions that rewrite JMP, JSR, BRA, BSR, RTS, RTE, TRAPA, BF/S, BT/S, BSRF, BRAF.
5.1.2
Exception Processing Operations
exception processing sources detected begin processing according timing shown table 5.2. Table
Exception
Timing Exception Source Detection Start Exception Processing
Source Timing Source Detection Start Processing Starts when changes from high. Detected when instruction decoded starts when previous executing instruction finishes executing. Detected when instruction decoded starts when previous executing instruction finishes executing. Trap instruction General illegal instructions Illegal slot instructions Starts from execution TRAPA instruction. Starts from decoding undefined code anytime except after delayed branch instruction (delay slot). Starts from decoding undefined code placed delayed branch instruction (delay slot) instructions that rewrite
Power-on reset Address error Interrupts Instructions
When exception processing starts, operates follows: Exception processing triggered reset: initial values program counter (PC) stack pointer (SP) fetched from exception processing vector table respectively H'00000000 H'00000004 addresses). section 5.1.3, Exception Processing Vector Table, more information. then written vector base register (VBR) 1111 written interrupt mask bits (I3-I0) status register (SR). program begins running from address fetched from exception processing vector table. Exception processing triggered address errors, interrupts instructions: saved stack indicated R15. interrupt exception processing, interrupt priority level written SR's interrupt mask bits (I3-I0). address error instruction exception processing, I3-I0 bits affected. start address then fetched from exception processing vector table program begins running from that address.
5.1.3
Exception Processing Vector Table
Before exception processing begins running, exception processing vector table must memory. exception processing vector table stores start addresses exception service routines. (The reset exception processing table holds initial values SP.) exception sources given different vector numbers vector table address offsets, from which vector table addresses calculated. During exception processing, start addresses exception service routines fetched from exception processing vector table, which indicated this vector table address. Table shows vector numbers vector table address offsets. Table shows vector table addresses calculated. Table Exception Processing Vector Table
Vector Numbers (Reserved system) (Reserved system) General illegal instruction (Reserved system) Slot illegal instruction (Reserved system) (Reserved system) address error DMAC address error Interrupts User break (Reserved system) Trap instruction (user vector) Vector Table Address Offset H'00000000-H'00000003 H'00000004-H'00000007 H'00000008-H'0000000B H'0000000C-H'0000000F H'00000010-H'00000013 H'00000014-H'00000017 H'00000018-H'0000001B H'0000001C-H'0000001F H'00000020-H'00000023 H'00000024-H'00000027 H'00000028-H'0000002B H'0000002C-H'0000002F H'00000030-H'00000033 H'00000034-H'00000037 H'0000007C-H'0000007F H'00000080-H'00000083 H'000000FC-H'000000FF
Exception Sources Power-on reset
Table
Exception Processing Vector Table (cont)
Vector Numbers IRQ0 IRQ1 IRQ2 IRQ3 IRQ6 IRQ7 Vector Table Address Offset H'00000100-H'00000103 H'00000104-H'00000107 H'00000108-H'0000010B H'0000010C-H'0000010F H'00000110-H'00000113 H'00000114-H'00000117 H'00000118-H'0000011B H'0000011C-H'0000011F H'00000120-H'00000124 H'000003FC-H'000003FF
Exception Sources Interrupts
(Reserved system) (Reserved system) Interrupt
On-chip peripheral module*
Note: vector numbers vector table address offsets each on-chip peripheral module interrupt given section Interrupt Controller, table 6.3, Interrupt Exception Processing Vectors Priorities.
Table
Calculating Exception Processing Vector Table Addresses
Vector Table Address Calculation Vector table address (vector table address offset) (vector number) Vector table address (vector table address offset) (vector number)
Exception Source Resets Address errors, interrupts, instructions
Notes: VBR: Vector base register Vector table address offset: table 5.3. Vector number: table 5.3.
5.2.1
Resets
Power-on Reset
When driven low, does power-on reset. reliably reset LSI, should kept least duration oscillation settling time when applying power when standby mode (when clock circuit halted) least (when clock circuit running). During power-on reset, internal status registers on-chip peripheral modules initialized. Appendix Status, status individual pins during power-on reset status. power-on reset status, power-on reset exception processing starts when first driven period time then returned high. will then operate follows: initial value (execution start address) program counter (PC) fetched from exception processing vector table. initial value stack pointer (SP) fetched from exception processing vector table. vector base register (VBR) cleared H'00000000 interrupt mask bits (I3-I0) status register (SR) (1111). values fetched from exception processing vector table program counter (PC) program begins executing. certain always perform power-on reset processing when turning system power
Address Errors
Address errors occur when instructions fetched data read written, shown table 5.5. Table Cycles Address Errors
Cycle Type Master Cycle Description Instruction fetched from even address Instruction fetched from address Instruction fetched from other than on-chip peripheral module space* Instruction fetched from on-chip peripheral module space* Data read/write Word data accessed from even address DMAC Word data accessed from address Longword data accessed from longword boundary Longword data accessed from other than long-word boundary Byte word data accessed on-chip peripheral module space* Longword data accessed 16-bit on-chip peripheral module space* Longword data accessed 8-bit on-chip peripheral module space* Address Errors None (normal) Address error occurs None (normal) Address error occurs None (normal) Address error occurs None (normal) Address error occurs None (normal) None (normal) Address error occurs
Instruction fetch
External memory space accessed single-chip mode Address error occurs Note: section State Controller.
5.3.1
Address Error Exception Processing
When address error occurs, cycle which address error occurred ends. When executing instruction then finishes, address error exception processing starts operates follows: status register (SR) saved stack. program counter (PC) saved stack. value saved start address instruction executed after last executed instruction. exception service routine start address fetched from exception processing vector table that corresponds address error that occurred program starts executing from that address. jump that occurs delayed branch.
Interrupts
Table shows sources that start interrupt exception processing. These divided into NMI, user breaks, on-chip peripheral modules. Table
Type On-chip peripheral module
Interrupt Sources
Request Source (external input) IRQ0-IRQ3, IRQ6, IRQ7 (external input) Direct memory access controller (DMAC) Multifunction timer pulse unit (MTU) Serial communication interface (SCI) converter Compare match timer (CMT) Watchdog timer (WDT) state controller (BSC) Number Sources
Each interrupt source allocated different vector number vector table offset. section Interrupt Controller, table 6.3, Interrupt Exception Processing Vectors Priorities, more information vector numbers vector table address offsets. 5.4.1 Interrupt Priority Level
interrupt priority order predetermined. When multiple interrupts occur simultaneously (overlap), interrupt controller (INTC) determines their relative priorities starts processing according results.
priority order interrupts expressed priority levels 0-16, with priority lowest priority highest. interrupt priority cannot masked, always accepted. interrupts on-chip peripheral module interrupt priority levels freely using INTC's interrupt priority level setting registers through (IPRA IPRH) shown table 5.7. priority levels that 0-15. Level cannot set. section 6.3.1, Interrupt Priority Registers (IPRA-IPRH), more information IPRA IPRH. Table
Type On-chip peripheral module
Interrupt Priority Order
Priority Level 0-15 0-15 Comment Fixed priority level. Cannot masked. with interrupt priority level setting registers through (IPRA IPRH). with interrupt priority level setting registers through (IPRA IPRH).
5.4.2
Interrupt Exception Processing
When interrupt occurs, priority level ascertained interrupt controller (INTC). always accepted, other interrupts only accepted they have priority level higher than priority level interrupt mask bits (I3-I0) status register (SR). When interrupt accepted, exception processing begins. interrupt exception processing, saves program counter (PC) stack. priority level value accepted interrupt written bits I3-I0. NMI, however, priority level value I3-I0 (level 15). Next, start address exception service routine fetched from exception processing vector table accepted interrupt, that address jumped execution begins. section 6.4, Interrupt Operation, more information interrupt exception processing.
Exceptions Triggered Instructions
Exception processing triggered trap instructions, general illegal instructions, illegal slot instructions, shown table 5.8.
Table
Type
Types Exceptions Triggered Instructions
Source Instruction TRAPA Undefined code placed immediately after delayed branch instruction (delay slot) instructions that rewrite Comment Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite JMP, JSR, BRA, BSR, RTS, RTE, TRAPA, BF/S, BT/S, BSRF, BRAF
Trap instructions Illegal slot instructions
General illegal instructions
Undefined code anywhere besides delay slot
5.5.1
Trap Instructions
When TRAPA instruction executed, trap instruction exception processing starts operates follows: status register (SR) saved stack. program counter (PC) saved stack. value saved start address instruction executed after TRAPA instruction. exception service routine start address fetched from exception processing vector table that corresponds vector number specified TRAPA instruction. That address jumped program starts executing. jump that occurs delayed branch. 5.5.2 Illegal Slot Instructions
instruction placed immediately after delayed branch instruction said placed delay slot. When instruction placed delay slot undefined code, illegal slot exception processing starts when that undefined code decoded. Illegal slot exception processing also starts when instruction that rewrites program counter (PC) placed delay slot. processing starts when instruction decoded. handles illegal slot instruction follows: status register (SR) saved stack. program counter (PC) saved stack. value saved jump address delayed branch instruction immediately before undefined code instruction that rewrites exception service routine start address fetched from exception processing vector table that corresponds exception that occurred. That address jumped program starts executing. jump that occurs delayed branch.
5.5.3
General Illegal Instructions
When undefined code placed anywhere other than immediately after delayed branch instruction (i.e., delay slot) decoded, general illegal instruction exception processing starts handles general illegal instructions same illegal slot instructions. Unlike processing illegal slot instructions, however, program counter value stored start address undefined code.
When Exception Sources Accepted
When address error interrupt generated after delayed branch instruction interruptdisabled instruction, sometimes accepted immediately stored instead, shown table 5.9. When this happens, will accepted when instruction that accept exception decoded. Table Generation Exception Sources Immediately after Delayed Branch Instruction Interrupt-Disabled Instruction
Exception Source Point Occurrence Immediately after delayed branch instruction*1 instruction*2 Address Error accepted Accepted Interrupt accepted accepted
Immediately after interrupt-disabled
Notes: Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
5.6.1
Immediately after Delayed Branch Instruction
When instruction placed immediately after delayed branch instruction (delay slot) decoded, neither address errors interrupts accepted. delayed branch instruction instruction located immediately after (delay slot) always executed consecutively, exception processing occurs during this period. 5.6.2 Immediately after Interrupt-Disabled Instruction
When instruction immediately following interrupt-disabled instruction decoded, interrupts accepted. Address errors accepted.
Stack Status after Exception Processing Ends
status stack after exception processing ends shown table 5.10. Table 5.10 Types Stack Status After Exception Processing Ends
Types Address error Address instruction bits after executed instruction bits Stack Status
Trap instruction Address instruction after TRAPA instruction General illegal instruction Start address illegal instruction Interrupt Address instruction after executed instruction bits Illegal slot instruction bits bits bits bits bits
Jump destination address delay branch instruction bits bits
5.8.1
Notes
Value Stack Pointer (SP)
value stack pointer must always multiple four. not, address error will occur when stack accessed during exception processing. 5.8.2 Value Vector Base Register (VBR)
value vector base register must always multiple four. not, address error will occur when stack accessed during exception processing. 5.8.3 Address Errors Caused Stacking Address Error Exception Processing
When stack pointer multiple four, address error will occur during stacking exception processing (interrupts, etc.) address error exception processing will start soon first exception processing ended. Address errors will then also occur stacking this address error exception processing. ensure that address error exception processing does into endless loop, address errors accepted that point. This allows program control shifted address error exception service routine enables error processing. When address error occurs during exception processing stacking, stacking cycle (write) executed. During stacking status register (SR) program counter (PC), both, value will multiple four after stacking either. address value output during stacking value, address where error occurred itself output. This means write data stacked will undefined.
Section Interrupt Controller (INTC)
Overview
interrupt controller (INTC) ascertains priority interrupt sources controls interrupt requests CPU. INTC registers setting priority each interrupt which used user order priorities which interrupt requests processed. 6.1.1 Features
INTC following features: levels interrupt priority: setting eight interrupt-priority level registers, priorities interrupts on-chip peripheral module interrupts levels different request sources. noise canceler function: input level bits indicate status. reading these bits with interrupt exception service routine, status confirmed, enabling used noise canceler. 6.1.2 Block Diagram
Figure block diagram INTC.
IRQ0 IRQ1 IRQ2 IRQ3 IRQ6 IRQ7
Input control
Priority ranking judgment
Comparator
Interrupt request
DMAC (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request)
IPRA-IPRH interface Internal
Module
DMAC: MTU: CMT: SCI: A/D: WDT: BSC:
INTC ICR: Interrupt control register Direct memory access controller ISR: ststus register Multifunction timer pulse unit IPRA-IPRH: Interrupt priority level setting Compare match timer registers Serial communication interface Status register converter Watchdog timer state controller (DRAM refresh control section)
Figure INTC Block Diagram
6.1.3
Configuration
Table shows INTC configuration. Table
Name Non-maskable interrupt input Interrupt request input pins
Configuration
Abbreviation IRQ0-IRQ3, IRQ6, IRQ7 Function Input non-maskable interrupt request signal Input maskable interrupt request signals
6.1.4
Register Configuration
INTC registers shown table 6.2. These registers priority interrupts control external interrupt input signal detection. Table
Name Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt control register status register
Register Configuration
Abbr. IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH
Initial Value Address H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000
Access Sizes
H'FFFF8348 H'FFFF834A H'FFFF834C H'FFFF834E H'FFFF8350 H'FFFF8352 H'FFFF8354 H'FFFF8356 H'FFFF8358 H'FFFF835A
R(W)* H'0000
Notes: value when high H'8000; when low, H'0000. Only written, order clear flags.
Interrupt Sources
There three types interrupt sources: NMI, IRQ, on-chip peripheral modules. Each interrupt priority expressed priority level with lowest highest). Giving interrupt priority level masks 6.2.1 Interrupts
interrupt priority always accepted. Input detected edge. edge select (NMIE) interrupt control register (ICR) select either rising falling edge. interrupt exception processing sets interrupt mask level bits (I3-I0) status register (SR) level 6.2.2 Interrupts
interrupts requested input from pins IRQ0-IRQ3, IRQ6, IRQ7. sense select bits (IRQ0S-IRQ3S, IRQ6S, IRQ7S) interrupt control register (ICR) select level detection falling edge detection each pin. priority level from each using interrupt priority registers (IPRA-IPRB). When interrupts level detection, interrupt request signal sent INTC during period level. Interrupt request signals sent INTC when becomes high level. Interrupt request levels confirmed reading flags (IRQ0F-IRQ3F, IRQ6F, IRQ7F) status register (ISR). When interrupts falling edge detection, interrupt request signals sent INTC upon detecting change from high level. interrupt request detection results maintained until interrupt request accepted. Confirmation that interrupt requests have been detected possible reading flags (IRQ0F-IRQ3F, IRQ6F, IRQ7F) status register (ISR), writing after reading interrupt request detection results withdrawn. interrupt exception processing, interrupt mask bits (I3-I0) status register (SR) priority level value accepted interrupt.
6.2.3
On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts interrupts generated following on-chip peripheral modules: Direct memory access controller (DMAC) Multifunction timer pulse unit (MTU) Compare match timer (CMT) Serial communication interface (SCI) converter (A/D) Watchdog timer (WDT) state controller (BSC)
different interrupt vector assigned each interrupt source, exception service routine does have decide which interrupt occurred. Priority levels between assigned individual on-chip peripheral modules interrupt priority registers (IPRC- IPRH). On-chip peripheral module interrupt exception processing sets interrupt mask level bits (I3-I0) status register (SR) priority level value on-chip peripheral module interrupt that accepted. 6.2.4 Interrupt Exception Vectors Priority Rankings
Table lists interrupt sources their vector numbers, vector table address offsets interrupt priorities. Each interrupt source allocated different vector number vector table address offset. Vector table addresses calculated from vector numbers address offsets. interrupt exception processing, exception service routine start address fetched from vector table indicated vector table address. table 5.4, Calculating Exception Processing Vector Table Addresses. interrupts on-chip peripheral module interrupt priorities freely between each module setting interrupt priority registers (IPRA-IPRH). ranking interrupt sources IPRC-IPRH, however, must order listed under Priority Order Within Setting Range table cannot changed. power-on reset assigns priority level interrupts on-chip peripheral module interrupts. same priority level assigned more interrupt sources interrupts from those sources occur simultaneously, their priority order default priority order indicated right table 6.3.
Table
Interrupt Exception Processing Vectors Priorities
Interrupt Vector Vector DEI0 DEI1 TGI0A TGI0B TGI0C TGI0D TCI0V Vector Table Address Offset Interrupt Priority (Initial Value) Priority within Setting Default Range Priority High High
Interrupt Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ6 IRQ7 DMAC0 DMAC1 MTU0
Corresponding (Bits) IPRA (15-12) IPRA (11-8) IPRA (7-4) IPRA (3-0) IPRB (7-4) IPRB (3-0) IPRC (15-12) IPRC (11-8) IPRD (15-12)
H'0000002C H'0000002F H'00000100 H'00000103 H'00000104 H'00000107 H'00000108 H'0000010B
H'0000010C H'0000010F H'00000118 H'0000011B
H'0000011C H'0000011F H'00000120 H'00000123 H'00000130 H'00000133 H'00000160 H'00000163 H'00000164 H'00000167 H'00000168 H'0000016B
H'0000016C H'0000016F H'00000170 H'00000173 IPRD (11-8)
Table
Interrupt Exception Processing Vectors Priorities (cont)
Interrupt Vector Vector Vector Table Address Offset H'00000180 H'00000183 H'00000184 H'00000187 H'00000190 H'00000193 H'00000194 H'00000197 Interrupt Priority (Initial Value) IPRE (15-12) IPRD (3-0) Priority within Setting Default Range Priority High High High IPRE (11-8) High IPRF (7-4) High High
Interrupt Source MTU1 TGI1A TGI1B TCI1V TCI1U MTU2 TGI2A TGI2B TCI2V TCI2U SCI0 ERI0 RXI0 TXI0 TEI0 SCI1 ERI1 RXI1 TXI1 TEI1
Corresponding (Bits) IPRD (7-4)
H'000001A0 H'000001A3 H'000001A4 H'000001A7 H'000001B0 H'000001B3 H'000001B4 H'000001B7 H'00000200 H'00000203 H'00000204 H'00000207 H'00000208 H'0000020B
H'0000020C H'0000020F H'00000210 H'00000213 H'00000214 H'00000217 H'00000218 H'0000021B IPRF (3-0)
High
H'0000021C H'0000021F
Table
Interrupt Exception Processing Vectors Priorities (cont)
Interrupt Vector Vector Vector Table Address Offset H'00000220 H'00000223 H'00000228 H'0000022B H'00000240 H'00000243 H'00000250 H'00000253 H'00000260 H'00000263 H'00000264 H'00000267 IPRG (7-4) IPRG (3-0) IPRH (15-12) High Interrupt Priority (Initial Value) Priority within Setting Default Range Priority High
Interrupt Source A/D*
Corresponding (Bits) IPRG (15-12)
CMT0 CMT1
CMI0 CMI1
Note: Vector SH7014 only SH7016, SH7017 only
6.3.1
Description Registers
Interrupt Priority Registers (IPRA-IPRH)
Interrupt priority registers (IPRA-IPRH) 16-bit readable/writable registers that priority levels from interrupts on-chip peripheral module interrupts. Correspondence between interrupt request sources each IPRA-IPRH bits shown table 6.4.
Bit:
Initial value: R/W: Bit:
Initial value: R/W:
Table
Interrupt Request Sources IPRA-IPRH
Bits
Register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register
15-12 IRQ0 Reserved DMAC0 MTU0 MTU2 Reserved WDT,
11-8 IRQ1 Reserved DMAC1 MTU0 MTU2 Reserved Reserved Reserved
IRQ2 IRQ6 Reserved MTU1 Reserved SCI0 CMT0 Reserved
IRQ3 IRQ7 Reserved MTU1 Reserved SCI1 CMT1 Reserved
indicated table 6.4, four pins groups on-chip peripheral modules allocated each register. Each corresponding interrupt priority ranks established setting value from (0000) (1111) each four-bit groups 15-12, 11-8, 3-0. Interrupt priority rank becomes level (lowest) setting H'0, level (highest) setting H'F. multiple on-chip peripheral modules assigned BSC, those multiple modules same priority rank. IPRA-IPRH initialized H'0000 power-on reset manual reset. They initialized standby mode.
6.3.2
Interrupt Control Register (ICR)
16-bit register that sets input signal detection mode external interrupt input IRQ0-IRQ3, IRQ6, IRQ7 indicates input signal level pin. initialized power-on reset, initialized standby mode.
Bit: NMIL Initial value: R/W: Bit: IRQ0S Initial value: R/W: IRQ1S IRQ2S IRQ3S IRQ6S NMIE IRQ7S
Note: When input high: when input low:
15-NMI Input Level (NMIL): Sets level signal input pin. This read determine level. This cannot modified.
NMIL Description input level input level high
Bits 2-Reserved: These bits always read write value should always 8-NMI Edge Select (NMIE)
NMIE Description Interrupt request detected falling edge input (initial value) Interrupt request detected rising edge input
Bits 0-IRQ0-IRQ3, IRQ6, IRQ7 Sense Select (IRQ0S-IRQ3S, IRQ6S, IRQ7S): These bits IRQ0-IRQ3, IRQ6, IRQ7 interrupt request detection mode.
Bits 7-4, IRQ0S-IRQ3S, IRQ6S, IRQ7S
Description Interrupt request detected level input (initial value) Interrupt request detected falling edge input
6.3.3
Status Register (ISR)
16-bit register that indicates interrupt request status external interrupt input pins IRQ0-IRQ3, IRQ6, IRQ7. When interrupts edge detection, held interrupt requests withdrawn writing IRQnF after reading IRQnF power-on reset initializes standby mode does not.
Bit: Initial value: R/W: Bit: IRQ0F Initial value: R/W: IRQ1F IRQ2F IRQ3F IRQ6F IRQ7F
Bits 2-Reserved: These bits always read write value should always Bits 0-IRQ0-IRQ3, IRQ6, IRQ7 Flags (IRQ0F-IRQ3F, IRQ6F, IRQ7F): These bits display IRQ0-IRQ3, IRQ6, IRQ7 interrupt request status.
Bits 7-4, IRQ0F-IRQ3F, IRQ6F, IRQ7F
Detection Setting Level detection
Description IRQn interrupt request exists. Clear conditions: When IRQn input high level
Edge detection
IRQn interrupt request detected. (initial value) Clear conditions: When written after reading IRQnF status When IRQn interrupt exception processing been executed
Level detection
IRQn interrupt request exists. conditions: When IRQn input level
Edge detection
IRQn interrupt request detected. conditions: When falling edge occurs IRQn input
ISR.IRQnF IRQnS level, edge) Level detection Edge detection interrupt request
Selection
RESIRQn
(IRQn interrupt acceptance/IRQnF write after IRQnF read)
Figure External Interrupt Process
6.4.1
Interrupt Operation
Interrupt Sequence
sequence interrupt operations explained below. Figure flowchart operations. interrupt request sources send interrupt request signals interrupt controller. interrupt controller selects highest priority interrupt interrupt requests sent, following priority levels interrupt priority level setting registers (IPRA-IPRH). Lower-priority interrupts ignored. They held pending until interrupt requests designated edge-detect type accepted. interrupts, however, withdrawal possible accessing status register (ISR). section 6.2.2, Interrupts, details. Interrupts held pending edge detection cleared power-on reset. these interrupts have same priority level multiple interrupts occur within single module, interrupt with highest default priority highest priority within setting range indicated table 6.3) selected. interrupt controller compares priority level selected interrupt request with interrupt mask bits (I3-I0) CPU's status register (SR). request priority level equal less than level I3-I0, request ignored. request priority level higher than level bits I3-I0, interrupt controller accepts interrupt sends interrupt request signal CPU. detects interrupt request sent from interrupt controller when decodes next instruction executed. Instead executing decoded instruction, starts interrupt exception processing (figure 6.4). saved onto stack.
priority level accepted interrupt copied interrupt mask level bits status register (SR). reads start address exception service routine from exception vector table accepted interrupt, jumps that address, starts executing program there. This jump delay branch.
Program execution state
Interrupt? NMI?
Level interrupt? Save stack Save stack Copy accept-interrupt level Reads exception vector table Branches exception service routine level
Level interrupt? level
Level interrupt? level
Interrupt mask bits status register
Figure Interrupt Sequence Flowchart
6.4.2
Stack after Interrupt Exception Processing
Figure shows stack after interrupt exception processing.
Address 4n-8 4n-4 PC*1 bits bits SP*2
Notes:
Start address next instruction (return destination instruction) after executing instruction Always certain that multiple
Figure Stack after Interrupt Exception Processing
Interrupt Response Time
Table indicates interrupt response time, which time from occurrence interrupt request until interrupt exception processing starts fetching first instruction interrupt service routine begins. Figure shows pipeline when interrupt accepted.
Table
Interrupt Response Time
Number States
Item DMAC active judgment
NMI, Peripheral Module
Notes state required interrupt signals which DMAC activation possible
Compare identified interrupt priority with mask level Wait completion sequence currently being executed
longest sequence interrupt address-error exception processing m4). interrupt-masking instruction follows, however, time even longer. Performs saves vector address fetch.
Time from start interrupt exception processing until fetch first instruction exception service routine starts Interrupt response time Total: Minimum: Maximum:
0.35 0.42 28.7 0.67 0.70 28.7 MHz*
Note: When m1-m4 number states needed following memory accesses. save (longword write) save (longword write) Vector address read (longword read) Fetch first instruction interrupt service routine
Interrupt acceptance
Instruction (instruction replaced interrupt exception processing) Overrun fetch Interrupt service routine start instruction
Instruction fetch (instruction fetched from memory where program stored). Instruction decoding (fetched instruction decoded). Instruction execution (data operation address calculation performed according results decoding). Memory access (data memory accessed).
Figure Pipeline when Interrupt Accepted
Data Transfer with Interrupt Request Signals
following data transfers done using interrupt request signals: Activate DMAC only, without generating interrupt Among interrupt sources, those designated DMAC activating sources masked input INTC. masking condition listed below:
Mask condition (DE0 source selection DE1)
Figure shows control block diagram.
Interrupt source Interrupt source flag clear DMAC) DMAC
Interrupt source (those designated DMAC activating sources) interrupt request
Figure Interrupt Control Block Diagram
6.6.1
Handling DMAC Activating Sources Interrupt Sources
Select DMAC source interrupt sources activating sources masked regardless interrupt priority level register settings register settings. Activating sources applied DMAC when interrupts occur. DMAC clears activating sources time data transfer. 6.6.2 Treating Interrupt Sources DMAC Activating Sources
Either select DMAC source, clear When interrupts occur, interrupt requests sent CPU. clears interrupt source performs necessary processing interrupt processing routine.
Section Cache Memory (CAC)
Overview
on-chip cache memory (CAC) with kbyte cache data 256-entry cache tag. cache data cache space used on-chip space when cache being used. 7.1.1 Features
following features. cache cache data configuration shown figure 7.1. 1-kbyte capacity External memory space DRAM space) instruction code relative data caching entry cache (tag address bits) 4-byte line length Direct replacement algorithm Valid flag bit) included purges
Valid bit) Cache address bits) Cache data Data bits)
address
Entry Offset address address
entries
Data
signal
Figure Cache Cache Data Configuration
7.1.2
Block Diagram
Figure shows block diagram cache.
Cache
Cache controller
Cache data Internal address state controller
Cache
External interface CCR: Cache control register
Figure Cache Block Diagram 7.1.3 Register Configuration
cache register, which used control enabling disabling each cache space. register configuration shown table 7.1. Table
Name Cache control register
Internal data
Register Configuration
Abbreviation Initial Value H'0000* Address H'FFFF8740 Access Size (Bits)
Note: Bits 15-5 undefined.
7.2.1
Register Explanation
Cache Control Register (CCR)
cache control register (CCR) selects cache enable/disable each space. 16-bit readable/writable register. initialized H'0000 power resets, initialized standby mode.
Bit: Initial value: R/W: Bit: Initial value: R/W: DRAM
Note: Bits 15-5 undefined.
Bits 15-5-Reserved: Reading these bits gives undefined values. write value should always 4-DRAM Space Cache Enable (CEDRAM): Selects whether DRAM space cache object (enable) exclude (disable). disables, enables such use.
CEDRAM Description DRAM space cache disabled (initial value) DRAM space cache enabled
3-CS3 Space Cache Enable (CECS3): Selects whether space cache object (enable) exclude (disable). disables, enables such use.
CECS3 Description space cache disabled (initial value) space cache enabled
2-CS2 Space Cache Enable (CECS2): Selects whether space cache object (enable) exclude (disable). disables, enables such use.
CECS2 Description space cache disabled (initial value) space cache enabled
1-CS1 Space Cache Enable (CECS1): Selects whether space cache object (enable) exclude (disable). disables, enables such use.
CECS1 Description space cache disabled (initial value) space cache enabled
0-CS0 Space Cache Enable (CECS0): Selects whether space cache object (enable) exclude (disable). disables, enables such use.
CECS0 Description space cache disabled (initial value) space cache enabled
Address Array Data Array
There special cache space controlling cache. This space divided into address array data array, where addresses (tag address, including valid bit) data (4-byte line length) cache control recorded. special cache space shown table 7.2. used on-chip space when cache being used. Table Special Cache Space
Address H'FFFFF000 H'FFFFF3FF H'FFFFF400 H'FFFFF7FF Size kbyte kbyte Width bits bits
Space Classification Address array Data array
7.3.1
Cache Address Array Read/Write Space
cache address array compulsory read/write (figure 7.3).
Address Entry address bits)
Upper bits address array space address bits) bits) address bits) Valid bit)
bits)
Data
bits)
Figure Cache Address Array Address Array Read: Designates entry address reads corresponding address value/valid value. Address Array Write: Designates entry address writes designated address value/valid value. 7.3.2 Cache Data Array Read/Write Space
cache data array compulsory read/write (figure 7.4).
Address Data Data bits) Upper bits data array space address bits) Entry address bits)
bits)
Figure Cache Data Array Data Array Read: Designates entry address reads corresponding line data. Data Array Write: Designates entry address writes designated data corresponding line.
7.4.1
Cautions
Cache Initialization
Always initialize cache before enabling Specifically, address array write write valid bits entries (256 times), that is,those address range H'FFFFF000- H'FFFFF3FFF. Writes address array data array CPU, DMAC possible while cache enabled. reads, undefined values will read out. 7.4.2 Forced Access Address Array Data Array
While cache enabled, possible write address array data array CPU, DMAC, read will return undefined value. cache must disabled before making forced access address array data array. 7.4.3 Cache Miss Penalty Cache Fill Timing
When cache miss occurs, single idle cycle generated penalty immediately before cache fill (access from external memory event cache miss), shown figure 7.5. However, case consecutive cache misses, idle cycles generated second subsequent cache misses, shown figure 7.6. timing cache fill from normal space, assert period immediately before cycle last cycle when four cycles generated, such word access 8-bit space) extended additional cycle, shown figures 7.6. Similarly, timing cache fill from DRAM space, assert period immediately before cycle extended additional cycle shown figure 7.7. down mode, next cycle delayed cycle shown figure 7.8.
Internal address Address Data Mis-hit Idle cycle Idle cycle Idle cycle assert extension
Figure Cache Fill Timing Case Non-Consecutive Cache Miss from Normal Space Wait, Assert Extension)
Internal address Address Data assert additional extension Miss-hit
Figure Cache Fill Timing Case Consecutive Cache Misses from Normal Space Wait, Assert Extension)
Internal address Address CASx Miss-hit Idle cycle
Idle cycle
COLUMN assert extension Idle cycle
Data
Figure Cache Fill Timing Case Non-Consecutive Cache Miss from DRAM Space (Normal Mode, Wait)
space access
DRAM access
DRAM access
Internal address Address CASx Miss-hit COLUMN Wait space Miss-hit COLUMN assert extension
Data
Figure Cache Fill Timing Case Consecutive Cache Misses from DRAM Space (RAS Down Mode, Wait) 7.4.4 Cache after Cache Miss
first cache after cache miss regarded cache miss, cache fill without idle cycle generation performed. next operates cache hit.
Section State Controller (BSC)
Overview
state controller (BSC) divides address spaces outputs control various types memory. This enables memories like DRAM, SRAM, linked dir
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