AVAILABLE MILITARY SPECIFICATIONS AS8E128K32 ASSIGNMENT

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AVAILABLE MILITARY SPECIFICATIONS AS8E128K32 ASSIGNMENT

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Austin Semiconductor, Inc. 128K EEPROM Memory Array
AVAILABLE MILITARY SPECIFICATIONS
AS8E128K32
ASSIGNMENT
(Top View)
Lead
(Pins connects package)
5962-94585 MIL-STD-883
Access times 120, 140, 150, 200, 250, Built decoupling caps noise operation Organized 128K x32; User configurable 256K 512K Operation with single volt supply power CMOS Compatible Inputs Outputs Operating Temperature Ranges: Military: -55oC +125oC Industrial: -40oC +85oC
FEATURES
Lead
(Pins grounds package)
OPTIONS
MARKINGS
-120 -140 -150 -200 -250 -300 Lead CQFP
Timing Package Ceramic Quad Flat pack Grid Array- Series Grid Array- Series
GENERAL DESCRIPTION
Austin Semiconductor, Inc. AS8E128K32 Megabit EEPROM Module organized 128K bit. User configurable 256K 512Kx module achieves high speed access, power consumption high reliability employing advanced CMOS memory technology. military grade product manufactured compliance MIL-STD 883, making AS8E128K32 ideally suited military space applications. module offered 1.075 inch square ceramic grid array substrate. This package design provides optimum space saving solution boards that accept through hole packaging. module also offered lead 0.990 inch square ceramic quad flat pack. max. height 0.200 inch. This package design targeted those applications which require profile Packaging.
more products information please visit site www.austinsemiconductor.com
AS8E128K32 Rev. 9/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
DEVICE IDENTIFICATION
extra bytes EEPROM memory available each user identification. raising 0.5V using address locations 1FF80H 1FFFFH bytes written read from same manner regular memory array.
AS8E128K32
last byte written will result complement written data presented I/O7. Once write cycle been completed, true data valid outputs, next write cycle begin. DATA Polling begin anytime during write cycle.
TOGGLE DEVICE OPERATION
128K EEPROM memory solution electrically erasable programmable memory module that accessed like Static read write cycle without need external components. device contains 128-byte-page register allow writing bytes data simultaneously. During write cycle, address bytes data internally latched, freeing address data other operations. Following initiation write cycle, device will automatically write latched data using internal control timer. write cycle detected DATA polling I/O7. Once write cycle been detected access read write begin. addition DATA Polling module provides another method determining write cycle. During write operation, successive attempts read data from device will result I/O6 accessed toggling between zero. Once write completed, I/O6 will stop toggling valid data will read. Reading toggle begin time during write cycle.
DATA PROTECTION
precautions taken, inadvertent writes occur during transitions host power supply. module incorporated both hardware software features that will protect memory against inadvertent writes.
READ
memory module accessed like Static RAM. When High, data stored memory location determined address pins asserted outputs. module read bit, device. outputs high impedance state when either high. This dual-line control gives designers flexibility preventing contention their system.
HARDWARE PROTECTION
Hardware features protect against inadvertent writes module following ways: sense below (typical) write function inhibited; power-on delay once reached device will automatically time (typical) before allowing write; write inhibit holding low, high high inhibits write cycles; noise filter pulses less than (typical) inputs will initiate write cycle.
BYTE WRITE
pulse input with (respectively) high initiates write cycle. address latched falling edge WE\, whichever occurs last. data latched first rising edge WE\. Once BWDW (byte, word double word) write been started will automatically time itself completion.
SOFTWARE DATA PROTECTION
software controlled data protection feature been implemented memory module. When enabled, software data protection (SDP), will prevent inadvertent writes. feature enabled disabled user shipped with disabled, enabled host system issuing series three write commands; three specific bytes data written three specific addresses (refer Software Data Protection Algorithm). After writing three byte command sequence after entire module will protected from inadvertent write operations. should noted, that once protected host still perform byte page write module. This done preceding data written same three byte command sequence used enable SDP. Once set, will remain active unless disable command sequence issued. Power transitions disable will protect 128K EEPROM during power-up Power-down conditions. command sequences must conform page write timing specifications. data enable disable command sequences written device memory addresses used sequence written with data either byte page write operation. After setting SDP, attempt write device without three byte command sequence will start internal write timers. data will written device; however, duration tWC, read operations will effectively polling operations.
Austin Semiconductor, Inc. reserves right change products specifications without notice.
PAGE WRITE
page write operation 128K EEPROM allows BWDWs data written into device during single internal programming period. Each BWDW must written within 150-µ (tBLC) previous BWDW. tBLC limit exceeded memory module will cease accepting data commence internal programming operation. each high transition during page write operation, A7-A16 must same. A0-A6 inputs used specify which bytes within page written. bytes loaded order altered within same load period. Only bytes which specified writing will written; unnecessary cycling other bytes within page does occur.
DATA POLLING
This memory module features DATA Polling indicate write cycle. During byte page write cycle attempted read
AS8E128K32 Rev. 9/01
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS* Voltage Supply Relative .-.5V +7.0V Storage Temperature .-65°C +150°C Short Circuit Output Current (per I/O).20mA Voltage Relative Vss.-.5V Vcc+1 Junction Temperature**.+150°C Thermal Resistance junction case (JC): Package Type Q.11.3° Package Type PN.2.8°
AS8E128K32
*Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operation section this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature airflow, humidity (plastics).
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS (-55oC<TA<125oC -40oC +85oC; 10%)
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AS8E128K32 Rev. 9/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
CAPACITANCE TABLE1 (VIN MHz, 25oC)
SYMBOL CADD CWE, PARAMETER Capacitance Capacitance Capacitance Capacitance UNITS
AS8E128K32
NOTE: This parameter guaranteed tested.
TRUTH TABLE
MODE Read Write Standby/Write Write Inhibit Write Inhibit Output Disable High DOUT High
NOTES: Refer Programming Waveforms
TEST CONDITIONS
Current Source
TEST SPECIFICATIONS
Input pulse levels.V Input rise fall times.5ns Input timing reference levels.1.5V Output reference levels.1.5V Output load.See Figure
Device Under Test
1.5V (Bipolar Supply)
Ceff 50pf
Current Source
NOTES: programmable from programmable from typically midpoint VOL. adjusted simulate typical resistive load circuit.
AS8E128K32 Rev. 9/01
Figure
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
AS8E128K32
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS (-55oC +125oC -40oC +85oC; +10%)
DESCRIPTION
Address Output Delay Output Delay Output Delay Output Float Output Hold from OE\, Address, whichever comes first
SYMBOL
UNITS
tACC
READ WAVEFORMS(1,2,3)
ADDRESS
ADDRESS VALID
tACC tACC
OUTPUT VALID
NOTES: delayed tACC-tCE after address transition without impact tACC. delayed tCE-tOE after falling edge without impact tACC-tOE after address change without inpact tACC. specified from whichever occurs first 5pF).
AS8E128K32 Rev. 9/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
AS8E128K32
ELECTRICAL CHARACTERISTICS RECOMMENDED WRITE CHARACTERISTICS (-55oC +125oC; +10%)
Symbol tBLC tWPH Parameter Write Cyce Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High Units
tOES tOES
WRITE CYCLE (Chip Enable Controlled)
tOEH
ADDRESS
ADDRESS VALID
tWPH
DATA VALID
tOES tOES
WRITE CYCLE (Write Enable Controlled)
tOEH tOEH
ttAS
ADDRESS
ttWP tWPH tWPH
AS8E128K32 Rev. 9/01
DATA VALID
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
PAGE MODE CHARACTERISTICS
Symbol
tAS, tOES tDH, tOEH
AS8E128K32
Parameter
Address, Set-Up time Address, Hold time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE\ CE\) Data Set-up Time Data, Hold Time
Unit
PAGE MODE WRITE WAVEFORMS(1,2)
tWPH tWPH
tBLC tBLC
DATA
NOTES:
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE127
through must specify page address during each high transition CE\). must high only when both low. Valid Data Valid Address
CHIP ERASE WAVEFORMS
msec (min.)
msec (min.)
12.0V 0.5V
AS8E128K32 Rev. 9/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
Software Data Protection Enable Algorithm(1)
Load Data Address 5555 Load Data Address 2AAA Load Data Address 5555 Load Data Address(4) Load Last Byte Last Address
AS8E128K32
Software Data Protection Disable Algorithm(1)
Load Data Address 5555 Load Data Address 2AAA Load Data Address 5555 Load Data Address 5555 Load Data Address 5555 Load Data Address(4) Load Last Byte Last Address Exit Data Protect State(3)
Writes Enabled(2)
Enter Data Protect State
NOTES: Data Format: I/O7 I/O0 (Hex); Address Format: (Hex) Write Protect state will active write even other data loaded. Write Protect state will deactivated period even other data loaded. bytes data loaded.
SOFTWARE PROTECTED PROGRAM CYCLE WAVEFORM(1)(2)(3)
A0-A6
tBLC
BYTE ADDRESS
5555
A7-A16
2AAA
5555
PAGE ADDRESS
DATA
BYTE BYTE BYTE
A0-A14 selected bytes must conform addressing sequence first three bytes shown above. After command sequence been issued page write operation follows, page address inputs (A7-A16) selected bytes must same each high transition CE\). Must high only when both low. AS8E128K32 Rev. 9/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
DATA POLLING CHARACTERISTICS(1)
Symbol
tOEH
AS8E128K32
Parameter
Data Hold Time Hold Time Output Delay
Units
Write Recovery Time
NOTES: These parameters characterized 100% tested. Read Characteristics.
DATA POLLING WAVEFORMS
I/O7
tOEH High-Z
TOGGLE CHARACTERISTICS(1)
Symbol
tOEH
Parameter
Data Hold Time Hold Time Output Delay High Pulse Write Recovery Time
Units
tOEPH OEHP
ItCC
NOTES: These parameters characterized 100% tested. Read Characteristics.
TOGGLE WAVEFORMS(1,2,3)
tOEH tOEH
tOEHP
HIGH
NOTES:
Toggling either Both will operate toggle bit. Beginning ending state I/O6 will vary. address location used address should vary.
Austin Semiconductor, Inc. reserves right change products specifications without notice.
AS8E128K32 Rev. 9/01
Austin Semiconductor, Inc.
AS8E128K32
MECHANICAL DEFINITIONS*
Case #703 (Package Designator 5962-94585, Case Outline
DETAIL
DETAIL
SPECIFICATIONS SYMBOL 0.123 0.000 0.013 0.010 0.800 0.870 0.980 0.936 0.050 0.005 0.035 0.045 0.890 1.000 0.956 0.200 0.020 0.017
*All measurements inches.
AS8E128K32 Rev. 9/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
AS8E128K32
MECHANICAL DEFINITIONS*
Case #904 (Package Designator 5962-94585, Case Outline
(identified 0.060 square pad)
SPECIFICATIONS SYMBOL D1/E1 0.135 0.025 0.016 0.045 0.065 1.065 1.000 0.600 0.100 0.132 0.155 0.181 0.035 0.020 0.055 0.075 1.085
*All measurements inches.
AS8E128K32 Rev. 9/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc. ORDERING INFORMATION
EXAMPLE: AS8E128K32Q-250/XT Device Number AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 Package Type Speed -120 -140 -150 -200 -250 -300 Process
AS8E128K32
EXAMPLE: AS8E128K32P-200/883C Device Number AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 Package Type Speed -120 -120 -140 -140 -150 -150 -200 -200 -250 -250 -300 -300 Process
*AVAILABLE PROCESSES Industrial Temperature Range Extended Temperature Range 883C Full Military Processing
-40oC +85oC -55oC +125oC -55oC +125oC
PACKAGE NOTES Pins grounds. Pins connects.
AS8E128K32 Rev. 9/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc. DSCC PART NUMBER CROSS REFERENCE*
Package Designator
Part
AS8E128K32Q-120/883C AS8E128K32Q-120/883C AS8E128K32Q-140/883C AS8E128K32Q-140/883C AS8E128K32Q-150/883C AS8E128K32Q-150/883C AS8E128K32Q-200/883C AS8E128K32Q-200/883C AS8E128K32Q-250/883C AS8E128K32Q-250/883C AS8E128K32Q-300/883C AS8E128K32Q-300/883C
AS8E128K32
Part
5962-9458506HMA 5962-9458506HMC 5962-9458505HMA 5962-9458505HMC 5962-9458504HMA 5962-9458504HMC 5962-9458503HMA 5962-9458503HMC 5962-9458502HMA 5962-9458502HMC 5962-9458501HMA 5962-9458501HMC
Package Designator
Part
AS8E128K32P-120/883C AS8E128K32P-120/883C AS8E128K32P-140/883C AS8E128K32P-140/883C AS8E128K32P-150/883C AS8E128K32P-150/883C AS8E128K32P-200/883C AS8E128K32P-200/883C AS8E128K32P-250/883C AS8E128K32P-250/883C AS8E128K32P-300/883C AS8E128K32P-300/883C AS8E128K32PN-120/883C AS8E128K32PN-120/883C AS8E128K32PN-140/883C AS8E128K32PN-140/883C AS8E128K32PN-150/883C AS8E128K32PN-150/883C AS8E128K32PN-200/883C AS8E128K32PN-200/883C AS8E128K32PN-250/883C AS8E128K32PN-250/883C AS8E128K32PN-300/883C AS8E128K32PN-300/883C
Part
5962-9458506H5A 5962-9458506H5C 5962-9458505H5A 5962-9458505H5C 5962-9458504H5A 5962-9458504H5C 5962-9458503H5A 5962-9458503H5C 5962-9458502H5A 5962-9458502H5C 5962-9458501H5A 5962-9458501H5C 5962-9458506H4A 5962-9458506H4C 5962-9458505H4A 5962-9458505H4C 5962-9458504H4A 5962-9458504H4C 5962-9458503H4A 5962-9458503H4C 5962-9458502H4A 5962-9458502H4C 5962-9458501H4A 5962-9458501H4C
part number reference only. Orders received referencing part number will processed SMD.
AS8E128K32 Rev. 9/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.

AVAILABLE MILITARY SPECIFICATIONS AS8E128K32 ASSIGNMENT

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