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T7531A/T7536 16-Channel Programmable Codec Chip
Serial microcontroller control interface JTAG test port
Single power supply operation Per-channel programmable transmit gain 19.4 range, better than 0.01 steps Per-channel programmable receive gain 25.4 range, better than 0.01 steps Per-channel programmable internal balance networks Programmable termination impedances Per-channel programmable µ-law, A-law, linear output Automatic gain calibration Advanced board- self-test capability Programmable time-slot assignment Data rate 2.048 4.096 Differential transmit amplifiers Single-ended differential receive amplifiers Analog digital loopbacks Sigma-delta converters with dither noise reduction
VRTX T7536 OCTAL
General Description
T7531A custom, 16-channel line card signal processor which, together with pair custom T7536 octal converters, comprises low-cost, highly programmable voice codec that compatible with worldwide POTS lines. Transmit receive gains hybrid balance coefficients programmable channel. Termination impedance programmable chip set. These functions, well time-slot assignment, calibration, board test, controlled microcontroller interface. engine T7531A used test line card. When voice processing required, spare processing time allocated perline basis suite user-controlled board-test routines. Providing intelligent board-test functionality line-card level frees switch from having perform test error diagnosis tasks.
INTERFACE
VRTX T7536 OCTAL
T7531A DIGITAL SIGNAL PROCESSOR
CK16
MICROPROCESSOR INTERFACE
5-3793.c
Figure System Block Diagram
T7531A/T7536 16-Channel Programmable Codec Chip
Table Contents
Contents Page Figures Page
Features General Description. T7536 Description. T7531A Description Information Chip Functional Description Transmit Path. Receive Path. Other Chip Functions. T7531A Functional Blocks Engine Timing. T7531A Program Structure Control Engine Microprocessor Interface Engine Time-Slot Information Tables Engine Path Coefficient Table Time-Slot Control Word Operations Performed Engine T7531A Start-Up Microprocessor Start-Up Engine Powering Time Slot T7531A. Disabling Time Slot T7531A. T7536 Powerup/Powerdown. Changing Space Active Time Slot Engine Memory Requirements T7531A Reset Start-Up. Hardware Reset Internal Reset. Reset T7536 Devices. Start-Up After Internal Reset. Autocalibration User Test Features Self-Test Board-Test Routines. Handling Precautions Absolute Maximum Ratings. Electrical Characteristics Characteristics Transmission Characteristics Timing Characteristics Software Interface Applications Outline Diagram. 68-Pin PLCC Ordering Information.
Figure System Block Diagram Figure Block Diagram T7536 Octal Converter Figure Block Diagram T7536 Analog Channel Figure T7531A Block Diagram Figure T7531A Digital Path Figure Control, PCM, Octal Interfaces Figure T7536 68-Pin PLCC Figure T7531A 68-Pin PLCC Figure Timing Characteristics Interface Assuming 2.048 Rate Figure Timing Diagram Microprocessor Write/Read to/from Control Interface Figure 16-Channel Line Card Solution
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Table Contents
Tables Page
Table T7536 Descriptions Table T7531A Descriptions Table Active Time-Slot Spacing Frame Table Engine Channel_0 Path Coefficients Table Maps Engine Time-Slot Control Word Table Default Per-Board Coefficient Tables Table Engine Time-Slot Information Table Table Summary Microprocessor Commands Control T7531A Data Processing Table Digital Interface Table Analog Interface Table T7536 Power Dissipation Table T7531A Power Dissipation Table Gain Dynamic Range Table Noise (per Channel) Table Distortion Group Delay Table Crosstalk Table Interface Timing Table Serial Control Port Timing Table Engine Memory Table T7531A Time-Slot Assignment Memory Table 20A. T7531A Time-Slot Assignment Registers 0x1400-0x140F Table 20B. Disable Null Channel Table T7531A Channel Register Memory T7536 Device Table T7531A Channel Register Memory T7536 Device Table T7536 Powerup/Powerdown Registers 0x1500-0x1507 0x1540-0x1547 Table T7536 Channel Control Register 0x1508-0x150F 0x1548-0x154F Table T7536 Control Register Transmit Gain Table T7536 Control Register Analog Termination Impedance Table T7536 Control Register Digital Loopback Table T7536 Channel Test Register 0x1510 0x1550 Table Bits T7536 Channel Test Register 0x1510 0x1550 Table T7536 Channel Control Register 0x1518-0x151F 0x1558-0x155F Table T7536 Control Register Receive Gain Table T7531A Control Register Table Bits 15:8 T7531A Board Control Word 0x1FFE Table Bits T7531A Board Control Word 0x1FFE Table Bits 15:9 T7531A Board Control Word 0x1FFC Table Bits T7531A Board Control Word 0x1FFC Table Bits 15:0 T7531A Board Control Word 0x1FFA Table Bits 15:0 T7531A Board Control Word 0x1FF8 Table Bits 15:0 T7531A Board Control Word 0x1FF6 Table Bits 15:0 T7531A Reset Microprocessor Commands 0x7FFF Table Engine Memory
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
General Description (continued)
T7536 Description
T7536 block diagram shown Figure Each eight channels consists antialias filter, sigma-delta converters, reconstruction smoothing filters, termination impedance synthesis, selectable gain. digital oversampled data multiplexed onto serial data port designed interface with T7531A. Another serial interface accepts control data from T7531A activating various gain settings, self-test, powerdown modes. This chip also contains precision voltage reference. packaged 68-pin PLCC.
VTX[7:0] VRTX[7:0] VRP[7:0] VRN[7:0] 8-CHANNEL ANALOG HYBRID TERMINATION
OSDX[1:0] OVERSAMPLED DATA INTERFACE OSDR[1:0] OSCK OSFS
VDDA VSSA VOLTAGE REFERENCE CONTROL INTERFACE
RSTB
5-3794.b
Figure Block Diagram T7536 Octal Converter
DIGITAL LOOPBACK VRTX GAIN AAF* 1.024
GAIN
REFERENCES
GAIN RECEIVE FILTER
1.024
5-3796.d
Antialiasing filter.
Figure Block Diagram T7536 Analog Channel Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
General Description (continued)
T7531A Description
shown Figure T7531A contains digital signal processor (DSP) engine surrounded customized input/output frame. frame performs µ-law A-law conversion well decimation interpolation functions needed interface sigma-delta streams digital signal processor engine. sigmadelta converters operate 1.024 sample rate, while signal processor operates ksamples/s. function frame control timing digital data going signal processor that group delay minimized. frame also contains integrated phase-locked loop which synthesizes required internal clocks chip set. microcontroller interface used download gain balance network settings, powerup/powerdown commands, time-slot assignments, digital loopback settings, commands T7536 octal chips. This chip packaged 68-pin PLCC.
SYSTEM INTERFACE CLOCK SYNTHESIZER DATA TRANSFER µ/A-LAW CONVERTER MICROPROCESSOR CONTROL INTERFACE UPCS UPCK UPDI UPDO HIGHZB RSTB T_SYNC TSTCLK DECIMATOR INTERPOLATOR TEST T7536 OVERSAMPLED INTERFACE T7536 CONTROL INTERFACE
JTAG DIGITAL SIGNAL PROCESSING ENGINE
STSXB
FILT2
FILT1
CK16
FVDD
FVSS
OSCK
OSFS
CCS0
CCS1
OSDX/R[3:0]
5-3795.c (F)r03
Figure T7531A Block Diagram
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
General Description (continued)
T7531A Description (continued)
PCMRX
µ/A-LAW LINEAR
RECV FILTER
INTERPOLATOR
DIGITAL
1.024
BALANCE FILTER
FILTER
PCMTX
LINEAR µ/A-LAW
FILTER
DECIMATOR
1.024
5-3797.b
Figure T7531A Digital Path
OCTAL INTERFACE T7536 T7531A OSFS OSCK OSDR0 OSDR1 OSDX0 OSDX1 CCS0 SYNC CLOCK DATA DATA DATA DATA CHIP SELECT CONTROL REGISTER CONTROL REGISTER OSFS OSCK OSDR0 OSDR1 OSDX0 OSDX1 CCS0 STSXB UPCK UPCS UPDI UPDO
CONTROL INTERFACE
CLOCK CHIP SELECT CONTROL REGISTER CONTROL REGISTER MICROPROCESSOR
CODEC
CLOCK FRAME SYNC DATA RECEIVE DATA TRANSMIT BACKPLANE DRIVER ENABLE
T7536 OSFS OSCK CCS1 OSDR2 OSDR3 OSDX2 OSDX3 CHIP SELECT DATA DATA DATA DATA CCS1 OSDR2 OSDR3 OSDX2 OSDX3
INTERFACE
CODEC
5-4229.b
Figure Control, PCM, Octal Interfaces
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Information
OSDR1 OSDR0 OSDX1 OSDX0
OSCK
OSFS
RSTB
TEST
VTX7
VRTX7 VRP7 VRN7 VSSA VRN6 VRP6 VRTX6 VTX6 VDDA VTX5 VRTX5 VRP5 VRN5 VSSA VRN4 VRP4 VRTX4
VTX0
VDDD
VDDA
VDDA
VSSD
VRTX0 VRP0 VRN0 VSSA VRN1 VRP1 VRTX1 VTX1 VDDA VTX2 VRTX2 VRP2 VRN2 VSSA VRN3 VRP3 VRTX3
T7536
VTX3
VDDA
VSSA
VDDA
VTX4
VDDA
5-4230.b
Figure T7536 68-Pin PLCC
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Information (continued)
TSTCLK
FILT3
FILT2
FILT1
FVDD
FVSS
SCKSEL STSXB UPCK UPCS UPDI UPDO
CK16 TEST HIGHZB RSTB T_SYNC CCS1 CCS0
T7531A
OSCK
OSFS
OSDX0
OSDX1
OSDR3
OSDX3
OSDR1
OSDR0
OSDR2
OSDX2
5-4231.b
Figure T7531A 68-Pin PLCC
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Information (continued)
Table T7536 Descriptions Number Name VTX[7:0] VRTX[7:0] VRP[7:0] VRN[7:0] VDDA Type Name/Function Analog Input. Transmit signal voltage encoded. Transmit Reference Voltage. +2.4 reference. Each must have separate supply associated with corresponding pin. Noninverting Receive Output. This drive high-impedance loads either differentially single ended. complement output. Inverting Receive Output. This drive high-impedance loads either differentially single ended. complement output. Analog Power Supply. Power supply decoupling capacitor (0.1 should connected from each VDDA analog ground. Capacitors should located close possible device pins. Analog Ground. Digital Power Supply. Decouple with capacitor digital ground. Digital Ground. Oversampled Transmit Data. Four channels 1.024 transmit data transmitted T7531A through each these pins. data rate 4.096 MHz. Oversampled Receive Data. Four channels 1.024 receive data received from T7531A each these pins. data rate 4.096 MHz. Interface Clock. 4.096 clock that enters this from T7531A serves clock oversampled data transmission between this chip T7531A. This master clock input T7536. Interface Frame Sync. This signal serves frame sync oversampled data interface between T7536 T7531A. Control Data Interface Input. T7531A sends control register address data T7536 through this pin. address byte data byte accepted each time toggled. Control Data Interface Output. Control register contents clocked through this pin. Control Interface Chip Select (Active-Low). This active-low input enables control interface. Reset (Active-Low). This input must pulled high normal operation. When pulled momentarily least while OSCK active, programmable registers device reset states specified under powerup initialization. This internal pull-up resistor. Test. This factory test purposes only. Connect VDDD normal operation. This internal pull-down resistor. Connect. connection chip. These pins used logic level points.
VSSA VDDD VSSD OSDX[1:0]
OSDR[1:0]
OSCK
OSFS
RSTB
32-37, 39-41
TEST
Note: input, output; CMOS input, CMOS output; analog input, analog output; indicates pull-down device included this lead, indicates pull-up device included this lead.
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Information (continued)
Table T7531A Descriptions Number Name UPDI UPDO UPCK
UPCS
Type
Name/Function Control Data Interface Input. microcontroller sends control register address data T7531A through this pin. Control Data Interface Output. microcontroller receives control register contents from this pin. Inactive state high impedance. Control Data Interface Clock. clock control interface. Speed limited 4.096 MHz. Control Interface Chip Select (Active-Low). This active-low input enables control interface. Oversampled Transmit Data. Four channels Msamples/s transmit data received from T7536 chips through each these pins. data rate 4.096 MHz. Oversampled Receive Data. Four channels Msamples/s receive data transmitted T7536 chips each these pins. data rate 4.096 MHz. 4.096 Clock. Clock data transfer to/from T7536 chips. Oversampling Sync. synchronization pulse data transfer to/from T7536 chips. Filter. External filter clock synthesizer block. Connect resistor series with capacitor ground. Placement these components critical power supply decoupling capacitor placement. Filter. External filter clock synthesizer block. Connect resistor series with capacitor ground. Placement these components critical power supply decoupling capacitor placement. Filter. External filter clock synthesizer's voltage regulator. Connect capacitor ground. Synthesizer VDD. Power supply clock synthesizer block. Synthesizer Ground. Ground connection clock synthesizer block. Backplane Drive Enable (Active-Low). Active when transmitting valid data; high impedance otherwise. This provides enable signal backplane line driver. Master Clock Input. This clock used shift data into pins. input clock synthesizer used generate internal clocks. Rate 4.096 MHz. Master Clock Select Input. logic selects 2.048 SCK. logic high selects 4.096 SCK. internal pull-up device included, providing 4.096 operation with external connections. Receive Input. data this shifted into T7531A falling edges SCK. Data only entered valid time slots defined registers.
OSDX[3:0]
OSDR[3:0]
OSCK OSFS FILT1
FILT2
FILT3 FVDD FVSS
STSXB
SCKSEL
Note: input, output; CMOS input, CMOS output; analog input, analog output; indicates pull-up device included this lead.
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Information (continued)
Table T7531A Descriptions (continued) Number Name Type Name/Function Transmit Output. This remains high-impedance state except during transmit time slots defined registers. Data shifted rising edge SCK. Frame Sync. Active-high pulse square wave with pulse repetition rate. rising edge defines start transmit receive frames. T7536 Control Data Output. Control register information T7536 chips. Data valid only when either CCS0 CCS1 low. T7536 Control Data Input. Control register information from T7536 chips. Data valid only when either CCS0 CCS1 low. internal pull-up device provided. Control Interface Chip Select. These active-low outputs select associated T7536 chips. JTAG Common Test Clock. Rate MHz. JTAG Serial Data Input. pull-up device provided. JTAG Serial Data Output. JTAG Mode Select. pull-up device provided. 3-State Control (Active-Low). When pulled low, device output pins into high-impedance state. pull-up device provided. Test Mode Input (Active-Low). This input allows bypass clock synthesizer uses TSTCLK drive chip. pull-up device provided. Clock Output. clock output (50% duty cycle). Test Clock. Test mode 98.304 clock input bypass clock synthesizer. Connect. make connections these pins. Test Sync (Active-Low). Used factory testing. make connection this pin. pull-up device provided. Reset (Active-Low). logic initiates reset. pull-up device provided. Digital Power Supply. Power supply decoupling capacitors (0.1 should connected from each ground. Capacitors should located close possible device pins. Digital Ground.
CCS[1:0]
HIGHZB TEST
CK16 TSTCLK
T_SYNC RSTB
Note: input, output; CMOS input, CMOS output; analog input, analog output; indicates that pull-up device included this lead.
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
gain equalization. case transmit gain, this level found (3.2 V/log (3.15/20)) 2.23 Vp-p. This level worst-case dBm0 level. Decimator decimator filters high-frequency components down-samples kHz. also reorders channels transmit signals into sequence that determined time-slot assignment. Digital Transmit Gain Adjustment transmit absolute relative gains specified 15-bit binary numbers representing their linear magnitude. These gains default 4000 Hex. This equates gain relative gain equates 1.65 gain absolute gain. gain, program absolute gain 34ED Hex. Gain varied from minus infinity (off) (0000 Hex) relative gain 7.65 absolute gain (7FFF Hex). relative gain control allows adjustment without hybrid balance termination coefficient modification. Band Filtering bandpass filter transmit path removes power line ringing frequencies, eliminates most signal energy above. This allows encoder transmit filtered signal ksamples/s, worldwide standard. transmit filtering implemented with low-pass filter, followed high-pass filter. data samples enter filter ksamples/s. They first low-pass filtered kHz. After low-pass filtering, sampling rate reduced ksamples/s. samples then high-pass filtered low-pass filter also serves equalizer complex termination impedance cases. given equalizer coefficients that modify this filter required each complex termination impedance. These supplied user manual. µ-Law, A-Law, Linear Modes transmit path, ksamples/s signal output from filter processed prior transmission over system interface. 16-bit linear signal compressed according either µ-law A-law, transmitted consecutive 8-bit words. selection programmable microprocessor interface. Please note, when using A-law, linear value always encoded Lucent Technologies Inc.
Chip Functional Description
Transmit Path
Antialias Filter Converter line interface circuit must provide transmit signal, VTX, reference voltage, VRTX, which voltage signal that channel. input signal goes into programmable-gain amplifier. signal then passed through antialias filter followed converter. converter operates 1.024 MHz. processed output signals multiplexed into groups four channels each onto output pins OSDX[1:0], each which operates 4.096 MHz. precision, on-chip voltage reference helps ensure accurate highly stable transmission levels. important understand difference between gain levels should T7536 these levels would standard codec. T7536 best thought data acquisition system, codec. Hybrid balance, fine gain adjust, A-law coding, filtering, equalization done after T7536 processor T7531A. analog gain adjust taps should used absolute level output. This done using gain adjust taps. analog taps should signal input converter close possible full-scale input level largest signal level that will present input. This optimizes dynamic range A/D. gain should thus used maximum signal level range between 2.25 Vp-p Vp-p. should used signals with maximum signal level range between Vp-p 2.25 Vp-p. should used signals with maximum signal level range between Vp-p Vp-p. Higher gain levels should used signals with smaller absolute levels. signal level produce dBm0 level digital transmit output T7531A fixed quantity explained above. line with complex impedance echo signal, extra headroom must allowed signal level must account headroom. this specification, largest possible dBm0 level signal assumed. This guarantees that distortion specification will exceeded practical signal levels. largest possible signal that headroom
T7531A/T7536 16-Channel Programmable Codec Chip Other Chip Functions
Voltage Reference T7536 precision on-chip voltage reference which ensures accurate highly stable transmission levels. Hybrid Balance hybrid balance function provided digital block T7531A. T7531A implements 9-tap single-pole digital balance filter which replica echo digitally subtracted from transmit plus near-end echo signal. coefficients user programmable per-line basis microprocessor interface. Analog Termination Impedance Synthesis Termination impedance matching implemented maximize power transfer capability loop interface minimize signal reflections between transmit receive paths. resistive component, implemented T7536 device, comprises variable attenuated path between capacitive component imple. mented digital domain. Analog termination impedance (ATI) provided with gain settings match voltage drive/current sense line interface circuit with following characteristics: where termination impedance ohms, 82.5 resistance each protection resistor, SLIC transmit gain (300 L7585), SLIC receive gain L7585), T7536 feedback gain. polarity gain positive (positive voltage swing gives positive voltage swing VRP). gain values corresponding effective termination impedance shown Table gain tolerances ±2%. Differential receive output assumed.
Chip Functional Description
(continued)
Receive Path
receive direction, signal received from system interface converted 16-bit linear signal. Receive Path Filtering 16-bit linear signal filtered interpolated ksamples/s meet receive signal loss characteristics. This filter smooths data following interpolation from ksamples/s ksamples/s. Digital Receive Gain receive absolute relative gains specified 15-bit binary numbers representing their linear magnitude. These gains default 4000 Hex. This equates gain relative gain equates -0.211 gain absolute gain. gain, program absolute gain 4193 Hex. Gain varied from minus infinity (0000 Hex) relative gain absolute gain (7FFF Hex). relative gain control allows adjustment without hybrid balance termination coefficient modification. Interpolator Digital Sigma-Delta Modulator sampling frequency receive signal from digital gain adjustment increased from interpolator, which removes most high-frequency signal images above kHz. interpolator also maps each time slots appropriate line channel through digital sigma-delta modulator. digital sigma-delta modulator converts interpolated signal 1.024 stream which then sent T7536 device. Decoder, Filters, Receive Amplifier Receive data enters T7536 pins OSDR[1:0] 4.096 MHz; four channels time-division multiplexed onto each pin. data demultiplexed into eight individual channels. processed signal each channel passes through switched-capacitor reconstruct filters, followed smoothing filter. programmable gain amplifier included, followed output amplifier capable driving load ±1.58 single-ended (relative VOS) ±3.16 differential peak overload. single-ended operation, load must coupled VRN).
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
back mode used check T7536 functionality from T7531A device. also used during calibration sequence. There loopback mode T7531A. Loopback oversampled data interface controlled board control word This mode allows T7531A test itself. When 0x1FFE selected, channels octal interface receive data (OSDRn) looped back T7531A transmit inputs (OSDXn). Interchip Control Interface control interface 4-pin interface used send control information T7536 from T7531A, read back control register contents. pins consist chip select input (CCS0/CCS1), data input (CDI), data output (CDO). transfer control data synchronous with 4.096 OSCK, which also used oversampled data transfer.
Chip Functional Description
(continued)
Other Chip Functions (continued)
Digital Termination Impedance Synthesis filter T7531A synthesizes complex termination impedances. filter utilizes alpha beta coefficients (board control words respectively) perform synthesis. alpha beta coefficients required each termination impedance balance network. These provided user manual. Alpha bits [9:0] represent time constant impedance that filter going synthesize. bits formatted two's complement. Alpha bits must nonzero value. Beta bits [7:0] represent gain filter. Beta coefficients also formatted two's complement. Setting beta equal zero turns function. There constraint value protection resistor with regard termination impedance synthesis hybrid balance. synthesis operate properly, total series Tip/Ring resistance must greater. Coefficients with L7585 SLIC protection value resistance 82.5 82.5 Ring. Loopback Modes There four loopback modes T7536. first loopback modes controlled channel test (ACT) register. bits place eight channels into loopback mode. Analog digital loopback described shown block diagram form Table Analog loopback allows check functionality from Tip/Ring including T7536. Digital loopback allows T7531A check T7536 functionality. third loopback mode used autocalibration sequence (control register This mode provides loopback between selected channel channel four given T7536. channel calibrated selected control register (see Table 27). Channel four only channel T7536 that trimmed gain accuracy. Every other channel uses channel four reference calibrated during autocalibration sequence. fourth loopback mode digital loopback mode located control register This operates like digital loopback mode described notes register (Table 29). Unlike register, this digital loopback mode selectable channel. This loop14
T7531A Functional Blocks
Clock Synthesizer clock synthesizer block phase-lock loop (PLL) circuit which takes supplied backplane uses produce 98.304 engine clock. input clock, SCK, 2.048 4.096 MHz. on-chip clock synthesizer advantages shown below:
Precludes need extra clocks over backplane. Constrains high-speed engine clock within device. Synchronizes clocks used line card backplane clock, thus reducing board noise beat frequencies.
clock generator block takes output divides down produce lower-frequency clocks used T7531A T7536. T7531A System Interface system interface full-duplex interface used exchange data with system. system master this bus. control information transmitted over system interface; control instructions routed over microprocessor interface.
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
T7531A Microprocessor Interface This interface between microprocessor other external controller) T7531A device carries user-supplied program variables control test instructions both T7531A T7536 octal converters. external device master microprocessor interface. interface serial asynchronous, consists four pins (UPCK, UPCS, UPDI, UPDO). data rate determined customer's choice external device, exceed 4.096 MHz. Microprocessor interface commands consist words, address data. Address data bits wide. T7531A expects address first. first address word flag, which tells T7531A whether must receive send data (receive, send, Addresses less than 0x1400 refer engine space. read from engine required, microprocessor interface issues read interrupt engine. it's write engine, microprocessor interface shifts data word saves into data register before sending write interrupt engine. Once every time segment, engine checks whether interrupt outstanding from microprocessor interface block. engine reads address register. it's read, engine fetches word from RAM, places data register, shifts microprocessor. it's write, puts contents data register into RAM. pause therefore exists between external controller issuing address receiving data read back. data rate 2.048 allows cycles frame, i.e., eight address/data pairs with pause between words. Since engine process only interrupt every T7531A requires separation between address data read write instructions microprocessor interrupt (see Figure 10). This, effect, requires UPCK gapped.
Chip Functional Description
(continued)
T7531A Functional Blocks (continued)
system interface used lines serviced T7531A. data rate ksamples/s/line, total required channel capacity Kwords/s each direction. 4.096 rate, each word takes 1.95 transmit interleaved with 5.86 dead time. frame sync, SFS, presented system interface rate. single clock frame sync used control both transmit receive directions. beginning first time slot frame identified from input (see Figure nondelayed mode, active coincident with time slot frame (and frame programmed offset between delayed mode, active cycle earlier. amount skew offset between transmit receive frames time slots programmable board control word 0x1FFC. offset frame, i.e., bits mode. Table listing invalid offset values. offset skew takes place system interface block. active transmit receive time slots determined card address. number time slots within frame varies according rate SCK. Only time slots ever active frame, shown Table T7531A obtains card address board control word 0x1FFE. µ-law A-law mode, each word only bits long occupies time slot. linear mode, word bits long occupies adjacent time slots. first clocked valid time slot, last following (invalid) time slot.
Table Active Time-Slot Spacing Frame Rate (MHz) 2.048 4.096 Total Time Slots Card Address Valid Time Slots Invalid Time Slots 1-3, 5-7, 61-63 2-4, 6-8, 62-63 0-1, 3-5, 7-9, 0-2, 4-6, 8-10, 60-62
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
write locations start-up ensure proper operation. Twice frame, state machine reads entire from bottom sequence sends contents each location interpolator channel numbers channels. state machine performs same procedure decimator provide with channel numbers. performing oversampled sigma-delta rate, round trip group delay significantly minimized.
Chip Functional Description
(continued)
T7531A Functional Blocks (continued)
Addresses 0x1400 refer registers external engine. address word from microprocessor 0x1400 through 0x140F, activates state machine. address word from microprocessor 0x1500 through 0x15FF, activates T7536 control state machine. Microprocessor data address words flushed T7531A addressing 0x7FFF with data word 0xFFFF (see Table 40). T7536 Octal Control Interface T7536 chips cannot accessed microcontroller directly; T7536's registers accessed T7531A microprocessor interface. microprocessor communicates serially with T7536 simply writing reading 16-bit address 16-bit data. octal control interface block translates this address data into 8-bit address 8-bit data needed T7536. octal control interface block waits until microprocessor interface block receives bits address word determines whether this read write operation looking this write operation T7536 chip, receives another 16-bit data word. T7531A Time-Slot Assignment (TSA) block contains dual-port which readable writable microprocessor interface. Table gives words. time-slot order, i.e., location 0x1400 time slot 0x1401 time slot bits (B3-B0) indicate which possible channel numbers assigned this time slot. time-slot assignment controlled microprocessor writing address 0x1400 through 0x140F. block also generates control signals flags used synchronize TSA, interpolator decimator, T7536 interface blocks. preinitialized, microprocessor required
Engine Timing
engine processes lines every frame. order simplify synchronization data exchanges, processing frame broken into equal time segments each. code identical each time segment. Synchronization between engine rest chip enforced system interface block, which issues interrupt every This interrupt only unmasked interrupt processed engine. interrupt service routine forces code branch start processing loop.
T7531A Program Structure
engine firmware performs three types operations: Signal processing path data. accesses initiated microprocessor interface. Data program flow operations. signal processing algorithms performed T7531A implemented firmware held ROM. Many firmware parameters user programmable microprocessor interface. Interrupts from microprocessor interface handled once every time segment (7.8 µs), appropriate accesses made engine registers.
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip Engine Path Coefficient Table
microprocessor interface control coefficients, shown Table engine contains space hold separate sets coefficients each channel, labeled channel_0 through channel_15. coefficients held channel order, since they hold information that channel specific does change with time slot (see Table 18). Table shows path coefficient space channel_0. Table Engine Channel_0 Path Coefficients Address rgain_rel_0 Reserved rgain_abs_0 tgain_abs_0 bf_coef_0 Reserved tgain_rel_0 Purpose path relative gain path absolute gain path absolute gain Balance filter coefficients path relative gain Number Initial Words Value (4000 (4000 (4000 initialized (4000
Chip Functional Description
(continued)
Control Engine Microprocessor Interface
There four types commands that external controlling device issue engine: Downloading data RAM. Activating deactivating lines. Changing routine run. Periodic read and/or refresh space. these commands must only involve reading writing that engine does have perform test- branch-type operations when microprocessor interface command received. complete memory engine given Table microprocessor interface allowed read location engine write specified addresses.
Engine Time-Slot Information Tables
T7531A, engine been contain tables which hold pointers coefficients data buffers required process each time slot. Each table starts 32-word boundary accessed firmware using direct addressing instructions. Each table part part (see Table 18). tables labeled through time-slot order, i.e., table used when processing data time slot Time-slot number vary between used conjunction with card address provide time-slot positions (see Table
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Data Sheet February 1999 Operations Performed Engine T7531A Start-Up
engine performs start-up code after been reset. interrupts disabled. First, engine computes checksum verify their integrity. Next, engine walks through each time-slot information table sets data buffer coefficient pointers. engine channel-order time-slot assignment, i.e., table points channel_0 start-up settings Time-Slot Information Table (i.e., time slot shown Table first locations bank hold channel address table, where pointers start coefficient space each channel held. These pointers during start-up routine. Pointers three sets default coefficients also engine then walks through coefficient tables sets them their initial values shown previous section. filter coefficients (one lines) taken from written their locations. engine takes about execute startup code. code, interrupt system enabled engine enters sleep mode.
Chip Functional Description
(continued)
Time-Slot Control Word
engine works time-slot order. function performed decimator/interpolator. engine required reorder data way. advantages this approach that group delay introduced function very small, code needed context switching small. When microprocessor assigns time slot RAM, also issue time-slot control word (TCW) instruction engine enable time slot link correct coefficients. contains information shown Tables only looked when time slot inactive. initial setup TCWs assumes channel-order time-slot assignment.
Table Maps Engine Time-Slot Control Word Register Function Channel Number Powerup Modify Coefficients Default Per-Board Coefficient Tables Initial Value channel_(time-slot number)
Table Default Per-Board Coefficient Tables Mode Select Default Tables Default Table Coefficient Default Table Coefficient Default Table Coefficient
Table Engine Time-Slot Information Table Variable tcw_0 rx_rtn_0 tx_rtn_0 data storage Function Time-slot Control Word Address Receive Routine Address Transmit Routine Reserved Initialized Address above rpath_inactive tpath_inactive
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T7531A/T7536 16-Channel Programmable Codec Chip
dynamic time-slot assignment used, microprocessor must next download command, which block uses time slot required channel number. microprocessor must enable time slot setting powerup TCW. This causes engine change routine addresses active. maximum commands minimum command therefore needed power channel.
Chip Functional Description
(continued)
Microprocessor Start-Up Engine
Once interrupt system enabled, engine looks read write interrupt from microprocessor interface once every time segment, i.e., times frame. coefficients every channel independently controlled, microprocessor write directly addresses coefficient tables. This requires total microprocessor commands each channel, i.e., frames channels. Prior activating time slots, microprocessor option bulk downloading coefficients coefficient tables. When channel needs linked time slot, microprocessor must send that time slot with modify coefficient (MC) (see Table 5A). causes inactive routine that time slot pointers from that time-slot space channel space RAM. also causes inactive routine check default coefficient bits TCW. set, appropriate default table coefficients copied over space channel. This mechanism allows microprocessor download coefficients that used multiple channels. mix-and-match approach used, i.e., some channels with independent sets coefficients, while other channels default setting. During start-up, microprocessor must also download commands used block physical channels time slots. This required initialize known values. When locations have been microprocessor must send BCW2 (0x1FFC). This flags control start normal operation.
Disabling Time Slot T7531A
disable time slot, microprocessor must send command that sets address either routine TX_inactive RX_inactive, respectively. inactive routines come into next time segment this time slot. Upon returning from inactive routine, engine checks microprocessor interrupt then enters sleep mode rest time segment.
T7536 Powerup/Powerdown
Each channel powered independently. There control register addresses that used control power each channel. both cases, first address word controls power. powerup, powerdown. address provided each channel which controls power (0x1508-0x150F 0x1548- 0x154F), address followed data word which controls other programmable functions same channel. second address (0x1500- 0x1507 0x1540-0x1547) provided each channel that controls only power.
Powering Time Slot T7531A
Depending application, microprocessor choose coefficients channel just prior enabling use. This requires microprocessor commands coefficients must from scratch, commands appropriate default already been either case, microprocessor must ensure that parts channel prior enabling time slot. Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Data Sheet February 1999 T7531A Reset Start-Up
chips support both hardware software reset.
Chip Functional Description
(continued)
Changing Space Active Time Slot
microprocessor only allowed change four locations active time slot:
Hardware Reset
T7531A reset functions handled reset control block. Hardware reset occurs board powered with RSTB low. Since RSTB Schmitt trigger buffer with internal pull-up, capacitor attached external RSTB causes pull high after specified period time. power-on reset, T7531A requires that this period time give on-chip clock synthesizer block time start producing clock edges T7531A T7536 chips (although have reached final accuracy yet). Successful hardware reset device requires that: signals should valid start power-on reset period. (and therefore RSTB) should have been least prior commencing power-on reset ensure that JTAG controller powerup reset circuit time clear JTAG controller. during normal operation, falls below defined minimum value, min, power-on reset procedure described above must repeated. Hardware reset occurs RSTB pulsed high-low-high during normal operation (i.e., loss power).
Relative transmit gain Relative receive gain Address receive routine Address transmit routine
Absolute gains time-slot assignment only altered when time slot inactive. Note that engine does check active time slots. Following initial powerup, line card likely service without being reset long continues operate trouble-free. Therefore, microprocessor option continuously monitoring variables programmed reading them back from engine/microprocessor interface rewriting them.
Engine Memory Requirements
size engine internal dual-port 16-bit words engine. storage used user-programmable variables intermediate storage data being processed device. memory given Table on-chip used both program data. engine firmware based. hardware development system code also based. engine memory given Table
Table Summary Microprocessor Commands Control T7531A Data Processing Function Required Number Commands Bulk register download BCW2 Individual register download Coefficient download channel use/share coefficients already downloaded default tables Enable time slot (fixed TSA) Enable time slot (dynamic TSA) Disable time slot Change gain value gain When Issued Start-up Prior activating time slot Start-up when time slot inactive Start-up when time slot inactive When time slot inactive When time slot inactive When time slot active time
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip Start-Up After Internal Reset
There specific sequence microprocessor interface instructions that must followed after internal reset order properly configure T7531A T7536s normal operation. nondefault values required, T7531A board control word (address 0x1FFE) must updated. locations must written before 0x1FFC. must disabled (see Table 20B). channel test register must normal operation (addresses 0x1510 0x1550 0x0004). T7531A control registers must set. channels must powered (addresses 0x1500-0x1507 0x1540-0x1547 must 0x8000). amplitude calibration sine wave must writing address 0x0580 coefficient 0xAA20, address 0x0581 coefficient 0xF49D. channels must into initialization mode (addresses 0x1518-0x151F 0x1558-0x155F must 0x0080). engine address 0x0002 must 0x0700 begin first part T7536 calibration start-up sequence. After T7536 channels must into loopback mode (addresses 0x1508-0x151F 0x1548-0x154F must 0x8001). engine address 0x0002 must 0x0720 begin second part T7536 calibration start-up sequence. After both T7536s should sent soft reset (addresses 0x1517 0x1557 0x8000) channel test register should normal operation (addresses 0x1510 0x1550 0x0004). Normal T7531A operation commences with next frame sync. chips ready channels enabled filter coefficients set.
Chip Functional Description
(continued)
Internal Reset
Internal reset defined process that starts when internal reset line brought low. This happens consequence hardware (RTSB) software (BCW1) reset. internal reset process performs following functions: frequency synthesizer does receive reset signal, thus unaffected reset. Following power-on reset T7531A, frequency synthesizer takes mode determined SCKSEL pin. T7531A custom logic jams resettable latches, counters, registers their default values. data latched T7531A interfaces during internal reset. engine held reset state. internal reset line held minimum allow frequency synthesizer reach final accuracy. internal counter started when internal reset line goes low. counts frame sync pulses before releasing internal reset line. When internal reset line goes high (internal) signal held low, engine begins start-up routine fetching first instruction from location internal ROM. rising edge internal reset line, T7531A custom logic blocks commence their normal operation.
Reset T7536 Devices
There options reset T7536 chips. T7536s make same hardware reset pulse T7531A. T7531A supplies OSCK T7536s soon available, i.e., before hardware reset gone away. recommended that hardware reset applied chips simultaneously. Alternatively, T7536s reset through software reset (Tables 22), which generated external controlling device routed T7536s T7531A. This only occur when OSCK guaranteed valid, i.e., within power-on hardware reset.
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Off-Line Programmable System Test Capability T7531A standard 4-pin test access port known JTAG that used testing debugging. user option downloading custom firmware engine JTAG port, running engine place normal ROM-based code. DSP16 hardware development tool provides powerful user interface real-time code development debug. user also execute self-test routine which exercises significant portions T7531A T7536 devices. On-Line Per-Channel Test Capability addition active (i.e., normal voice processing functions) inactive routines, user select routines listed Table altering routines address time-slot information table (see Table Inactive Mode with Loopback This pair routines that used parts channel. Data from looped back without modification SDX.
Chip Functional Description
(continued)
Autocalibration
Autocalibration analog self-test trimming procedure controlled core. Sine wave signals generated receive direction. These signals looped back analog side T7536, return signal amplitudes measured transmit path. This procedure provides on-the-spot fault coverage transmit receive paths. also calibrates octal devices modifying gain each channel. Channel four T7536 only channel trimmed factory absolute gain accuracy. When autocalibration run, channels trimmed with reference channel four. That gain each channel adjusted that absolute gain equivalent that trimmed channel. Performing trimming this manner provides channel-tochannel gain matching better than 0.01 This much better performance than could achieved using conventional trimming. Trimmed values placed data storage, absolute gain values then modified accordingly time absolute gain register changed. calibration sequence measures looped-back power result compares calibrated channel. trim window ±0.2 channel exhibits power value which greater than ±0.2 calibration procedure sets failure flag that channel. Trimming will performed failed channel, channel's trimmed gain will left failed channel, therefore, left previous state still used. results calibration held address 0x07F4 transmit (pass 0x07F5 receive (pass high every failed channel. preceding section discussed sequence instructions that must followed order properly configure T7531A normal operation. autocalibration procedure mandatory after hardware reset.
Self-Test Board-Test Routines
Using following routines, programs written test only codec function also attached circuitry, like SLIC, relays, protection devices, cabling. Tone Generation tone generation mode, part channel used send sine wave signal line. sine wave frequency, 1024 points long. filter implemented tone generation.
User Test This section outlines T7531A test features architecture. more information board-test capabilities, T7531A/T7536 User Manual.
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T7531A/T7536 16-Channel Programmable Codec Chip
Peak Detection This routine examines incoming signal saves maximum minimum signal values.
Chip Functional Description
(continued)
Self-Test Board-Test Routines
(continued) Tone Detection tone detection mode, part channel used detect signal energy from line given frequency kHz. This routine performs discrete Fourier transform (DFT) capture analyze reflected tone. routine does employ transmit bandpass filters. number frames sample reflected tone must defined. number frames that must power should complete cycles tone value. Generation This routine generates signal (value defined user) path. Variance Computation variance routine computes variance small noise signals from path around computed mean level. This routine employs transmit bandpass filters out-of-band noise reduction.
Handling Precautions
Although protection circuitry been designed into this device, proper precautions should taken avoid exposure electrostatic discharge (ESD) during handling mounting. Lucent Technologies employs human-body model (HBM) charged-device model (CDM) ESD-susceptibility testing protection design evaluation. voltage thresholds dependent circuit parameters used define model. industry-wide standard been adopted CDM. standard (resistance 1500 capacitance widely accepted used comparison. threshold presented here obtained using these circuit parameters: Threshold Device Voltage T7531A >1000 T7536 >1000
Absolute Maximum Ratings
Stresses excess absolute maximum ratings cause permanent damage device. These absolute stress ratings only. Functional operation device implied these other conditions excess those given operational section data sheet. Exposure absolute maximum ratings extended periods adversely affect device reliability. Parameter Ambient Operating Temperature Operating Junction Temperature Thermal Resistance, Junction Case Storage Temperature Range Power Supply Voltage Voltage with Respect Ground Package Power Dissipation Symbol Tstg 4.75 -0.25 5.25 5.25 Unit °C/W
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Electrical Characteristics
specifications: unless otherwise noted. Typical values Input signal frequency 1020 unless otherwise noted.
Characteristics
Table Digital Interface Parameter Input Voltage Output Voltage Symbol VOHC High High High High High Test Conditions TTL-compatible inputs TTL-compatible inputs -320 UPDO, UPDO, -120 Unit
Input Current
Pins Without Pull-up Pull-down Pins with Pull-up Pins with Pull-down
Output Current High-impedance State Table Analog Interface
Parameter Symbol Input Resistance RVTX Input Resistance RVRTX (dependent setting termination impedance) Common-mode Reference Voltage VVRTX Input Sink Current IVRTX Input Voltage Swing VVTX Load Resistance (differential) Load Capacitance Output Resistance Output Offset Voltage Between Output Offset Voltage Between VRN, Powerdown Output Voltage Swing (differential) VOSPD VRSW
Test Conditions 0.25 4.75 VRTX
Unit
VRTX from VSSA Digital input code corresponding code 1.02 Digital pattern corresponding idle code (µ-law) Channel powered down load differential maximum receive gain
-100 5.28
Vp-p Vp-p
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T7531A/T7536 16-Channel Programmable Codec Chip
Electrical Characteristics (continued)
Characteristics (continued)
Table T7536 Power Dissipation Parameter Powerdown Current Powerup Current Symbol Test Conditions IDD0 OSCK OSFS present, channels powered down IDD1 OSCK OSFS present, channels powered normal operation Unit
Table T7531A Power Dissipation Parameter Powerdown Current Powerup Current Symbol IDD0 IDD1 Test Conditions present, channels powered down inactive present, channels powered active 175* Unit
Powerup current exhibits negative temperature coefficient.
Transmission Characteristics
Table Gain Dynamic Range Parameter Absolute Levels Symbol Test Conditions Maximum dBm0 levels (1.02 kHz): (encoder milliwatt) (T7536 gain T7531A gain -1.65 VRP-VRN (decoder milliwatt) (T7536 gain 6.02 T7531A gain 0.21 Termination impedance Minimum dBm0 levels (1.02 kHz): (T7536 gain =12.04 T7531A gain -1.65 VRP-VRN (T7536 gain -12.04 T7531A gain 0.21 Termination impedance Transmit gain programmed maximum dBm0 test level, measured deviation digital code from ideal dBm0 level OSDX[1:0] digital outputs, with transmit gain Measured transmit gain over range from maximum minimum, calculated deviation from programmed gain relative 2.23 4.38 Unit Vp-p Vp-p
557.0 548.0
mVp-p mVp-p
Transmit Gain Absolute Accuracy
-0.25 -0.30
0.25 0.30
Transmit Gain Variation with Programmed Gain
GXAG
-0.1
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T7531A/T7536 16-Channel Programmable Codec Chip
Transmission Characteristics (continued)
Table Gain Dynamic Range (continued) Parameter Symbol Test Conditions Transmit Gain Variation GXAF Relative 1016 minimum gain with Frequency maximum gain, dBm0 signal, path gain 16.67 3000 3140 3380 3860 4600 above Transmit Gain Variation GXAL Sinusoidal test method reference with Signal Level level dBm0: dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 Receive Gain Absolute Receive gain programmed apply Accuracy dBm0 oversampled data OSDR0 OSDR1, measure VRP, differential: Relative Gain: Digital input dBm0 signal 3400 Relative Phase: Digital input dBm0 signal 3400 Receive Gain Variation GRAG Measure receive gain over range from maximum minimum setting, calculated with Programmed deviation from programmed gain relative Gain Receive Gain Variation GRAF Relative 1016 digital input dBm0 with Frequency code, minimum gain maximum gain: path gain below 3000 3140 3380 3860 4600 above Receive Gain Variation GRAL Sinusoidal test method, reference with Signal Level level dBm0: OSDR dBm0 dBm0 OSDR dBm0 dBm0 Relative Termination Impedance Gain Unit
-0.5 -1.8 -0.125 ±0.04 0.125 0.01 0.125 -0.57 -0.735 -0.550 0.015 -9.9 -8.98
-0.25 -0.50 -1.4
0.25 0.50
-0.25 -0.30 -0.01 -0.25 -0.1
0.25 0.30 0.01 0.25
-0.125 ±0.04 0.125 ±0.04 0.125 -0.57 -0.735 -0.550 0.015 -10.7 -8.98
-0.25 -0.50 -0.2
0.25 0.50
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T7531A/T7536 16-Channel Programmable Codec Chip
Transmission Characteristics (continued)
Table Noise (per Channel) Parameter Symbol Test Conditions transmit gain Transmit Noise, C-message Weighted Transmit Noise, transmit gain P-message Weighted receive gain, digital pattern correReceive Noise, sponding idle code, µ-law C-message Weighted Receive Noise, receive gain, digital pattern correP-message Weighted sponding idle code, µ-law Noise, Single Frequency kHz, loop around measurement, Vrms mVrms Power Supply Rejection, PSRX Transmit kHz* C-message weighted Power Supply Rejection, PSRR Measured Receive mVrms Digital pattern corresponding idle code, µ-law, C-message weighted Spurious Out-of-band dBm0, 3400 input Signals Channel oversampled data code applied OSDR0 Outputs OSDR1): 4600 7600 7600 8400 8400
Measured with dBm0 activation signal applied VFXI input channel under test.
Unit dBrnC0 dBm0p dBrnC0 dBm0p dBm0
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Transmission Characteristics (continued)
Table Distortion Group Delay Parameter Signal Total Distortion Transmit Receive C-message Weighted Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion Group Delay, Absolute Group Delay, Absolute
Varies function offset.
Symbol STDX STDR SFDX
SFDR
Test Conditions Sinusoidal test method level: dBm0 dBm0 dBm0 single frequency input, 3400 measure other single frequency dBm0 single frequency input, 3400 measure other single frequency Transmit receive, frequencies range (300 3400 1600 4.096 MHz, offset 1600
Unit
250*
Table Crosstalk Parameter Transmit Transmit Crosstalk, dBm0 Level Transmit Receive Crosstalk, dBm0 Level Receive Transmit Crosstalk, dBm0 Level Receive Receive Crosstalk, dBm0 Level Symbol CTX-X CTX-R Test Conditions 3400 channel channel 3400 channel other channel In-channel 3400 channel other channel In-channel 3400 channel channel Unit
CTR-X
CTR-R
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T7531A/T7536 16-Channel Programmable Codec Chip
Timing Characteristics
signal valid above below invalid between VIH. purposes this specification, following conditions apply:
input signals defined measured from VIH. measured from VIL. Delay times measured from input signal valid output signal valid. Setup times measured from data input valid clock input invalid. Hold times measured from clock signal valid data input invalid. Pulse widths measured from from VIH.
Table Interface Timing (See Figure Symbol fSCK Parameter Frequency (Selection frequency pin-strap programmable.) Period Jitter Period High Period Rise Time Fall Time Period High Test Conditions 2.048 4.096 1/fSCK 62.5 62.5 Unit
tSCK tSCHSCL tSCLSCH tSCH1SCH2 tSCL2SCL1 tFSHFSL
Measured from
tSFHSCL tSCLSFL tSCHDXV tDRVSCL tSCLDRX
Frame Sync High Setup Frame Sync Hold Time Data Enabled Entry Receive Data Setup Receive Data Hold
Measured from Measured from Measured from Measured from Measured from VIL: 2.048 0.488 4.096 0.244 CLOAD
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T7531A/T7536 16-Channel Programmable Codec Chip
Timing Characteristics (continued)
TIME SLOT tSFHSCL tSCLSFL tFSHFSL
TIME SLOT
tSCHSCL
tSCHDXV SDX* tDRVSCL tSCLDRX
tSCLSCH
5-4233.a
Card address offset assumed. Card address assumed. Notes: position frame sync pulse delayed mode. position frame sync pulse nondelayed mode.
Figure Timing Characteristics Interface Assuming 2.048 Rate
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Timing Characteristics (continued)
Table Serial Control Port Timing (See Figure 10.) Symbol tCSHLSET tCSLHHOD tUPDIST tUPDIHD tUPDODEL tUPDOHZDL tCKCSH Parameter
UPCS UPCK Setup UPCS UPCK Hold
Test Conditions
UPCK Period/2
Unit
tCKCSH1
UPDI UPCK Setup UPDI UPCK Hold UPCK UPDO Delay UPCS UPDO High-Z Duration UPCK UPCS High: Write Cycle Read Cycle Duration UPCK UPCS High
tCKCSH UPCK tCSHLSET UPCS tUPDIST tUPDIHD UPDI 13-2 tUPDIHD DATA bits) tUPDODEL HIGH-Z STATE UPDO 13-1 DATA bits)
5-4232a
tCSLHHOD tCKCSH1
13-1
ADDRESS
ADDRESS bits)
tUPDOHZDL
Notes: UPDI UPCS change rising edge UPCK microprocessor sampled falling edge UPCK UPDO changes rising edge UPCK sampled falling edge UPCK microprocessor.
Figure Timing Diagram Microprocessor Write/Read to/from Control Interface
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Software Interface
Table lists data space engine. Space channels allocated. total T7531A size Kwords, arranged Kbanks. Address used read/write flag read). microprocessor interface read address engine space. Table Engine Memory Address Range Bank 0x0000 0x00011 0x00021 0x0003-0x003F 0x00402 0x0080 0x00C0 0x0100 0x0140 0x0180 0x01C0 0x0200 0x0240 0x0280 0x02C0 0x0300 0x0340 0x0380 0x03C0 Bank 0x0400-0x040F 0x0410-0x0413 0x0414-0x0434 0x0435 0x0436 0x0437 0x0438 0x0439-0x0442 0x0443 0x0444 Memory Contents Write Microprocessor Interface Time-Slot Information Tables (See page 17.) Time-slot control word (time slot Receive routine address (time slot Transmit routine address (time slot Data storage (time slot Selected locations Time slot information table shown time slot Time slot information table shown time slot Time slot information table shown time slot Time slot information table shown time slot Time slot information table shown time slot Time slot information table shown time slot Time slot information table shown time slot Time slot information table shown time slot Time slot information table shown time slot Time slot information table shown time slot Time slot information table shown time slot Time slot information table shown time slot Time slot information table shown time slot Time slot information table shown time slot Time slot information table shown time slot Coefficient Reference Tables (See page 16.) Channel coefficient address table Default coefficient address table Reserved Per-Channel Coefficients (See page 16.) Receive path relative gain (channel Data storage (channel Receive path absolute gain (channel Transmit path absolute gain (channel Balance filter coefficients (channel Data storage (channel Transmit path relative gain (channel
receive transmit routine addresses only addresses that address code. time slots 1-15, address shown first address. Refer time slot range information.
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T7531A/T7536 16-Channel Programmable Codec Chip
Software Interface (continued)
Table Engine Memory (continued) Address Range 0x0445 0x0455 0x0465 0x0475 0x0485 0x0495 0x04A5 0x04B5 0x04C5 0x04D5 0x04E5 0x04F5 0x0505 0x0515 0x0525
Memory Contents Channel filter coefficients Channel filter coefficients Channel filter coefficients Channel filter coefficients Channel filter coefficients Channel filter coefficients Channel filter coefficients Channel filter coefficients Channel filter coefficients Channel filter coefficients Channel filter coefficients Channel filter coefficients Channel filter coefficients Channel filter coefficients Channel filter coefficients Per-Board4 Coefficients Receive filter coefficients Transmit (equalizer) filter coefficients Transmit gain coefficients filter compensation Unused
Write Microprocessor Interface shown channel shown channel shown channel shown channel shown channel shown channel shown channel shown channel shown channel shown channel shown channel shown channel shown channel shown channel shown channel
0x0535-0x053E 0x053F-0x0552 0x0553 0x0554-0x0560 0x0561 0x0562 0x0563 0x0564-0x056D 0x056E 0x056F-0x057C 0x057D-0x05EE 0x05EF-0x07EF 0x07F0 0x07F2 0x07F4 0x07F5 0x07F6
Default Per-Board4 Coefficient Tables Default Table receive path relative gain Default Table receive path absolute gain Default Table transmit path absolute gain Default Table balance filter coefficients Default Table transmit path relative gain Default Table coefficient Self-Test Flags Temporary storage self-test routines Unused Result checksum test Result checksum test Result path self-test Result path self-test code version number
receive transmit routine addresses only addresses that address code. time slots 1-15, address shown first address. Refer time slot range information. channels 1-15, address shown first address. Refer channel range information. Per-board refers function that common channels single chip set.
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T7531A/T7536 16-Channel Programmable Codec Chip
Software Interface (continued)
Table T7531A Time-Slot Assignment Memory registers written microprocessor interface. Address Range 0x1400 0x1401 0x1402 0x1403 0x1404 0x1405 0x1406 0x1407 0x1408 0x1409 0x140A 0x140B 0x140C 0x140D 0x140E 0x140F Memory Contents Time slot channel assignment Time slot channel assignment Time slot channel assignment Time slot channel assignment Time slot channel assignment Time slot channel assignment Time slot channel assignment Time slot channel assignment Time slot channel assignment Time slot channel assignment Time slot channel assignment Time slot channel assignment Time slot channel assignment Time slot channel assignment Time slot channel assignment Time slot channel assignment
Table 20A. T7531A Time-Slot Assignment Registers 0x1400-0x140F 15-6 used disable Number Function Null channel Binary-coded channel number 0-15
Table 20B. Disable Null Channel
Notes: Don't care. Bits default upon reset.
Function Disables null pointer Nulls channel Enables Disables
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T7531A/T7536 16-Channel Programmable Codec Chip
Software Interface (continued)
Table T7531A Channel Register Memory T7536 Device registers written microprocessor interface. Address Range 0x1500 0x1501 0x1502 0x1503 0x1504 0x1505 0x1506 0x1507 0x1508 0x1509 0x150A 0x150B 0x150C 0x150D 0x150E 0x150F 0x1510 0x1517 0x1518 0x1519 0x151A 0x151B 0x151C 0x151D 0x151E 0x151F Memory Contents Channel powerup/powerdown register Channel powerup/powerdown register Channel powerup/powerdown register Channel powerup/powerdown register Channel powerup/powerdown register Channel powerup/powerdown register Channel powerup/powerdown register Channel powerup/powerdown register Channel control register Channel control register Channel control register Channel control register Channel control register Channel control register Channel control register Channel control register channel test register Single-byte soft reset data word) Channel control register Channel control register Channel control register Channel control register Channel control register Channel control register Channel control register Channel control register Table T7531A Channel Register Memory T7536 Device registers written microprocessor interface. Address Range 0x1540 0x1541 0x1542 0x1543 0x1544 0x1545 0x1546 0x1547 0x1548 0x1549 0x154A 0x154B 0x154C 0x154D 0x154E 0x154F 0x1550 0x1557 0x1558 0x1559 0x155A 0x155B 0x155C 0x155D 0x155E 0x155F Memory Contents Channel powerup/powerdown register Channel powerup/powerdown register Channel powerup/powerdown register Channel powerup/powerdown register Channel powerup/powerdown register Channel powerup/powerdown register Channel powerup/powerdown register Channel powerup/powerdown register Channel control register Channel control register Channel control register Channel control register Channel control register Channel control register Channel control register Channel control register channel test register Single-byte soft reset data word) Channel control register Channel control register Channel control register Channel control register Channel control register Channel control register Channel control register Channel control register
Table T7536 Powerup/Powerdown Registers 0x1500-0x1507 0x1540-0x1547 Number Function 14-0 used
Notes: powerdown. powerup-normal operation.
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T7531A/T7536 16-Channel Programmable Codec Chip
Software Interface (continued)
Table T7536 Channel Control Register 0x1508-0x150F 0x1548-0x154F 14-8 used Number Function gain Termination impedance LPBK
Table T7536 Control Register Transmit Gain TXGAIN2 TXGAIN1 TXGAIN0 Mode transmit gain 3.01 transmit gain 6.02 transmit gain 9.03 transmit gain 12.04 transmit gain 12.04 transmit gain 12.04 transmit gain 12.04 transmit gain
Table T7536 Control Register Analog Termination Impedance Gain (See equation page 12.) 0.0000 0.0583 0.1417 0.2250 0.3083 0.3917 0.5000 0.5583 0.6417 0.7083 0.8083 0.8917 0.9750 1.0583 1.2167 2.0000 Analog Termination Impedance 165* 1365
This value equivalent protection resistor value multiplied
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T7531A/T7536 16-Channel Programmable Codec Chip
Software Interface (continued)
Table T7536 Control Register Digital Loopback LPBK Mode Normal operation Digital loopback
Table T7536 Channel Test Register 0x1510 0x1550 Number Function 15-4 used Read address Reserved Analog loopback Digital loopback
Table Bits T7536 Channel Test Register 0x1510 0x1550 Number Normal operation Read address Reserved Normal operation Normal operation Analog loopback Normal operation Digital loopback Function
Notes: Read address provides previous read write address whenever address being written into register. When analog loopback high, data that enters analog transmit path (VTX) converted 1.024 digital stream routed back analog receive path (VRP VRN). output transmit path available oversampled data interface, receive path over, sampled data ignored.
A/D,
OVERSAMPLED DATA INTERFACE
OSDX OSDR
5-5134
When digital loopback high, oversampled data receive (OSDR) routed oversampled data transmit (OSDX). receive signal propagated VRN/VRP transmit signal from disconnected. reference voltage VRTX still required this mode.
A/D,
OVERSAMPLED DATA INTERFACE
OSDX OSDR
5-5135
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T7531A/T7536 16-Channel Programmable Codec Chip
Software Interface (continued)
Table T7536 Channel Control Register 0x1518-0x151F 0x1558-0x155F 15-8 used SUSEQ Number Function used Receive gain
Notes: SUSEQ normal operation. SUSEQ start-up calibration sequence.
Table T7536 Control Register Receive Gain RXGAIN2 RXGAIN1 RXGAIN0 Mode Levels, Termination Impedance 6.02 receive gain 3.01 receive gain receive gain -3.01 receive gain -6.02 receive gain -9.03 receive gain -12.04 receive gain -12.04 receive gain
Table T7531A Control Register Address Range 0x1FFE 0x1FFC 0x1FFA 0x1FF8 0x1FF6 Register Contents Board control word Board control word Board control word Board control word Board control word Write Microprocessor Interface
Note: board control word controls function that common channels given chip set.
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T7531A/T7536 16-Channel Programmable Codec Chip
Software Interface (continued)
Table Bits 15:8 T7531A Board Control Word 0x1FFE Number Function Normal operation Soft reset Normal operation test mode Normal operation dither circuit Normal operation Nodecim test mode Normal operation Linear mode
Table Bits T7531A Board Control Word 0x1FFE Number Function Delayed data timing Nondelayed data timing µ-law A-law, including even inversion A-law, even inversion C1C0 card address binary Reserved Normal operation Normal operation Loopback
Notes: bits board control register will zeros upon hardware reset. loopback mode, OSDR0, OSDR1, OSDR2, OSDR3 looped back with delay OSCLK clock cycles OSDX0, OSDX1, OSDX2, OSDX3, respectively. Test modes production testing only. µ-law/A-law companding mode provides bits data with first (bit defined last (bit LSB. sign bit, bits through chord bits, bits through interval bits. linear mode, µ-law/A-law conversion interface block disabled bits linear data provided. linear mode, sign bit, bits through intervals, bits insignificant. Each interval represents 0.0001362745 Vrms with 8031 intervals being maximum signal output dBm0. Negative values two's complement positive values. don't care.
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Software Interface (continued)
Table Bits 15:9 T7531A Board Control Word 0x1FFC Number Function 15-9 used Table Bits T7531A Board Control Word 0x1FFC BOF8 BOF7 BOF6 Number BOF5-3 Function BOF2 BOF1 BOF0 BOF8-0 offset binary*
following offset values valid should used: When using 2.048 SCK: offset 112, 128, 144, 160, 176, 192, 208, 224, 240. When using 4.096 SCK: offset 128, 160, 192, 224, 256, 288, 320, 352, 384, 416, 448, 480. Note: Bits through used; assumed zeros. BOF[8:0] provide fixed offset, relative frame synchronization strobe (SFS), first transmitted each time slot. offset number data periods which transmission first delayed. subsequent transmissions also follow this offset. default value after hardware reset powerup 1A3; however, this register must still written after reset.
Table Bits 15:0 T7531A Board Control Word 0x1FFA Number Function 15-5 used test bits
Note: test only, normal operation. default value after hardware reset powerup
Table Bits 15:0 T7531A Board Control Word 0x1FF8 Number Function 15-10 used alpha coefficients
Note: default value after hardware reset powerup
Table Bits 15:0 T7531A Board Control Word 0x1FF6 Number Function 15-8 used
Note: default value after hardware reset powerup
beta coefficients
Table Bits 15:0 T7531A Reset Microprocessor Commands 0x7FFF Number Function Clear address data words T7531A
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Software Interface (continued)
Table shows memory engine ROM. information accessible microprocessor. total size Kwords. Table Engine Memory Address Range 0x0003 0x0008 0x000B 0x0380 0x03B0 0x03B8 0x0400 0x0500 0x0600 0x0610 0x0680 0x0690 0x0700 0x0720 0x07A0 0x0860 0x0A80 0x0B00 0x0B60 0x0B80 0x0C00 0x0E00 0x0F00 0x0F10 0x0F20 0x0F30 0x0F40 0x0F60 0x0FFE 0x0FFF Memory Contents interrupt service routine Time-slot sync interrupt service routine Start-up routine Time segment controller (ts_proc) Reserved Reserved Transmit path active routine Receive path active routine Transmit path inactive/loopback routine Transmit path inactive routine Receive path inactive/loopback routine Receive path inactive routine Self-test pass setup (TX) Self-test pass setup (RX) Tone generation start-up Tone detection start-up Variance calculation Peak detection generation checker checker Variance calculation with filters Simultaneous start-up tone generator routine Simultaneous start-up tone generator original variance routine Routine places halves time slot into inactive loopback Places halves time slot into inactive routine Routine copying values channel coefficient table 16-channel tables Approximate location code Checksum 0x0000 0x07FF Checksum 0x0800 0x0FFD
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
4.096 rate. microprocessor control interface standard 4-wire serial port connection, microprocessor clock (UPCK), chip select (UPCS), data input (UPDI), output (UPDO). T7531A generates clock microprocessor use. This clock always present. interface consists system clock (SCK) input either 2.048 4.096 MHz, system frame sync (SFS) input, system data transmit port (DX), system data receive (DR) port. Other than power supply decoupling, only external components required codec chip resistors three capacitors. These required internal clock synthesizer filter circuit T7531A. clock synthesizer generates 98.304 master clock use.
Applications
Figure shows full line card implementation using T7531A/T7536 codec L7585 SLIC with integrated relays. T7531A T7536 devices support SLIC devices (only L7585 SLIC illustrated). Figure portrays only transmission paths inside L7585 SLIC. L7585 functionality includes eight solid-state relays, performing ring, test, break functions, ring-trip detector, quiet polarity reversal, operating states, more. complete functionality this SLIC, refer L7585 data sheet. analog connection between SLIC codec direct; external components required. transfer control data octal interface between T7531A T7536 devices also direct. Data synchronous with OSCK transmits
VBAT BGND VCCA AGND SLIC DGND L7585 VCCD RELAY TRNG RRNG RRTF CRTF DCOUT
FB1* 0.047
FB2* 0.047
0.22 OCTAL INTERFACE OSFS OSFS OSCK OSCK OSDR0 OSDR0 OSDR1 OSDR1 OSDX0 OSDX0 OSDX1 OSDX1 CCS0 CCS0 CONTROL INTERFACE UPCK UPCS UPDI UPDO CK16 SCKSEL RSTB STSXB INTERFACE CCS1 OSDR2 OSDR3 OSDX2 OSDX3 FILT1 FILT2 FILT3 FVSS RSTB MICROPROCESSOR
RINGING
VDDA
RING 82.5 TEST-IN
RCVP VRTX
VRP0 VTX0 VRTX0 CHANNELS
SURGE PROTECTOR
CODEC T7536
VITR
CLOCK
RGX1 8.25
NDET
TEST VDDD TEST
VDDD
VSSD
VSSA
82.5
RPROG 64.9 IPROG RLCTH 24.9 LCTH CHANNEL VRN0 RCVN
FVDD
RSTB RSTB RSTB OSFS OSCK CCS1 OSDR2 VSSD OSDR3 OSDX2 OSDX3
T7531A
PARALLEL DATA MICROPROCESSOR CHANNELS 8-15
VDDA
CODEC T7536
VDDD
VSSA
12-3351.d
Optional quiet reverse battery. 4.096 operation; 2.048 operation, SCKSEL VSS.
Figure 16-Channel Line Card Solution Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Outline Diagram
68-Pin PLCC
Dimensions millimeters. controlling dimensions inches. Note: dimensions this outline diagram intended informational purposes only. detailed schematics assist your design efforts, please contact your Lucent Technologies Sales Representative.
25.146 0.127 24.231 0.102 IDENTIFIER ZONE
24.231 0.102 25.146 0.127
5.080 SEATING PLANE 0.10 1.27 0.330/0.533 0.51 MIN,
5-2139.r13
Lucent Technologies Inc.
T7531A/T7536 16-Channel Programmable Codec Chip
Ordering Information
Device Code T-7531A T-7531A ML-TR T-7536 T-7536 ML-TR Package 68-Pin PLCC 68-Pin PLCC 68-Pin PLCC 68-Pin PLCC Temperature Comcode 107529729 107578627 107393993 107412041
additional information, contact your Microelectronics Group Account Manager following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: AMERICA: Microelectronics Group, Lucent Technologies Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Fong Universe Building, 1800 Zhong Shan Road, Shanghai 200233 China Tel. (86) 6440 0468, ext. 316, (86) 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 299, (44) 1189 Technical Inquiries: GERMANY: (49) 95086 (Munich), UNITED KINGDOM: (44) 1344 (Ascot), FRANCE: (33) (Paris), SWEDEN: (46) (Stockholm), FINLAND: (358) 4354 2800 (Helsinki), ITALY: (39) 6608131 (Milan), SPAIN: (34) 1441 (Madrid)
Lucent Technologies Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. rights under patent accompany sale such product(s) information.
Copyright 1999 Lucent Technologies Inc. Rights Reserved
February 1999 DS99-093ALC (Replaces DS98-272ALC)
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