Integrated clock recovery data retiming Surface-mount package Single s
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LG1600KXH Clock Data Regenerator
Integrated clock recovery data retiming Surface-mount package Single supply Robust FPLL design Operation 1e-3 SONET/SDH compatible loss signal alarm High effective allows long lengths Jitter tolerance exceeding ITU-T/Bellcore clock jitter generation: <0.005 Standard custom data rates 0.50 Gbits/s-5.5 Gbits/s Complementary I/Os
Figure LG1600KXH Open View
Applications
SONET/SDH receiver terminals regenerators OC-12 through OC-96/STM-4 through STM-32 SONET/SDH test equipment Proprietary rate systems Digital video transmission Clock doublers quadruplers
LG1600KXH Clock Data Regenerator
Regenerated clock data available from complementary outputs that either coupled, provide output match, coupled with ground receiving end. second-order filter bandwidth user with external resistor between ground (required). internal capacitor provides sufficient damping most applications. critical applications, damping increased using external capacitor between pins device powered single -5.2 compatible supply typically consumes LG1600KXH comes standard rates, factory tuned rate between Mbits/s 5500 Mbits/s. test fixture (TF1004A) with connectors available allow quick evaluation LG1600KXH.
Functional Description
LG1600KXH Clock Data Regenerator (CDR) compact, single device solution clock recovery data retiming high-speed communication systems such fiber-optic data links long-span fiberoptic regenerators terminals. Using frequency phase-lock loop (FPLL) techniques, device regenerates clean clock error-free data signals from nonreturn-to-zero (NRZ) data input, corrupted jitter intersymbol interference. LG1600KXH exceeds ITU-T/Bellcore jitter tolerance requirements SONET/SDH systems. device houses integrated circuits alumina substrate inside hermetically sealed (1.2 in.) surface-mount package: GaAs that contains high-speed part FPLL well highly sensitive decision circuit; silicon bipolar that contains loop filter, acquisition, signal detect circuitry. ac-coupled complementary data inputs driven differentially well single ended. feedback voltage V-FB maintains data input threshold V-TH (decision level) that optimum wide range duty cycle input levels (connect V-TH). needed, user supply external threshold compensate different mark densities distorted input signals (see Figure 10).
Theory Operation
digital regenerator task retransmitting stream that received from remote source with same fidelity which originally transmitted. basic properties digital signal need restored: timing transitions between bits value each bit.
V-TH
V-FB
V+OUT V-OUT
0.047
0.047
V-IN V+IN
0.047
V+CLKO V-CLKO
0.047
0.047 FREQ. PHASE DETECT.
V+FB
LOOP CONTROL SIGNAL DETECT 0.047 VREF CEXT REXT
12-3225(F)r.5
Figure LG1600KXH Block Diagram Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Theory Operation (continued)
FLIP-FLOP
Consequently, timing information that present data needs extracted decision value each must made. Both timing instant decision levels critical, since economics data transmission dictate largest distance possible between transmitter receiver. practically closed data therefore expected output receiver, allowing only small decision window. added complication nonreturn-to-zero (NRZ) systems absence clock component data signal itself. Practical clock recovery circuits have used combination nonlinear processing extract spectral component clock frequency narrowband filtering using filter dielectric resonator. relative bandwidth such filter must order tenths percent minimize data pattern dependence resulting clock. Temperature behavior passband characteristics, such group delay, must tightly matched that data path. These extreme requirements make such discrete design very difficult manufacture Gbits/s data rates. LG1600KXH clock data regenerator relies phase-lock loop techniques, rather than passive filtering. filter properties determined frequencies where parasitic elements play only minor roll stability easily maintained. Furthermore, reference frequency determined data rate itself, rather than physical properties bandpass filter. Although PLLs eliminate some shortcomings passive bandpass filters used clock recovery circuits, care taken design LG1600KXH preserve desired properties such linearity jitter characteristics. linear jitter transfer makes easier system designer predict overall performance link. result, architecture chosen device basically different from conventional clock recovery circuit. transition detector extracts pulse train from incoming data signal which used reference signal PLL. transition pulse train seen clock signal that modulated with instantaneous transition density data signal. locks onto frequency phase this pulse train freewheels during times when transitions absent. LG1600KXH features dual phase detectors; driven in-phase clock which also driving decision circuit flip-flop, other driven quadrature clock. phase detectors produce zero output when their respective clocks centered with respect transition pulses. Lucent Technologies Inc.
DATA CIRCULATOR
TRANSITION PULSE
FROM
DELAYED DATA STUB LOGIC
12-3226(F)r.3
Figure Frequency Phase Detector transition pulse half width period, timing diagram Figure shows in-phase clock ends center data when quadrature-phase detector output forced zero loop. (patented) transition detector comprised (active) circulator, shorted stub, exclusive-OR gate. circulator/stub combination produces delayed version data. transition input circuit results output pulse from exclusive-OR gate whose width equals return delay stub. stub tuned given rate adjusted that in-phase clock exactly centered error-free phase range retiming flip-flop.
DATA
DELAYED DATA
TRANSITION PULSE
CLOCK
CLOCK
12-3227(F)r.2
Figure Timing Diagram
LG1600KXH Clock Data Regenerator
Theory Operation (continued)
TIME
-360°
-180°
180°
360° PHASE
TIME
12-3228(C)r.4
Figure Frequency Phase Detector Characteristics frequency detector separate function integral part phase-lock loop. transition between frequency phase acquisition completely avoided. Figure shows output characteristics FPD, which essentially extended range phase detector. quadrature clock phases used produce hysteresis, which extends phase detector range ±270°. extended range gives phase detector static frequency sensitivity demonstrated Figure clock frequencies lower than rate (the phase increasing), trajectory diagram Figure followed. When frequency exceeds rate, lower trajectory applies. Since linear part phase detector produces netzero output, first instance, positive pulses into loop filter increasing frequency, while latter case, produces negative pulses. wide, 540° range phase detector also responsible high jitter tolerance LG1600KXH associated immunity cycle slip under high jitter conditions. clock momentarily misaligned much 270° still return original position. This property extremely important synchronous systems, since cycle slip would cause misalignment demultiplexer following circuit resulting loss frame condition. LG1600KXH handle error rates 1e-3 result lowfrequency jitter.
12-3229(C)r.3
Figure Frequency Detector Operation
Dimensioning
LG1600KXH employs heavily damped second-order phase-lock loop. linear model this depicted Figure conventional secondorder equation describing jitter transfer shown below: where denote input output phase, respectively, damping ratio natural frequency. most clock recovery applications very high damping required that renders essentially first-order system with slight peaking that generally undesirable. second-order equation above does provide much insight into peaking bandwidth parameters.
PHASE DETECTOR INTERNAL EXTERNAL LOOP FILTER CAPACITANCE
12-3230(F)r.4
Figure Phase-Lock Loop Linear Model
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
moderate damping, 0.1), bandwidth approximated loop gain pole product: KdRxKo while jitter peaking expressed terms product bandwidth loop filter time constant: last expressions make clear, bandwidth controlled value external resistor (see Figure while peaking depends both resistor value (quadratically) total loop filter capacitance.
Theory Operation (continued)
more useful expression characteristics following*: jitter transfer directly expressed physical loop gain pole product, loop filter time constant, Damping ratio, natural frequency, simply relate these parameters follows:
Wolaver, D.H., Phase-Locked Loop Circuit Design, Prentice Hall, 1991.
(MHz)
(MHz)
LG1600KXH0622 0.15
LG1600KXH2488
12-3231(F)r.3-12-3232(F)r.3
Figure Jitter Bandwidth External Resistor Value
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Information
pinout LG1600KXH shown Figure
V+FB V+IN V-IN
VREF CEXT REXT
V-TH V-FB V+OUT V-OUT
V-CLKO V+CLKO
12-3233(F)r.1
Figure Diagram
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Information (continued)
descriptions LG1600KXH given Table Table Descriptions Symbol VREF CEXT REXT Name/Description Connect. Internal test point reserved future use. Reference Voltage. Nominally -3.2 used bias LG1605DXB (see data sheet). Load Terminal optional external capacitor increase damping (normally connected). Terminal external resistor bandwidth (REQUIRED). Loss Signal Indicator. Provides approximately sink current with data signal present, interface CMOS, when connected logic through resistor. Normally grounded when used. Recovered Clock Out. couple terminate into GND. Recovered Clock Out. couple terminate into GND. Supply Voltage. -5.2 nominal. Warning: Connecting positive voltage this will permanently damage device. Regenerated Data Out. couple terminate into GND. Regenerated Data Out. couple terminate into GND. Feedback Voltage. Connect V-TH. Input Threshold Voltage. Connect V-FB. Negative Data Input. Internally coupled. Positive Data Input. Internally coupled. Feedback Voltage. Internally connected; normally used. Internal Connection. grounded. Ground. Connect ground plane coplanar/microstrip circuit board.
V-CLKO V+CLKO
Body
V-OUT V+OUT V-FB V-TH V-IN V+IN V+FB
Ground. Does need connected. pins provide necessary ground connections.
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Absolute Maximum Ratings
Stresses excess absolute maximum ratings cause permanent latent damage device. These absolute stress ratings only. Functional operation device implied these other conditions excess those given operational sections data sheet. Exposure absolute maximum ratings extended periods adversely affect device reliability. Table Absolute Maximum Ratings Parameter Supply Voltage Range (VSS) Loss Signal Bias Voltage (VDD) Power Dissipation Voltage (all pins) Transient Voltage Couple Pins (V±IN, REXT) Storage Temperature Range Operating Temperature Range Unit
Recommended Operating Conditions
Table Recommended Operating Conditions Parameter Case Temperature Power Supply Symbol tCASE -4.7 -5.7 Unit
Handling Precautions
Although protection circuitry been designed into this device, proper precautions should taken avoid exposure electrostatic discharge (ESD) during handling mounting. Lucent Technologies Microelectronics Group employs human-body model (HBM) ESD-susceptibility testing protection design evaluation. (resistance 1500 capacitance used. threshold presented Table obtained using these circuit parameters. Table Threshold Threshold Device LG1600KXH Voltage
Mounting Connections
Certain precautions must taken when using solder. installation using constant temperature solder, temperatures under employed periods time seconds, maximum. installation with soldering iron (battery operated nonswitching only), soldering temperature should greater than soldering time each lead must exceed seconds.
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Electrical Characteristics
tCASE -4.7 -5.7 rate Gbits/s ±0.05% data pattern PRBS, V±IN 1e-9, unless otherwise indicated. Note: Minimum maximum values testing requirements. Typical values characteristics device result engineering evaluations. Typical values information purposes only part testing requirements. Parameter Symbol Conditions Data Input Voltage V-IN Single ended either input Data Input Voltage V+IN V-IN Differential Data Output Voltage V±OUT Clock Output Voltage V±CLKO Output Pulse Width RelaPW% tCASE tive Period 1/fB Clock Output Duty Cycle DCCLKO tCASE Clock/Data Output Transitr, tion Time Maximum Error Rate BERMAX Jitter modulation kHz, tCASE Output Voltage, VLOSL Output Voltage, High VLOSH V-IN Loss Signal Delay Jitter Generation Jitter Transfer Bandwidth Output Reference Voltage Jitter Tolerance JGEN VREF JTOL Measured from last data transition, tCASE User adjustable with suggested Figure tCASE Load ground fmod kHz, tCASE fmod kHz, tCASE fmod kHz, tCASE Measured from first data transition*, tCASE -5.7 -4.7 1e-3 -3.4 fmod 0.15 -0.8 0.0025 -3.15 fB/fmod 1600 1000 1000 0.005 -2.9 Unit mVp-p mVp-p mVp-p mVp-p
Acquisition/Recovery Time Supply Current
Parameter guaranteed design characterization production tested.
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Test Circuit
ALTERNATIVE V-TH
OPTIONAL THRESHOLD CONTROL
OPTIONAL µF/fB
V-FB
V+OUT
V-OUT
0.047
0.047
OPTIONAL pF/fB V+CLKO V-CLKO
V-IN V+FB V+IN
0.047 0.047
0.047
FREQ. PHASE DETECT.
DATA GENERATOR
LOOP CONTROL SIGNAL DETECT 0.047 VREF CEXT REXT VLOS OPTIONAL (SEE TEXT) REQUIRED
12-3234(F)r.4
Notes: Resistor determines bandwidth required normal operation. recommended value optimal jitter transfer performance. Capacitor optional used increase damping critical applications. outputs either coupled, indicated, terminated into first case, good output return loss obtained. latter configuration provides -800 output swing easy interface dc-coupled circuits.
Figure LG1600KXH Typical Test Circuit
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Typical Performance Characteristics
LG1600KXH0553
LG1600KXH2488
LG1600KXH4977
Figure LG1600KXH Typical Patterns
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Typical Performance Characteristics (continued)
V±OUT
V+CLKO
OUTPUT TIMING
OUTPUT TIMING (ps)
1/4x
-100 1000 PERIOD (ps)
12-3235(F)r.2
1500
2000
Figure Data Clock Output Timing Diagram
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Typical Performance Characteristics (continued)
BLANKING PULSE INPUT DATA OUTPUT DATA ERROR SIGNAL
ERROR RECOVERY TIME
1000 INPUT BLANKING (µs)
12-3236(F)r.3
RECOVERY TIME (µs)
Figure Error Recovery Timing Diagram
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Typical Performance Characteristics (continued)
DATA BLNK PATTERN GENERATOR DATA DATA MIXER DATA ERROR DETECTOR DIGITIZING OSCILLOSCOPE
PULSE GENERATOR TRIG
OSCILLOSCOPE
12-3237(F)r.4
Figure Error Recovery Test Circuit
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Outline Diagram
68-Pin Surface-Mount Package
Dimensions inches.
1.180 0.590
0.050
R0.020 0.158 0.015 0.010+0.005 -0.002 0.030 DETAIL 0-5°
1.370 0.10
0.010
DETAIL
12-3350(F).a
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Ordering Information
Device Code LG1600KXH0622 LG1600KXH1244 LG1600KXH1250 LG1600KXH1298 LG1600KXH2380 LG1600KXH2488 LG1600KXH2666 TF1004A Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Surface-Mount Package Test Fixture Temperature Comcode 108418583 108418591 108418609 108418625 108418617 108193087 108418575 106497621
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Appendix
test fixture mentioned data sheet sold separately described detail below.
5-7831(F)
Figure TF1004A Test Fixture
TF1004A Test Fixture
connectors Easy package placement Good performance
Test Fixture Functional Description
TF1004A test fixture used characterize 68-pin surface-mount packages high-speed fiber-optic communications. fixture consists metallized substrate (PTFE filled material) fastened brass base with connectors mounting hardware package. package leads make contact circuit traces fixture through pressure ring four finger nuts. TF1004A preassembled fully tested prior shipment.
Before Test Fixture
possible stress during shipment, connectors misaligned. Check each continuity. necessary, realign retighten with 5/64 wrench.
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Appendix (continued)
Instructions Test Fixture
pair flat-tip tweezers used insert remove package from test fixture. Always wear grounding strap prevent ESD. insert package, remove four finger nuts gently lift pressure ring test fixture. Place pressure ring, cavity side flat safe surface. Connect metal tube general-purpose vacuum source with flexible tubing. vacuum source should off. Place package, down, flat safe surface. Locate package. Insert package into pressure ring (lid down) with located next orientation mark turn vacuum. vacuum will retain package pressure ring during following steps. Align vertically conductive material circuit board. Place pressure ring down over alignment pins gently tighten finger nuts. Remove vacuum, desired. vacuum source tubing removed convenience.
V-FB (48)
V+OUT V-OUT (43) (38)
(35)
V-TH (51) V-IN (55) V+IN (60) V+FB (65) (17) (14) V+CLK (31) V-CLK (26) (18)
VREF
CEXT
(11) REXT
INTERNAL CONNECTION CONNECT (##) PACKAGE NUMBER
5-7832(F)r.1
Figure TF1004A Connector Assignment
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator
Notes
Lucent Technologies Inc.
LG1600KXH Clock Data Regenerator Interactive Terminal Transmission Convergence
Preliminary
additional information, contact your Microelectronics Group Account Manager following: http://www.lucent.com/micro FPGA information, http://www.lucent.com/orca INTERNET: docmaster@micro.lucent.com E-MAIL: AMERICA: Microelectronics Group, Lucent Technologies Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Fong Universe Building, 1800 Zhong Shan Road, Shanghai 200233 China Tel. (86) 6440 0468, ext. 316, (86) 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 368, (44) 1189 Technical Inquiries: GERMANY: (49) 95086 (Munich), UNITED KINGDOM: (44) 1344 (Ascot), FRANCE: (33) (Paris), SWEDEN: (46) (Stockholm), FINLAND: (358) 4354 2800 (Helsinki), ITALY: (39) 6608131 (Milan), SPAIN: (34) 1441 (Madrid)
Lucent Technologies Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. rights under patent accompany sale such product(s) information.
Copyright 1999 Lucent Technologies Inc. Rights Reserved
June 1999 DS99-255HSPL
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