T7690 T1/E1 Quad Line Interface, T7693 T1/E1 Quad Line Interface (DS98

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T7690 T1/E1 Quad Line Interface, T7693 T1/E1 Quad Line Interface (DS98

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T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
T7690 T1/E1 Quad Line Interface, T7693 T1/E1 Quad Line Interface (DS98-233TIC) Data Sheet Correction
Diagram
Pins were switched diagram. should RRING4 should RTIP4.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
additional information, contact your Microelectronics Group Account Manager following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: AMERICA: Microelectronics Group, Lucent Technologies Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Fong Universe Building, 1800 Zhong Shan Road, Shanghai 200233 China Tel. (86) 6440 0468, ext. 316, (86) 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 299, (44) 1189 Technical Inquiries: GERMANY: (49) 95086 (Munich), UNITED KINGDOM: (44) 1344 (Ascot), FRANCE: (33) (Paris), SWEDEN: (46) 7070 (Stockholm), FINLAND: (358) 4354 2800 (Helsinki), ITALY: (39) 6608131 (Milan), SPAIN: (34) 1441 (Madrid)
Lucent Technologies Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. rights under patent accompany sale such product(s) information.
Copyright 1998 Lucent Technologies Inc. Rights Reserved Printed U.S.A.
September 1998 DA98-021TIC (Must accompany DS98-233TIC)
Printed Recycled Paper
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Features
Description
T7690 T7693 fully integrated quad line interfaces containing four transmit receive channels both North American (T1/DS1) European (E1/CEPT) applications. devices have many same functions Lucent Technologies Microelectronics Group T7290A provide additional flexibility system designer. Included parallel microprocessor interface that allows user define architecture, initiate loopbacks, monitor alarms. interface compatible with many commercially available microprocessors. receiver performs clock data recovery using fully integrated digital phase-locked loop. This digital implementation prevents false lock conditions that common when recovering sparse data patterns with analog phase-locked loops. Equalization circuitry receiver guarantees high level interference immunity. option, sliced data retiming) output receive data pins. Transmit equalization implemented with lowimpedance output drivers that provide shaped waveforms transformer, guaranteeing template conformance. quad device will interface digital cross connect (DSX) lengths operation line impedances CEPT operation. selectable jitter attenuator placed receive signal path low-bandwidth line-synchronous applications, placed transmit path multiplexer applications where DS1/CEPT signals demultiplexed from higher rate signals. jitter attenuator will perform clock smoothing required resulting demultiplexed gapped clock.
Four fully integrated T1/E1 line interfaces Includes driver, receiver, equalization, clock recovery, jitter attenuation functions Ultralow power consumption Robust operation increased system margin High interference immunity On-chip transmit equalization improved sensitivity Low-impedance drivers reduced power consumption Selectable transmit receive jitter attenuation/ clock smoothing 3-state transmit drivers High-speed microprocessor interface Automatic transmit monitor function Per-channel powerdown systems that compliant with AT&T CB119; TR-TSY-000170, TR-TSY-000009, TRTSY-000499, TR-TSY-000253; ANSI T1.102 T1.403; ITU-T G.703, G.732, G.735-9, G.775, G.823-4, I.431 Common transformer transmit/receive Fine-pitch spacing) surface-mount package, 100-pin bumpered quad flat pack operating temperature range
Applications
SONET/SDH multiplexers Asynchronous multiplexers (M13) Digital access cross connects (DACs) Channel banks Digital radio base stations, remote wireless modules interfaces
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Table Contents
Contents Page Contents Page
Features Applications Description Block Diagram Information System Interface Options Receiver Data Recovery Jitter Receiver Configuration Modes Clock/Data Recovery Mode (CDR) Zero Substitution Decoding (CODE) Alternate Logic Mode (ALM) Alternate Clock Mode (ACM) Loss Shutdown (LOSSD) Receiver Alarms Analog Loss Signal (ALOS) Alarm Digital Loss Signal (DLOS) Alarm Bipolar Violation (BPV) Alarm Receiver Specifications CEPT Receiver Specifications Transmitter Output Pulse Generation Jitter Transmitter Configuration Modes Zero Substitution Encoding/Decoding (CODE) Ones (AIS, Blue Signal) Generator (TBS) Transmitter Alarms Loss Transmit Clock (LOTC) Alarm Transmit Driver Monitor (TDM) Alarm Transmitter Pulse Template Specifications CEPT Transmitter Pulse Template Specifications Jitter Attenuator Data Delay Generated (Intrinsic) Jitter Jitter Transfer Function Jitter Tolerance Jitter Attenuator Enable Jitter Attenuator Receive Path Enable (JAR) Jitter Attenuator Transmit Path Enable (JAT)
Loopbacks Full Local Loopback (FLLOOP) Remote Loopback (RLOOP) Digital Local Loopback (DLLOOP) Other Features Powerdown (PWRDN) RESET (RESET, SWRESET) Loss XCLK Reference Clock (LOXC) In-Circuit Testing Driver 3-State (ICT) Microprocessor Interface Overview Microprocessor Configuration Modes Microprocessor Interface Pinout Definitions Microprocessor Clock (MPCLK) Specifications Internal Chip Select Function Microprocessor Interface Register Architecture Alarm Register Overview (0000, 0001) Alarm Mask Register Overview (0010, 0011) Global Control Register Overview (0100, 0101) Channel Configuration Register Overview (0110-1001) Other Registers Timing XCLK Reference Clock Power Supply Bypassing T7690 External Line Termination Circuitry T7693 External Line Termination Circuitry Absolute Maximum Ratings Handling Precautions Operating Conditions Timing Characteristics Outline Diagram 100-Pin BQFP Ordering Information DS98-233TIC Replaces DS97-098TIC Include Following Updates
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Block Diagram
T7690/T7693 block diagram shown Figure illustration purposes, only four on-chip line interfaces shown. names that apply four channels followed designation [1-4].
ALOS
DLOS DECODER* RPD/RDATA[1-4] RND/BPV[1-4] RCLK/ALOS[1-4]
RTIP[1-4] RRING[1-4] FLLOOP BLUE SIGNAL) LINE INTERFACE
EQUALIZER
SLICERS
CLOCK/DATA RECOVERY*
JITTER ATTENUATOR* (TRANSMIT RECEIVE PATH)
FLLOOP (DURING BLUE SIGNAL)
XCLK XCLK DLLOOP SYSTEM INTERFACE
LOTC PULSEWIDTH CONTROLLER XCLK
TTIP[1-4] DRIVERS TRING[1-4]
PULSE EQUALIZER
JITTER ATTENUATOR* (TRANSMIT RECEIVE PATH)
RLOOP TCLK[1-4] TPD/TDATA[1-4] TND[1-4] A[3:0] AD[7:0] RDY_DTACK WR_DS RD_R/W ALE_AS MPMUX MPMODE MPCLK
ENCODER*
BLUE SIGNAL (AIS) LOXC MICROPROCESSOR INTERFACE XCLK LOXC BCLK
5-3683(C)r.7
Function bypassed using microprocessor interface.
Figure Block Diagram (Single Channel)
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Information
RND1/BPV1 RND4/BPV4 RPD4/RDATA4 RCLK4/ALOS4 TND4 TPD4/TDATA4 TCLK4 MPCLK GNDC VDDC TCLK3 TPD3/TDATA3 TND3 RCLK3/ALOS3 RPD3/RDATA3 GNDD2 RRING2 RRING3 TRING2 TRING3 RND2/BPV2 RND3/BPV3 VDDD2 GNDX2 GNDX3 GNDX2 GNDX3 RTIP2 RTIP3 GNDD3 GNDA2 GNDA3 VDDX2 VDDX3 VDDD3 VDDA2 GNDS VDDA3 TTIP2 TTIP3
RRING1
RRING4
TRING1
TRING4
GNDX1
GNDX1
GNDX4
GNDX4
GNDD1
GNDD4
GNDA1
GNDA4
VDDX1
VDDX4
RTIP1
TTIP4
RTIP4
VDDA1
VDDA4
VDDD1
RPD1/RDATA1 RCLK1/ALOS1 TND1 TPD1/TDATA1 TCLK1 WR_DS MPMUX MPMODE RD_R/W ALE_AS RDY_DTACK GNDC VDDC XCLK BCLK LOXC RESET TCLK2 TPD2/TDATA2 TND2 RCLK2/ALOS2 RPD2/RDATA2
CHANNEL
CHANNEL
MICROPROCESSOR CONTROL
CHANNEL
CHANNEL
VDDD4
TTIP1
GNDS
5-3684(C)r.2
Figure Diagram
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Information (continued)
Table Descriptions Symbol GNDS GNDX1 GNDX2 GNDX3 GNDX4 TTIP1 TTIP2 TTIP3 TTIP4 VDDX1 VDDX2 VDDX3 VDDX4 TRING1 TRING2 TRING3 TRING4 VDDA1 VDDA2 VDDA3 VDDA4 RTIP1 RTIP2 RTIP3 RTIP4 RRING1 RRING2 RRING3 RRING4 GNDA1 GNDA2 GNDA3 GNDA4 Ground Reference Analog Circuitry. Receive Bipolar Ring. Negative bipolar receive input data from analog line interface. Receive Bipolar Tip. Positive bipolar receive input data from analog line interface. Power Supply Analog Circuitry. T7690 device requires power supply these pins. T7693 device requires power supply these pins. Transmit Bipolar Ring. Negative bipolar transmit output data analog line interface. Power Supply Line Drivers. T7690 device requires power supply these pins. T7693 device requires power supply these pins. Transmit Bipolar Tip. Positive bipolar transmit output data analog line interface. Type* Name/Description Ground Reference Substrate. Ground Reference Line Drivers.
power, input, output, input with internal pull-up.
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Information (continued)
Table Descriptions (continued) Symbol GNDD1 GNDD2 GNDD3 GNDD4 VDDD1 VDDD2 VDDD3 VDDD4 RND1/BPV1 RND2/BPV2 RND3/BPV3 RND4/BPV4 Receive Negative Data. When dual-rail (DUAL register clock recovery mode (CDR register this signal receive negative output data terminal equipment. When data slicing mode (CDR this signal sliced negative output data front end. Bipolar Violation. When single-rail (DUAL register clock recovery mode (CDR register CODE (register this signal asserted high indicate occurrence code violation receive data stream. CODE this signal asserted indicate occurrence bipolar violation receive data system. Receive Positive Data. When dual-rail (DUAL register clock recovery mode (CDR register this signal receive positive output data terminal equipment. When data slicing mode (CDR this signal sliced positive output data front end. Receive Data. When single-rail (DUAL register clock recovery mode (CDR register this signal receive output data. Power Supply Digital Circuitry. T7690 device requires power supply these pins. T7693 device requires power supply these pins. Type* Name/Description Ground Reference Digital Circuitry.
RPD1/ RDATA1 RPD2/ RDATA2 RPD3/ RDATA3 RPD4/ RDATA4 RCLK1/ ALOS1 RCLK2/ ALOS2 RCLK3/ ALOS3 RCLK4/ ALOS4 TND1 TND2 TND3 TND4
Receive Clock. clock recovery mode (CDR register this signal receive clock terminal equipment. duty cycle RCLK Analog Loss Signal. data slicing mode (CDR register this signal asserted high indicate low-amplitude receive data RTIP/RRING inputs.
Transmit Negative Data. Transmit negative input data from terminal equipment.
power, input, output, input with internal pull-up.
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Information (continued)
Table Descriptions (continued) Symbol TPD1/ TDATA1 TPD2/ TDATA2 TPD3/ TDATA3 TPD4/ TDATA4 TCLK1 TCLK2 TCLK3 TCLK4 WR_DS Write (Active-Low). MPMODE (pin 21), this asserted microprocessor initiate write cycle. Data Strobe (Active-Low). MPMODE (pin 21), this becomes data strobe microprocessor. When (write), applied this latches signal data into internal registers. Microprocessor Multiplex Mode. Setting MPMUX allows microprocessor interface accept multiplexed address data signals. Setting MPMUX allows microprocessor interface accept demultiplexed (separate) address data signals. Microprocessor Mode. When MPMODE device uses address latch enable type microprocessor read/write protocol with separate read write controls. Setting MPMODE allows device address strobe type microprocessor read/write protocol with separate data strobe combined read/write control. Read (Active-Low). MPMOD (pin 21), this asserted microprocessor initiate read cycle. Read/Write. MPMODE (pin 21), this asserted high microprocessor indicate read cycle asserted indicate write cycle. Address Latch Enable. MPMODE (pin 21), this becomes address latch enable microprocessor. When this transitions from high low, address inputs latched into internal registers. Address Strobe (Active-Low). MPMODE (pin 21), this becomes address strobe microprocessor. When this transitions from high low, address inputs latched into internal registers. Chip Select (Active-Low). This asserted microprocessor enable microprocessor interface. MPMUX (pin 20), externally tied internal chip selection function (see Internal Chip Select Function section). internal pull-up this pin. Transmit Clock. (1.544 ppm) CEPT (2.048 ppm) clock signal from terminal equipment. Type* Name/Description Transmit Positive Data. When dual-rail mode (DUAL register this signal transmit positive input data from terminal equipment. Transmit Data. When single-rail mode (DUAL register this signal transmit input data from terminal equipment.
MPMUX
MPMODE
RD_R/W
ALE_AS
power, input, output, input with internal pull-up.
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Information (continued)
Table Descriptions (continued) Symbol Type* Name/Description Interrupt. This asserted high indicate interrupt produced alarm condition register activation this masked microprocessor registers Ready. MPMODE (pin 21), this asserted high indicate device completed read write operation. This 3-state condition when (pin high. Data Transfer Acknowledge (Active-Low). MPMODE (pin 21), this asserted indicate device completed read write operation. Ground Reference Microprocessor Interface Control Circuitry. Power Supply Microprocessor Interface Control Circuitry. T7690 device requires power supply these pins. T7693 device requires power supply these pins. Reference Clock. valid reference clock (24.704 operation, 32.768 CEPT operation) must provided this input certain applications (see XCLK Reference Clock section). XCLK must independent, continuously active, ungapped, unjittered clock guarantee device performance specifications. internal pull-up this pin. Blue Clock. Input clock signal used transmit blue signal (alarm indication signal (AIS) data pattern). mode, this clock 1.544 ppm, CEPT mode, this clock 2.048 ppm. internal pull-up this pin. Loss XCLK. This asserted high when XCLK signal (pin present. Hardware Reset (Active-Low). RESET forced low, internal states line interface paths reset data flow through each channel will momentarily disrupted (see RESET (RESET, SWRESET) section). RESET must held minimum internal pull-up this pin. In-Circuit Test Control (Active-Low). forced low, certain output pins placed high-impedance state (see In-Circuit Testing Driver 3-State (ICT) section). internal pull-up this pin. Microprocessor Interface Address/Data Bus. MPMUX (pin 20), these pins become bidirectional, 3-statable data bus. MPMUX these pins become multiplexed address/data bus. this mode, only lower bits (AD[3:0]) used internal register addresses.
RDY_DTACK
GNDC VDDC
XCLK
BCLK
LOXC RESET
power, input, output, input with internal pull-up.
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Information (continued)
Table Descriptions (continued) Symbol MPCLK Type* Name/Description Microprocessor Interface Address. MPMUX (pin 20), these pins become address microprocessor interface registers. MPMUX (pin externally tied high internal chip selection function (see Internal Chip Select Function section). this function used, A[3:0] must externally tied low. Microprocessor Interface Clock. Microprocessor interface clock rates from twice frequency line clock (3.088 operation, 4.096 CEPT operation) 16.384 supported.
power, input, output, input with internal pull-up.
System Interface Options
system interface configured operate number different modes, shown Table Dual-rail single-rail operation possible using DUAL control (register Dual-rail mode enabled when DUAL single-rail mode enabled when DUAL dual-rail operation, data received from line interface RTIP RRING appears (pins (pins system interface data transmitted from system interface (pins (pins appears TTIP TRING line interface. single-rail operation, data received from line interface RTIP RRING appears RDATA (pins system interface data transmitted from system interface TDATA (pins appears TTIP TRING line interface. both dual-rail single-rail operation, clock/data recovery mode selectable (register When clock data recovery enabled system interface operates nonreturn-tozero (NRZ) digital format. When clock data recovery disabled system interface operates unretimed sliced data data format (see Data Recovery section). single-rail mode only, B8ZS/HDB3 encoding/decoding selected setting CODE (register This allows coding violations, such receiving consecutive same polarity from line interface, output (pins (see Zero Substitution Encoding/Decoding (CODE) section). Table Mapping Configuration Dual-rail System Interface with Clock Recovery Dual-rail System Interface with Data Slicing Only Single-rail System Interface with Clock Recovery Single-rail System Interface with Data Slicing Only RCLK/ ALOS RCLK ALOS RCLK ALOS RPD/ RDATA RDATA RND/BPV TPD/ TDATA TDATA USED
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998 Jitter
receiver designed accommodate large amounts input jitter. receiver jitter performance exceeds requirements shown Table Table Jitter transfer independent input ones density line interface.
Receiver
Data Recovery
receive line interface transmission format device bipolar alternate mark inversion (AMI). accepts input data with frequency tolerance ±130 (DS1) (CEPT). receiver first restores incoming data detects analog loss signal. Subsequent processing optional depends programmable device configuration established within microprocessor interface registers. receiver operates with high interference immunity, utilizing equalizer restore fast rise/fall times following maximum cable loss. signal then peakdetected sliced produce digital representations data. Selectable clock recovery sliced data, digital loss signal, jitter attenuation, data decoding performed. applications bypassing clock recovery function (CDR receive digital output format unretimed sliced data positive negative data). clock recovery applications (CDR receive digital output format nonreturn zero (NRZ) with selectable dual-rail single-rail system interface. recovered clock (RCLK, pins only provided when (see Table Timing recovery performed digital phase-locked loop that uses XCLK (pin reference lock incoming data. Because reference clock multiple received data rate, output RCLK (pins will always valid DS1/CEPT clock that eliminates false-lock conditions. During periods with input signal, free-run frequency defined XCLK/16. RCLK always active with duty-cycle centered 50%, deviating more than ±5%. Valid data recovered within first periods after application XCLK. delay data through receive circuitry approximately periods, depending CODE configurations. Additional delay introduced jitter attenuator selected operation receive path (see Data Delay section).
Receiver Configuration Modes
Clock/Data Recovery Mode (CDR) clock/data recovery function receive path selectable (register clock data recovery function enabled provides recovered clock (RCLK) with retimed data (RPD/RDATA, RND). clock data recovery function disabled, data from slicers provided over system. this mode, ALOS available RCLK/ALOS pins, downstream functions selected microprocessor register (JAR, ACM, LOSSD) ignored. Zero Substitution Decoding (CODE) When single-rail operation selected with DUAL (register B8ZS/HDB3 zero substitution decoding selected CODE (register CODE B8ZS/HDB3 decoding function enabled receive path decoded receive data code violations appear RDATA pins, respectively. CODE receive data bipolar violations (such consecutive same polarity) appear RDATA pins, respectively. Alternate Logic Mode (ALM) alternate logic mode (ALM) control (register selects receive transmit data polarity (i.e., active-high active-low). receiver circuitry (and transmit input) assumes data active-low polarity. receiver circuitry (and transmit input) assumes data active-high polarity. control used conjunction with control (register determine receive data retiming mode.
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Digital Loss Signal (DLOS) Alarm digital loss signal (DLOS) detector guarantees quality signal defined standards documents, reports status alarm registers During operation, digital loss signal (DLOS indicated more consecutive occur receive data stream. DLOS indication deactivated when average ones density least 12.5% received contiguous pulse positions. During CEPT operation, DLOS indicated when more consecutive occur receive data stream. DLOS indication deactivated when average ones density least 12.5% received contiguous pulse positions. LOSSTD control (register selects conformance protocols DLOS Table TR-TSY-000009 adds additional constraint more than consecutive when determining 12.5% density. Table Digital Loss Signal Standard Select LOSSTD Mode T1M1.3/93-005 ITU-T G.775 TR-TSY-000009 CEPT Mode ITU-T G.775 ITU-T G.775
Receiver (continued)
Receiver Configuration Modes (continued)
Alternate Clock Mode (ACM) alternate clock mode (ACM) control (register selects positive negative clock edge receive clock (RCLK) receive data retiming. control used conjunction with (register control determine receive data retiming modes. receive data retimed positive edge receive clock. receive data retimed negative edge receive clock. Note that this control does affect timing relationship transmitter inputs. Loss Shutdown (LOSSD) loss shutdown (LOSSD) control (register places digital receiver outputs (RPD, RND) predetermined state when digital loss signal (DLOS) alarm occurs register bits LOSSD outputs forced their inactive states (selected ALM) receive clock (RCLK) free runs during DLOS alarm condition. LOSSD RPD, RND, RCLK outputs will remain unaffected during DLOS alarm condition.
Bipolar Violation (BPV) Alarm
Receiver Alarms
Analog Loss Signal (ALOS) Alarm analog loss signal (ALOS) detector monitors incoming signal amplitude reports status alarm registers During CEPT modes operation, analog loss signal indicated (ALOS amplitude receive input drops below voltage that below nominal pulse amplitude. slicer outputs clamped inactive state clock recovery will provide free-running RCLK when ALOS alarm circuitry also provides hysteresis eliminate ALOS chattering. time required detect ALOS between timed blue clock (see Ones (AIS, Blue Signal) Generator (TBS) section). Detection time independent signal amplitude before loss condition occurs.
bipolar violation (BPV) alarm used only singlerail mode operation device (see System Interface Options section). When B8ZS(DS1)/ HDB3(CEPT) coding used (i.e., CODE violations receive data (such more consecutive rail) indicated RND/BPV pins. When B8ZS(DS1)/HDB3(CEPT) coding used (i.e., CODE HDB3/B8ZS code violations reflected RND/BPV pins.
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Receiver (continued)
Receiver Specifications
During operation, receiver will perform specified Table Table Receiver Specifications Parameter Analog Loss Signal: Threshold Hysteresis Maximum Sensitivity Jitter Transfer: Bandwidth, Single-pole Rolloff Peaking Generated Jitter Jitter Tolerance 3.84 0.032 0.04 Unit UIpk-pk Specification TR-TSY-000499 TR-TSY-000499 TR-TSY-000499, ITU-T G.824 ITU-T G.823-4, TR-TSY-000009, TR-TSY-000499, TR-TSY-000170
Return Loss: 1.544 1.544 2.316 Digital Loss Signal: Flag Asserted, Consecutive Positions Flag Deasserted Data Density Maximum Consecutive Zeros
zeros
12.5
ones zeros zeros
TR-TSY-000009 ITU-T G.775, T1M1.3/93-005
Below nominal pulse amplitude using Lucent transformers: 2745G3 T7690 components with values Figure Table 2664AL T7693 components with values Figure Table Amount cable loss. Using Lucent transformers: 2745G3 T7690 components with values Figure Table 2664AL T7693 components with values Figure Table
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Receiver (continued)
CEPT Receiver Specifications
During CEPT operation, receiver will perform specified Table Table CEPT Receiver Specifications Parameter Analog Loss Signal: Threshold Hysteresis Maximum Sensitivity: Jitter Transfer: Bandwidth, Single-pole Rolloff Peaking Generated Jitter Jitter Tolerance Return 2.048 2.048 3.072 Digital Loss Signal: Flag Asserted, Consecutive Positions Flag Deasserted Loss: 12.5 13.5 0.032 0.04 Unit UIpk-pk ITU-T G.775 zeros ones Specification ITU-T G.775 ETSI 233:1992 ITU-T G.703 ITU-T G.735-9 ITU-T G.823, I.431 ITU-T G.823, I.431 ITU-T G.703
Below nominal pulse amplitude 2.37 applications using Lucent transformers: 2745CA T7690 (CEPT option CEPT applications) components with values Figure Table 2664AJ T7693 (CEPT option CEPT applications) components with values Figure Table 2745AJ2 T7690 (CEPT option components with values Figure Table 2664AK T7693 (CEPT option components with values Figure Table Amount cable loss allowed when asynchronous interference signal added with desired signal source. Using Lucent transformers: 2745CA T7690 (CEPT option CEPT applications) components with values Figure Table 2664AJ T7693 (CEPT option CEPT applications) components with values Figure Table 2745AJ2 T7690 (CEPT option components with values Figure Table 2664AK T7693 (CEPT option components with values Figure Table
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Additional delay results jitter attenuator selected transmit path (see Data Delay section). Transmit pulse shaping controlled on-chip pulse-width controller pulse equalizer. pulsewidth controller produces high-speed timing signals accurately control transmit pulse widths. This eliminates need tightly controlled transmit clock duty cycle that usually required discrete implementations. pulse equalizer controls amplitudes these pulse shapes. Different pulse
Transmitter
Output Pulse Generation
transmitter accepts clock with data single-rail mode (DUAL register positive negative data dual-rail mode (DUAL from system. device converts this data balanced bipolar signal (AMI format) with optional B8ZS(DS1)/HDB3(CEPT) encoding jitter attenuation. Low-impedance output drivers produce these pulses line interface. Positive output positive pulse TTIP, negative output positive pulse TRING. Binary converted null pulses. total delay data from system interface transmit driver approximately periods, depending CODE (register configuration.
equalizations selected through proper settings EQA, EQB, (registers bits described Table Table Equalizer/Rate Control Transmitter Equalization* Feet
Service
Clock Rate
Maximum Cable Loss
Meters
1.544
CEPT Used
2.048
(Option (Option
mode, distance 22-gauge (ABAM) cable specified. maximum cable loss figures other cable types. CEPT mode, equalization specified coaxial twisted-pair cable. Loss measured kHz. applications, option recommended over option lower device power dissipation. Option allows same transformer used CEPT applications.
Jitter
intrinsic jitter transmit path, i.e., jitter TTIP/TRING when jitter applied TCLK (and jitter attenuator selected, typically nspk-pk will exceed 0.02 UIpk-pk.
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface Transmitter Alarms
Loss Transmit Clock (LOTC) Alarm loss transmit clock alarm (LOTC indicated clocks transmit path disappear (registers bits This includes loss TCLK input, loss RCLK during remote loopback, loss jitter attenuator output clock (when enabled), loss clock from pulse-width controller. these conditions, core transmitter timing clock lost data driven onto line. Output drivers TTIP TRING placed highimpedance state when this alarm condition active. LOTC interrupt asserted between after clock disappears, deasserts immediately after detecting first clock edge. Transmit Driver Monitor (TDM) Alarm transmit driver monitor detects conditions: nonfunctional link faults primary transmit transformer, periods data transmission. alarm (registers bits ORed function both faults provides information about integrity transmit signal path. first monitoring function provided detect nonfunctional links protect device from damage. alarm (TDM when transmitter's line drivers (TTIP TRING) shorted power supply ground, TTIP TRING shorted together. Under these conditions, internal circuitry protects device from damage excessive power supply current consumption 3-stating output drivers. monitor detects faults transformer primary, transformer secondary faults detected. monitor operates comparing line pulses with transmit inputs error detect mode. After transmit clock cycles, transmitter powered normal operating mode. drivers attempt correctly transmit next data bit. error persists, remains active eliminate alarm chatter transmitter internally protected another transmit clock cycles. This process repeated until error condition removed alarm deactivated. second monitoring function indicate periods data transmission. alarm (TDM when consecutive zeros have been transmitted cleared detection single pulse. This alarm condition does alter state functionality signal path.
Transmitter (continued)
Transmitter Configuration Modes
Zero Substitution Encoding/Decoding (CODE) Zero substitution encoding/decoding (B8ZS/HDB3) activated only single-rail system interface mode (DUAL setting CODE (register Data received from line interface RTIP RRING will B8ZS/HDB3 decoded before appearing RDATA (pins system interface. Likewise, data transmitted from system interface TDATA (pins will B8ZS/HDB3 encoded before appearing TTIP TRING line interface. This mode also allows coding violations, such receiving consecutive same polarity from line interface, output (pins 89). Ones (AIS, Blue Signal) Generator (TBS) When transmit blue signal control (TBS given channel (registers continuous stream bipolar transmitted line interface (AIS). TPD/TDATA inputs ignored during this mode. input ignored when remote loopback (RLOOP) selected using loopback control bits LOOPA LOOPB (registers bits (See Loopbacks section.) maintain application flexibility, clock source used blue signal selected configuring BCLK (pin 30). data rate clock input BCLK pin, will used transmit blue signal. BCLK then TCLK used transmit blue signal (the smoothed clock from jitter attenuator used selected). BCLK then XCLK (after being divided factor used transmit blue signal. After BCLK established, minimum required device properly select clock. above options, clock tolerance must meet normal line transmission rates (DS1 1.544 ppm; CEPT 2.048 ppm).
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Table DSX-1 Pulse Template Corner Points (from CB119) Maximum Curve 1100 1250 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 Minimum Curve 1100 1250 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05
Transmitter (continued)
Transmitter Pulse Template Specifications
pulse shape template specified (defined CB119 ANSI T1.102) illustrated Figure device also meets pulse template specified ITU-T G.703 (not shown).
NORMALIZED AMPLITUDE
During operation, transmitter tip/ring (TTIP/ TRING pins) will perform specified Table
1000 1250
-0.5 TIME (ns)
5-1160(C)r.6
Figure DSX-1 Isolated Pulse Template Table Transmitter Specifications Parameter Output Pulse Amplitude DSX* Output Pulse Width Positive/Negative Pulse Imbalance Power 1.544
12.6
17.9
Unit
Specification AT&T CB119, ANSI T1.102
Levels:
accordance with interfaces described Absolute Maximum Ratings section Handling Precautions section. Total power difference. Measured band around specified frequency. Below power kHz.
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Transmitter (continued)
CEPT Transmitter Pulse Template Specifications
CEPT pulse shape template specified system output (defined ITU-T G.703) shown Figure
(244
100%
(244
NOMINAL PULSE
(244
(244 244)
5-3145(C)r.8
Figure ITU-T G.703 Pulse Template During CEPT operation, transmitter tip/ring (TTIP/TRING pins) will perform specified Table Table CEPT Transmitter Specifications Parameter Output Pulse Amplitude*: Output Pulse Width Positive/Negative Pulse Imbalance: Pulse Amplitude Pulse Width Zero Level (percentage pulse amplitude) Return Loss: 2.048 2.048 3.072 2.13 2.37 ±1.5 ±1.0 2.61 Unit CH-PTT Specification ITU-T G.703
accordance with interfaces described Absolute Maximum Ratings section Handling Precautions section, measured transformer secondary. Using Lucent transformers: 2745CA T7690 (CEPT option CEPT applications) components with values Figure Table 2664AJ T7693 (CEPT option CEPT applications) components with values Figure Table 2745AJ2 T7690 (CEPT option components with values Figure Table 2664AK T7693 (CEPT option components with values Figure Table
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998 Jitter Transfer Function
jitter transfer function describes amount jitter specific equipment that transferred from input output over frequency range. jitter attenuator exhibits single-pole rolloff dB/decade) jitter transfer characteristic that peaking nominal filter corner frequency bandwidth) CEPT operation less than given frequency, different jitter amplitudes will cause slight variations attenuation because finite quantization effects. Jitter amplitudes less than approximately will have greater attenuation than single-pole rolloff characteristic. Measurement jitter transfer function involves stimulating circuit with sinusoidal jitter test signal. difference between output signal power test signal power, given frequency, jitter transfer. When output signal power below noise floor, cannot measured. Halting jitter transfer function measurements because noise floor limitations acceptable during conformance testing.
Jitter Attenuator
selectable jitter attenuator provided narrowbandwidth jitter transfer function applications. This selection done control bits, which global affect four channels. application provide narrow-bandwidth jitter filtering line-synchronization receive path. Another jitter attenuator provide clock smoothing transmit signaling path applications such synchronous/asynchronous demultiplexers. these applications, TCLK will have instantaneous frequency that higher than data rate periods TCLK suppressed (gapped) order average long-term TCLK frequency within transmit line rate specification. jitter attenuator does degrade jitter specifications receiver clock/data recovery circuit. addition, jitter attenuator must meet specifications narrow-bandwidth applications listed Table Table List Low-Bandwidth Jitter Specification Documents Application TR-TSY-000009 TR-TSY-000253 TR-TSY-000499 CEPT ITU-T G.735 ITU-T I.431
Jitter Tolerance
minimum jitter tolerance jitter attenuator occurs when XCLK frequency long-term average frequency input clock their extreme-frequency tolerances. minimum tolerance peak-to-peak highest jitter frequency kHz.
Data Delay Jitter Attenuator Enable
Providing narrow-bandwidth jitter filtering requires data buffering increase data delay through jitter attenuator. nominal data delay jitter attenuator periods, with maximum data delay periods. This delay dependent input clock frequency, XCLK frequency, input jitter, gapped clock patterns. jitter attenuator selected using bits (register bits microprocessor interface. These control bits global affect four channels unless given channel powerdown mode (PWRDN Because there only attenuator function device, selection must made between either transmit receive path. both activated same time, jitter attenuator will disabled. Note that power consumption increases slightly per-channel basis when jitter attenuator active, described Table jitter attenuation selected, valid XCLK (pin signal must available.
Generated (Intrinsic) Jitter
Generated jitter amount jitter appearing output port when applied input signal jitter. jitter attenuator this device outputs maximum 0.04 peak-to-peak intrinsic jitter.
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface Full Local Loopback (FLLOOP)
full local loopback (FLLOOP) connects transmit line driver input receiver analog front-end circuitry. Valid transmit output data continues sent network. transmit blue signal (all-1s signal) sent network, looped data affected. ALOS alarm continues monitor receive line interface signal while DLOS monitors looped data.
Jitter Attenuator (continued)
Jitter Attenuator Enable (continued)
Jitter Attenuator Receive Path Enable (JAR) When jitter attenuator receive (JAR attenuator enabled receive data path between clock/data recovery decoder (see Figure Under this condition, jitter characteristics jitter attenuator apply receiver. When clock/data recovery outputs bypass disabled attenuator directly enter decoder function. receive path will then exhibit jitter characteristics clock recovery function described Jitter section. (register ignored because clock recovery will disabled. Jitter Attenuator Transmit Path Enable (JAT) When jitter attenuator transmit (JAT attenuator enabled transmit data path between encoder pulse-width controller/ pulse equalizer (see Figure Under this condition, jitter characteristics jitter attenuator apply transmitter. When encoder outputs bypass disabled attenuator directly enter pulse-width controller/pulse equalizer. transmit path will then pass jitter from TCLK line interface outputs TTIP/TRING.
Remote Loopback (RLOOP)
remote loopback (RLOOP) connects recovered clock retimed data transmitter system interface sends data back line. receiver front end, clock/data recovery, encoder/ decoder enabled) jitter attenuator enabled), transmit driver circuitry exercised during this loopback. transmit clock, transmit data, inputs ignored. Valid receive output data continues sent system interface. This loopback mode very useful isolating failures between systems.
Digital Local Loopback (DLLOOP)
digital local loopback (DLLOOP) connects transmit clock data through encoder/decoder pair receive clock data output pins system interface. This loopback operational encoder/ decoder pair enabled disabled. blue signal transmitted without effect looped signal.
Loopbacks
device three independent loopback paths that activated using LOOPA LOOPB (registers bits shown Table locations these loopbacks illustrated Figure Table Loopback Control
Operation Normal Full Local Loopback Remote Loopback Digital Local Loopback Symbol FLLOOP* RLOOP DLLOOP LOOPA LOOPB
During transmit blue signal condition, looped data will transmitted data from system all-1s signal. Transmit blue signal request ignored.
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998 Loss XCLK Reference Clock (LOXC)
LOXC output (pin active when XCLK reference clock (pin absent. LOXC flag asserted between after XCLK disappears, deasserts immediately after detecting first clock edge XCLK. During LOXC alarm condition, clock recovery jitter attenuator functions automatically disabled. Therefore, and/or RCLK, RPD, RND, DLOS outputs will unknown. there will effect receiver. jitter attenuator enabled transmit path (JAT during this alarm condition, then LOTC will also indicated.
Other Features
Powerdown (PWRDN)
Each line interface channel independent powerdown mode controlled PWRDN (registers This provides power savings systems that backup channels. PWRDN corresponding channel will standby mode, consuming only small amount power. recommended that alarm registers corresponding channel masked with MASK (registers during powerdown mode. line interface channel powerdown mode needs placed into service, channel should turned (PWRDN approximately before data applied. line interface channel will never service, VDDA VDDD pins connected ground plane, resulting power consumption.
In-Circuit Testing Driver 3-State (ICT)
function input (pin determined ICTMODE (register ICTMODE activated (ICT then output buffers (TTIP, TRING, RCLK, RPD, RND, LOXC, RDY_DTACK, INT, AD[7:0]) placed high-impedance state. in-circuit testing, RESET used activate ICTMODE without having write bit. ICTMODE then only TTIP TRING outputs channels will placed highimpedance state. TTIP TRING outputs have limiting high-impedance capability approximately
RESET (RESET, SWRESET)
device provides both hardware reset (RESET; software reset (SWRESET; register that functionally equivalent. When device reset, signal-path alarm monitor states initialized known starting configuration. status registers (pin also cleared. writable microprocessor interface registers affected reset, with exception bits register (see Global Control Register Overview (0100, 0101) section). During reset condition, data transmission will momentarily interrupted device will respond those register bits affected reset. powerup device, software reset (register initialized. must written prior writing other bits register reset condition initiated setting RESET SWRESET minimum After leaving reset condition (with RESET SWRESET only bits register need restored.
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
interrupt-driven mode, more device alarms will assert active-high output (pin once alarm activation. After microprocessor reads alarm status registers, output will deassert. polled mode, however, microprocessor monitors various device alarm status periodically reading alarm status registers without (pin 25). both interrupt polled methods alarm servicing, status register will clear microprocessor read cycle only when alarm condition within signaling channel longer exists; otherwise, register remains set. device flexibility, there default powerup reset states, except register read/write registers must written microprocessor system start-up guarantee proper device functionality. Details concerning microprocessor interface configuration modes, pinout definitions, clock specifications, register bank architecture, timing specifications diagrams described following sections.
Microprocessor Interface
Overview
device equipped with microprocessor interface that operate with most commercially available microprocessors. Inputs MPMUX MPMODE (pins used configure this interface into four possible modes, shown Table MPMUX setting selects either multiplexed 8-bit address/data (AD[7:0]) demultiplexed 4-bit address (A[3:0]) 8-bit data (AD[7:0]). MPMODE setting selects associated control signals required access registers within device. When microprocessor interface configured operate multiplexed address/data modes (MPMUX user access internal chip select function that allows microprocessor selectively read/write specific T7693 multiple T7693 environment (see Internal Chip Select Function section). microprocessor interface operate speeds 16.384 interrupt-driven polled mode without requiring wait-states. microprocessors operating greater than 16.384 MHz, RDY_DTACK output used introduce wait-states read/write cycles.
Microprocessor Configuration Modes
Table highlights four microprocessor modes controlled MPMUX MPMODE inputs (pins 21). Table Microprocessor Configuration Modes Mode MODE MODE MODE MODE MPMODE MPMUX Address/Data DEMUXed MUXed DEMUXed MUXed Generic Control, Data, Output Names R/W, A[3:0], AD[7:0], INT, DTACK R/W, AD[7:0], INT, DTACK ALE, A[3:0], AD[7:0], INT, ALE, AD[7:0], INT,
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Microprocessor Interface (continued)
Microprocessor Interface Pinout Definitions
MODE [1-4] specific definitions given Table Note that microprocessor interface uses same pins modes. Table MODE [1-4] Microprocessor Definitions Configuration
MODE
Number
69-76 79-82
Device Name
WR_DS RD_R/W ALE_AS RDY_DTACK AD[7:0] A[3:0] MPCLK WR_DS RD_R/W
Generic Name
DTACK AD[7:0] A[3:0] MPCLK
Pin_Type
Input Input Input Input Output Output Input Input Input Input
Assertion Sense
Active-Low Active-Low Active-High Active-Low Active-Low
Function
Data Strobe Read/Write Read Write Address Strobe Chip Select Interrupt Data Acknowledge Data Address Microprocessor Clock Data Strobe Read/Write Read Write Address Strobe Chip Select Interrupt Data Acknowledge Address/Data Microprocessor Clock Write Read Address Latch Enable Chip Select Interrupt Ready Data Address Microprocessor Clock Write Read Address Latch Enable Chip Select Interrupt Ready Address/Data Microprocessor Clock
MODE
69-76 MODE 69-76 79-82 MODE 69-76
ALE_AS RDY_DTACK AD[7:0] MPCLK WR_DS RD_R/W ALE_AS RDY_DTACK AD[7:0] A[3:0] MPCLK WR_DS RD_R/W ALE_AS RDY_DTACK AD[7:0] MPCLK
DTACK AD[7:0] MPCLK AD[7:0] A[3:0] MPCLK AD[7:0] MPCLK
Input Input Output Output Input Input Input Input Input Output Output Input Input Input Input Input Input Output Output Input
Active-Low Active-High Active-Low Active-Low Active-Low Active-Low Active-High Active-High Active-Low Active-Low Active-Low Active-High Active-High
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Microprocessor Interface (continued)
Microprocessor Clock (MPCLK) Specifications
microprocessor interface designed operate clock speeds 16.384 without requiring waitstates. Wait-states needed higher microprocessor clock speeds required. microprocessor clock (MPCLK, specification shown Table This clock must supplied only RDY_DTACK outputs required synchronous MPCLK. Otherwise, MPCLK must connected ground (GNDD). Table Microprocessor Input Clock Specifications Name Symbol Period Tolerance Trise Tfall Duty Cycle High MPCLK Unit
Internal Chip Select Function
When microprocessor interface configured operate multiplexed address/data modes (MPUX user access internal chip select function. This function allows microprocessor selectively read write specific quad line interface device system eight devices microprocessor bus. Externally tying (pin (pin every line interface device enables internal chip select function. Individual device addresses established externally connecting other three address pins A[2:0] unique address value range through 111. order line interface device respond register read write request from microprocessor, address data AD[6:4] (pins must match specific address defined A[2:0]. pins tied low, internal chip select function disabled line interface devices will respond microprocessor write request. However, none line interface devices will respond microprocessor read/write request.
Microprocessor Interface Register Architecture
register bank architecture microprocessor interface shown Table register bank consists sixteen 8-bit registers classified alarm registers, global control registers, channel configuration/maintenance registers. Registers alarm registers used storing various device alarm status read-only. other registers read/write. Registers contain individual mask bits alarms registers Registers designated global control registers used functions four channels. channel configuration registers registers through used configure individual channel functions parameters. Registers must cleared user after powerup proper device operation. Registers through reserved proprietary functions must addressed during operation. following sections describe these registers detail.
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Microprocessor Interface (continued)
Microprocessor Interface Register Architecture (continued)
Table Register
Designation Address
Alarm Registers (Read Only) 0000 0001 LOTC2 LOTC4 TDM2 TDM4 DLOS2 DLOS4 ALOS2 ALOS4 LOTC1 LOTC3 TDM1 TDM3 DLOS1 DLOS3 ALOS1 ALOS3
Alarm Mask Registers (Read/Write) 0010 0011 MLOTC2 MLOTC4 MTDM2 MTDM4 MDLOS2 MDLOS4 MALOS2 MALOS4 MLOTC1 MLOTC3 MTDM1 MTDM3 MDLOS1 MDLOS3 MALOS1 MALOS3
Global Control Registers (Read/Write) 0100 0101 HIGHZ4 LOSSD HIGHZ3 HIGHZ2 HIGHZ1 ICTMODE DUAL CODE LOSSTD SWRESET GMASK
Channel Configuration Registers (Read/Write) 12-15 0110 0111 1000 1001 1010 1011 1100-1111 EQA1 EQA2 EQA3 EQA4 EQB1 EQB2 EQB3 EQB4 EQC1 EQC2 EQC3 EQC4 LOOPA1 LOOPA2 LOOPA3 LOOPA4 RESERVED LOOPB1 LOOPB2 LOOPB3 LOOPB4 TBS1 TBS2 TBS3 TBS4 MASK1 MASK2 MASK3 MASK4 PWRDN1 PWRDN2 PWRDN3 PWRDN4
Notes: numerical suffix appended name identifies channel number. Bits shown parentheses indicate state forced during reset condition. registers must configured user before device operate required particular application. Register register must written after powerup device. Registers 12-15 reserved should written. they written they must always written with
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Microprocessor Interface (continued)
Microprocessor Interface Register Architecture (continued)
Alarm Register Overview (0000, 0001) bits alarm registers represent status transmitter receiver alarms LOTC, TDM, DLOS, ALOS four channels shown Table alarm indicators active-high automatically clear microprocessor read corresponding alarm condition longer exists. Persistent alarm conditions will cause remain set. These read-only registers. Table Alarm Registers Bits Symbol* ALOS[1:2] DLOS[1:2] TDM[1:2] LOTC[1:2] Description
Alarm Register Analog loss signal alarm channels Digital loss signal alarm channels Transmit driver monitor alarm channels Loss transmit clock alarm channels Alarm Register ALOS[3:4] Analog loss signal alarm channels DLOS[3:4] Digital loss signal alarm channels TDM[3:4] Transmit driver monitor alarm channels LOTC[3:4] Loss transmit clock alarm channels
numerical suffix identifies channel number.
Alarm Mask Register Overview (0010, 0011) bits alarm mask registers Table allow microprocessor selectively mask each channel alarm prevent from generating interrupt. mask bits correspond alarm status bits alarm registers active-high disable corresponding alarm from generating interrupt. These registers read/write registers. Table Alarm Mask Registers Bits Symbol* MALOS[1:2] MDLOS[1:2] MTDM[1:2] MLOTC[1:2] MALOS[3:4] MDLOS[3:4] MTDM[3:4] MLOTC[3:4] Description Alarm Mask Register Mask analog loss signal alarm channels Mask digital loss signal alarm channels Mask transmit driver monitor alarm channels Mask loss transmit clock alarm channels Alarm Mask Register Mask analog loss signal alarm channels Mask digital loss signal alarm channels Mask transmit driver monitor alarm channels Mask loss transmit clock alarm channels
numerical suffix identifies channel number.
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Microprocessor Interface (continued)
Microprocessor Interface Register Architecture (continued)
Global Control Register Overview (0100, 0101) bits global control registers Table Table allow microprocessor configure various device functions over four channels. control bits (with exception LOSSTD ICTMODE) active-high. These read/write registers. Table Global Control Register (0100) Symbol GMASK Description Global Control Register GMASK globally masks channel alarms when GMASK preventing receiver transmitter alarms from generating interrupt. GMASK after device reset. SWRESET provides same function hardware reset. used device initialization through microprocessor interface. software reset must cleared after powerup prior writing other bits register LOSSTD selects conformance protocol DLOS receiver alarm function. ICTMODE changes function pin. ICTMODE after device reset. HIGHZ available each individual channel. When HIGHZ TTIP TRING transmit drivers specified channel placed high-impedance state. HIGHZ[1:4] after device reset.
SWRESET
LOSSTD ICTMODE HIGHZ[1:4]
Table Global Control Register (0101) Symbol Description Global Control Register used enable disable clock/data recovery function. used enable disable jitter attenuator function receive path. control bits mutually exclusive; i.e., either control set, both. used enable disable jitter attenuator function transmit path. control bits mutually exclusive; i.e., either control should set, both. CODE used enable disable B8ZS/HDB3 zero substitution coding (decoding) transmit (receive) path. used conjunction with DUAL valid only single-rail operation. DUAL used select single dual-rail mode operation. selects transmit receive data polarity (i.e., active-low active-high). bits used together determine transmit receive data retiming modes. selects positive negative edge receive clock (RCLK[1:4]) receive data retiming. bits used together determine transmit receive data retiming modes. LOSSD selects shutdown function digital loss signal alarm (DLOS). Lucent Technologies Inc.
CODE
DUAL
LOSSD
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Microprocessor Interface (continued)
Microprocessor Interface Register Architecture (continued)
Channel Configuration Register Overview (0110-1001) control bits channel configuration registers Table used select equalization, loopbacks, generation, channel alarm masking, channel powerdown mode each channel (1-4). PWRDN[1-4], MASK[1-4], TBS[1-4] bits active-high. These read/write registers. Table Channel Configuration Registers Symbol* PWRDN[1:4] MASK[1:4] TBS[1:4] LOOPB[1:4] LOOPA[1:4] EQC[1:4], EQB[1:4], EQA[1:4] Description Channel Configuration Registers (6-9) PWRDN powers down channel when used. MASK masks interrupts channel. enables transmission signal line interface. LOOPB LOOPA bits select channel loopback modes. EQC, EQB, bits select type service (DS1 CEPT) associated transmitter cable equalization/termination impedances.
numerical suffix identifies channel number. Channel suffix shown description.
Other Registers bits registers must cleared microprocessor after device powerup.
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Microprocessor Interface (continued)
Timing
timing specifications microprocessor interface given Table microprocessor interface pins CMOS levels. outputs, except address/data AD[7:0], rated capacitive load AD[7:0] outputs rated load. minimum read write cycle time device configurations. Table Microprocessor Interface Timing Specifications Setup (ns) (Min)
Modes Address Valid Asserted (Read, Write) Asserted Address Invalid (Read, Write) Asserted Asserted High (Read) Asserted Asserted (Read, Write) DTACK Asserted
DTACK Asserted Data Valid (Read) Asserted (Read) Data Valid Negated (Read, Write) Negated Negated (Read) Data Invalid Negated (Read) DTACK Negated (Read, Write) Asserted Width (Read) Asserted Width Asserted (Write) (Write) Asserted
Symbol
Configuration
Parameter
Hold (ns) (Min)
Delay (ns) (Max)
Data Valid Negated (Write)
Negated DTACK Negated (Write) Negated Data Invalid (Write) (Write) Asserted Width Address Valid Asserted (Read, Write)
Modes
Asserted (Read, Write) Address Invalid Asserted Asserted (Read)
Asserted (Read) Data Valid Asserted (Read) Asserted Negated Data Invalid (Read) Negated Negated (Read)
Asserted Asserted (Write) Asserted Asserted Data Valid Negated (Write) Asserted (Write) Asserted
Negated Negated (Write) Negated Data Invalid
Asserted (Read, Write) Width Asserted (Read) Width Asserted (Write) Width
read write timing diagrams four microprocessor interface modes shown Figures 5-12.
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Microprocessor Interface (continued)
Timing (continued)
MINIMUM READ CYCLE
A[3:0] VALID ADDRESS
DTACK AD[7:0] VALID DATA
5-3685(C)r.3
Figure Mode 1-Read Cycle Timing (MPMODE MPMUX
MINIMUM WRITE CYCLE
A[3:0] VALID ADDRESS
DTACK AD[7:0] VALID DATA
5-3686(C)r.3
Figure Mode 1-Write Cycle Timing (MPMODE MPMUX Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Microprocessor Interface (continued)
Timing (continued)
MINIMUM READ CYCLE DTACK AD[7:0] VALID DATA VALID ADDRESS VALID DATA VALID ADDRESS
5-3687(C)r.4
Figure Mode 2-Read Cycle Timing (MPMODE MPMUX
MINIMUM WRITE CYCLE
DTACK AD[7:0] VALID DATA VALID ADDRESS VALID DATA VALID ADDRESS
5-3688(C)r.4
Figure Mode 2-Write Cycle Timing (MPMODE MPMUX
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Microprocessor Interface (continued)
Timing (continued)
MINIMUM READ CYCLE
A[3:0] AD[7:0] VALID DATA VALID ADDRESS
5-3689(C)r.3
Figure Mode 3-Read Cycle Timing (MPMODE MPMUX
MINIMUM WRITE CYCLE
A[3:0] AD[7:0] VALID DATA
5-3690(C)r.3
VALID ADDRESS
Figure Mode 3-Write Cycle Timing (MPMODE MPMUX
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Microprocessor Interface (continued)
Timing (continued)
MINIMUM READ CYCLE AD[7:0] VALID DATA
5-3691(C)r.4
VALID DATA
VALID ADDRESS
VALID ADDRESS
Figure Mode 4-Read Cycle Timing (MPMODE MPMUX
MINIMUM WRITE CYCLE AD[7:0] VALID DATA
5-3692(C)r.4
VALID DATA
VALID ADDRESS
VALID ADDRESS
Figure Mode 4-Write Cycle Timing (MPMODE MPMUX
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
XCLK Reference Clock
device requires high-frequency reference clock both clock/data recovery jitter attenuation options (CDR XCLK signal (pin conditionally required MPCLK signal (pin supplied interrupt generation microprocessor interface. other device configuration, XCLK required. required, XCLK must continuously active (i.e., ungapped, unjittered, unswitched) independent reference clock such external system oscillator system clock proper operation. must derived from recovered line clock (i.e., from RCLK synthesized frequency RCLK). specifications XCLK defined Table Table XCLK Timing Specifications Parameter Frequency CEPT Range Duty Cycle Value -100 24.704 32.768 Unit
Power Supply Bypassing
External bypassing required channels. capacitor must connected between VDDX GNDX. addition, capacitor must connected between VDDD GNDD, capacitor must connected between VDDA GNDA. Ground plane connections required GNDX, GNDD, GNDA. Power plane connections also required VDDX VDDD. need reduce high-frequency coupling into analog supply (VDDA) require inductive bead inserted between power plane VDDA every channel. External bypassing also required microprocessor power supply pins. capacitor must connected between every pair VDDC GNDC pins. VDDC GNDC connected directly power ground planes, respectively. Capacitors used power supply bypassing should placed close possible device pins maximum effectiveness.
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
T7690 External Line Termination Circuitry
transmit receive tip/ring connections provide matched interface cable (i.e., terminating impedance matches characteristic impedance cable). diagram Figure shows appropriate external components interface cable single transmit/receive channel. component values summarized Table based specific application.
EQUIPMENT INTERFACE RECEIVE DATA TRANSFORMER RRING DEVICE CHANNEL) TRANSMIT DATA TRING TTIP RTIP
5-3693(C).d
Figure External Line Termination Circuitry Table Termination Components Application* Cable Type Symbol Name Twisted Pair 71.5 1.14 CEPT Coaxial Option 28.7 82.5 26.1 1.08 Option 15.4 1.36 CEPT Twisted Pair 26.1 1.36 Unit
Center Capacitor Receive Primary Impedance Receive Series Impedance Receive Secondary Impedance Equivalent Line Termination Tolerance Transmit Series Impedance Transmit Load Termination Transformer Turns Ratio
Resistor tolerances ±1%. Transformer turns ratio tolerances ±2%. CEPT applications, option recommended over option lower device power dissipation. Table shows power option option increases power dissipation channel when driving ones data. Option allows same transformer used CEPT applications. tolerance allowed transmit load termination.
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
T7693 External Line Termination Circuitry
transmit receive tip/ring connections provide matched interface cable (i.e., terminating impedance matches characteristic impedance cable). diagram Figure shows appropriate external components interface cable single transmit/receive channel. component values summarized Table based specific application.
EQUIPMENT INTERFACE RECEIVE DATA TRANSFORMER RRING DEVICE CHANNEL) TRANSMIT DATA TRING TTIP RTIP
5-3693(C).dr.1
Figure External Line Termination Circuitry Table Termination Components Application* Cable Type Symbol Name Twisted Pair CEPT Coaxial Option 1.91 Option 5.36 2.42 CEPT Twisted Pair 2.42 Unit
Center Capacitor Receive Primary Impedance Receive Series Impedance Receive Secondary Impedance Equivalent Line Termination Tolerance Transmit Series Impedance Transmit Load Termination Transformer Turns Ratio
Resistor tolerances ±1%. Transformer turns ratio tolerances ±2%. CEPT applications, option recommended over option lower device power dissipation. Table shows power option option increases power dissipation channel when driving ones data. Option allows same transformer used CEPT applications. tolerance allowed transmit load termination.
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Absolute Maximum Ratings
Stresses excess absolute maximum ratings cause permanent latent damage device. These absolute stress ratings only. Functional operation device implied these other conditions excess those given operational sections this device specification. Exposure absolute maximum ratings extended periods adversely affect device reliability. Table Absolute Maximum Ratings Parameter Supply Voltage Storage Temperature Maximum Voltage (digital pins) with Respect VDDD Minimum Voltage (digital pins) with Respect GNDD Maximum Allowable Voltages (RTIP[1-4], RRING[1-4]) with Respect Minimum Allowable Voltages (RTIP[1-4], RRING[1-4]) with Respect -0.5 -0.5 -0.5 Unit
Handling Precautions
Although protection circuitry been designed into this device, proper precautions should taken avoid exposure electrostatic discharge (ESD) during handling mounting. Lucent employs human-body model (HBM) charged-device model (CDM) ESD-susceptibility testing protection design evaluation. voltage thresholds dependent circuit parameters used defined model. industry-wide standard been adopted CDM. However, standard (resistance 1500 capacitance widely used and, therefore, used comparison purposes. threshold presented here obtained using these circuit parameters. Table Threshold Voltage Device T7690 T7693 Voltage >1500 >1000
Operating Conditions
Table Recommended Operating Conditions Parameter Ambient Temperature T7690 Power Supply T7693 Power Supply* Symbol 4.75 3.135 5.25 3.465 Unit
Required under loading conditions. Each single transmit pulse requires current spike from power supply approximately Circuit pack routing should minimize impedance.
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Operating Conditions (continued)
Table Power Specifications (For T7690: T7693: Device power specification includes power line specified data ones density. Parameter Channel:* (transmit, receiver data slicing mode, jitter attenuator) (transmit, receiver clock recovery mode, jitter attenuator) (transmit, receiver clock recovery mode, jitter attenuator active) During Powerdown Mode (PWRDN Quad Total: Typical T7690 CEPT T7693 970** CEPT 720** Unit
single channel (receive transmit paths) ones density data. standby purposes. channel will never used, connecting pins ground plane recommended, resulting power consumption. nominal VDD, Every function channel operational with ones density. 5.25 Every function channel operational with 100% ones density. 3.465 Every function channel operational with 100% ones density.
Timing Characteristics
Table Logic Interface Characteristics internal pull-up provided RESET pins. internal pull-up provided XCLK, BCLK pins. This requires these input pins sink more than buffers CMOS levels. Parameter Input Voltage: High Input Leakage Output Voltage: High Input Capacitance Load Capacitance*
allowed AD[7:0] (pins 76).
Symbol
Test Conditions
GNDD GNDD
VDDD
Unit
-5.0
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
Timing Characteristics (continued)
Table Interface Data Timing digital system interface timing shown Figure then RCLK signal Figure will inverted. Symbol tTCLTCL Parameter Average TCLK Clock Period: CEPT TCLK Duty Cycle* TCLK Minimum High/Low Time Transmit Data Setup Time Transmit Data Hold Time Clock Rise Time (10%/90%) Clock Fall Time (90%/10%) RCLK Duty Cycle Receive Data Setup Time Receive Data Hold Time Receive Propagation Delay 647.7 488.0 Unit
tTDC tTDVTCL tTCLTDX tTCH1TCH2 tTCL2TCL1 tRCHRCL tRDVRCH tRCHRDX tRCLRDV
Refers each individual period applications. Refers each individual period applications using gapped TCLK.
tTCLTCL TCLK tTDVTCL tTCLTDX TPDATA TNDATA tRCLRDV RCLK* tRDVRCH tRCHRDX RPDATA RNDATA
tTCH1TCH2
tTCL2TCL1
5-1156(C)r.5
Invert RCLK
Figure Interface Data Timing (ACM
Lucent Technologies Inc.
Data Sheet 1998
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Outline Diagram
100-Pin BQFP
Dimensions millimeters.
22.860 0.305 22.350 0.255 19.050 0.405
0.255
IDENTIFIER ZONE EDGE CHAMFER 22.350 0.255 19.050 0.405 22.860 0.305
GAGE PLANE SEATING PLANE 0.91/1.17
DETAIL
0.175 0.025 0.280 0.075 0.150
DETAIL
DETAIL
DETAIL
4.570 3.555 0.255 SEATING PLANE 0.10
0.635
0.760 0.255
5-1970(C).r10
Ordering Information
Device Code 7690 FL-DB 7693 FL-DB Package 100-Pin BQFP 100-Pin BQFP Temperature Comcode (Ordering Number) 107202434 107202723
Lucent Technologies Inc.
T7690 T1/E1 Quad Line Interface T7693 T1/E1 Quad Line Interface
Data Sheet 1998
DS98-233TIC Replaces DS97-098TIC Include Following Updates
Page Table Global Control Register (0100), added register address table title. Page Table Global Control Register (0101), added register address table title. Page Channel Configuration Register Overview (0110-1001), corrected register address section heading. Pages Figure Figure External Line Termination Circuitry, updated transformer. Page corrected Device Codes T7693 Comcode (Ordering Number).
additional information, contact your Microelectronics Group Account Manager following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com AMERICA: Microelectronics Group, Lucent Technologies Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Fong Universe Building, 1800 Zhong Shan Road, Shanghai 200233 China Tel. (86) 6440 0468, ext. 316, (86) 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 299, (44) 1189 Technical Inquiries: GERMANY: (49) 95086 (Munich), UNITED KINGDOM: (44) 1344 (Bracknell), FRANCE: (33) (Paris), SWEDEN: (46) 7070 (Stockholm), FINLAND: (358) 4354 2800 (Helsinki), ITALY: (39) 6608131 (Milan), SPAIN: (34) 1441 (Madrid)
Lucent Technologies Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. rights under patent accompany sale such product(s) information.
Copyright 1998 Lucent Technologies Inc. Rights Reserved Printed U.S.A.
1998 DS98-233TIC (Replaces DS97-098TIC)

T7690 T1/E1 Quad Line Interface, T7693 T1/E1 Quad Line Interface (DS98

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