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T7289A DS1 Line Interface

T7289A DS1 Line Interface

Data Sheet January 1998
T7289A DS1 Line Interface
Features
Description
The Lucent Technologies Microelectronics Group T7289A DS1 Line Interface is an integrated circuit that provides a line interface between the DS1 cross connect (DSX) and terminal equipment circuits for cable distances of up to 655 ft. for 22-gauge, plastic, insulated cable (PIC). The T7289A device performs receive-pulse regeneration, timing recovery, and transmit-pulse shaping and equalization functions. The device is manufactured by using low-power CMOS technology and is available in a 28-pin, plastic DIP or in a 28-pin, plastic SOJ package. The T7289A device is functionally compatible with the T7289, LC1046A, and LC1046C devices for 1.544 Mbits / s operation but provides improved jitter transfer and crosstalk characteristics with a selectable single-rail / dual-rail system interface.
Fully integrated DS1 line interface Intended for use in systems that must comply with PUB 43802, CB119, TR-TSY-000170, and TRTSY-000499 (Category I equipment) Low power dissipation On-chip transmit equalization Monolithic clock recovery High jitter accommodation Excellent transmit template performance Single-rail / dual-rail interface Pin-selectable B8ZS encoder and decoder (during single-rail mode only) Loopback modes for fault isolation Multiple link-status and alarm features Minimal external circuitry required
T7289A DS1 Line Interface
Data Sheet January 1998
Description (continued)
LINE LENGTH SELECT INSERT BLUE SIGNAL
TRANSMIT LINE
OUTPUT DRIVERS
SELECTABLE PULSE EQUALIZATION
B8ZS ENCODER AND RAIL CONVERSION
TRANSMIT DATA
LOOPBACKS
TRANSMIT CLOCK
RECEIVE LINE
RECEIVE ANALOG INPUT
CLOCK EXTRACTION & RETIMING
B8ZS DECODER AND BPV DETECTION AND RAIL CONVERSION
RECEIVED DATA
LOSS OF SIGNAL
RECEIVED CLOCK SINGLE-RAIL / DUAL-RAIL SELECT BIPOLAR VIOLATION ALARM
5-4348(C)
Figure 1. T7289A Block Diagram
Pin Information
LOS LOC BZSC / TNDATA BPV / RNDATA RCLK RDATA / RPDATA TCLK TDATA / TPDATA LP1 LP2 LP3 ALMT RBC TBC 1 2 3 4 5 6 28 27 26 25 24 23 T1 R1 SD GNDA VDDA DUAL T2 VDDD R2 GNDD EC1 EC2 EC3 BCLK
5-4349(C)
7 T7289A-PL 22 8 T7289A-EL 21 9 10 11 12 13 14 20 19 18 17 16 15
Figure 2. Pin Diagram
Lucent Technologies Inc.
Data Sheet January 1998
T7289A DS1 Line Interface
Pin Information (continued)
Table 1. Pin Descriptions This table refers to a cleared pin as low (0) and a set pin as high (1). Pin 1 2 Symbol
LOS LOC
Type Ou Ou
BZSC / TNDATA
BPV / RNDATA
RCLK RDATA / RPDATA
TCLK TDATA / TPDATA
Lucent Technologies Inc.
T7289A DS1 Line Interface
Data Sheet January 1998
Pin Information (continued)
BCLK EC3 EC2 EC1 GNDD R2 VDDD T2 DUAL VDDA GNDA SD
Table 2. Equalizer Control Other bit combinations represent test modes not to be used for normal operation. Distance to DSX (Ft.) (Applies Only to 22-gauge PIC ABAM Cable) 0-133 133-267 267-400 400-533 533-655 Maximum Cable Loss (dB at 772 kHz) EC1 EC2 EC3
Use maximum loss figures for other cable types.
Lucent Technologies Inc.
Data Sheet January 1998
T7289A DS1 Line Interface
Overview
The T7289A device is a fully integrated DS1 line interface that requires only two line-interface transformers and three input termination resistors to provide a bidirectional line interface between a DS1 cross connect (DSX) and terminal equipment. A typical application diagram is shown in Figure 3. This device is specified for use with 22-gauge, plastic-insulated ABAM cable, as well as other cable types. The circuit is divided into three main blocks: transmit converter, receive converter, and logic. The transmit and receive converters process information signals through the device in the transmit and receive directions, respectively the logic is the control and status interface for the device.
RECEIVED DATA T1 500 200 500 1:2 VDDD RECEIVE INPUT R1 +5 V 1 µF GNDD GNDA T2 100 LOAD TRANSMIT OUTPUT R2 1.14:1 (DS1)
5-4350(C)
RDATA / RPDATA BPV / RNDATA RCLK
TRANSMITTED DATA
T7289A DS1 LINE INTERFACE
TDATA / TPDATA BZSC / TNDATA TCLK
Note: Lucent 2745 family pulse transformers for through-hole mounting or Lucent 2758 family pulse transformers for surface mounting are recommended.
Figure 3. Typical Application Diagram for Bipolar Signal Interfacing
Lucent Technologies Inc.
T7289A DS1 Line Interface
Data Sheet January 1998
The output pulse waveform consists of four distinct levels: overshoot, pulse, backswing, and tail. They are produced by a high-speed D / A converter and are driven onto the line by using low-impedance output buffers. There are five different pulse shapes, corresponding to 133-ft. increments of cable, that are obtained by setting the appropriate equalizer control inputs. The positive and negative pulses meet the amplitude, rise and fall time, overshoot, undershoot, template, and power requirements for the office DSX cross connect as given in Compatibility Bulletin 119 (CB119). A typical DS1 output waveform at the DSX relative to the CB119 template is shown in Figure 4. The analog circuitry is shown in Figure 5. The clock multiplier shown in Figure 5 produces the high-speed timing waveforms needed by the D / A converter. The clock multiplier also eliminates the need for the tightly controlled transmit clock duty cycle usually required in discrete implementations. Transmitter specifications are given in Table 7.
Transmit Converter
The line-interface transmission format is return-to-zero, bipolar alternate mark inversion (AMI), requiring transmission and sensing of alternately positive and negative pulses. During single-rail operation, the transmit converter accepts unipolar data at TDATA and converts the signal to a balanced bipolar data signal. Binary 1s in the TDATA data stream become pulses of alternating polarity transmitted between the two output rails, T2 and R2. For dual-rail operation, a binary 1 on TPDATA results in the transmission of a positive pulse between T2 and R2, and a binary 1 on TNDATA results in a negative pulse. Binary 0s are transmitted as null pulses. All necessary transmit pulse shaping is done on-chip, eliminating the need for external shaping networks. This is done by shaping the pulses at the bipolar output (T2, R2) according to the selected equalizer control (EC1-EC3) inputs (see Table 2).
NORMALIZED AMPLITUDE (V)
1.0 CB119 TEMPLATE
0 T7289A OUTPUT PULSE SHAPE 0 250 500 750 1000 1250
5-4351(C)
TIME (ns)
Figure 4. Typical T7289A Output Waveform at DSX
Lucent Technologies Inc.
Data Sheet January 1998
T7289A DS1 Line Interface
Transmit Converter (continued)
LP1 LOS SD
ANALOG SIGNAL DETECTOR T1 R1 RECEIVER ANALOG INPUT PDATA NDATA RPDATA M U X DATA / CLOCK RNDATA RECOVERY RCLK
DIGITAL SIGNAL DETECTOR
RDATA / RPDATA BPV / RNDATA RCLK TRANSMIT AND RECEIVE LOGIC TDATA / TPDATA BZSC / TNDATA TCLK
TP DATA T2 R2 TRANSMIT OUTPUT DRIVERS D / A SELECTABLE PULSE EQUALIZATION TN DATA
4 TIMING SIGNALS
CLOCK MULTIPLIER
5-4352(C)
Figure 5. T7289A Analog Block Diagram
Receive Converter
For robust operation, the PLL is augmented with a frequency-acquisition capability. The frequency acquisition circuitry is intended to guarantee proper phaselocking during start-up conditions, such as powerup or data activation. Once the T7289A device is phaselocked to data, the frequency-acquisition mode will not be activated. A continuous (i.e., ungapped, unswitched) 1.544 MHz reference clock must be present at TCLK to enable the frequency-acquisition circuitry. However, the receive PLL will operate even in the absence of TCLK. Because the clock output of the receive converter is derived from the ICO, a free-running clock can be present at the output of the receive converter without data being present at the input. A shutdown pin (SD) is provided to block this clock, if desired, to eliminate the free-running clock upon loss of the input signal.
Lucent Technologies Inc.
T7289A DS1 Line Interface
Data Sheet January 1998
The PLL is designed to accommodate large amounts of input jitter with high power supply rejection for operation in noisy environments. Low jitter sensitivity to power supply noise allows compact line-card layouts that employ many line interfaces on one board. The minimum input jitter tolerance, as specified in AT&T Publication 43802, and the measured T7289A device jitter tolerance are shown for the DS1 rate in Figure 6. The data shown is typical for measurement to a BER of 10-6. Subtracting approximately 0.02 U.I. from the given data yields the jitter accommodation for error-free operation. Receiver specifications are shown in Table 8.
Receive Converter (continued)
Loopback 1 Signal x x x x Active No Signal Active No Signal x
Outputs Receive Side Normal Free-running VCO Normal No output Normal loopback Free-running VCO Normal loopback No output Unaffected
Active LOS Detectors Analog and digital Analog and digital Analog and digital Analog and digital Digital only Digital only Digital only Digital only x
Lucent Technologies Inc.
Data Sheet January 1998
T7289A DS1 Line Interface
Receive Converter (continued)
INPUT JITTER AMPLITUDE (U.I. PEAK-TO-PEAK)
MEASURED DATA POINTS 220 - 1 PATTERN 1 / 8 PATTERN JITTER JITTER JITTER JITTER FREQUENCY AMPLITUDE FREQUENCY AMPLITUDE (kHz) (U.I.pp) (kHz) (U.I.pp) 2.0 6.5 20 10 8.0 1.1 8.0 1.8 20 0.66 20 0.7 30 0.52 30 0.45 40 0.49 40 0.45 50 0.48 50 0.45 60 0.48 70 0.48
(10k, 0.3)
(70k, 0.3)
(8k, 0.1)
(50k, 0.1)
JITTER FREQUENCY (kHz)
5-4353(C)
Figure 6. DS1 Jitter Tolerance
Digital Logic
The logic provides alarms, optional B8ZS coding, bluesignal insertion (AIS) circuits, and maintenance loopbacks. It accepts dual-rail or single-rail data patterns.
mode is selected, pin 8 (TDATA / TPDATA) accepts the positive rail transmit data, and pin 3 (BZSC / TNDATA) is reconfigured to accept negative rail transmit data. Pin 6 (RDATA / RPDATA) outputs positive rail receive data, and pin 4 (BPV / RNDATA) is reconfigured to output negative rail receive data. In dual-rail mode, the B8ZS and bipolar violation functions are disabled. For single-rail operation, TDATA is active-high and
RDATA is active-low. For dual-rail operation, TPDATA,
Single-Rail / Dual-Rail Option
To implement the rail-select feature, the dual pin (pin 23) is cleared for single-rail mode and set for dual-rail mode. When single-rail mode is selected, pin 8 (TDATA / TPDATA) accepts transmit data and pin 6 (RDATA / RPDATA) outputs inverted receive data. When dual-rail
TNDATA, RPDATA, and RNDATA are all active-high. This interface scheme is consistent with the dual-rail interfaces of other Lucent Line Interface products.
Lucent Technologies Inc.
T7289A DS1 Line Interface
Data Sheet January 1998
Digital Logic (continued)
Single-Rail / Dual-Rail Option (continued)
Device Anomaly
T7289A-EL, T7289A-PL, T7289A-EL2, and T7289A-PL2
T7289A-EL, T7289A-PL, T7289A-EL2, T7289A-PL2, T7289A-EL3, and T7289A-PL3
The T7289A-EL, T7289A-PL, T7289A-EL2, T7289APL2, T7289A-EL3, and T7289A-PL3 devices have been found to be sensitive to voltage surges on the transmit analog interface leads. The device may latch-up when excessive voltage surges are present on the line. The device must be power-cycled to clear the condition. The immunity to voltage surges has been enhanced in the T7289A-EL4 and T7289A-PL4. Lucent Technologies Inc.
Data Sheet January 1998
T7289A DS1 Line Interface
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter dc Supply Voltage Range Power Dissipation Storage Temperature Range Symbol VDD Pdis Tstg Min -0.5 - -65 Max 6.5 500 125 Unit V mW °C
Handling Precautions
Electrical Characteristics
Operating Conditions
Lucent Technologies Inc.
T7289A DS1 Line Interface
Data Sheet January 1998
Electrical Characteristics (continued)
Operating Conditions (continued)
Below the power at 772 kHz. Total power difference.
Min 2.4 333 12.6 -29 - - 95 1:1.12 35 25 8
Typ 3.0 350 16.5 -39 - - 100 1:1.14 - - -
Max 3.6 362 17.9 - 0.5 50 105 1:1.16 - - -
Unit V ns dBm dB dB ns - dB dB dB
Lucent Technologies Inc.
Data Sheet January 1998
T7289A DS1 Line Interface
Electrical Characteristics (continued)
Operating Conditions (continued)
Input Density (1s) ICO Free-running Frequency Error Input Transformer Turns Ratio Input Termination Input Resistance, R1 or T1
Minimum sensitivity (maximum cable loss limit) occurs when the frequency of Vac is near the clock rate.
Timing Characteristics
All duty cycle and timing relationships are referenced to a TTL 1.4 V threshold level.
Loss-of-Clock Indication Timing
Lucent Technologies Inc.
T7289A DS1 Line Interface
Data Sheet January 1998
Timing Characteristics (continued)
Loss-of-Clock Indication Timing (continued)
tTCLTCL TCLK tr tf
TDATA OR TPDATA TNDATA tTDVTCL tTCLTDV
tRCLRDV RCLK
tRDVRCH BPV / RDATA OR RPDATA RNDATA tRCHRDV
5-4361(C)
Figure 7. Timing Diagram (Single-Rail or Dual-Rail)
Lucent Technologies Inc.
Data Sheet January 1998
T7289A DS1 Line Interface
Outline Diagrams
28-Pin, Plastic DIP
Dimensions are in millimeters.
1 PIN #1 IDENTIFIER ZONE W
H SEATING PLANE 0.38 MIN 2.54 TYP 0.023 MAX
5-4410.R1
Number of Pins (N) 28
Package Dimensions (DIP) Maximum Length Including Leads (L) 37.34 Maximum Width Without Leads (B) 13.97 Maximum Width Including Leads (W) 15.49 Maximum Height Above Board (H) 5.59
Lucent Technologies Inc.
T7289A DS1 Line Interface
Data Sheet January 1998
Outline Diagrams (continued)
28-Pin, Plastic SOJ
Dimensions are in millimeters.
1 PIN #1 IDENTIFIER ZONE W
H SEATING PLANE 0.10 1.27 TYP 0.020 MAX 0.64 MIN
5-4413.R1
Number of Pins (N) 28
Package Dimensions (SOJ) Maximum Length Including Leads (L) 18.03 Maximum Width Without Leads (B) 7.62 Maximum Width Including Leads (W) 8.81 Maximum Height Above Board (H) 3.18
Ordering Information
Device Code T - 7289A - - - PL4 T - 7289A - - - EL4 Package 28-Pin DIP 28-Pin SOJ Temperature -40 °C to +85 °C -40 °C to +85 °C Comcode (Ordering Number) 107056699 107056673
Lucent Technologies Inc.
Data Sheet January 1998
T7289A DS1 Line Interface
DS97-196TIC Replaces DS92-072SMOS Catalog CA95-003TIC Version to Incorporate the Following Updates
1. Data sheet format. 2. Note: CA95-003TIC version of data sheet had device advisory AY93-025TCOM incorporated in it.
Lucent Technologies Inc.
T7289A DS1 Line Interface Interactive Terminal Transmission Convergence
Preliminary Data Sheet January 1998
For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com / micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 For data requests in Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 324 299, FAX (44) 1734 328 148 For technical inquiries in Europe: CENTRAL EUROPE: (49) 89 95086 0 (Munich), NORTHERN EUROPE: (44) 1344 865 900 (Bracknell UK), FRANCE: (33) 1 41 45 77 00 (Paris), SOUTHERN EUROPE: (39) 2 6601 1800 (Milan) or (34) 1 807 1700 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
January 1998 DS97-196TIC (Replaces DS92-072SMOS)
Printed On Recycled Paper