Single-rail/dual-rail interface compatible with LC1135B device Fu
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T7288 CEPT/E1 Line Interface
Single-rail/dual-rail interface compatible with LC1135B device
Fully integrated 2.048 Mbits/s line interface Intended systems that must comply with ITU-T specifications G.703, G.823, I.431, G.732, G.735-G.739 Pin-selectable operation Monolithic clock recovery power dissipation: twisted pair, typical coaxial, typical Minimal external circuitry required Robust frequency acquisition/phase-locked loop Pin-selectable HDB3 encoder decoder Loopback modes fault isolation Multiple link-status alarm features
Description
Lucent Technologies Microelectronics Group T7288 CEPT/E1 Line Interface integrated circuit that provides 2.048 Mbits/s line interface either twisted-pair coaxial cable specified ITU-T requirements G.703, G.823, I.431, G.732, G.735-G.739. device performs receive pulse regeneration, timing recovery, transmit pulse driving functions. T7288 device manufactured using low-power CMOS technology available 28-pin, plastic 28-pin, plastic package surface mounting. T7288 device functionally compatible with LC1135B device. digital circuitry shown Figure analog circuitry shown Figure
HDB3/TNDATA HDB3 CODE VIOLATION DETECTION
SR/DR
BIPOLAR VIOLATION DETECTION
RECEIVE LOSS CLOCK DETECTION
DUAL-TOSINGLERAIL CONVERTER
HDB3 DECODER
RDATA/ RPDATA
BLUE SIGNAL (AIS) GENERATOR
VIO/ RNDATA
RCLK
SR/DR
HDB3/TNDATA
SINGLE-TODUALRAIL CONVERTER
TRANSMIT
ENCODER
TDATA/ TPDATA
BLUE (AIS) SIGNAL GENERATOR
HDB3/ TNDATA
TCLK OUPUT DRIVERS LOGIC OUPUT DRIVERS LOGIC
ANALOG FUNCTIONS BCLK
ANALOG FUNCTIONS
ALMT
VDDA
GNDD
GNDA
5-4343(C)
Figure Digital Block Diagram
T7288 CEPT/E1 Line Interface
Information
HDB3/TNDATA VIO/RNDATA RCLK RDATA/RPDATA TCLK TDATA/TPDATA ALMT GNDA VDDA VDDD GNDD SR/DR BCLK
5-4344(C)
T7288-PL T7288-EL
Figure Diagram Table Descriptions Symbol
Type
Name/Function Loss Signal (Active-Low). This cleared upon loss data signal receiver inputs. Loss Clock (Active-Low). This cleared when indicating that loss clock occurred. When transitions occur RCLK either RDATA (for single-rail operation) RPDATA RNDATA (for dual-rail operation) outputs. valid clock must present BCLK this function operate properly. HDB3 Enable/N-Rail Transmit Data. SR/DR this insert HDB3 substitution code transmit side remove substitution code receive side. SR/DR this used n-rail transmit input data (internal pull-down included). Violation/N-Rail Receive Data. SR/DR HDB3 bipolar violations receive-side input detected, causing set; HDB3 HDB3 code violations cause set. SR/DR this used n-rail receive output data. Receive Clock. Output receive clock signal terminal equipment. Receive Data/P-Rail Receive Data. SR/DR this used 2.048 Mbits/s unipolar output data with 100% duty cycle. SR/DR this used p-rail receive output data. Transmit Clock. Input clock signal (2.048 ppm). Transmit Data/P-Rail Transmit Data. SR/DR this used 2.048 Mbits/s unipolar input data. SR/DR this used p-rail transmit input data.
HDB3/ TNDATA
VIO/RNDATA
RCLK RDATA/ RPDATA TCLK TDATA/ TPDATA
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Information (continued)
Table Descriptions (continued) Symbol
Type
Name/Function Loopback Enable (Active-Low). This cleared full local loopback (transmit converter output receive converter input). Most transmit receive analog circuitry exercised this loopback (internal pull-up included). Loopback Enable (Active-Low). This cleared remote loopback. loopback high (pin inserts blue signal (AIS) transmit side (internal pull-up included). Loopback Enable (Active-Low). This cleared digital local loopback. Only transmit receive digital sections exercised this loopback (internal pull-up included). Alarm Test Enable (Active-Low). This cleared, forcing testing without affecting data transmission (internal pullup included). Receive Blue Control. This insert blue signal (AIS) receive side (internal pull-down included). Transmit Blue Control. This insert blue signal (AIS) transmit side. This control priority over loopback both operated (internal pull-down included). Blue Clock. Blue clock (AIS) input signal (2.048 ppm). This clock independent transmit clock. Single-Rail (Active-Low)/Dual-Rail Operation. (internal pulldown included), single-rail operation selected; SR/DR dual-rail operation selected (see Tables 4-6). Framer Logic Mode. (internal pull-down included), logic mode operation occurs. logic mode operation occurs (see Tables 4-6). Connection. Test manufacturing purposes only. This must left floating tied GNDD. Digital Ground.
ALMT
BCLK
SR/DR
GNDD VDDD VDDA GNDA
Transmit Bipolar Ring. Negative bipolar transmit output. Digital Supply (±10%). Transmit Bipolar Tip. Positive bipolar transmit output. Impedance Select. This cleared coaxial cable operation shielded twisted-pair operation (internal pull-down included). Analog Supply (±10%). Analog Ground.
Shutdown Enable. this high, loss-of-signal detection (LOS forces causes following (see Table single-rail operation: RCLK high, RDATA low. dual-rail, logic mode operation: RCLK high, RPDATA RNDATA low. dual-rail, logic mode operation: RCLK low, RPDATA RNDATA high (internal pull-down included). Receive Bipolar Ring. Negative bipolar receive input. Receive Bipolar Tip. Positive bipolar receive input.
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Overview
T7288 device fully integrated line interface that requires only transformers, three input termination resistors, output impedance-matching resistors provide bidirectional line interface between 2.048 Mbits/s CEPT/E1 data link terminal equipment. Typical application diagrams shown Figure Figure coaxial cable shielded twisted-pair operation, respectively. circuit divided into three main blocks: transmit converter, receive converter, logic. transmit receive converters process information signals through device transmit receive directions, respectively; logic control status interface device. Figure Figure include matched-impedance transmit-interface section order match output impedance transmitter line. Table G.703/CH-PTT specifications transmit-interface return loss.
RECEIVED DATA VDDD RECEIVE INPUT GNDD GNDA LOAD 15.4 1.36:1
5-4345(C)r.2
RDATA/RPDATA VIO/RNDATA RCLK
TRANSMITTED DATA
MATCHED-IMPEDANCE TRANSMIT INTERFACE 15.4
T7288 CEPT/E1 LINE INTERFACE
VDDA
TRANSMIT OUTPUT
TDATA/TPDATA HDB3/TNDATA TCLK
Note: Lucent 2741 family pulse transformers recommended.
Figure Typical Application Diagram Coaxial Environment
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Overview (continued)
RECEIVED DATA VDDD RECEIVE INPUT RDATA/RPDATA VIO/RNDATA RCLK
TRANSMITTED DATA
MATCHED-IMPEDANCE TRANSMIT INTERFACE 26.1 TRANSMIT OUTPUT 26.1
T7288 CEPT/E1 LINE INTERFACE
VDDA GNDD GNDA
TDATA/TPDATA HDB3/TNDATA TCLK
5-4346(C)r.2
LOAD
1.36:1 Note: Lucent 2741 family pulse transformers recommended.
Figure Typical Application Diagram Shielded Twisted-Pair Environment Table Return Loss (Resistor Tolerance: Transmit Side, Receive Side) Interference Transmit: 2.048 2.048 3.072 Receive: 2.048 2.048 3.072 Unit
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Overview (continued)
Transmit Converter
line-interface transmission format return-to-zero, bipolar alternate mark inversion (AMI), requiring transmission sensing alternately positive negative pulses. transmit converter accepts unipolar data clock converts signal balanced bipolar data signal. Binary data stream become pulses alternating polarity transmitted between output rails, Binary transmitted null pulses. output pulse waveform nominally rectangular. pulses produced high-speed converter driven onto line low-impedance output buffers. positive negative pulses meet ITU-T specification G.703 template requirements. normalized pulse template shown Figure block diagram analog circuitry shown Figure clock multiplier shown Figure uses phase-locked loop (PLL) produce high-speed timing waveforms needed produce well-controlled pulse width. clock multiplier also eliminates need tightly controlled transmit clock duty cycle usually required discrete implementations. Transmitter specifications given Table
(244
100%
(244
NOMINAL PULSE
(244
(244 244)
5-3145(C)
Note: corresponds nominal peak value.
Figure ITU-T G.703 Pulse Template
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Overview (continued)
Transmit Converter (continued)
ANALOG SIGNAL DETECTOR RECEIVER ANALOG INPUT PDATA NDATA DATA/CLOCK RECOVERY RCLK
DIGITAL SIGNAL DETECTOR
RDATA/RPDATA VIO/RNDATA RCLK TRANSMIT RECEIVE LOGIC TDATA/TPDATA HDB3/TNDATA TCLK
TRANSMIT OUTPUT DRIVERS HIGH-SPEED TIMING SIGNALS
CLOCK MULTIPLIER
TCLK
5-4347(C)
Figure T7288 Analog Block Diagram
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
continuously present (i.e., ungapped, unswitched) 2.048 reference clock must present BCLK enable frequency-acquisition circuitry. However, receive will operate even absence 2.048 clock BCLK. 2.048 clock TCLK also used provide 2.048 reference BCLK. Because clock output receive converter derived from ICO, free-running clock present output receive converter without data being present input. shutdown (SD) provided block this clock, desired, eliminate free-running clock upon loss input signal. Both analog digital methods loss-of-signal detection used T7288 device. analog signal detector shown Figure uses output receiver peak detector determine signal present input amplitude drops below 0.25 typical, analog detector output becomes active. Analog loss signal registered, most, several milliseconds after drop signal level, depending variety factors, such initial signal amplitude. Hysteresis (140 typical) provided analog detector eliminate chattering. digital signal detector counts recovered data. more than consecutive occur, digital signal detector becomes active. normal operation, detector outputs ORed together form LOS; however, loopback only digital signal detector used monitor looped signal. Table describes operation shutdown, LOS, functions normal operation loopback designed accommodate large amounts input jitter with high power supply rejection operation noisy environments. jitter sensitivity power supply noise allows compact line-card layouts that employ many line interfaces board. minimum input jitter tolerance, specified ITU-T specification G.823, measured T7288 device jitter tolerance shown Figure Receiver specifications shown Table T7288 device satisfies ITU-T jitter transfer function requirement recommendations G.735-G.739 (see Figure
Overview (continued)
Receive Converter
receive converter accepts bipolar input signals (T1, R1), with maximum loss 1024 kHz, through interconnection cable. received signal rectified while amplitude rise time restored. These input signals peak-detected sliced receiver front end, producing digital signals PDATA NDATA (see Figure Receive decision levels automatically adjusted peak-to-zero signal levels. timing extracted means circuitry that locks internal, freerunning, current-controlled oscillator (ICO) 2.048 component. employs 3-state phase detector lowvoltage/temperature coefficient ICO. freerunning frequency trimmed within ±2.5% data rate wafer probe, with operating conditions, free-running oscillator frequency deviates from data rate less than ±7%, alleviating problem harmonic lock. robust operation, augmented with frequency-acquisition capability. This feature detects recovered clock (RCLK) deviates more than +1.7%/-1.6% frequency from 2.048 reference clock, which must provided BCLK. RCLK frequency within prescribed range BCLK frequency, T7288 device enters training mode which receive input data disconnected from PLL, RCLK frequency steered equal BCLK frequency. After frequency acquisition completed, reconnects receive input data acquire proper phase-lock timing RCLK with respect incoming data. Valid data available when proper phase-lock been achieved. frequency acquisition circuitry intended avoid improper harmonic locking during start-up situations, such powerup data interruption. Once T7288 device phase-locked data, frequency-acquisition mode will activated.
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Overview (continued)
Receive Converter (continued)
Table Shutdown, LOS, Truth Table don't care. Inputs
ALMT Input Signal Loopback
Outputs Signal Active signal Active signal Receive RCLK* Data* Normal Normal Free-running Normal Normal High Normal loopback Normal loopback Free-running Normal loopback Normal loopback High Unaffected Unaffected Active Detectors Analog digital Analog digital Analog digital Analog digital Digital only Digital only Digital only Digital only
Active signal Active signal
These values apply single-rail dual-rail/logic mode dual-rail/logic mode logic-level outputs except looped-back data inverse that shown above. Activated analog loss-of-signal detection. Digital detection forces receive data low. Analog detection merely forces receive data stop transitions; receive data will forced either high with analog detection. All-0s looped-back data, HDB3 operation. Sufficiently sparse looped-back data (not HDB3 encoded) also causes receive freerun; therefore, properly timed loopback data guaranteed.
10.0 2.9) G.823 SPECIFICATION (20, 1.5) (2.4k, 1.5) MEASURED T7288 PERFORMANCE 10-6
INPUT JITTER AMPLITUDE (U.I. PEAK-TO-PEAK)
(18k, 0.2)
MEASURED DATA POINTS JITTER JITTER JITTER JITTER FREQUENCY AMPLITUDE FREQUENCY AMPLITUDE (kHz) (U.I.pp) (kHz) (U.I.pp) 0.45 0.44 0.43 0.67 0.43 0.52 0.43 0.46
(100k, 0.2)
0.01
JITTER FREQUENCY (kHz)
5-4354(C)
Note: Measurement conditions-random data, cable loss, BCLK clock present.
Figure Random Input Data Jitter Tolerance (HDB3 Encoded) Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Overview (continued)
Receive Converter (continued)
G.735-G.739 SPECIFICATION T7288 MEASURED
(36k,
(JOUT/JIN) (dB)
dB/DECADE
(100k, -8.4
FREQUENCY (kHz)
Notes: Equivalent binary content input signal: 1000. Jitter input amplitude U.I. peak-to-peak.
Figure Receive Jitter Transfer Function
Digital Logic
logic provides alarms, optional HDB3 coding, blue signal (AIS) insertion circuits, maintenance loopbacks. also optionally performs dual-rail single-rail conversion data provides alternate logic polarity (logic mode dual-rail mode receive clock receive transmit data. Single-Rail/Dual-Rail Interface Alternate Logic Mode T7288 device supports either single-rail dual-rail operation setting control SR/DR. single-rail mode T7288 receiver converts bipolar input signals (T1, unipolar output signal RDATA. T7288 transmitter converts unipolar input signal TDATA balanced bipolar data signal pins desired, HDB3 control used HDB3 encoding/decoding. Violation information available output VIO.
dual-rail mode T7288 receiver converts bipolar input signals (T1, p-rail n-rail, nonreturn-to-zero output data pins RPDATA RNDATA, respectively. T7288 transmitter converts nonreturn-to-zero p-rail n-rail input data pins TPDATA TNDATA, respectively, balanced bipolar data signal pins dual-rail mode, HDB3 encoding/decoding bipolar violation output functions unavailable. dual-rail mode, alternate-logic polarity mode available control FLM. T7288 device operates logic mode RCLK inverted with respect logic mode input output data (TPDATA, TNDATA, RPDATA, RNDATA) activelow (see Figures 10-13). Internal pull-downs signals SR/DR default operation single-rail, logic mode (see Table
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Overview (continued)
Digital Logic (continued)
Table Rail Interface Logic Mode Options
Single-/Dual-Rail Single Dual Dual
Logic Mode
Default operation (identical with LC1135B) both pins unconnected. illegal option.
Table Single-Rail Operation (Default State)
SR/DR left unconnected internal pull-down circuitry).
Name HDB3/TNDATA VIO/RNDATA RDATA/RPDATA TDATA/TPDATA
Function HDB3 enable LC1135B device violation LC1135B device RDATA receive data LC1135B device TDATA transmit data LC1135B device
Table Dual-Rail Operation
SR/DR
Alarms
Name HDB3/TNDATA VIO/RNDATA RDATA/RPDATA TDATA/TPDATA
Function N-rail transmit input data N-rail receive output data P-rail receive output data P-rail transmit input data
independent loss clock (LOC) output provided that loss clock detected when shutdown option effect. wire-ORed produce single alarm. bipolar violation output included HDB3 giving alarm (VIO) each time violation occurs (two more successive rail). violation alarm output held latch cycle internal clock (RCLK). HDB3 mode, HDB3 code violations detected alarm produced. alarm test (ALMT) provided test alarm outputs, LOS, LOC, VIO. Clearing this forces alarm outputs alarm state without affecting data transmission.
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Overview (continued)
Digital Logic (continued)
HDB3 Option T7288 device contains HDB3 encoder decoder (for single-rail mode only, i.e., SR/DR that selected setting HDB3 pin. This allows encoder substitute zero-substitution code four consecutive detected data stream, illustrated Table represents violation HDB3 code, represents bipolar pulse correct polarity. decoder detects zero-substitution code reinserts four data stream. Case Preceding mark polarity opposite polarity preceding violation violation itself. Case Preceding mark polarity same polarity preceding violation violation itself. Table HDB3 Substitution Code Case Before HDB3 After HDB3 0000 000V Case 0000 B00V
Blue Signal (AIS) Generators There blue signal (AIS) generators this device. (RBC substitutes all-1s signal RDATA output (SR/DR RPDATA RNDATA (SR/DR toward terminal equipment. other (TBC substitutes bipolar, all-1s signal bipolar data transmit converter that used keep line repeaters active. Loopback Paths T7288 device three independent loopback paths that activated clearing respective control inputs, LP1, LP2, LP3. Loopback bridges data stream from transmit converter (transmit converter included) input receive converter. This maintenance loop includes most internal circuitry. Loopback provides loopback data recovered clock from bipolar inputs (T1, bipolar outputs transmit converter (T2, R2). receive front end, receive PLL, transmit driver circuitry exercised. loop used isolate failures between systems. overrides this function. Loopback loops data stream loopback bypasses transmit receive converters. blue signal (AIS) transmitted line when this loopback. Loopbacks operated simultaneously provide transmission loops both directions.
Current Pulses
With other pins grounded, current pulses maximum value time widths allowed T1/R1 T2/R2 pins without damaging device, shown table below. Also, help ensure long-term reliability, average value current-pulse train specified. Table Current Pulses Maximum Value ±200 Width Average Value
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Absolute Maximum Ratings
Stresses excess absolute maximum ratings cause permanent damage device. These absolute stress ratings only. Functional operation device implied these other conditions excess those given operational sections data sheet. Exposure absolute maximum ratings extended periods adversely affect device reliability. Parameter Supply Voltage Power Dissipation Storage Temperature Maximum Voltage (any pin) with Respect Minimum Voltage (any pin) with Respect Maximum Allowable Voltages (T1, with Respect Symbol Tstg -0.5 -0.5 -5.0 Unit
Handling Precautions
Although protection circuitry been designed into this device, proper precautions should taken avoid exposure electrostatic discharge (ESD) during handling mounting. Lucent employs human-body model (HBM) charged-device model (CDM) ESD-susceptibility testing protection design evaluation. voltage thresholds dependent circuit parameters used define model. industry-wide standard been adopted CDM. However, standard (resistance 1500 capacitance widely used therefore used comparison purposes. threshold presented here obtained using these circuit parameters: Human-Body Model Threshold Device T7288 Voltage >2500
DEVICE TESTING
REGULATED HIGH-VOLTAGE POWER SUPPLY
SOCKET
5-2263(C).a
Notes: P1-0 power supply. R1-At least high-voltage, carbon composition. RL1-High-voltage relay bounceless type (mercury-wetted equivalent). C1-100 capacitor. R2-1500 carbon composition shunt capacitance.
Figure Circuit Schematic Human-Body Simulator Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Electrical Characteristics
10%. Table Logic Interface Electrical Characteristics Parameter Input Voltage: High Output Voltage*: High Input Capacitance Load Capacitance Symbol Conditions sink source GNDD GNDD VDDD VDDD Unit
Digital outputs drive purely capacitive loads full output levels (VDDD, GNDD).
Internal pull-up resistors provided following input leads: LP1, LP2, LP3, ALMT. Internal pull-down devices provided following leads: RBC, HDB3/TNDATA, TBC, SR/DR, FLM, internal pull-up pull-down devices require input source sink more than Table Transmitter Specifications Parameter Output Pulse Amplitude: Pulse Width (50%) Positive/Negative Pulse Imbalance Zero Level Output Transformer Turns Ratio
Percentage nominal pulse amplitude.
2.14 2.70 1:1.33
2.37
2.60 3.30
Unit
1:1.36 1:1.39
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Electrical Characteristics (continued)
Table Receiver Specifications Parameter Receiver Sensitivity* Allowed Cable Loss Interference Interfering PBRS, Below Transmitted PBRS PLL: Bandwidth Peaking Free-running Frequency Error Input Transformer Turns Ratio Input Resistance, Each Input Ground
Measured peak-to-zero, reference). Transfer characteristics (1/4 input).
0.24 1:2.0
1:2.1
Unit
10-9
1:1.9
Table Jitter Hz-100 Parameter Receive Plus Transmit Jitter T2/R2 Transmit Jitter T2/R2 Table Power Dissipation 10%. Parameter Power Dissipation: Power Dissipation: Power Dissipation: Symbol Pdis Pdis Pdis Pdis Pdis Pdis Conditions transmit receive data, transmit receive data, PRBS (50% transmit receive data, Unit 0.06 0.012 0.09 0.04 Unit U.I. peak-to-peak U.I. peak-to-peak
Note: measurements with matched-impedance transmit interface (see Figure Figure with applied digital input leads.
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Timing Characteristics
duty-cycle timing relationships reference TTL, threshold level.
Loss-of-Clock Indication Timing
clock must absent guarantee loss-of-clock indication. However, loss-of-clock indication occur clock absent little 1.95 depending timing relationship interruption with respect timing cycle. returning clock must present 3.91 guarantee normal condition loss-of-clock (LOC). However, loss-of-clock indication return normal immediately, depending timing relationship signal return with respect timing cycle. Table Clock Timing Relationships 10%; load capacitance Symbol tTCLTCL tTCHTCL tTDVTCL tTCLTDV tRCLRCL tRCHRDV tRDVRCH tRCLRDV TCLK Duty Cycle Data Setup Time, TDATA TCLK Data Hold Time, TCLK TDATA Description TCLK Clock Period RCLK Unit
Clock Rise Time (10%-90%) Clock Fall Time (10%-90%) RCLK Duty Cycle Data Hold Time, RCLK RDATA, Data Setup Time, RDATA,
Propagation Delay, RCLK RDATA,
tolerance ppm. TDATA single-rail mode; TPDATA TNDATA dual-rail mode. RDATA single-rail mode; RPDATA RNDATA dual-rail mode.
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Timing Characteristics (continued)
Timing Diagrams (Single-Rail Dual-Rail, Logic Mode
tTCLTCL TCLK
TDATA TPDATA TNDATA tTDVTCL tTCLTDV
5-4357(C)
Figure Transmit Timing
tRCLRDV RCLK
tRDVRCH RDATA RPDATA RNDATA tRCHRDV
5-4358(C)
Figure Receive Timing
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Timing Characteristics (continued)
Timing Diagrams (Dual-Rail, Logic Mode
tTCLTCL TCLK
TPDATA TNDATA
ACTIVELOW
tTDVTCL
tTCLTDV
5-4359(C)
Figure Transmit Timing
tRCLRDV RCLK
tRDVRCH ACTIVELOW
RPDATA RNDATA
tRCHRDV
5-4360(C)
Figure Receive Timing
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Outline Diagrams
28-Pin, Plastic
Dimensions millimeters.
IDENTIFIER ZONE
SEATING PLANE 0.38 2.54 0.023
5-4410.R1
Number Pins
Package Dimensions (DIP) Maximum Length Including Leads 37.34 Maximum Width Without Leads 13.97 Maximum Width Including Leads 15.49 Maximum Height Above Board 5.59
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
Outline Diagrams (continued)
28-Pin, Plastic
Dimensions millimeters.
IDENTIFIER ZONE
SEATING PLANE 0.10 1.27 0.020 0.64
5-4413.R1
Number Pins
Package Dimensions (SOJ) Maximum Length Including Leads 18.03 Maximum Width Without Leads 7.62 Maximum Width Including Leads 8.81 Maximum Height Above Board 3.18
Ordering Information
Device Code 7288 7288 Package 28-Pin 28-Pin Temperature Comcode (Ordering Number) 105742597 105742605
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface
DS97-195TIC Replaces DS92-071SMOS Catalog CA95-003TIC Version Incorporate Following Updates
Data sheet format.
Lucent Technologies Inc.
T7288 CEPT/E1 Line Interface Interactive Terminal Transmission Convergence
Preliminary
additional information, contact your Microelectronics Group Account Manager following: INTERNET: http://www.lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 data requests Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 299, (44) 1734 technical inquiries Europe: CENTRAL EUROPE: (49) 95086 (Munich), NORTHERN EUROPE: (44) 1344 (Bracknell UK), FRANCE: (33) (Paris), SOUTHERN EUROPE: (39) 6601 1800 (Milan) (34) 1700 (Madrid)
Lucent Technologies Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. rights under patent accompany sale such product(s) information.
Copyright 1997 Lucent Technologies Inc. Rights Reserved Printed U.S.A.
January 1998 DS97-195TIC (Replaces DS92-071SMOS)
Printed Recycled Paper
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