MC9S12C Family Device User Guide V00.03 Original Release Date: 20
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DOCUMENT NUMBER 9S12C-FamilyDGV1/D 9S12CFAMDGV1/D
MC9S12C Family Device User Guide V00.03
Original Release Date: 2003 Revised: FEBRUARY 2003
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. ©Motorola, Inc., 2002
Device User Guide 9S12C-FamilyDGV1/D V00.03
Revision History
Version Revision Effective Number Date Date
00.01 00.02 00.03 25.JAN.03 25.JAN.03 07.FEB.03 07.FEB.03 25.FEB.03 25.FEB.03
Author
Description Changes
Original Version. Based user guide version 01.12 Enhanced PortK description Part number table revision preface QFP112 Emulation pinout correction Enhanced part number explanation preface Reduced pseudo STOP current spec. C64,C96,C128
Device User Guide 9S12C-FamilyDGV1/D V00.03
Table Contents
Section Introduction
Overview. Features Modes Operation Block Diagram Device Memory Map. Detailed Register Part Assignments.
Section Signal Description
Device Pinout Signal Properties Summary 2.2.1 Initialization LQFP bond-out versions Detailed Signal Descriptions. 2.3.1 EXTAL, XTAL Oscillator Pins 2.3.2 RESET External Reset 2.3.3 TEST Test 2.3.4 Loop Filter 2.3.5 BKGD TAGHI MODC Background Debug, High Mode 2.3.6 PA[7:0] ADDR[15:8] DATA[15:8] Port Pins 2.3.7 PB[7:0] ADDR[7:0] DATA[7:0] Port Pins 2.3.8 NOACC XCLKS Port 2.3.9 MODB IPIPE1 Port 2.3.10 MODA IPIPE0 Port 2.3.11 ECLK- Port E-Clock Output 2.3.12 LSTRB Port Low-Byte Strobe (LSTRB). 2.3.13 Port Read/Write. 2.3.14 Port input Maskable Interrupt 2.3.15 XIRQ Port input Maskable Interrupt 2.3.16 PAD[7:0] AN[7:0] Port Pins [7:0] 2.3.17 PP[7] KWP[7] Port [7]. 2.3.18 PP[6] KWP[6]/ROMCTL Port 2.3.19 PP[5:0] KWP[5:0] PW[5:0] Port Pins [5:0]
Device User Guide 9S12C-FamilyDGV1/D V00.03
2.3.20 PJ[7:6] KWJ[7:6] Port Pins [7:6] 2.3.21 Port 2.3.22 MOSI Port 2.3.23 Port 2.3.24 MISO Port 2.3.25 TXCAN Port 2.3.26 RXCAN Port 2.3.27 PS[3:2] Port Pins [3:2] 2.3.28 Port 2.3.29 Port 2.3.30 PPT[7:5] IOC[7:5] Port Pins [7:5] 2.3.31 PT[4:0] IOC[4:0] PW[4:0]- Port Pins [4:0] Power Supply Pins 2.4.1 VDDX,VSSX Power Ground Pins Drivers 2.4.2 VDDR, VSSR Power Ground Pins Drivers Internal Voltage Regulator 2.4.3 VDD1, VDD2, VSS1, VSS2 Core Power Pins 2.4.4 VDDA, VSSA Power Supply Pins VREG 2.4.5 VRH, Reference Voltage Input Pins 2.4.6 VDDPLL, VSSPLL Power Supply Pins
Section System Clock Description Section Modes Operation
4.3.1 4.3.2 4.3.3 4.4.1 4.4.2 4.4.3 4.4.4 Overview. Chip Configuration Summary Security. Securing Microcontroller Operation Secured Microcontroller Unsecuring Microcontroller Power Modes Stop Pseudo Stop. Wait Run.
Section Resets Interrupts
Device User Guide 9S12C-FamilyDGV1/D V00.03
Overview. Vectors 5.2.1 Vector Table. Resets 5.3.1 Reset Summary Table 5.3.2 Effects Reset
Section HCS12 Core Block Description
Device-specific information. 6.1.1 PPAGE. 6.1.2 alternate clock 6.1.3 Extended Address Range Emulation Implications
Section Voltage Regulator (VREG) Block Description
Device-specific information. 7.1.1 VREGEN 7.1.2 VDD1, VDD2, VSS1, VSS2
Section Recommended Printed Circuit Board Layout Section Clock Reset Generator (CRG) Block Description
Device-specific information. 9.1.1 XCLKS
Section Oscillator (OSC) Block Description Section Timer (TIM) Block Description Section Analog Digital Converter (ATD) Block Description
12.1 Device-specific information. 12.1.1 (voltage reference low).
Section Serial Communications Interface (SCI) Block Description Section Serial Peripheral Interface (SPI) Block Description Section Flash Block Description
Device User Guide 9S12C-FamilyDGV1/D V00.03
Section Block Description Section Pulse Width Modulator (PWM) Block Description Section MSCAN Block Description Section Port Integration Module (PIM) Block Description Appendix Electrical Characteristics
General. A.1.1 Parameter Classification A.1.2 Power Supply A.1.3 Pins A.1.4 Current Injection. A.1.5 Absolute Maximum Ratings A.1.6 Protection Latch-up Immunity A.1.7 Operating Conditions A.1.8 Power Dissipation Thermal Characteristics A.1.9 Characteristics A.1.10 Supply Currents
Appendix Electrical Specifications
B.3.1 B.3.2 B.4.1 B.4.2 B.4.3 B.4.4 B.4.5 B.5.1 B.5.2 Voltage Regulator Operating Conditions Chip Power-up LVI/LVR graphical explanation Output Loads Resistive Loads Capacitive Loads Characteristics Operating Characteristics Range Operating Characteristics 3.3V Range Factors influencing accuracy. accuracy Range) accuracy (3.3V Range) NVM, Flash EEPROM timing. Reliability.
Device User Guide 9S12C-FamilyDGV1/D V00.03
Reset, Oscillator PLL. B.6.1 Startup B.6.2 Oscillator B.6.3 Phase Locked Loop MSCAN.
Appendix Electrical Specifications
Master Mode. Slave Mode. External Timing C.3.1 General Muxed Timing
Appendix Package Information
General. 80-pin package. 52-pin LQFP package. 48-pin LQFP package.
Appendix Emulation Information
General. E.1.1 PK[2:0] XADDR[16:14]. 112-pin LQFP package.
Device User Guide 9S12C-FamilyDGV1/D V00.03
Device User Guide 9S12C-FamilyDGV1/D V00.03
List Figures
Figure Order Partnumber Coding Figure MC9S12C-Family Block Diagram Figure MC9S12C128 User configurable Memory Figure MC9S12C96 User Configurable Memory Figure MC9S12C64 User Configurable Memory Figure MC9S12C32 User Configurable Memory Figure Assignments MC9S12C-Family Figure assignments LQFP MC9S12C-Family. Figure Assignments LQFP MC9S12C-Family Figure Loop Filter Connections Figure Colpitts Oscillator Connections (PE7=1) Figure Pierce Oscillator Connections (PE7=0) Figure External Clock Connections (PE7=0) Figure Clock Connections. Figure Recommended Layout LQFP) Figure Recommended Layout LQFP) Figure Recommended Layout QFP) Figure Voltage Regulator Chip Power-up Voltage Drops (not scaled) Figure Accuracy Definitions Figure Basic functional diagram Figure Jitter Definitions Figure Maximum clock jitter approximation Figure Master Timing (CPHA=0) Figure Master Timing (CPHA=1) Figure Slave Timing (CPHA=0) Figure Slave Timing (CPHA=1) Figure General External Timing. Figure 80-pin Mechanical Dimensions (case 841B) Figure 52-pin LQFP Mechanical Dimensions (case 848D-03) Figure 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE Figure 19-1 Assignments 112-pin LQFP. Figure 19-2 112-pin LQFP mechanical dimensions (case 987)80-pin Mechanical Dimensions (case 841B)125
Device User Guide 9S12C-FamilyDGV1/D V00.03
Device User Guide 9S12C-FamilyDGV1/D V00.03
List Tables
Table Package Option Summary Table Part Number Coding Table Document References Table Device Register Overview $0000 $000F MEBI (Core User Guide) $0010 $0014 (Core User Guide) $0018 $0018 Miscellaneous Peripherals (Device User Guide) $0019 $0019 VREG3V3 (Voltage Regulator) $0015 $0016 (Core User Guide) $0017 $0017MMC (Core User Guide) $001A $001B Miscellaneous Peripherals (Device User Guide) $001C $001D (Core User Guide, Device User Guide) $001E $001E MEBI (Core User Guide) $001F $001F (Core User Guide) $0020 $002F (including BKP) (Core User Guide) $0030 $0031 (Core User Guide) $0032 $0033 MEBI (Core User Guide) $0034 $003F (Clock Reset Generator) $0040 $006F (Timer Channels) $0070 $007F Reserved $0080 $009F (Analog Digital Converter Channel) $00A0 $00C7 Reserved $00D0 $00D7 Reserved $00C8 $00CF (Asynchronous Serial Interface) $00D8 $00DF (Serial Peripheral Interface) $00E0 $00FF (Pulse Width Modulator) $0100 $010F Flash Control Register $0110 $013F Reserved $0140 $017F (Motorola Scalable MSCAN) Table Detailed MSCAN Foreground Receive Transmit Buffer Layout. $0180 $023F Reserved $0240 $027F (Port Interface Module) $0280 $03FF Reserved space
Device User Guide 9S12C-FamilyDGV1/D V00.03
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table B-10 Table B-11 Table B-12 Table B-13 Table Table Table Table
Assigned Part Numbers Memory size registers Signal Properties MC9S12C-Family Power Ground Connection Summary Mode Selection Clock Selection Based Interrupt Vector Locations Reset Summary Device Specfic Flash PAGE Mapping Recommended External Component Values. Absolute Maximum Ratings Latch-up Test Conditions Latch-Up Protection Characteristics Operating Conditions Thermal Package Characteristics Characteristics 3.3V Characteristics Supply Current Characteristics MC9S12C32 Supply Current Characteristics MC9S12C64,MC9S12C96,MC9S12C128 Voltage Regulator Electrical Parameters Voltage Regulator Capacitive Loads Operating Characteristics Operating Characteristics Electrical Characteristics Conversion Performance Conversion Performance Timing Characteristics Reliability Characteristics. Startup Characteristics. Oscillator Characteristics Characteristics MSCAN Wake-up Pulse Characteristics. Measurement Conditions Master Mode Timing Characteristics. Slave Mode Timing Characteristics. Expanded Timing Characteristics Range).
Device User Guide 9S12C-FamilyDGV1/D V00.03
Table
Expanded Timing Characteristics (3.3V Range)
Device User Guide 9S12C-FamilyDGV1/D V00.03
Device User Guide 9S12C-FamilyDGV1/D V00.03
Preface
Device User Guide provides information about MC9S12C-Family devices made standard HCS12 blocks HCS12 processor core. This document part customer documentation. complete device manuals also includes HCS12 Core User Guide individual Block User Guides implemented modules. effort reduce redundancy module specific information located only respective Block User Guide. applicable, special implementation details module given block description sections this document. Family offers extensivce range package temperature speed options. Table summarises package option size configuration. Table lists partnumber coding based package, speed temperature preliminary options Table Package Option Summary
Package
48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP
Device
MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C96 MC9S12C96 MC9S12C96 MC9S12C64 MC9S12C64 MC9S12C64 MC9S12C32 MC9S12C32 MC9S12C32
Part Number
MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C96 MC9S12C96 MC9S12C96 MC9S12C64 MC9S12C64 MC9S12C64 MC9S12C32 MC9S12C32 MC9S12C32
Mask1
0L09S 0L09S 0L09S 1L45J 1L45J 1L45J
Temp.2 Option
Flash
I/O3,4
128K
NOTES: Maskset dependent errata accessed 25MHz. 25MHz. 25MHz derivatives feature CAN, SCI, SPI, 8-channel A/D, 6-channel channel timer. ports capable digital input output.
Device User Guide 9S12C-FamilyDGV1/D V00.03
MC9S12 (P)C
Speed Option Package Option Temperature Option Preliminary Option Device Title Controller Family
Temperature Options -40°C 85°C -40°C 105°C -40°C 125°C Package Options 80QFP 52LQFP 48LQFP Speed Options 25MHz 16MHz
Figure Order Partnumber Coding Table Part Number Coding
Part Number
MC9S12C64PCFA16 MC9S12C64PCPB16 MC9S12C64PCFU16 MC9S12C64CFA16 MC9S12C64CPB16 MC9S12C64CFU16 MC9S12C64PVFA16 MC9S12C64PVPB16 MC9S12C64PVFU16 MC9S12C64VFA16 MC9S12C64VPB16 MC9S12C64VFU16 MC9S12C64PMFA16 MC9S12C64PMPB16 MC9S12C64PMFU16 MC9S12C64MFA16 MC9S12C64MPB16 MC9S12C64MFU16 MC9S12C64PCFA25 MC9S12C64PCPB25 MC9S12C64PCFU25 MC9S12C64CFA25 MC9S12C64CPB25 MC9S12C64CFU25 MC9S12C64PVFA25 MC9S12C64PVPB25 MC9S12C64PVFU25 MC9S12C64VFA25
Mask
0L09S 0L09S 0L09S 0L09S 0L09S 0L09S 0L09S 0L09S 0L09S 0L09S 0L09S 0L09S 0L09S 0L09S 0L09S
Temp.
-40°C, 85°C -40°C, 85°C -40°C, 85°C -40°C, 85°C -40°C, 85°C -40°C, 85°C -40°C, 105°C -40°C, 105°C -40°C, 105°C -40°C,105°C -40°C,105°C -40°C, 105°C -40°C, 125°C -40°C, 125°C -40°C, 125°C -40°C,125°C -40°C,125°C -40°C, 125°C -40°C, 85°C -40°C, 85°C -40°C, 85°C -40°C, 85°C -40°C, 85°C -40°C, 85°C -40°C, 105°C -40°C, 105°C -40°C, 105°C -40°C,105°C
Package
48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP
Speed
16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz
Description
PreliminaryC64 using C128 PreliminaryC64 using C128 PreliminaryC64 using C128 Final using Final using Final using PreliminaryC64 using C128 PreliminaryC64 using C128 PreliminaryC64 using C128 Final using Final using Final using PreliminaryC64 using C128 PreliminaryC64 using C128 PreliminaryC64 using C128 Final using Final using Final using PreliminaryC64 using C128 PreliminaryC64 using C128 PreliminaryC64 using C128 Final using Final using Final using PreliminaryC64 using C128 PreliminaryC64 using C128 PreliminaryC64 using C128 Final using
Device User Guide 9S12C-FamilyDGV1/D V00.03 Mask
0L09S 0L09S 0L09S 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J 1L45J
Part Number
MC9S12C64VPB25 MC9S12C64VFU25 MC9S12C64PMFA25 MC9S12C64PMPB25 MC9S12C64PMFU25 MC9S12C64MFA25 MC9S12C64MPB25 MC9S12C64MFU25 MC9S12C32CFA16 MC9S12C32CPB16 MC9S12C32CFU16 MC9S12C32VFA16 MC9S12C32VPB16 MC9S12C32VFU16 MC9S12C32MFA16 MC9S12C32MPB16 MC9S12C32MFU16 MC9S12C32CFA25 MC9S12C32CPB25 MC9S12C32CFU25 MC9S12C32VFA25 MC9S12C32VPB25 MC9S12C32VFU25 MC9S12C32MFA25 MC9S12C32MPB25 MC9S12C32MFU25 MC9S12C128CFA16 MC9S12C128CPB16 MC9S12C128CFU16 MC9S12C128VFA16 MC9S12C128VPB16 MC9S12C128VFU16 MC9S12C128MFA16 MC9S12C128MPB16 MC9S12C128MFU16 MC9S12C128CFA25 MC9S12C128CPB25 MC9S12C128CFU25 MC9S12C128VFA25 MC9S12C128VPB25 MC9S12C128VFU25 MC9S12C128MFA25 MC9S12C128MPB25 MC9S12C128MFU25
Temp.
-40°C,105°C -40°C, 105°C -40°C, 125°C -40°C, 125°C -40°C, 125°C -40°C,125°C -40°C,125°C -40°C, 125°C -40°C, 85°C -40°C, 85°C -40°C, 85°C -40°C,105°C -40°C,105°C -40°C, 105°C -40°C,125°C -40°C,125°C -40°C, 125°C -40°C, 85°C -40°C, 85°C -40°C, 85°C -40°C,105°C -40°C,105°C -40°C, 105°C -40°C,125°C -40°C,125°C -40°C, 125°C -40°C, 85°C -40°C, 85°C -40°C, 85°C -40°C,105°C -40°C,105°C -40°C, 105°C -40°C,125°C -40°C,125°C -40°C, 125°C -40°C, 85°C -40°C, 85°C -40°C, 85°C -40°C,105°C -40°C,105°C -40°C, 105°C -40°C,125°C -40°C,125°C -40°C, 125°C
Package
52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP 48LQFP 52LQFP 80QFP
Speed
25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz
Description
Final using Final using PreliminaryC64 using C128 PreliminaryC64 using C128 PreliminaryC64 using C128 Final using Final using Final using C128 C128 C128 C128 C128 C128 C128 C128 C128 C128 C128 C128 C128 C128 C128 C128 C128 C128
Device User Guide 9S12C-FamilyDGV1/D V00.03
Table Document References
User Guide
HCS12 Core User Guides Analog Digital Converter: Channel (ATD_10B8C) Block User Guide Clock Reset Generator (CRG) Block User Guide Serial Communications Interface (SCI) Block User Guide Serial Peripheral Interface (SPI) Block User Guide Motorola Scalable (MSCAN) Block User Guide Pulse Width Modulator: bit, channel (PWM_8B6C) Block User Guide Timer bit, channel (TIM_16B8C) Block User Guide Voltage Regulator (VREG) Block User Guide Oscillator (OSC) Block User Guide (Port Integration Module) PIM_9C32 Block User Guide 32Kbyte Flash EEPROM (FTS32K) Block User Guide 64Kbyte Flash EEPROM (FTS64K) Block User Guide 128Kbyte Flash EEPROM (FTS128K) Block User Guide
Version
Document Order Number
HCS12COREUG/D S12ATD10B8CV2/D S12CRGV4/D S12SCIV2/D S12SPIV3/D S12MSCANV2/D S12PWM8B6V1/D S12TIM16B8CV1/D S12VREG3V3V2/D S12OSCV2/D S12C32PIMV1/D S12FTS32KV1/D S12FTS64KV1/D S12FTS128KV1/D
NOTES: refer flash, flash, flash C128 128K flash document
Terminology
Acronyms Abbreviations invented terms, symbols, notations
Device User Guide 9S12C-FamilyDGV1/D V00.03
Section Introduction
Overview
MC9S12C-Family 48/52/80 Flash-based Industrial/Automotive network control family. Members MC9S12C-Family deliver power flexibility core (CPU12) family whole range cost space sensitive, general purpose Industrial Automotive network applications. MC9S12C-Family members comprised standard on-chip peripherals including 16-bit central processing unit (CPU12), 128K bytes Flash EEPROM, bytes RAM, asynchronous serial communications interface (SCI), serial peripheral interface (SPI), 8-channel 16-bit timer module (TIM), 6-channel 8-bit Pulse Width Modulator (PWM), 8-channel, 10-bit analog-to-digital converter (ADC) software compatible module (MSCAN12). MC9S12C-Family full 16-bit data paths throughout. inclusion circuit allows power consumption performance adjusted suit operational requirements. addition ports available each module, dedicated port bits available with Wake-Up capability from STOP WAIT mode. MC9S12C-Family available packages, with version compatible HCS12 Family derivatives
Features
16-bit HCS12 CORE HCS12 Upward compatible with M68HC11 instruction Interrupt stacking programmer's model identical M68HC11 iii. Instruction queue Enhanced indexed addressing (memory interface) (interrupt control) (background debug mode) DBG12 (enhanced debug12 module, including breakpoints change-of-flow trace buffer) MEBI Multiplexed Expansion Interface (available only package version) 12-port bits available wake interrupt function with digital filtering 64K, 128KByte Flash EEPROM (erasable 512-byte sectors) Byte
Wake-up interrupt inputs Memory options
Analog-to-Digital Converters
Device User Guide 9S12C-FamilyDGV1/D V00.03
8-channel module with 10-bit resolution. External conversion trigger capability Five receive three transmit buffers Flexible identifier filter programmable bit, Four separate interrupt channels error wake-up Low-pass filter wake-up function Loop-back self test operation 8-Channel Timer Each Channel Configurable either Input Capture Output Compare Simple Mode Modulo Reset Timer Counter 16-Bit Pulse Accumulator External Event Counting Gated Time Accumulation Programmable period duty cycle 8-bit 6-channel 16-bit 3-channel Separate control each pulse width duty cycle Center-aligned left-aligned outputs Programmable clock select logic with wide range frequencies Fast emergency shutdown input asynchronous serial communications interface (SCI) synchronous serial peripheral interface (SPI) Windowed watchdog, Real time interrupt, Clock monitor, Pierce current Colpitts oscillator Phase-locked loop clock frequency multiplier
second, software compatible modules
Timer Module (TIM)
channels
Serial interfaces
(Clock Reset Generator Module)
Device User Guide 9S12C-FamilyDGV1/D V00.03
Limp home mode absence external clock power crystal oscillator reference clock 32MHz equivalent 16MHz Speed single chip 32MHz equivalent 16MHz Speed expanded modes Option: 50MHz equivalent 25MHz Speed Supports input voltage range from 2.97V 5.5V power mode capability Includes voltage reset (LVR) circuitry Includes voltage interrupt (LVI) circuitry lines with input drive capability package) dedicated input only lines (IRQ, XIRQ) converter inputs Single-wire background debugmode (BDM) On-chip hardware breakpoints Enhanced DBG12 debug features
Operating frequency
Internal 2.5V Regulator
48-Pin LQFP, 52-Pin LQFP 80-Pin package
Development support
Modes Operation
User modes (Expanded modes only available package version). Mormal Emulation Operating Modes Normal Single-Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Single-Chip Mode with active Background Debug Mode Special Test Mode (Motorola only) Special Peripheral Mode (Motorola only)
Special Operating Modes
Device User Guide 9S12C-FamilyDGV1/D V00.03
power modes Stop Mode Pseudo Stop Mode Wait Mode
Device User Guide 9S12C-FamilyDGV1/D V00.03
Block Diagram
Figure MC9S12C-Family Block Diagram
VSSR VDDR VDDX VSSX
Voltage Regulator
VDDA VSSA IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7
VDDA VSSA PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7
DDRAD DDRT Keypad Interrupt DDRP DDRJ DDRS DDRM
VDD2 VSS2 VDD1 VSS1 BKGD VDDPLL VSSPLL EXTAL XTAL RESET TEST/VPP
32K, 64K, 96K, 128K Byte Flash Byte
Background MODC Debug12 Module Clock Reset Generation Module
HCS12 Timer Module
Watchdog Clock Monitor Periodic Interrupt
PPTS
XIRQ System Integration LSTRB/TAGLO Module ECLK (SIM) MODA/IPIPE0 MODB/IPIPE1 NOACC/XCLKS
DDRE
Module
Multiplexed Address/Data
DDRA
DDRB
MSCAN
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8
DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8
Multiplexed Wide
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
RXCAN TXCAN MISO MOSI
Signals shown Bold available Package Signals shown Bold Italic available Package
Internal Logic 2.5V
VDD1,2 VSS1,2
Driver
VDDX VSSX
2.5V
VDDPLL VSSPLL
Converter
VDDA VSSA
bonded internally VSSA packages
Voltage Regulator
VDDR VSSR
PTAD
Device User Guide 9S12C-FamilyDGV1/D V00.03
Device Memory
Table shows device register MC9S12C-Family after reset. following figures Figure 1-2, Figure 1-2, Figure Figure 1-4) illustrate full device memory with flash RAM. Table Device Register Overview
Address
$000 $017 $018 $019 $01A $01B $01C $01F $020 $02F $030 $033 $034 $03F $040 $06F $070 $07F $080 $09F $0A0 $0C7 $0C8 $0CF $0D0 $0D7 $0D8 $0DF $0E0 $0FF $100 $10F $110 $13F $140 $17F $180 $23F $240 $27F $280 $3FF Reserved Voltage Regulator (VREG) Device register CORE (MEMSIZ, IRQ, HPRIO) CORE (DBG) CORE (PPAGE1) Clock Reset Generator (CRG) Standard Timer Module16-bit 8-channels (TIM) Reserved Analog Digital Convert (ATD) Reserved Serial Communications Interface (SCI) Reserved Serial Peripheral Interface (SPI) Pulse Width Modulator 8-bit channels (PWM) Flash Control Register Reserved Motorola Scalable (MSCAN) Reserved Port Integration Module (PIM) Reserved
Module
CORE (Ports E,Modes, Inits, Test)
Size
NOTES: External memory paging supported this device (6.1.1 PPAGE).
Device User Guide 9S12C-FamilyDGV1/D V00.03
$0000 $0000 $0400 $03FF $0000
Register Space Mappable Boundary Fixed Flash EEPROM
$3FFF $3000 $3000 $3FFF $4000 $4000 Bytes Mappable Boundary
Fixed Flash EEPROM
$7FFF $8000 $8000 Page Window Flash EEPROM Pages
$BFFF $C000 $C000 Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
Active)
figure shows useful map, which reset. After reset $0000 $03FF: Register Space $0000 $0FFF: (only visible $0400 $0FFF) Flash Erase Sector Size 1024 Bytes
Figure MC9S12C128 User configurable Memory
Device User Guide 9S12C-FamilyDGV1/D V00.03
$0000 $0000 $0400 $03FF $0000
Register Space Mappable Boundary Fixed Flash EEPROM
$3FFF $3000 $3000 $3FFF $4000 $4000 Bytes Mappable Boundary
Fixed Flash EEPROM
$7FFF $8000 $8000 Page Window Flash EEPROM Pages
$BFFF $C000 $C000 Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
Active)
figure shows useful map, which reset. After reset $0000 $03FF: Register Space $0000 $0FFF: (only visible $0400 $0FFF) Flash Erase Sector Size 1024 Bytes
Figure MC9S12C96 User Configurable Memory
Device User Guide 9S12C-FamilyDGV1/D V00.03
$0000 $0000 $0400 $03FF $0000
Register Space Mappable Boundary Fixed Flash EEPROM
$3FFF $3000 $3000 $3FFF $4000 $4000 Bytes Mappable Boundary
Fixed Flash EEPROM
$7FFF $8000 $8000 Page Window Flash EEPROM Pages
$BFFF $C000 $C000 Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
Active)
figure shows useful map, which reset. After reset $0000 $03FF: Register Space $0000 $0FFF: (only visible $0400 $0FFF) Flash Erase Sector Size Bytes
Figure MC9S12C64 User Configurable Memory
Device User Guide 9S12C-FamilyDGV1/D V00.03
$0000 $0000 $0400 $03FF
Register Space Mappable Boundary
$3800
$3800 $3FFF
Bytes Mappable Boundary
$4000
$8000
$8000 Page Window Flash EEPROM Pages
$BFFF $C000 $C000 Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
Active)
figure shows useful map, which reset. After reset $0000 $03FF: Register Space $0800 $0FFF: Flash Erase Sector Size Bytes
Figure MC9S12C32 User Configurable Memory
Detailed Register
detailed register MC9S12C Family listed address order below.
Device User Guide 9S12C-FamilyDGV1/D V00.03
$0000 $000F
Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved
MEBI (Core User Guide)
Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: NOACCE Write: Read: MODC Write: Read: PUPKE Write: Read: RDPK Write: Read: Write: Read: Write: MODB PIPOE MODA NECLK PUPEE RDPE LSTRE IVIS RDWE PUPBE RDPB PUPAE RDPA ESTR
$0010 $0014
Address $0010 $0011 Address Name INITRM INITRG Name
(Core User Guide)
Read: RAM15 Write: Read: Write: RAM14 REG14 RAM13 REG13 RAM12 REG12 RAM11 REG11 RAMHAL
Device User Guide 9S12C-FamilyDGV1/D V00.03
$0010 $0014
Address $0012 $0013 $0014 Name INITEE MISC Reserved Read: Write: Read: Write: Read: Write:
(Core User Guide)
EE15 EE14 EE13 EE12 EE11 EXSTR1 EXSTR0 ROMHM EEON ROMON
$0015 $0016
Address $0015 $0016 Name ITCR ITEST Read: Write: Read: Write:
(Core User Guide)
INTE INTC INTA WRINT INT8 ADR3 INT6 ADR2 INT4 ADR1 INT2 ADR0 INT0
$0017 $0017
Address $0017 Name Reserved Read: Write:
(Core User Guide)
$0018 $0018
Address $0018 Name Reserved Read: Write:
Miscellaneous Peripherals (Device User Guide)
$0019 $0019
Address $0019 Name VREGCTRL Read: Write:
VREG3V3 (Voltage Regulator)
LVDS LVIE LVIF
$001A $001B
Address $001A $001B Name PARTIDH PARTIDL Read: Write: Read: Write:
Miscellaneous Peripherals (Device User Guide)
ID15 ID14 ID13 ID12 ID11 ID10
Device User Guide 9S12C-FamilyDGV1/D V00.03
$001C $001D
Address $001C $001D Name MEMSIZ0 MEMSIZ1
(Core User Guide, Device User Guide)
Read: reg_sw0 Write: Read: rom_sw1 Write: rom_sw0 eep_sw1 eep_sw0 ram_sw2 ram_sw1 pag_sw1 ram_sw0 pag_sw0
$001E $001E
Address $001E Name INTCR Read: Write:
MEBI (Core User Guide)
IRQE IRQEN
$001F $001F
Address $001F Name HPRIO Read: Write:
(Core User Guide)
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
$0020 $002F
Address $0020 $0021 $0022
$0023 $0024 $0025 $0026 $0027
(including BKP) (Core User Guide)
read DBGEN write read write read write
read write read write read write read write read write PAGSEL
Name DBGC1
TRGSEL
BEGIN
DBGBRK
CAPMOD
DBGSC
DBGTBH DBGTBL DBGCNT DBGCCX DBGCCH DBGCCL
EXTCMP RWCEN RWBEN
$0028 $0029 $002A
$002B
DBGC2
BKPCT0
DBGC3
BKPCT1 DBGCAX BKP0X DBGCAH BKP0H
read BKABEN FULL TAGAB BKCEN TAGC write read BKAMBH BKAMBL BKBMBH BKBMBL RWAEN write read PAGSEL EXTCMP write
read write
Device User Guide 9S12C-FamilyDGV1/D V00.03
$0020 $002F
Address
$002C $002D $002E $002F
(including BKP) (Core User Guide)
read write read write read write read write PAGSEL
Name
DBGCAL BKP0L DBGCBX BKP1X DBGCBH BKP1H DBGCBL BKP1L
EXTCMP
$0030 $0031
Address $0030 $0031 Name PPAGE Reserved Read: Write: Read: Write:
(Core User Guide)
PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
$0032 $0033
Address $0032 $0033 Name PORTK1 DDRK(1) Read: Write: Read: Write:
MEBI (Core User Guide)
NOTES: Only applicable special emulation-only bond outs, emulation extended memory map.
$0034 $003F
Address $0034 $0035 $0036 $0037 $0038 $0039 $003A Name SYNR REFDV CTFLG TEST ONLY CRGFLG CRGINT CLKSEL PLLCTL
(Clock Reset Generator)
Read: Write: Read: Write: Read: TOUT7 Write: Read: RTIF Write: Read: RTIE Write: Read: PLLSEL Write: Read: Write: TOUT6 PROF PSTP PLLON SYN5 TOUT5 SYSWAI AUTO SYN4 TOUT4 LOCKIF LOCKIE ROAWAI SYN3 REFDV3 TOUT3 LOCK PLLWAI SYN2 REFDV2 TOUT2 TRACK CWAI SYN1 REFDV1 TOUT1 SCMIF SCMIE RTIWAI SYN0 REFDV0 TOUT0 COPWAI SCME
Device User Guide 9S12C-FamilyDGV1/D V00.03
$0034 $003F
Address $003B $003C $003D $003E $003F Name RTICTL COPCTL FORBYP TEST ONLY CTCTL TEST ONLY ARMCOP
(Clock Reset Generator)
Read: Write: Read: WCOP Write: Read: RTIBYP Write: Read: TCTL7 Write: Read: Write: RTR6 RSBCK COPBYP TCTL6 RTR5 TCTL5 RTR4 PLLBYP TCTL4 RTR3 TCLT3 RTR2 TCTL2 RTR1 TCTL1 RTR0 TCTL0
$0040 $006F
Address $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo) TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TSCR2 TFLG1 TFLG2 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
(Timer Channels)
IOS7
FOC7
IOS6
FOC6
IOS5
FOC5
IOS4
FOC4
IOS3
FOC3
IOS2
FOC2
IOS1
FOC1
IOS0
FOC0
OC7M7 OC7D7
OC7M6 OC7D6
OC7M5 OC7D5
OC7M4 OC7D4
OC7M3 OC7D3
OC7M2 OC7D2
OC7M1 OC7D1
OC7M0 OC7D0
TOV7 EDG7B EDG3B
TSWAI TOV6 EDG7A EDG3A
TSFRZ TOV5 EDG6B EDG2B
TFFCA TOV4 EDG6A EDG2A
TOV3 EDG5B EDG1B TCRE
TOV2 EDG5A EDG1A
TOV1 EDG4B EDG0B
TOV0 EDG4A EDG0A
Device User Guide 9S12C-FamilyDGV1/D V00.03 Address $0050 $0051 $0052 $0053 $0054 $0055 $0056 $0057 $0058 $0059 $005A $005B $005C $005D $005E $005F $0060 $0061 $0062 $0063 $0064 $0065 $0066 $0067 Name (hi) (lo) (hi) (lo) (hi) (lo) (hi) (lo) (hi) (lo) (hi) (lo) (hi) (lo) (hi) (lo) PACTL PAFLG PACNT (hi) PACNT (lo) Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAOVF
PAIF
Device User Guide 9S12C-FamilyDGV1/D V00.03 Address $0068 $0069 $006A $006B $006C $006D $006E $006F Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
$0070 $007F
$0070 $007F Reserved Read: Write:
Reserved
$0080 $009F
Address $0080 $0081 $0082 $0083 $0084 $0085 $0086 $0087 $0088 $0089 $008A Name ATDCTL0 ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT0 Reserved ATDTEST0 ATDTEST1 Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
(Analog Digital Converter Channel)
ADPU SRES8 AFFC SMP1 DSGN AWAI SMP0 SCAN ETORF ETRIGLE PRS4 MULT FIFOR ETRIGP PRS3 ETRIG FIFO PRS2 ASCIE FRZ1 PRS1 ASCIF FRZ0 PRS0
Device User Guide 9S12C-FamilyDGV1/D V00.03
$0080 $009F
Address $008B $008C $008D $008E $008F $0090 $0091 $0092 $0093 $0094 $0095 $0096 $0097 $0098 $0099 $009A $009B $009C $009D $009E $009F Name ATDSTAT1 Reserved ATDDIEN Reserved PORTAD0 ATDDR0H ATDDR0L ATDDR1H ATDDR1L ATDDR2H ATDDR2L ATDDR3H ATDDR3L ATDDR4H ATDDR4L ATDDR5H ATDDR5L ATDDR6H ATDDR6L ATDDR7H ATDDR7L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
(Analog Digital Converter Channel)
CCF7 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 CCF6 Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 Bit8 Bit8 Bit8 Bit8 Bit8 Bit8 Bit8 Bit8
$00A0 $00C7
$00A0 $00C7 Reserved Read: Write:
Reserved
Device User Guide 9S12C-FamilyDGV1/D V00.03
$00C8 $00CF
Address $00C8 $00C9 $00CA $00CB $00CC $00CD $00CE $00CF Name SCIBDH SCIBDL SCICR1 SCICR2 SCISR1 SCISR2 SCIDRH SCIDRL
(Asynchronous Serial Interface)
Read: Write: Read: SBR7 Write: Read: LOOPS Write: Read: Write: Read: TDRE Write: Read: Write: Read: Write: Read: Write:
SBR12
SBR11
SBR10
SBR9
SBR8
SBR6 SCISWAI TCIE
SBR5 RSRC RDRF
SBR4 ILIE IDLE
SBR3 WAKE
SBR2 BRK13
SBR1 TXDIR
SBR0
$00D0 $00D7
$00D0 $00D7 Reserved Read: Write:
Reserved
$00D8 $00DF
Address $00D8 $00D9 $00DA $00DB $00DC $00DD $00DE $00DF Name SPICR1 SPICR2 SPIBR SPISR Reserved SPIDR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
(Serial Peripheral Interface)
SPIE SPIF Bit7 SPPR2 SPTIE SPPR1 SPTEF MSTR CPOL CPHA SPR2 SSOE SPISWAI SPR1 LSBFE SPC0 SPR0 Bit0
MODFEN BIDIROE SPPR0 MODF
Device User Guide 9S12C-FamilyDGV1/D V00.03
$00E0 $00FF
Address $00E0 $00E1 $00E2 $00E3 $00E4 $00E5 $00E6 $00E7 $00E8 $00E9 $00EA $00EB $00EC $00ED $00EE $00EF $00F0 $00F1 $00F2 $00F3 $00F4 $00F5 $00F6 Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC PWMSCLA PWMSCLB PWMSCNTA PWMSCNTB PWMCNT0 PWMCNT1 PWMCNT2 PWMCNT3 PWMCNT4 PWMCNT5 PWMPER0 PWMPER1 PWMPER2 PWMPER3 PWMPER4 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
(Pulse Width Modulator)
PCKB2 CON45 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 PWME3 PPOL3 PCLK3 CAE3 PSWAI PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ PWME1 PPOL1 PCLK1 PCKA1 CAE1 PWME0 PPOL0 PCLK0 PCKA0 CAE0
Device User Guide 9S12C-FamilyDGV1/D V00.03 Address $00F7 $00F8 $00F9 $00FA $00FB $00FC $00FD $00FE $00FF Name PWMPER5 PWMDTY0 PWMDTY1 PWMDTY2 PWMDTY3 PWMDTY4 PWMDTY5 Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
$0100 $010F
Address $0100 $0101 $0102 $0103 $0104 $0105 $0106 $0107 $0108 $0109 $010A $010B Name FCLKDIV FSEC FTSTMOD FCNFG FPROT
FSTAT
Flash Control Register
Read: FDIVLD Write: Read: KEYEN1 Write: Read: Write: Read: CBEIE Write: Read: FPOPEN Write: Read: CBEIF Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: PRDIV8 KEYEN0 CCIE CCIF CMDB6 FDIV5 KEYACC FPHDIS PVIOL CMDB5 FDIV4 WRALL FPHS1 ACCERR FDIV3 FPHS0 FDIV2 FPLDIS BLANK CMDB2 FDIV1 SEC1 BKSEL1 FPLS1 FDIV0 SEC0 BKSEL0 FPLS0 CMDB0
FCMD Reserved Factory Test Reserved Factory Test Reserved Factory Test Reserved Factory Test Reserved Factory Test
Device User Guide 9S12C-FamilyDGV1/D V00.03
$0100 $010F
Address $010C $010D $010E $010F Name Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write:
Flash Control Register
$0110 $013F
$0110 $003F Reserved Read: Write:
Reserved
$0140 $017F
Address $0140 $0141 $0142 $0143 $0144 $0145 $0146 $0147 $0148 $0149 $014A $014B $014C $014D Name CANCTL0 CANCTL1 CANBTR0 CANBTR1 CANRFLG CANRIER CANTFLG CANTIER CANTARQ CANTAAK CANTBSEL CANIDAC Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
(Motorola Scalable MSCAN)
RXFRM CANE
RXACT
CSWAI LOOPB
SYNCH
TIME
WUPE WUPM
SLPRQ SLPAK
INITRQ INITAK
CLKSRC
LISTEN
SJW1 SAMP WUPIF WUPIE
SJW0 TSEG22 CSCIF CSCIE
BRP5 TSEG21 RSTAT1
BRP4 TSEG20 RSTAT0
BRP3 TSEG13 TSTAT1
BRP2 TSEG12 TSTAT0
BRP1 TSEG11 OVRIF OVRIE
TXE1
BRP0 TSEG10 RXFIE
TXE0
RSTATE1 RSTATE0 TSTATE1 TSTATE0
TXE2
TXEIE2
ABTRQ2
TXEIE1
ABTRQ1
TXEIE0
ABTRQ0
ABTAK2
ABTAK1
ABTAK0
IDAM1
IDAM0
IDHIT2
IDHIT1
IDHIT0
Device User Guide 9S12C-FamilyDGV1/D V00.03
$0140 $017F
Address $014E $014F $0150 $0153 $0154 $0157 $0158 $015B $015C $015F $0160 $016F $0170 $017F Name CANRXERR CANTXERR CANIDAR0 CANIDAR3 CANIDMR0 CANIDMR3 CANIDAR4 CANIDAR7 CANIDMR4 CANIDMR7 CANRXFG CANTXFG
(Motorola Scalable MSCAN)
Read: RXERR7 Write: Read: TXERR7 Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
RXERR6 TXERR6
RXERR5 TXERR5
RXERR4 TXERR4
RXERR3 TXERR3
RXERR2 TXERR2
RXERR1 TXERR1
RXERR0 TXERR0
FOREGROUND RECEIVE BUFFER Table FOREGROUND TRANSMIT BUFFER Table
Table Detailed MSCAN Foreground Receive Transmit Buffer Layout
Address $xxx0 Name Extended Standard CANxRIDR0 Extended Standard CANxRIDR1 Extended Standard CANxRIDR2 Extended Standard CANxRIDR3 CANxRDSR0 CANxRDSR7 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Write: Read: CANRxDLR Write: Read: Reserved Write: Read: CANxRTSRH Write: Read: CANxRTSRL Write: Extended Read: CANxTIDR0 Write: Standard Read: Write: ID28 ID10 ID20 ID14 ID27 ID19 ID13 ID26 ID18 ID12 ID25 SRR=1 ID11 ID24 IDE=1 IDE=0 ID10 ID23 ID17 ID22 ID16 ID21 ID15
$xxx1
$xxx2
$xxx3 $xxx4$xxxB $xxxC $xxxD $xxxE $xxxF
DLC3
DLC2
DLC1
DLC0
TSR15 TSR7 ID28 ID10
TSR14 TSR6 ID27
TSR13 TSR5 ID26
TSR12 TSR4 ID25
TSR11 TSR3 ID24
TSR10 TSR2 ID23
TSR9 TSR1 ID22
TSR8 TSR0 ID21
$xx10
Device User Guide 9S12C-FamilyDGV1/D V00.03
Address $xx11 Name Extended CANxTIDR1 Standard Extended CANxTIDR2 Standard Extended CANxTIDR3 Standard CANxTDSR0 CANxTDSR7 CANxTDLR CONxTTBPR CANxTTSRH CANxTTSRL Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: ID20 ID14 ID19 ID13 ID18 ID12 SRR=1 ID11 IDE=1 IDE=0 ID10 ID17 ID16 ID15
$xx12
$xx13 $xx14$xx1B $xx1C $xx1D $xx1E $xx1F
DLC3
DLC2 PRIO2 TSR10 TSR2
DLC1 PRIO1 TSR9 TSR1
DLC0 PRIO0 TSR8 TSR0
PRIO7 TSR15 TSR7
PRIO6 TSR14 TSR6
PRIO5 TSR13 TSR5
PRIO4 TSR12 TSR4
PRIO3 TSR11 TSR3
$0180 $023F
$0180 $023F Reserved Read: Write:
Reserved
$0240 $027F
Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
(Port Interface Module)
$0240 $0241 $0242 $0243 $0244 $0245 $0246 $0247 $0248
PTIT DDRT RDRT PERT PPST Reserved MODRR
PTT7 PTIT7 DDRT7 RDRT7 PERT7 PPST7
PTT6 PTIT6 DDRT7 RDRT6 PERT6 PPST6
PTT5 PTIT5 DDRT5 RDRT5 PERT5 PPST5
PTT4 PTIT4 DDRT4 RDRT4 PERT4 PPST4
PTT3 PTIT3 DDRT3 RDRT3 PERT3 PPST3
PTT2 PTIT2 DDRT2 RDRT2 PERT2 PPST2
PTT1 PTIT1 DDRT1 RDRT1 PERT1 PPST1
PTT0 PTIT0 DDRT0 RDRT0 PERT0 PPST0
MODRR4 MODRR3 MODRR2 MODRR1 MODRR0
PTS3
PTS2
PTS1
PTS0
Device User Guide 9S12C-FamilyDGV1/D V00.03 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: PTP7 Write: Read: PTIP7 Write: Read: DDRP7 Write: Read: RDRP7 Write: Read: PERP7 Write: Read: PPSP7 Write: Read: PIEP7 Write: Read: PIFP7 Write: Read: Write: PTP6 PTIP6 DDRP7 RDRP6 PERP6 PPSP6 PIEP6 PIFP6 PTM5 PTIM5 DDRM5 RDRM5 PERM5 PPSM5 WOMM5 PTP5 PTIP5 DDRP5 RDRP5 PERP5 PPSP5 PIEP5 PIFP5 PTM4 PTIM4 DDRM4 RDRM4 PERM4 PPSM4 WOMM4 PTP4 PTIP4 DDRP4 RDRP4 PERP4 PPSP4 PIEP4 PIFP4 PTIS3 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 PTM3 PTIM3 DDRM3 RDRM3 PERM3 PPSM3 WOMM3 PTP3 PTIP3 DDRP3 RDRP3 PERP3 PPSP3 PIEP3 PIFP3 PTIS2 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 PTM2 PTIM2 DDRM2 RDRM2 PERM2 PPSM2 WOMM2 PTP2 PTIP2 DDRP2 RDRP2 PERP2 PPSP2 PIEP2 PIFP2 PTIS1 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 PTM1 PTIM1 DDRM1 RDRM1 PERM1 PPSM1 WOMM1 PTP1 PTIP1 DDRP1 RDRP1 PERP1 PPSP1 PIEP1 PIFP1 PTIS0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 PTM0 PTIM0 DDRM0 RDRM0 PERM0 PPSM0 WOMM0 PTP0 PTIP0 DDRP0 RDRP0 PERP0 PPSS0 PIEP0 PIFP0
$0249 $024A $024B $024C $024D $024E $024F $0250 $0251 $0252 $0253 $0254 $0255 $0256 $0257 $0258 $0259 $025A $025B $025C $025D $025E $025F $0260
PTIS DDRS RDRS PERS PPSS WOMS Reserved PPTIM DDRM RDRM PERM PPSM WOMM Reserved PTIP DDRP RDRP PERP PPSP PIEP PIFP Reserved
Device User Guide 9S12C-FamilyDGV1/D V00.03 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: PTJ7 PTIJ7 DDRJ7 RDRJ7 PERJ7 PPSJ7 PIEJ7 PIFJ7
PTAD7 PTIAD7
$0261 $0262 $0263 $0264 $0265 $0266 $0267 $0268 $0269 $026A $026B $026C $026D $026E $026F $0270 $0271 $0272 $0273 $0274 $0275 $0276$027F
Reserved Reserved Reserved Reserved Reserved Reserved Reserved PTIJ DDRJ RDRJ PERJ PPSJ PIEJ PIFJ PTAD PTIAD DDRAD RDRAD PERAD PPSAD Reserved
PTJ6 PTIJ6 DDRJ7 RDRJ6 PERJ6 PPSJ6 PIEJ6 PIFJ6
PTAD6 PTIAD6
PTAD5 PTIAD5
PTAD4 PTIAD4
PTAD3 PTIAD3
PTAD2 PTIAD2
PTAD1 PTIAD1
PTAD0 PTIJ7
DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0 RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0
Read: PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0 Write:
Read: PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0 Write: Read: Write:
Device User Guide 9S12C-FamilyDGV1/D V00.03
$0280 $03FF
Address Name Read: $0280 Reserved $2FF Write: Read: $0300 Unimplemented $03FF Write:
Reserved space
Part Assignments
part located 8-bit registers PARTIDH PARTIDL (addresses $001A $001B after reset). read-only value unique part each revision chip. Table shows assigned part numbers. Table Assigned Part Numbers
Device MC9S12C32 MC9S12C32 MC9S12C64 MC9S12C96 MC9S12C128 Mask Number 0L45J 1L45J 0L09S Part $3300 $3300 $3100
NOTES: coding follows: 15-12: Major family identifier 11-8: Minor family identifier 7-4: Major mask revision number including transfers 3-0: Minor full mask revision
device memory sizes located 8-bit registers MEMSIZ0 MEMSIZ1 (addresses $001C $001D after reset). Table shows read-only values these registers. Refer section Module Mapping Control (MMC) HCS12 Core User Guide further details. Table Memory size registers
Device MC9S12C32 MC9S12C32 MC9S12C64 MC9S12C64 MC9S12C96 MC9S12C96 MC9S12C128 MC9S12C128 Register name MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 Value
Device User Guide 9S12C-FamilyDGV1/D V00.03
Section Signal Description
Device Pinout
PP4/KWP4/PW4 PP5/KWP5/PW5 PP7/KWP7 VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PJ6/KWJ6 PJ7/KWJ7 PP6/KWP6/ROMCTL PS1/TXD PS0/RXD VSSA PW3/KWP3/PP3 PW2/KWP2/PP2 PW1/KWP1/PP1 PW0/KWP0/PP0 PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
MC9S12C-Family
VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Signals shown Bold available Package Signals shown Bold Italic available Package
Figure Assignments MC9S12C-Family
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL VSSPLL EXTAL XTAL TEST/VPP LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
Device User Guide 9S12C-FamilyDGV1/D V00.03
PP4/KWP4/PW4
PP5/KWP5/PW5
PM0/RXCAN
PM1/TXCAN
PM2/MISO
PM4/MOSI
PM5/SCK
PS0/RXD VSSA
PS1/TXD
PM3/SS
VDDX
VSSX
PW3/KWP3/PP3 PW0/IOC0/PT0
PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD
VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00
MC9S12C-Family
VDDR
RESET
VDDPLL
EXTAL
VSSR
XTAL
Signals shown Bold italic available Package
Figure assignments LQFP MC9S12C-Family
XCLKS/PE7
TEST/VPP IRQ/PE1 XIRQ/PE0
ECLK/PE4
VSSPLL
Device User Guide 9S12C-FamilyDGV1/D V00.03
PM0/RXCAN
PM1/TXCAN
PP5/KWP5
PM2/MISO
PM4/MOSI
PM5/SCK
PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD
PS0/RXD VSSA
PS1/TXD
PM3/SS
VDDX
VSSX
VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 XIRQ/PE0
MC9S12C-Family
LQFP
XTAL
VDDR
RESET
VDDPLL
EXTAL
VSSR
Figure Assignments LQFP MC9S12C-Family
XCLKS/PE7
TEST/VPP IRQ/PE1
ECLK/PE4
VSSPLL
Device User Guide 9S12C-FamilyDGV1/D V00.03
Signal Properties Summary
Table Signal Properties
Name Name Name Power Function Function Function Domain
EXTAL XTAL RESET TEST BKGD PA[7:3] MODC NOACC IPIPE1 IPIPE0 ECLK LSTRB XIRQ ADDR[15:1/ DATA[15:1] TAGHI XCLKS MODB MODA TAGLO VDDPLL VDDPLL VDDX VDDPLL VSSX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
Internal Pull Resistor
CTRL None PUCR Reset State None Oscillator pins External reset loop filter Test only
Description
Background debug, mode pin, signal high Port pin, access, clock select Port pipe status Port pipe status Port pin, clock output Port pin, strobe, signal Port pin, expanded modes Port input, external interrupt Port input, non-maskable interrupt
While RESET low: Down While RESET low: Down PUCR PUCR PUCR PUCR PUCR PUCR
Disabled Port multiplexed address/data
PA[2:1]
PA[0] PB[7:5] PB[4] PB[3:0] PAD[7:0] PP[7] PP[6] PP[5]
ADDR[10:9/ DATA[10:9]
ADDR[8]/ DATA[8] ADDR[7:5]/ DATA[7:5] ADDR[4]/ DATA[4] ADDR[3:0]/ DATA[3:0] AN[7:0] KWP[7] KWP[6] KWP[5]
ROMCTL
VDDX
VDDX VDDX VDDX VDDX VDDA VDDX VDDX VDDX
PUCR
PUCR PUCR PUCR PUCR
Disabled Port multiplexed address/data
Disabled Port multiplexed address/data Disabled Port multiplexed address/data Disabled Port multiplexed address/data Disabled Port multiplexed address/data
PERAD/P Disabled Port pins inputs PSAD PERP/ PPSP PERP/ PPSP PERP/ PPSP Disabled Port Pins keypad wake-up Disabled Port Pins, keypad wake-up ROMON enable.
Disabled Port Pin, keypad wake-up, output
PP[4:3]
PP[2:0] PJ[7:6]
KWP[4:3]
KWP[2:0] KWJ[7:6]
PW[4:3]
PW[2:0]
VDDX
VDDX VDDX
PERP/ PPSP
PERP/ PPSP PERJ/ PPSJ
Disabled Port Pin, keypad wake-up, output
Disabled Port Pins, keypad wake-up, outputs Disabled Port Pins keypad wake-up
Device User Guide 9S12C-FamilyDGV1/D V00.03 Internal Pull Resistor
CTRL PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERS/ PPSS PERS/ PPSS PERS/ PPSS PERT/ PPST PERT/ PPST Reset State
Name Name Name Power Function Function Function Domain
PS[3:2] PT[7:5] PT[4:0] MOSI MISO TXCAN RXCAN IOC[7:5] IOC[4:0] PW[4:0] VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
Description
Disabled Port signal Disabled Port MOSI signal Disabled Port signal Disabled Port MISO signal Disabled Port transmit signal Disabled Port receive signal Port Pins Port transmit signal Port receive signal
Disabled Port Pins shared with timer (TIM) Disabled Port Pins shared with timer
2.2.1 Initialization LQFP bond-out versions
Bonded Pins port pins bonded chosen package user should initialize registers inputs with enabled pull resistance avoid excess current consumption. This applies following pins: (48LQFP): Port A[7:1], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[4:0], Port J[7:6], PortS[3:2] (52LQFP): Port A[7:3], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[2:0], Port J[7:6], PortS[3:2]
Detailed Signal Descriptions
2.3.1 EXTAL, XTAL Oscillator Pins
EXTAL XTAL crystal driver external clock pins. reset device clocks derived from EXTAL input frequency. XTAL crystal output.
Device User Guide 9S12C-FamilyDGV1/D V00.03
2.3.2 RESET External Reset
RESET active bidirectional control signal that acts input initialize known start-up state. also acts open-drain output indicate that internal failure been detected either clock monitor watchdog circuit. External circuitry connected RESET should include large capacitance that would interfere with ability this signal rise valid logic within ECLK cycles after drive released. Upon detection reset, internal circuit drives RESET clocked reset sequence controls when begin normal processing.
2.3.3 TEST Test
This reserved test must tied applications.
2.3.4 Loop Filter
Dedicated used create loop filter. more detailed information.PLL loop filter. Please your Motorola representative interactive application note compute loop filter elements. current leakage this must avoided.
VDDPLL VDDPLL
Figure Loop Filter Connections
2.3.5 BKGD TAGHI MODC Background Debug, High Mode
BKGD TAGHI MODC used pseudo-open-drain background debug communication. expanded modes operation when instruction tagging input this during falling edge E-clock tags high half instruction word being read into instruction queue. also used operating mode select rising edge during reset, when state this latched MODC bit.
Device User Guide 9S12C-FamilyDGV1/D V00.03
2.3.6 PA[7:0] ADDR[15:8] DATA[15:8] Port Pins
PA7-PA0 general purpose input output pins. expanded modes operation, these pins used multiplexed external address data bus. PA[7:1] pins available package version. PA[7:3] available package version.
2.3.7 PB[7:0] ADDR[7:0] DATA[7:0] Port Pins
PB7-PB0 general purpose input output pins. expanded modes operation, these pins used multiplexed external address data bus. PB[7:5] PB[3:0] pins available package version.
2.3.8 NOACC XCLKS Port
general purpose input output pin. During expanded modes operation, NOACC signal, when enabled, used indicate that current cycle unused "free" cycle. This signal will assert when using bus.The XCLKS input signal which controls whether crystal combination with internal Colpitts (low power) oscillator used whether Pierce oscillator/external clock circuitry used. state this latched rising edge RESET. input logic EXTAL configured external clock drive Pierce Oscillator. input logic high Colpitts oscillator circuit configured EXTAL XTAL. Since this input with pull-up device during reset, left floating, default configuration Colpitts oscillator circuit EXTAL XTAL.
EXTAL XTAL VSSPLL nature translated ground Colpitts oscillator voltage bias applied crystal .Please contact crystal manufacturer crystal Crystal ceramic resonator
Figure Colpitts Oscillator Connections (PE7=1)
Device User Guide 9S12C-FamilyDGV1/D V00.03
Figure Pierce Oscillator Connections (PE7=0)
EXTAL
Crystal ceramic resonator
XTAL
VSSPLL
zero (shorted) when with higher frequency crystals. Refer manufacturer's data.
Figure External Clock Connections (PE7=0)
EXTAL
CMOS-COMPATIBLE EXTERNAL OSCILLATOR (VDDPLL-Level)
XTAL
connected
2.3.9 MODB IPIPE1 Port
general purpose input output pin. used operating mode select during reset. state this latched MODB rising edge RESET. This shared with instruction queue tracking signal IPIPE1. This input with pull-down device which only active when RESET low. PE[6] available package versions.
Device User Guide 9S12C-FamilyDGV1/D V00.03
2.3.10 MODA IPIPE0 Port
general purpose input output pin. used operating mode select during reset. state this latched MODA rising edge RESET. This shared with instruction queue tracking signal IPIPE0. This input with pull-down device which only active when RESET low. This available package versions.
2.3.11 ECLK- Port E-Clock Output
ECLK output connection internal clock. used demultiplex address data expanded modes used timing reference. ECLK frequency equal crystal frequency reset. ECLK initially configured ECLK output with stretch expanded modes. clock output function depends upon settings NECLK PEAR register, IVIS MODE register ESTR EBICTL register. clocks, including clock, halted when STOP mode. possible configure interface slow external memory. ECLK stretched such accesses. Reference MISC register (EXSTR[1:0] bits) more information. normal expanded narrow mode, clock available external select decode logic constant speed clock external application system. Alternatively used general purpose input output pin.
2.3.12 LSTRB Port Low-Byte Strobe (LSTRB)
modes this used general-purpose input with active pull-up reset. strobe function required, should enabled setting LSTRE PEAR register. This signal used write operations. Therefore external byte writes will possible until this function enabled. This also used TAGLO Special Expanded modes multiplexed with LSTRB function. This available package versions.
2.3.13 Port Read/Write
modes this used general-purpose input with active pull-up reset. read/write function required should enabled setting RDWE PEAR register. External writes will possible until enabled. This available package versions.
2.3.14 Port input Maskable Interrupt
input provides means applying asynchronous interrupt requests MCU. Either falling edge-sensitive triggering level-sensitive triggering program selectable (INTCR register). always enabled configured level-sensitive triggering reset. disabled clearing IRQEN (INTCR register). When reset function masked condition code register. This always input always read. There active pull-up this while reset immediately reset. pull-up turned clearing PUPEE PUCR register.
Device User Guide 9S12C-FamilyDGV1/D V00.03
2.3.15 XIRQ Port input Maskable Interrupt
XIRQ input provides means requesting maskable interrupt after reset initialization. During reset, condition code register (CCR) interrupt masked until software enables Because XIRQ input level sensitive, connected multiple-source wired-OR network. This always input always read. There active pull-up this while reset immediately reset. pull-up turned clearing PUPEE PUCR register.
2.3.16 PAD[7:0] AN[7:0] Port Pins [7:0]
PAD7-PAD0 general purpose pins also analog inputs analog digital converter. order standard I/O, corresponding ATDDIEN register must set. These bits cleared reset configure pins operation.
2.3.17 PP[7] KWP[7] Port
general purpose input output pin, shared with keypad interrupt function. When configured input, generate interrupts causing exit STOP WAIT mode. This available package versions.
2.3.18 PP[6] KWP[6]/ROMCTL Port
general purpose input output pin, shared with keypad interrupt function. When configured input, generate interrupts causing exit STOP WAIT mode. This available package versions. During expanded modes operation, this used enable Flash EEPROM memory memory (ROMCTL). rising edge RESET, state this latched ROMON bit. PP6=1 emulation modes equates ROMON (ROM space externally mapped) PP6=0 expanded modes equates ROMON (ROM space externally mapped)
2.3.19 PP[5:0] KWP[5:0] PW[5:0] Port Pins [5:0]
PP[5:0] general purpose input output pins, shared with keypad interrupt function. When configured inputs, they generate interrupts causing exit STOP WAIT mode. PP[5:0] also shared with output signals, PW[5:0]. Pins PP[2:0] only available package version. Pins PP[4:3] available package version.
2.3.20 PJ[7:6] KWJ[7:6] Port Pins [7:6]
PJ[7:6] general purpose input output pins, shared with keypad interrupt function. When configured inputs, they generate interrupts causing exit STOP WAIT mode. These pins available package version package version.
Device User Guide 9S12C-FamilyDGV1/D V00.03
2.3.21 Port
general purpose input output also serial clock Serial Peripheral Interface (SPI).
2.3.22 MOSI Port
general purpose input output also master output (during master mode) slave input (during slave mode) Serial Peripheral Interface (SPI).
2.3.23 Port
general purpose input output also slave select Serial Peripheral Interface (SPI).
2.3.24 MISO Port
general purpose input output also master input (during master mode) slave output (during slave mode) Serial Peripheral Interface (SPI).
2.3.25 TXCAN Port
general purpose input output transmit pin, TXCAN, module.
2.3.26 RXCAN Port
general purpose input output receive pin, RXCAN, module.
2.3.27 PS[3:2] Port Pins [3:2]
general purpose input output pins. These pins available package versions.
2.3.28 Port
general purpose input output transmit pin, TXD, Serial Communication Interface (SCI).
2.3.29 Port
general purpose input output receive pin, RXD, Serial Communication Interface (SCI).
Device User Guide 9S12C-FamilyDGV1/D V00.03
2.3.30 PPT[7:5] IOC[7:5] Port Pins [7:5]
PT7-PT5 general purpose input output pins. They also configured timer system input capture output compare pins IOC7-IOC5.
2.3.31 PT[4:0] IOC[4:0] PW[4:0]- Port Pins [4:0]
PT4-PT0 general purpose input output pins. They also configured timer system input capture output compare pins IOC4-IOC0 outputs PW[4:0].
Power Supply Pins
2.4.1 VDDX,VSSX Power Ground Pins Drivers
External power ground drivers. Bypass requirements depend heavily pins loaded.
2.4.2 VDDR, VSSR Power Ground Pins Drivers Internal Voltage Regulator
External power ground drivers input internal voltage regulator. Bypass requirements depend heavily pins loaded. Connecting VDDR ground disables internal voltage regulator.
2.4.3 VDD1, VDD2, VSS1, VSS2 Core Power Pins
Power supplied through VSS. This 2.5V supply derived from internal voltage regulator. There static load those pins allowed. internal voltage regulator turned off, VDDR tied ground.
2.4.4 VDDA, VSSA Power Supply Pins VREG
VDDA, VSSA power supply ground input pins voltage regulator reference analog digital converter.
2.4.5 VRH, Reference Voltage Input Pins
reference voltage input pins analog digital converter.
2.4.6 VDDPLL, VSSPLL Power Supply Pins
Provides operating voltage ground Oscillator Phased-Locked Loop. This allows supply voltage Oscillator bypassed independently. This 2.5V voltage generated internal voltage regulator.
Device User Guide 9S12C-FamilyDGV1/D V00.03
Table MC9S12C-Family Power Ground Connection Summary
Mnemonic
VDD1 VDD2 VSS1 VSS2 VDDR VSSR VDDX VSSX VDDA VSSA VDDPLL VSSPLL
Nominal Voltage
Description
Internal power ground generated internal regulator. These also allow external source supply core VDD/VSS voltages bypass internal voltage regulator. LQFP packages VDD2 VSS2 available. External power ground, supply internal voltage regulator.
External power ground, supply drivers. Operating voltage ground analog-to-digital converters reference internal voltage regulator, allows supply voltage bypassed independently. Reference voltage converter. LQFP packages bonded VSSA. Provides operating voltage ground Phased-Locked Loop. This allows supply voltage bypassed independently. Internal power ground generated internal regulator.
NOTE:All pins must connected together application. Because fast signal transitions place high, short-duration current demands power supply, bypass capacitors with high-frequency characteristics place them close possible. Bypass requirements depend load.
Section System Clock Description
Clock Reset Generator provides internal clock signals core peripheral modules. Figure shows clock connections from modules. Consult Block User Guide details clock generation.
Device User Guide 9S12C-FamilyDGV1/D V00.03
S12_CORE core clock
Flash EXTAL clock oscillator clock XTAL VREG MSCAN
Figure Clock Connections
Section Modes Operation
Overview
Eight possible modes determine operating configuration MC9S12C Family. Each mode associated default memory external configuration controlled further pin. Three power modes exist device.
Chip Configuration Summary
operating mode reset determined states MODC, MODB, MODA pins during reset. MODC, MODB, MODA bits MODE register show current operating mode provide limited mode switching during operation. states MODC, MODB, MODA pins latched into these bits rising edge reset signal. ROMCTL signal allows setting ROMON MISC register thus controlling whether internal Flash visible memory map. ROMON mean Flash visible memory map. state ROMCTL latched into ROMON MISC register rising edge reset signal.
Device User Guide 9S12C-FamilyDGV1/D V00.03
Table Mode Selection
BKGD MODC
MODB
MODA
ROMCTL
ROMON
Mode Description
Special Single Chip, allowed ACTIVE. allowed other modes serial command required make active. Emulation Expanded Narrow, allowed Special Test (Expanded Wide), allowed Emulation Expanded Wide, allowed Normal Single Chip, allowed Normal Expanded Narrow, allowed Peripheral; allowed operations would cause conflicts (must used) Normal Expanded Wide, allowed
further explanation modes refer Core User Guide.
Table Clock Selection Based
XCLKS
Description
Colpitts Oscillator selected Pierce Oscillator/external clock selected
Security
device will make available security feature preventing unauthorized read write memory contents. This feature allows: Protection contents FLASH, Operation single-chip mode, Operation from external memory with internal FLASH disabled.
user must reminded that part security must with user's code. extreme example would user's code that dumps contents internal program. This code would defeat purpose security. same time user also wish back door user's program. example this user downloads through which allows access programming routine that updates parameters.
Device User Guide 9S12C-FamilyDGV1/D V00.03
4.3.1 Securing Microcontroller
Once user programmed FLASH, part secured programming security bits located FLASH module. These non-volatile bits will keep part secured through resetting part through powering down part. security byte resides portion Flash array. Check Flash Block User Guide more details security configuration.
4.3.2 Operation Secured Microcontroller
4.3.2.1 Normal Single Chip Mode This will most common usage secured part. Everything will appear same part secured with exception operation. operation will blocked. 4.3.2.2 Executing from External Memory user wish execute from external space with secured microcontroller. This accomplished resetting directly into expanded mode. internal FLASH will disabled. operations will blocked.
4.3.3 Unsecuring Microcontroller
order unsecure microcontroller, internal FLASH must erased. This done through external program expanded mode sequence commands. Unsecuring also possible Backdoor Access. Refer Flash Block Guide details. Once user erased FLASH, part reset into special single chip mode. This invokes program that verifies erasure internal FLASH. Once this program completes, user erase program FLASH security bits unsecured state. This generally done through BDM, user could also change expanded mode writing mode bits through BDM) jumping external program (again through commands). Note that part goes through reset before security bits reprogrammed unsecure state, part will secured again.
Power Modes
microcontroller features three main power modes. Consult respective Block User Guide information module behavior Stop, Pseudo Stop, Wait Mode. important source information about clock system Clock Reset Generator User Guide (CRG).
4.4.1 Stop
Executing STOP instruction stops clocks oscillator thus putting chip fully static mode. Wake from this mode done reset external interrupts.
Device User Guide 9S12C-FamilyDGV1/D V00.03
4.4.2 Pseudo Stop
This mode entered executing STOP instruction. this mode oscillator still running Real Time Interrupt (RTI) Watchdog (COP) module stay active. Other peripherals turned off. This mode consumes more current than full STOP mode, wake time from this mode significantly shorter.
4.4.3 Wait
This mode entered executing instruction. this mode will execute instructions. internal signals (address databus) will fully static. peripherals stay active. further power consumption reduction peripherals individually turn their local clocks.
4.4.4
Although this power mode, unused peripheral modules should enabled order save power.
Section Resets Interrupts
Overview
Consult Exception Processing section HCS12 Core User Guide information resets interrupts.
Vectors
5.2.1 Vector Table
Table lists interrupt sources vectors default order priority. Table Interrupt Vector Locations
Vector Address
$FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFF0, $FFF1
Interrupt Source
External Reset, Power Reset Voltage Reset (see Flags Register determine reset source) Clock Monitor fail reset failure reset Unimplemented instruction trap XIRQ Real Time Interrupt
Mask
None None None None None X-Bit I-Bit I-Bit
Local Enable
None COPCTL (CME, FCME) rate select None None None INTCR (IRQEN) CRGINT (RTIE)
HPRIO Value Elevate
Device User Guide 9S12C-FamilyDGV1/D V00.03
$FFEE, $FFEF $FFEC, $FFED $FFEA, $FFEB $FFE8, $FFE9 $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFDE, $FFDF $FFDC, $FFDD $FFDA, $FFDB $FFD8, $FFD9 $FFD6, $FFD7 $FFD4, $FFD5 $FFD2, $FFD3 $FFD0, $FFD1 $FFCE, $FFCF $FFCC, $FFCD $FFCA, $FFCB $FFC8, $FFC9 $FFC6, $FFC7 $FFC4, $FFC5 $FFBA $FFC3 $FFB8, $FFB9 $FFB6, $FFB7 $FFB4, $FFB5 $FFB2, $FFB3 $FFB0, $FFB1 $FF90 $FFAF $FF8E, $FF8F $FF8C, $FF8D $FF8A, $FF8B $FF80 $FF89 Port Emergency Shutdown VREG FLASH wake-up errors receive transmit lock Self Clock Mode Port Standard Timer channel Standard Timer channel Standard Timer channel Standard Timer channel Standard Timer channel Standard Timer channel Standard Timer channel Standard Timer channel Standard Timer overflow Pulse accumulator overflow Pulse accumulator input edge I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved I-Bit Reserved I-Bit Reserved Reserved Reserved I-Bit I-Bit Reserved I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved Reserved PIEP (PIEP7-0) PWMSDN(PWMIE) CTRL0 (LVIE) FCNFG (CCIE, CBEIE) CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0]) PLLCR (LOCKIE) PLLCR (SCMIE) PIEP (PIEP7-6) ATDCTL2 (ASCIE) (C0I) (C1I) (C2I) (C3I) (C4I) (C5I) (C6I) (C7I) TMSK2 (TOI) PACTL (PAOVI) PACTL (PAI) SPICR1 (SPIE, SPTIE) SCICR2 (TIE, TCIE, RIE, ILIE)
Resets
Resets subset interrupts featured inTable 5-1. different sources capable generating system reset summarized Table 5-2. When reset occurs, registers control bits changed known start-up states. Refer respective module Block User Guides register reset states.
Device User Guide 9S12C-FamilyDGV1/D V00.03
5.3.1 Reset Summary Table
Table Reset Summary
Reset
Power-on Reset External Reset Voltage Reset Clock Monitor Reset Watchdog Reset
Priority
Source
Module RESET VREG Module Module Module
Vector
$FFFE, $FFFF $FFFE, $FFFF $FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB
5.3.2 Effects Reset
When reset occurs, registers control bits changed known start-up states. Refer respective module Block User Guides register reset states. Refer HCS12 Core User Guides mode dependent configuration port reset. Refer Block User Guide reset configurations peripheral module ports. Refer Figure Figure footnotes locations memories depending operating mode after reset. array automatically initialized reset.
NOTE:
devices assembled 48-pin 52-pin LQFP packages non-bonded pins should configured outputs after reset order avoid current drawn from floating inputs. Refer Table affected pins.
Section HCS12 Core Block Description
Consult HCS12 Core User Guide information about HCS12 core modules, i.e. central processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed external interface (MEBI), debug12 module (DBG12) background debug mode module (BDM).
Device-specific information
6.1.1 PPAGE
External paging supported these devices. order access flash blocks address range $8000-$BFFF PPAGE register must loaded with corresponding value this range. Refer Table device specific page mapping. devices Flash Page visible $C000-$FFFF range ROMON set. devices Page also visible $4000-$7FFF range ROMHM cleared ROMON set. devices apart from MC9S12C32 Flash Page visible $0000-$3FFF range ROMON set.
Device User Guide 9S12C-FamilyDGV1/D V00.03
Table Device Specfic Flash PAGE Mapping
Device
MC9S12C32 MC9S12C32 MC9S12C64 MC9S12C64 MC9S12C64 MC9S12C64 MC9S12C96 MC9S12C96 MC9S12C96 MC9S12C96 MC9S12C96 MC9S12C96 MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C128 MC9S12C128
PAGE
PAGE visible with PPAGE contents
$04,$0C,$14,$1C,$24,$2C,$34,$3C $05,$0D,$15,$1D,$25,$2D,$35,$3D $06,$0E,$16,$1E,$26,$2E,$36,$3E $07,$0F,$17,$1F,$27,$2F,$37,$3F $00,$08,$10,$18,$20,$28,$30,$38 $01,$09,$11,$19,$21,$29,$31,$39 $02,$0A,$12,$1A,$22,$2A,$32,$3A $03,$0B,$13,$1B,$23,$2B,$33,$3B $04,$0C,$14,$1C,$24,$2C,$34,$3C $05,$0D,$15,$1D,$25,$2D,$35,$3D $06,$0E,$16,$1E,$26,$2E,$36,$3E $07,$0F,$17,$1F,$27,$2F,$37,$3F
6.1.2 alternate clock
section Core User Guide reference alternate clock equivalent oscillator clock.
6.1.3 Extended Address Range Emulation Implications
order emulate MC9S12C-Family devices, external addressing 128K memory required. This provided LQFP package version which includes necessary extra external address signals PortK[2:0]. This package version emulation only provided general production package. reset state DDRK S12_CORE $00, configuring pins inputs. reset state PUPKE PUCR register S12_CORE enabling internal PortK pullups. this reset state pull-ups provide defined state prevent floating input, thereby preventing unneccesary current flow input stage. prevent unneccesary current flow production package options, states DDRK PUPKE should changed software.
Device User Guide 9S12C-FamilyDGV1/D V00.03
Section Voltage Regulator (VREG) Block Description
Consult VREG Block User Guide information about dual output linear voltage regulator.
Device-specific information
VREG part IPBus domain.
7.1.1 VREGEN
VREGEN connected internally VDDR.
7.1.2 VDD1, VDD2, VSS1, VSS2
package versions, both internal 2.5V domain bonded sides device pairs (VDD1, VSS1 VDD2, VSS2). VDD1 VDD2 connected together internally. VSS1 VSS2 connected together internally. extra pair enables systems using package employ better supply routing further decoupling.
Section Recommended Printed Circuit Board Layout
must carefully laid ensure proper operation voltage regulator well itself. following rules must observed: Every supply pair must decoupled ceramic capacitor connected near possible corresponding pins C6). Central point ground star should VSSR pin. ohmic inductance connections between VSS1, VSS2 VSSR. VSSPLL must directly connected VSSR. Keep traces VSSPLL, EXTAL XTAL short possible occupied board area small possible. place other signals supplies underneath area occupied connection area MCU. Central power input should VDDA/VSSA pins.
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Table Recommended External Component Values
Component
Purpose
VDD1 filter VDD2 filter only) VDDA filter VDDR filter VDDPLL filter VDDX filter load
Type
ceramic ceramic ceramic X7R/tantalum ceramic X7R/tantalum
Value
220nF, 470nF1 220nF 100nF >=100nF 100nF >=100nF
specification chapter load loop filter specification chapter loop filter cutoff loop filter Quartz Colpitts mode only, recommended quartz manufacturer Specification chapter
NOTES: 48LQFP 52LQFP package versions, VDD2 available. Thus 470nF must connected VDD1.
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Figure Recommended Layout LQFP)
VDDX
VSSX
VSSA
VDDA VDD1 VSS1
VSSR
VDDR
Note Oscillator Colpitts mode.
VSSPLL VDDPLL
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Figure Recommended Layout LQFP)
NOTE Oscillator Colpitts mode.
VDDX
VSSX VSSA
VDDA VDD1 VSS1
VSSR VDDR VSSPLL VDDPLL
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Figure Recommended Layout QFP)
NOTE Oscillator Colpitts mode.
VSSA
VSSX
VDDX
VDDA
VDD1 VSS1
VSS2
VDD2
VSSR
VDDR
VSSPLL VDDPLL
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Section Clock Reset Generator (CRG) Block Description
Consult Block User Guide information about Clock Reset Generator module.
Device-specific information
part IPBus domain. Voltage Reset feature uses voltage reset signal from VREG module input module. When regulator output voltage supply internal chip logic falls below specified threshold signal from VREG module causes module generate reset. Consult VREG Block User Guide voltage level specifications.
9.1.1 XCLKS
XCLKS input signal active (see 2.3.8 NOACC XCLKS Port
Section Oscillator (OSC) Block Description
Consult Block User Guide information about Oscillator module.
Section Timer (TIM) Block Description
Consult TIM_16B8C Block User Guide information about Timer module. part IPBus domain.
Section Analog Digital Converter (ATD) Block Description
12.1 Device-specific information
part IPBus domain.
12.1.1 (voltage reference low)
package versions, bonded internally VSSA pin. Consult ATD_10B8C Block User Guide further information about Converter module.
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Section Serial Communications Interface (SCI) Block Description
Consult Block User Guide information about Serial Communications Interface module. part IPBus domain.
Section Serial Peripheral Interface (SPI) Block Description
Consult Block User Guide information about Serial Peripheral Interface module. part IPBus domain.
Section Flash Block Description
Consult FTS32K Block User Guide information about Flash module MC9S12C32. Consult FTS64K Block User Guide information about Flash module MC9S12C64. Consult FTS96K Block User Guidefor information about Flash module MC9S12C96. Consult FTS128K Block User Guide information about Flash module MC9S12C128. Flash part HCS12 domain.
Section Block Description
This module supports single-cycle misaligned word accesses without wait states. MC9S12C32 features single byte module. MC9S12C64, MC9S12C96 MC9S12C128 versions feature separate byte modules. Consult SRAM2K Block User Guide information about Module part HCS12 domain.
Section Pulse Width Modulator (PWM) Block Description
Only channels [5:0] implemented MC9S12C-Family.
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Consult PWM_8B6C Block User Guide information about Pulse Width Modulator Module. part IPBus domain.
Section MSCAN Block Description
Consult MSCAN Block User Guide information about Motorola Scalable Module. MSCAN part IPBus domain.
Section Port Integration Module (PIM) Block Description
Consult PIM_9C32 Block User Guide information about Port Integration Module versions MC9S12C-Family. part IPBus domain.
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Appendix Electrical Characteristics
General
NOTE:
electrical characteristics given this section preliminary should used guide only. Values cannot guaranteed Motorola subject change without notice. parts specified tested over 3.3V ranges. intermediate range, generally electrical specifications 3.3V range apply, parts tested production test intermediate range.
NOTE:
This supplement contains most accurate electrical information MC9S12C-Family microcontrollers available time publication. information should considered PRELIMINARY subject change. This introduction intended give overview several common topics like power supply, current injection etc.
A.1.1 Parameter Classification
electrical parameters shown this supplement guaranteed various methods. give customer better understanding following classification used parameters tagged accordingly tables where appropriate.
NOTE:
This classification will added later release specification
Those parameters guaranteed during production testing each individual device. Those parameters achieved design characterization measuring statistically relevant sample size across process variations. They regularly verified production monitors. Those parameters achieved design characterization small sample size from typical devices. values shown typical column within this category. Those parameters derived mainly from simulations.
A.1.2 Power Supply
MC9S12C-Family utilizes several pins supply power ports, converter, oscillator well digital core. VDDA, VSSA pair supplies converter. VDDX, VSSX pair supplies pins VDDR, VSSR pair supplies internal voltage regulator. VDD1, VSS1, VDD2 VSS2 supply pins digital logic. VDDPLL, VSSPLL supply oscillator PLL.
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VSS1 VSS2 internally connected metal. VDD1 VDD2 internally connected metal. VDDA, VDDX, VDDR well VSSA, VSSX, VSSR connected anti-parallel diodes protection.
NOTE:
following context VDD5 used either VDDA, VDDR VDDX; VSS5 used either VSSA, VSSR VSSX unless otherwise noted. IDD5 denotes currents flowing into VDDA, VDDX VDDR pins. used VDD1, VDD2 VDDPLL, used VSS1, VSS2 VSSPLL. used currents flowing into VDD1 VDD2.
A.1.3 Pins
There four groups functional pins. A.1.3.1 pins Those pins have nominal level This class pins comprised port pins, analog inputs, BKGD RESET inputs.The internal structure those pins identical, however some functionality disabled. E.g. pull-up pull-down resistors disabled permanently. A.1.3.2 Analog Reference This class made pins. package versions bonded VSSA pin. A.1.3.3 Oscillator pins XFC, EXTAL, XTAL dedicated oscillator have nominal 2.5V level. They supplied VDDPLL. A.1.3.4 TEST This used production testing only.
A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 range during instantaneous operating maximum current conditions. positive injection current (Vin VDD5) greater than IDD5, injection current flow VDD5 could result external power supply going regulation. Insure external VDD5 load will shunt current greater than maximum injection current. This will greatest risk when consuming power; e.g. system clock present, clock rate very which would reduce overall power consumption.
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A.1.5 Absolute Maximum Ratings
Absolute maximum ratings stress ratings only. functional operation under outside those maxima guaranteed. Stress beyond those limits affect reliability cause permanent damage device. This device contains circuitry protecting against damage high static voltage electrical fields; however, advised that normal precautions taken avoid application voltages higher than maximum-rated voltages this high-impedance circuit. Reliability operation enhanced unused inputs tied appropriate logic voltage level (e.g., either VSS5 VDD5).
Table Absolute Maximum Ratings
Rating
I/O, Regulator Analog Supply Voltage Digital Logic Supply Voltage1 Supply Voltage Voltage difference VDDX VDDR VDDA Voltage difference VSSX VSSR VSSA Digital Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single limit digital pins Instantaneous Maximum Current Single limit XFC, EXTAL, XTAL3 Instantaneous Maximum Current Single limit TEST4 Operating Temperature Range (packaged) Operating Temperature Range (junction) Storage Temperature Range
Symbol
VDD5 VDDPLL VDDX VSSX VRH, VILV VTEST
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.25
10.0
Unit
Tstg
NOTES: device contains internal voltage regulator generate logic supply supply. absolute maximum ratings apply when device powered from external source. digital pins internally clamped VSSX VDDX, VSSR VDDR VSSA VDDA. These pins internally clamped VSSPLL VDDPLL This clamped VSSPLL, clamped high. This must tied applications.
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A.1.6 Protection Latch-up Immunity
testing conformity with CDF-AEC-Q100 Stress test qualification Automotive Grade Integrated Circuits. During device qualification stresses were performed Human Body Model (HBM), Machine Model (MM) Charge Device Model. device will defined failure after exposure pulses device longer meets device specification. Complete parametric functional testing performed applicable device specification room temperature followed temperature, unless specified otherwise device specification. Table Latch-up Test Conditions
Model
Series Resistance Storage Capacitance Human Body Number Pulse positive negative Series Resistance Storage Capacitance Machine Number Pulse positive negative Minimum input voltage limit Latch-up Maximum input voltage limit
Description
Symbol
Value
1500 -2.5
Unit
Table Latch-Up Protection Characteristics
Rating
Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Latch-up Current 125°C positive negative Latch-up Current 27°C positive negative
Symbol
VHBM VCDM ILAT
2000 +100 -100 +200 -200
Unit
ILAT
A.1.7 Operating Conditions
This chapter describes operating conditions devices. Unless otherwise noted those conditions apply following data.
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NOTE:
Instead specifying ambient temperature parameters specified more meaningful silicon junction temperature. power dissipation calculations refer Section A.1.8 Power Dissipation Thermal Characteristics. Table Operating Conditions
Rating Symbol
VDD5 VDDPLL VDDX VSSX fosc fbus
2.97 2.25 2.25 -0.1 -0.1
2.75 2.75
Unit
I/O, Regulator Analog Supply Voltage Digital Logic Supply Voltage1 Supply Voltage Voltage Difference VDDX VDDA Voltage Difference VSSX VSSR VSSA Oscillator Frequency Operating Junction Temperature Range
NOTES: device contains internal voltage regulator generate logic supply supply.
A.1.8 Power Dissipation Thermal Characteristics
Power dissipation thermal characteristics closely related. user must assure that maximum operating junction temperature exceeded. average chip-junction temperature (TJ) obtained from: Junction Temperature, Ambient Temperature, Total Chip Power Dissipation, Package Thermal Resistance, [°C/W] total power dissipation calculated from: Chip Internal Power Dissipation,
cases with internal voltage regulator enabled disabled must considered: Internal Voltage Regulator disabled
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DDPLL DDPLL DSON
Which output currents ports associated with VDDX VDDM. RDSON valid: DSON ;for outputs driven
DSON ;for outputs driven high Internal voltage regulator enabled IDDR current shown Table overall current flowing into VDDR, which additionally contains current flowing into external loads with output high. DSON
respectively
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Which output currents ports associated with VDDX VDDR. Table Thermal Package Characteristics1
Rating
Thermal Resistance LQFP48, single layer PCB2 Thermal Resistance LQFP48, double sided with internal planes3 Junction Board LQFP48 Junction Case LQFP48 Junction Package LQFP48 Thermal Resistance LQFP52, single sided Thermal Resistance LQFP52, double sided with internal planes Junction Board LQFP52 Junction Case LQFP52 Junction Package LQFP52 Thermal Resistance single sided Thermal Resistance double sided with internal planes Junction Board QFP80 Junction Case QFP80 Junction Package QFP80
Symbol
Unit
oC/W
oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W
NOTES: values thermal resistance achieved package simulations Board according EIA/JEDEC Standard 51-2 Board according EIA/JEDEC Standard 51-7
A.1.9 Characteristics
This section describes characteristics pins. parameters always applicable, e.g. pins feature pull up/down resistances.
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Table Characteristics
Conditions 4.5< VDDX <5.5V Termperature from -40°C +140°C, unless otherwise noted
Input High Voltage Input High Voltage Input Voltage Input Voltage Input Hysteresis
Rating
Symbol
0.65*VDD5 VSS5
VDD5 0.35*VDD5
Unit
Input Leakage Current (pins high ohmic input mode)1 VDD5 VSS5 Output High Voltage (pins output mode) Partial Drive -2mA Output High Voltage (pins output mode) Full Drive -10mA Output Voltage (pins output mode) Partial Drive +2mA Output Voltage (pins output mode) Full Drive +10mA Internal Pull Device Current, tested Max.
-2.5
VDD5 VDD5
IPUL IPUH IPDH IPDL IICS IICP tPIGN tPVAL
-130
Internal Pull Device Current, tested Min.
Internal Pull Down Device Current, tested Min.
Internal Pull Down Device Current, tested Max.
Input Capacitance Injection current2 Single limit Total Device Limit. injected currents Port Interrupt Input Pulse filtered3 Port Interrupt Input Pulse passed3
-2.5
NOTES: Maximum leakage current occurs maximum operating temperature. Current decreases approximately one-half each temperature range from Refer Section A.1.4 Current Injection, more details Parameter only applies STOP Pseudo STOP mode.
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Table 3.3V Characteristics
Conditions VDDX=3.3V +/-10%, Termperature from -40°C +140°C, unless otherwise noted
Input High Voltage Input High Voltage Input Voltage Input Voltage Input Hysteresis
Rating
Symbol
0.65*VDD5 VSS5
VDD5 0.35*VDD5
Unit
Input Leakage Current (pins high ohmic input mode)1 VDD5 VSS5 Output High Voltage (pins output mode) Partial Drive -0.75mA Output High Voltage (pins output mode) Full Drive -4.5mA Output Voltage (pins output mode) Partial Drive +0.9mA Output Voltage (pins output mode) Full Drive +5.5mA Internal Pull Device Current, tested Max.
-2.5
VDD5 VDD5
IPUL IPUH IPDH IPDL IICS IICP tPIGN tPVAL
Internal Pull Device Current, tested Min. Internal Pull Down Device Current, tested Min.
Internal Pull Down Device Current, tested Max.
Input Capacitance Injection current2 Single limit Total Device Limit. injected currents Port Interrupt Input Pulse filtered3 Port Interrupt Input Pulse passed3
-2.5
NOTES: Maximum leakage current occurs maximum operating temperature. Current decreases approximately one-half each temperature range from Refer Section A.1.4 Current Injection, more details Parameter only applies STOP Pseudo STOP mode.
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A.1.10 Supply Currents
This section describes current consumption characteristics device well conditions measurements. A.1.10.1 Measurement Conditions measurements without output loads. Unless otherwise noted currents measured single chip mode, internal voltage regulator enabled 25MHz frequency using 4MHz oscillator. A.1.10.2 Additional Remarks expanded modes currents flowing system highly dependent load address, data control signals well duty cycle those signals. generally applicable numbers given. very good estimate take single chip currents currents external loads.
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Table Supply Current Characteristics MC9S12C32
Conditions shown Table with internal regulator enabled unless otherwise noted
Rating
Supply Current Single Chip Wait Supply current modules enabled VDDR<4.9V, only enabled(2) VDDR>4.9V, only enabled Pseudo Stop Current (RTI disabled)(2)(3) -40°C 27°C 85°C Temp Option 100°C 105°C Temp Option 120°C 125°C Temp Option 140°C Pseudo Stop Current (RTI enabled)2 -40°C 27°C 85°C 105°C 125°C Stop Current -40°C 27°C 85°C Temp Option 100°C 105°C Temp Option 120°C 125°C Temp Option 140°C
Symbol
IDD5
Unit
IDDW
1100 1300
1450 1900 4500
IDDPS1
IDDPS1
1000 1400 4000
IDDS(1)
NOTES: STOP current measured production test increased junction temperature, hence Temp Option test carried 100°C although Temperature specification 85°C. Similarly options temperature used test lies 15°C above temperature option specification. those power dissipation levels assumed
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Table Supply Current Characteristics MC9S12C64,MC9S12C96,MC9S12C128
Conditions shown Table with internal regulator enabled unless otherwise noted
Rating
Supply Current Single Chip, Wait Supply current modules enabled VDDR<4.9V, only enabled(2) VDDR>4.9V, only enabled Pseudo Stop Current (RTI disabled)(2)(3) -40°C 27°C 85°C Temp Option 100°C 105°C Temp Option 120°C 125°C Temp Option 140°C Pseudo Stop Current (RTI enabled)2 -40°C 27°C 85°C 105°C 125°C Stop Current -40°C 27°C 85°C Temp Option 100°C 105°C Temp Option 120°C 125°C Temp Option 140°C
Symbol
IDD5
Unit
IDDW
1000 1200
1400 1900 4800
IDDPS1
IDDPS1
1200 1700 4500
IDDS(1)
NOTES: STOP current measured production test increased junction temperature, hence Temp Option test carried 100°C although Temperature specification 85°C. Similarly options temperature used test lies 15°C above temperature option specification. those power dissipation levels assumed
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Appendix Electrical Specifications
Voltage Regulator Operating Conditions
Table Voltage Regulator Electrical Parameters
Characteristic
Input Voltages Regulator Current Reduced Power Mode Shutdown Mode Output Voltage Core Full Performance Mode Reduced Power Mode Shutdown Mode Output Voltage Full Performance Mode Reduced Power Mode2 Reduced Power Mode3 Shutdown Mode Voltage Interrupt5 Assert Level Deassert Level Voltage Reset6 Assert Level Assert Level C64, C96, C128 Power-on Reset7 Assert Level Deassert Level
Symbol
VVDDR, IREG
2.97
Typical
Unit
2.35
2.75 2.75
VDDPLL
2.35
2.75 2.75 2.75
VLVIA VLVID
4.30 4.42
4.53 4.65
4.77 4.89
VLVRA
2.25
2.35
VPORA VPORD
0.97
2.05
NOTES: High Impedance Output Current IDDPLL (Colpitts Oscillator) Current IDDPLL (Pierce Oscillator) High Impedance Output Monitors VDDA, active only Full Performance Mode. Indicates performance degradation supply voltage. Monitors VDD, active only Full Performance Mode. monitored (see Figure B-1) Monitors VDD. Active modes.
NOTE:
electrical characteristics given this section preliminary should used guide only. Values this section cannot guaranteed Motorola subject change without notice.
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Chip Power-up LVI/LVR graphical explanation
Voltage regulator modules (low voltage interrupt), (power-on reset) (low voltage reset) handle chip power-up drops supply voltage. Their function described Figure B-1. Figure Voltage Regulator Chip Power-up Voltage Drops (not scaled)
VLVID VLVIA VDDA
VLVRD VLVRA VPORD
enabled
disabled
Output Loads
B.3.1 Resistive Loads
on-chip voltage regulator intended supply internal logic oscillator circuits allows external loads.
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B.3.2 Capacitive Loads
capacitive loads specified Table B-2. Ceramic capacitors with dielectricum required. Table Voltage Regulator Capacitive Loads
Characteristic
external capacitive load VDDPLL external capacitive load
Symbol
CDDext CDDPLLext
Typical
12000 5000
Unit
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Characteristics
This section describes characteristics analog digital converter. available separate versions. this case internal bonded VSSA pin. specified tested both 3.3V range. ranges between 3.3V accuracy generally same 3.3V range tested this range production test.
B.4.1 Operating Characteristics Range
Table shows conditions under which operates. following constraints exist obtain full-scale, full range results: VSSA VDDA. This constraint exists since sample buffer amplifier drive beyond power supply levels that ties input level goes outside this range will effectively clipped. Table Operating Characteristics
Conditions shown Table unless otherwise noted. Supply Voltage 5V-10% VDDA <=5V+10%
Reference Potential
Rating
High Differential Reference Voltage1 Clock Frequency 10-Bit Conversion Period Clock Cycles2 Conv, Time 2.0MHz Clock fATDCLK 8-Bit Conversion Period Clock Cycles2 Conv, Time 2.0MHz Clock fATDCLK Recovery Time (VDDA=5.0 Volts) Reference Supply current
Symbol VRH-VRL fATDCLK NCONV10 TCONV10 NCONV10 TCONV10 tREC IREF
VSSA VDDA/2 4.75
VDDA/2 VDDA
Unit Cycles Cycles
5.25 0.375
NOTES: Full accuracy guaranteed when differential voltage less than 4.75V minimum time assumes final sample period clocks cycles while maximum time assumes final sample period clocks.
B.4.2 Operating Characteristics 3.3V Range
Table shows conditions under which operates. following constraints exist obtain full-scale, full range results: VSSA VDDA. This constraint exists since sample buffer amplifier drive
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beyond power supply levels that ties input level goes outside this range will effectively clipped
Table Operating Characteristics
Conditions shown Table unless otherwise noted; Supply Voltage 3.3V-10% VDDA 3.3V+10%
Reference Potential
Rating
High
Symbol VRH-VRL fATDCLK
VSSA VDDA/2
VDDA/2 VDDA
Unit Cycles Cycles
Differential Reference Voltage Clock Frequency 10-Bit Conversion Period
0.250
Clock Cycles1 NCONV10 Conv, Time 2.0MHz Clock fATDCLK TCONV10 8-Bit Conversion Period Clock Cycles(1) Conv, Time 2.0MHz Clock fATDCLK
NCONV8 TCONV8 tREC IREF
Recovery Time (VDDA=3.3 Volts) Reference Supply current
NOTES: minimum time assumes final sample period clocks cycles while maximum time assumes final sample period clocks.
B.4.3 Factors influencing accuracy
Three factors source resistance, source capacitance current injection have influenceon accuracy ATD. B.4.3.1 Source Resistance: input leakage current specified Table conjunction with source resistance there will voltage drop from signal source input. maximum source resistance specifies results error less than (2.5mV) maximum leakage current. device operating conditions less than worst case leakage-induced error acceptable, larger values source resistance allowable. B.4.3.2 Source capacitance When sampling additional internal capacitor switched input. This cause voltage drop charge sharing with external capacitance. maximum sampling error input voltage 1LSB, then external filter capacitor, 1024 (CINS- CINN).
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B.4.3.3 Current injection There cases consider. current injected into channel being converted. channel being stressed conversion values $3FF ($FF 8-bit mode) analog inputs greater than $000 values less than unless current higher than specified disruptive conditions. Current injected into pins neighborhood channel being converted. portion this current picked channel (coupling ratio This additional current impacts accuracy conversion depending source resistance. additional input voltage error converted channel calculated VERR IINJ, with IINJ being currents injected into pins adjacent converted channel. Table Electrical Characteristics
Conditions shown Table unless otherwise noted
Rating
input Source Resistance Total Input Capacitance Sampling Sampling Disruptive Analog Input Current Coupling Ratio positive current injection Coupling Ratio negative current injection
Symbol
CINN CINS
Unit
-2.5
10-4 10-2
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B.4.4 accuracy Range)
Table specifies conversion performance excluding errors current injection, input capacitance source resistance. Table Conversion Performance
Conditions shown Table unless otherwise noted VREF 5.12V. Resulting count 20mV count
fATDCLK 2.0MHz
10-Bit Resolution
Rating
Symbol
Unit
10-Bit Differential Nonlinearity 10-Bit Integral Nonlinearity 10-Bit Absolute Error1 8-Bit Resolution 8-Bit Differential Nonlinearity 8-Bit Integral Nonlinearity 8-Bit Absolute Error(1)
-2.5 -0.5 -1.0 -1.5 ±0.5
Counts Counts Counts
Counts Counts Counts
NOTES: These values include quantization error which inherently count converter.
B.4.5 accuracy (3.3V Range)
Table specifies conversion performance excluding errors current injection, input capacitance source resistance. Table Conversion Performance
Conditions shown Table unless otherwise noted VREF 3.328V. Resulting count 13mV count 3.25mV
fATDCLK 2.0MHz
10-Bit Resolution
Rating
Symbol
3.25
Unit
10-Bit Differential Nonlinearity 10-Bit Integral Nonlinearity 10-Bit Absolute 8-Bit Resolution 8-Bit Differential Nonlinearity 8-Bit Integral Nonlinearity 8-Bit Absolute Error(1) Error1
-1.5 -3.5 ±1.5 ±2.5 -0.5 -1.5 -2.0 ±1.5
Counts Counts Counts
Counts Counts Counts
NOTES: These values include quantization error which inherently count converter.
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following definitions also Figure B-2. Differential Non-Linearity (DNL) defined difference between adjacent switching steps.
1LSB
Integral Non-Linearity (INL) defined DNLs:
1LSB
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Vi-1
$3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5
10-Bit Absolute Error Boundary 8-Bit Absolute Error Boundary
10-Bit Resolution
$3F4 $3F3
3.25 9.75 16.25 19.5 22.75 29.25
Ideal Transfer Curve
10-Bit Transfer Curve
8-Bit Transfer Curve
3286 3289 3292 3295 3299 3302 3305 3309 3312 3315 3318 3321 3324 3328
Figure Accuracy Definitions
NOTE:
Figure shows only definitions, specification values refer Table B-6.
8-Bit Resolution
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NVM, Flash EEPROM
B.5.1 timing
time base program erase operations derived from oscillator. minimum oscillator frequency fNVMOSC required performing program erase operations. modules have means monitor frequency will prevent program erase operation frequencies above below specified minimum. Attempting program erase modules lower frequency full program erase transition assured. Flash program erase operations timed using clock derived from oscillator using FCLKDIV ECLKDIV registers respectively. frequency this clock must within limits specified fNVMOP. minimum program erase times shown Table calculated maximum fNVMOP maximum fbus. maximum times calculated minimum fNVMOP fbus 2MHz.
B.5.1.1 Single Word Programming programming time single word programming dependant frequency well frequency calculated according following formula.
swpgm NVMOP
B.5.1.2 Burst Programming This applies only Flash where words programmed consecutively using burst programming keeping command pipeline filled. time program consecutive word calculated
bwpgm NVMOP
time program whole
brpgm swpgm bwpgm
Burst programming more than times faster than single word programming. B.5.1.3 Sector Erase Erasing byte Flash sector takes:
4000 NVMOP
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setup times ignored this operation. B.5.1.4 Mass Erase Erasing block takes:
mass 20000 NVMOP
setup times ignored this operation.
Table Timing Characteristics
Conditions shown Table unless otherwise noted
Rating
External Oscillator Clock frequency Programming Erase Operations Operating Frequency Single Word Programming Time Flash Burst Programming consecutive word Flash Burst Programming Time Words Sector Erase Time Mass Erase Time Blank Check Time Flash block
Symbol
fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tera tmass check
20.42 678.42 1004
Unit
74.53 1035.53 26.73 1333 327786
tcyc
NOTES: Restrictions oscillator crystal mode apply! Minimum Programming times achieved under maximum operating frequency NVMOP maximum frequency fbus. Maximum Erase Programming times achieved under particular combinations NVMOP frequency Refer formulae Sections A.3.1.1 A.3.1.4 guidance. Minimum Erase times achieved under maximum operating frequency NVMOP Minimum time, first word array blank Maximum time complete check erased block.
B.5.2 Reliability
reliability blocks guaranteed stress test during qualification, constant process monitors burn-in screen early life failures. failure rates data retention program/erase cycling specified <2ppm defects over lifetime operating conditions noted. program/erase cycle specified transitions cell value from erased programmed erased,
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NOTE:
values shown Table target values subject further extensive characterization. Table Reliability Characteristics
Conditions shown Table unless otherwise noted
Rating
Data Retention average junction temperature TJavg 85°C Flash number Program/Erase cycles
Symbol
tNVMRET nFLPE
10,000
Unit
Years Cycles
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Reset, Oscillator
This section summarizes electrical characteristics various startup scenarios Oscillator Phase-Locked-Loop (PLL).
B.6.1 Startup
Table B-10 summarizes several startup characteristics explained this section. Detailed description startup behavior found Clock Reset Generator (CRG) Block User Guide. Table B-10 Startup Characteristics
Conditions shown Table unless otherwise noted
release level assert level
Rating
Symbol
VPORR VPORA PWRSTL nRST PWIRQ tWRS VLVRR VLVRA
2.07
Unit
tosc
0.97 2.25 2.55
Reset input pulse width, minimum input time Startup from Reset Interrupt pulse width, edge-sensitive mode Wait recovery startup time release level assert level
nosc tcyc
B.6.1.1 release level VPORR assert level VPORA derived from Supply. They also valid device powered externally. After releasing reset oscillator clock quality check started. after time tCQOUT valid oscillation detected, will start using internal self clock. fastest startup time possible given nuposc. B.6.1.2 release level VLVRR assert level VLVRA derived from Supply. They also valid device powered externally. After releasing reset oscillator clock quality check started. after time tCQOUT valid oscillation detected, will start using internal self clock. fastest startup time possible given nuposc. B.6.1.3 SRAM Data Retention Provided appropriate external reset signal applied MCU, preventing from executing code when VDD5 specification limits, SRAM contents integrity guaranteed after reset PORF Flags Register been set.
Device User Guide 9S12C-FamilyDGV1/D V00.03
B.6.1.4 External Reset When external reset asserted time greater than PWRSTL module generates internal reset, starts fetching reset vector without doing clock quality check, there oscillation before reset. B.6.1.5 Stop Recovery STOP controller woken external interrupt. clock quality check after performed before releasing clocks system. B.6.1.6 Pseudo Stop Wait Recovery recovery from Pseudo STOP Wait essentially same since oscillator stopped both modes. controller woken internal external interrupts. After twrs starts fetching interrupt vector.
B.6.2 Oscillator
device features internal Colpitts oscillator. asserting XCLKS input during reset this oscillator bypassed allowing input square wave. Before asserting oscillator internal system clocks quality oscillation checked each start from either power-on, STOP oscillator fail. tCQOUT specifies maximum time before switching internal self clock mode case proper oscillation detected. quality monitor also determines minimum oscillator start-up
Device User Guide 9S12C-FamilyDGV1/D V00.03
time tUPOSC. device features clock monitor. time-out asserted frequency incoming clock signal below Clock Monitor FailureAssert Frequency fCMFA. Table B-11 Oscillator Characteristics
Conditions shown Table unless otherwise noted
Rating
Crystal oscillator range (Colpitts) Crystal oscillator range (Pierce) 1(4) Startup Current Oscillator start-up time (Colpitts) Clock Quality check time-out Clock Monitor Failure Assert Frequency External square wave input frequency External square wave pulse width External square wave pulse width high External square wave rise time External square wave fall time Input Capacitance (EXTAL, XTAL pins) Operating Bias Colpitts Configuration EXTAL
Symbol
fOSC fOSC iOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF VDCBIAS
Unit
0.45
1003
NOTES: Depending crystal damping series resistor might necessary fosc 4MHz, 22pF. Maximum value extreme cases using high frequency crystals XCLKS during reset
B.6.3 Phase Locked Loop
oscillator provides reference clock PLL. Voltage Controlled Oscillator (VCO) also system clock source self clock mode. B.6.3.1 Component Selection This section describes selection components achieve good filter characteristics.
Device User Guide 9S12C-FamilyDGV1/D V00.03
VDDPLL fosc fref refdv+1 fcmp Phase Detector Loop Divider synr+1
fvco
Figure Basic functional diagram following procedure used calculate resistance capacitance values using typical values from Table B-12. grey boxes show calculation fVCO 50MHz fref 1MHz. E.g., these frequencies used fOSC 4MHz 25MHz clock. Gain desired frequency approximated
-90.48MHz/V
phase detector relationship given
current tracking mode.
316.7Hz/
loop bandwidth should chosen fulfill Gardner's stability criteria least factor typical values ensures good tr
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