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8-Bit A / D Converter AD673

VSS DIGITAL COMMON CONVERT MSB DB7 DB6

FEATURES Complete 8-Bit A / D Converter with Reference, Clock and Comparator 30 s Maximum Conversion Time Full 8- or 16-Bit Microprocessor Bus Interface Unipolar and Bipolar Inputs No Missing Codes Over Temperature Operates on +5 V and -12 V to -15 V Supplies MIL-STD-883 Compliant Version Available
8-Bit A / D Converter AD673
FUNCTIONAL BLOCK DIAGRAM
VSS DIGITAL COMMON CONVERT MSB DB7 DB6
8-BIT CURRENT OUTPUT DAC COMPARATOR 8-BIT SAR
ANALOG IN ANALOG COMMON
DB5 DB4 DB3
BIPOLAR OFFSET CONTROL
INT CLOCK
DB2 DB1 DB0 LSB DATA ENABLE
GENERAL DESCRIPTION
BURIED ZENER REF DATA READY
AD673
Protected by U.S. Patent Nos. 3, 940, 760 4, 213, 806 4, 136, 349 4, 400, 689 and 4, 400, 690.
PRODUCT HIGHLIGHTS
1. The AD673 is a complete 8-bit A / D converter. No external components are required to perform a conversion. 2. The AD673 interfaces to many popular microprocessors without external buffers or peripheral interface adapters. 3. The device offers true 8-bit accuracy and exhibits no missing codes over its entire operating temperature range. 4. The AD673 adapts to either unipolar (0 V to +10 V) or bipolar (-5 V to +5 V) analog inputs by simply grounding or opening a single pin. 5. Performance is guaranteed with +5 V and -12 V or -15 V supplies. 6. The AD673 is available in a version compliant with MILSTD-883. Refer to the Analog Devices Military Products Databook or current AD673 / 883B data sheet for detailed specifications.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD673-SPECIFICATIONS
FULL-SCALE CALIBRATION2
Positive True Binary Positive True Offset Binary
NOTES 1 Relative accuracy is defined as the deviation of the code transition points from the ideal transfer point on a straight line from the zero to the full scale of the device. 2 Full-scale calibration is guaranteed trimmable to zero with an external 200 potentiometer in place of the 15 fixed resistor. Full scale is defined as 10 volts minus 1 LSB, or 9.961 V. 3 Defined as the resolution for which no missing codes will occur. 4 The data output lines have active pull-ups to source 0 5 mA. The DATA READY line is open collector with a nominal 6 k internal pull-up resistor. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
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AD673
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
Model AD673JN AD673JD AD673SD2 AD673JP
Temperature Range 0°C to +70°C 0°C to +70°C -55°C to +125°C 0°C to +70°C
Package Option1 Plastic DIP (N-20) Ceramic DIP (D-20) Ceramic DIP (D-20) PLCC (P-20A)
FUNCTIONAL DESCRIPTION
The temperature compensated buried Zener reference provides the primary voltage reference to the DAC and ensures excellent stability with both time and temperature. The bipolar offset input controls a switch which allows the positive bipolar offset current (exactly equal to the value of the MSB less 1 / 2 LSB) to be injected into the summing (+) node of the comparator to offset the DAC output. Thus the nominal 0 V to +10 V unipolar input range becomes a -5 V to +5 V range. The 5 k thin-film input resistor is trimmed so that with a full-scale input signal, an input current will be generated which exactly matches the DAC output with all bits on.
UNIPOLAR CONNECTION
DIGITAL COMMON
CONVERT MSB DB7 DB6
ANALOG IN ANALOG COMMON
The AD673 contains all the active components required to perform a complete A / D conversion. Thus, for many applications, all that is necessary is connection of the power supplies (+5 V and -12 V to -15 V), the analog input and the convert pulse. However, there are some features and special connections which should be considered for achieving optimum performance. The functional pinout is shown in Figure 2. The standard unipolar 0 V to +10 V range is obtained by shorting the bipolar offset control pin (Pin 16) to digital common (Pin 17).
PIN 1 IDENTIFIER
8-BIT CURRENT OUTPUT DAC COMPARATOR
8-BIT SAR
DB5 DB4 DB3
BIPOLAR OFFSET CONTROL
INT CLOCK
DB2 DB1 DB0 LSB DATA ENABLE
20 DATA ENABLE 19 NC 18 DATA READY 17 DIGITAL COMMON
AD673
16 BIPOLAR OFFSET
BURIED ZENER REF DATA READY
AD673
TOP VIEW 15 ANALOG COMMON (Not to Scale) DB4 7 14 ANALOG IN DB3 6 DB5 8 13 V- 12 CONVERT 11 V+
Figure 1. AD673 Functional Block Diagram
DB6 9 MSB DB7 10
The SAR drives DR low to indicate that the conversion is complete and that the data is available to the output buffers. DATA ENABLE can then be activated to enable the 8-bits of data desired. DATA ENABLE should be brought high prior to the next conversion to place the output buffers in the high impedance state. REV. A -3-
PINS 1 & 2 ARE INTERNALLY CONNECTED TO TEST POINTS AND SHOULD BE LEFT FLOATING
Figure 2. AD673 Pin Connections
AD673
Full-Scale Calibration
Figure 4a shows how the converter zero may be offset to correct for initial offset and / or input signal offsets. As shown, the circuit gives approximately symmetrical adjustment in unipolar mode. Figure 5 shows the nominal transfer curve near zero for an AD673 in unipolar mode. The code transitions are at the edges of the nominal bit weights. In some applications it will be preferable to offset the code transitions so that they fall between the nominal bit weights, as shown in the offset characteristics.
Figure 3. Standard AD673 Connections
Unipolar Offset Calibration
This offset can easily be accomplished as shown in Figure 4b. At balance (after a conversion) approximately 2 mA flows into the Analog Common terminal. A 10 resistor in series with this terminal will result in approximately the desired l / 2 bit offset of the transfer characteristics. The nominal 2 mA Analog Common current is not closely controlled in manufacture. If high accuracy is required, a 20 potentiometer (connected as a rheostat) can be used as R1. Additional negative offset range may be obtained by using larger values of R1. Of course, if the zero transition point is changed, the full-scale transition point will also move. Thus, if an offset of 1 / 2 LSB is introduced, full scale trimming as described on the previous page should be done with an analog input of 9.941 volts. NOTE: During a conversion, transient currents from the Analog Common terminal will disturb the offset voltage. Capacitive decoupling should not be used around the offset network. These transients will settle appropriately during a conversion. Capacitive decoupling will "pump up" and fail to settle resulting in conversion errors. Power supply decoupling, which returns to analog signal common, should go to the signal input side of the resistive offset network.
Figure 4b. Figure 4a. Figure 4. Unipolar Offset Trimming
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AD673
BIPOLAR CONNECTION
To obtain the bipolar -5 V to +5 V range with an offset binary output code, the bipolar offset control pin is left open. A -5.00 volt signal will give a 8-bit code of 00000000 an input of 0.00 volts results in an output code of 10000000 and +4.961 volts at the input yields the 11111111 code. The nominal transfer curve is shown in Figure 6.
SAMPLE-HOLD AMPLIFIER CONNECTION TO THE AD673
Many situations in high-speed acquisition systems or digitizing rapidly changing signals require a sample-hold amplifier (SHA) in front of the A-D converter. The SHA can acquire and hold a signal faster than the converter can perform a conversion. A SHA can also be used to accurately define the exact point in time at which the signal is sampled. For the AD673, a SHA can also serve as a high input impedance buffer. Figure 8 shows the AD673 connected to the AD582 monolithic SHA for high speed signal acquisition. In this configuration, the AD582 will acquire a 10 volt signal in less than 10 µs with a droop rate less than 100 µV / ms. DR goes high after the conversion is initiated to indicate that reset of the SAR is complete. In Figure 8 it is also used to put the AD582 into the hold mode while the AD673 begins its conversion cycle. (The AD582 settles to final value well in advance of the first comparator decision inside the AD673).
Figure 6. AD673 Transfer Curve-Bipolar Operation
Note that in the bipolar mode, the code transitions are offset 1 / 4 LSB such that an input voltage of 0 volts -5 mV to +35 mV yields the code representing zero (10000000). Each output code is then centered on its nominal input voltage.
Full-Scale Calibration
DR goes low when the conversion is complete placing the AD582 back in the sample mode. Configured as shown in Figure 8, the next conversion can be initiated after a 10 µs delay to allow for signal acquisition by the AD582. Observe carefully the ground, supply, and bypass capacitor connections between the two devices. This will minimize ground noise and interference during the conversion cycle.
Full-Scale Calibration is accomplished in the same manner as in Unipolar operation except the full-scale input voltage is +4.61 volts.
Negative Full-Scale Calibration
The circuit in Figure 4a can also be used in Bipolar operation to offset the input voltage (nominally -5 V) which results in the 000000 00 code. R2 should be omitted to obtain a symmetrical range. The bipolar offset control input is not directly TTL compatible but a TTL interface for logic control can be constructed as shown in Figure 7.
Figure 8. Sample-Hold Interface to the AD673
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AD673
GROUNDING CONSIDERATIONS TIMING SPECIFICATIONS
CONTROL AND TIMING OF THE AD673
Parameter CONVERT Pulse Width DR Delay from CONVERT Conversion Time Data Access Time Data Valid after DE High Output Float Delay
Symbol Min Typ Max Units tCS tDSC tC tDD tHD tHL 500 - 10 0 50 - - 1 20 150 - 100 - 1.5 30 250 - 200 ns µs µs ns ns ns
MICROPROCESSOR INTERFACE CONSIDERATIONS- GENERAL
The operation of the AD673 is controlled by two inputs: CONVERT and DATA ENABLE.
Starting a Conversion
The conversion cycle is initiated by a positive-going CONVERT pulse at least 500 ns wide. The rising edge of this pulse resets the internal logic, clears the result of the previous conversion, and sets DR high. The falling edge of CONVERT begins the conversion cycle. When conversion is completed DR returns low. During the conversion cycle, DE should be held high. If DE goes low during a conversion, the data output buffers will be enabled and intermediate conversion results will be present on the data output pins. This may cause bus conflicts if other devices in a system are trying to use the bus.
VIH + VIL 2 CONVERT
tC tCS tDSC
Figure 9. Convert Timing
Reading the Data
The three-state data output buffers is enabled by DE. Access time of these buffers is typically 150 ns (250 maximum). The Data outputs remain valid until 50 ns after the enable signal returns high, and are completely into the high-impedance state 100 ns later.
DE VIH + VIL 2 HIGH IMPEDANCE
VOH VOL DATA VALID
DB0-DB7
HIGH IMPEDANCE
Figure 11. General AD673 Interface to 8-Bit Microprocessor
Figure 10. Read Timing
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AD673
In systems where this read-write interface is used, at least 30 microseconds (the maximum conversion time) must be allowed to pass between starting a conversion and reading the results. This delay or "time-out" period can be implemented in a short software routine such as a countdown loop, enough dummy instructions to consume 30 microseconds, or enough actual useful instructions to consume the required time. In tightlytimed systems, the DR line may be read through an external three-state buffer to determine precisely when a conversion is complete. Higher-speed systems may choose to use DR to signal an interrupt to the processor at the end of a conversion.
CONVERT Pulse Generation
The AD673 is tested with a CONVERT pulse width of 500 ns and will typically operate with a pulse as short as 300 ns. However, some microprocessors produce active WR pulses which are shorter than this. Either of the circuits shown in Figure 13 can be used to generate an adequate CONVERT pulse for the AD673. In both circuits, the short low-going WR pulse sets the CONVERT line high through a flip-flop. The rising edge of DR (which signifies that the internal logic has been reset) resets the flip-flop and brings CONVERT low, which starts the conversion. Note that tDSC is slightly longer when the result of the previous conversion contains a Logic 1 on the LSB. This means that the actual CONVERT pulse generated by the circuits in Figure 13 will vary slightly in width.
Figure 13a. Using 74LS00
Figure 13b. Using 1 / 2 74LS74
Figure 12. Typical AD673 Timing Diagram
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AD673
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Pin Ceramic DIP (D-20)
20-Pin Plastic DIP (N-20)
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PRINTED IN U.S.A.
C853c-5-3 / 87