8-Bit Converter AD673* FUNCTIONAL BLOCK DIAGRAM DIGITAL COMM
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FEATURES Complete 8-Bit Converter with Reference, Clock Comparator Maximum Conversion Time Full 16-Bit Microprocessor Interface Unipolar Bipolar Inputs Missing Codes Over Temperature Operates Supplies MIL-STD-883 Compliant Version Available
8-Bit Converter AD673*
FUNCTIONAL BLOCK DIAGRAM
DIGITAL COMMON CONVERT
8-BIT CURRENT OUTPUT COMPARATOR 8-BIT
ANALOG ANALOG COMMON
BIPOLAR OFFSET CONTROL
CLOCK
DATA ENABLE
GENERAL DESCRIPTION
BURIED ZENER DATA READY
AD673
AD673 complete 8-bit successive approximation analog-to-digital converter consisting DAC, voltage reference, clock, comparator, successive approximation register (SAR) 3-state output buffers-all fabricated single chip. external components required perform full accuracy 8-bit conversion AD673 incorporates advanced integrated circuit design processing technologies. successive approximation function implemented with (integrated injection logic). Laser trimming high stability SiCr thin-film resistor ladder network insures high accuracy, which maintained with temperature compensated sub-surface Zener reference. Operating supplies AD673 will accept analog inputs trailing edge positive pulse CONVERT line initiates conversion cycle. DATA READY indicates completion conversion. AD673 available versions. AD673J specified over +70°C temperature range AD673S guarantees relative accuracy missing codes from -55°C +125°C. package configurations offered. versions also offered 20-pin hermetically sealed ceramic DIP. AD673J also available 20-pin plastic DIP.
*Protected U.S. Patent Nos. 3,940,760; 4,213,806; 4,136,349; 4,400,689; 4,400,690.
PRODUCT HIGHLIGHTS
AD673 complete 8-bit converter. external components required perform conversion. AD673 interfaces many popular microprocessors without external buffers peripheral interface adapters. device offers true 8-bit accuracy exhibits missing codes over entire operating temperature range. AD673 adapts either unipolar bipolar analog inputs simply grounding opening single pin. Performance guaranteed with supplies. AD673 available version compliant with MILSTD-883. Refer Analog Devices Military Products Databook current AD673/883B data sheet detailed specifications.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD673-SPECIFICATIONS
Model RESOLUTION RELATIVE ACCURACY, TMIN TMAX UNIPOLAR OFFSET BIPOLAR OFFSET DIFFERENTIAL NONLINEARITY, TMIN TMAX TEMPERATURE RANGE TEMPERATURE COEFFICIENTS Unipolar Offset Bipolar Offset Full-Scale Calibration2 POWER SUPPLY REJECTION Positive Supply +4.5 +5.5 Negative Supply -15.75 -14.25 -12.6 -11.4 ANALOG INPUT IMPEDANCE ANALOG INPUT RANGES Unipolar Bipolar OUTPUT CODING Unipolar Bipolar LOGIC OUTPUT Output Sink Current (VOUT max, TMIN TMAX) Output Source Current4 (VOUT min, TMIN TMAX) Output Leakage LOGIC INPUTS Input Current Logic Logic CONVERSION TIME, TMIN TMAX POWER SUPPLY OPERATING CURRENT
voltages measured with respect digital common, unless otherwise noted)
AD673J +125 AD673S Units Bits Bits Bits
FULL-SCALE CALIBRATION2
Positive True Binary Positive True Offset Binary
Positive True Binary Positive True Offset Binary
+4.5 -11.4 +5.0 +7.0 -16.5
+4.5 -11.4 +5.0 +7.0 -16.5
NOTES Relative accuracy defined deviation code transition points from ideal transfer point straight line from zero full scale device. Full-scale calibration guaranteed trimmable zero with external potentiometer place fixed resistor. Full scale defined volts minus LSB, 9.961 Defined resolution which missing codes will occur. data output lines have active pull-ups source DATA READY line open collector with nominal internal pull-up resistor. Specifications subject change without notice. Specifications shown boldface tested production units final electrical test. Results from those tests used calculate outgoing quality levels. specifications guaranteed, although only those shown boldface tested production units.
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AD673
ABSOLUTE MAXIMUM RATINGS
Digital Common Digital Common -16.5 Analog Common Digital Common Analog Input Analog Common Control Inputs Digital Outputs (High Impedance State) Power Dissipation
ORDERING GUIDE
Model AD673JN AD673JD AD673SD2 AD673JP
Temperature Range +70°C +70°C -55°C +125°C +70°C
Relative Accuracy
Package Option1 Plastic (N-20) Ceramic (D-20) Ceramic (D-20) PLCC (P-20A)
NOTES Ceramic DIP; Plastic DIP; Plastic Leaded Chip Carrier. details grade package offering screened accordance with MIL-STD-883, refer Analog Devices Military Products Databook
FUNCTIONAL DESCRIPTION
block diagram AD673 shown Figure positive CONVERT pulse must least wide. goes high within after leading edge convert pulse indicating that internal logic been reset. negative edge CONVERT pulse initiates conversion. internal 8-bit current output sequenced integrated injection logic (I2L) successive approximation register (SAR) from most significant least significant provide output current which accurately balances input signal current through resistor. comparator determines whether addition each successively weighted current causes current greater less than input current; more, turned off. After testing bits, contains 8-bit binary code which accurately represents input signal within (0.05% full scale).
temperature compensated buried Zener reference provides primary voltage reference ensures excellent stability with both time temperature. bipolar offset input controls switch which allows positive bipolar offset current (exactly equal value less LSB) injected into summing node comparator offset output. Thus nominal unipolar input range becomes range. thin-film input resistor trimmed that with full-scale input signal, input current will generated which exactly matches output with bits
UNIPOLAR CONNECTION
DIGITAL COMMON
CONVERT
ANALOG ANALOG COMMON
AD673 contains active components required perform complete conversion. Thus, many applications, that necessary connection power supplies analog input convert pulse. However, there some features special connections which should considered achieving optimum performance. functional pinout shown Figure standard unipolar range obtained shorting bipolar offset control (Pin digital common (Pin 17).
IDENTIFIER
8-BIT CURRENT OUTPUT COMPARATOR
8-BIT
BIPOLAR OFFSET CONTROL
CLOCK
DATA ENABLE
DATA ENABLE DATA READY DIGITAL COMMON
AD673
BIPOLAR OFFSET
BURIED ZENER DATA READY
AD673
VIEW ANALOG COMMON (Not Scale) ANALOG CONVERT
Figure AD673 Functional Block Diagram
drives indicate that conversion complete that data available output buffers. DATA ENABLE then activated enable 8-bits data desired. DATA ENABLE should brought high prior next conversion place output buffers high impedance state. REV.
*PINS INTERNALLY CONNECTED TEST POINTS SHOULD LEFT FLOATING
Figure AD673 Connections
AD673
Full-Scale Calibration
thin-film input resistor laser trimmed produce current which matches full-scale current internal DAC-plus about 0.3%-when analog input voltage 9.961 volts volts LSB) applied input. input resistor trimmed this that fine trimming potentiometer inserted series with input signal, input current full scale input voltage trimmed down match full-scale current precisely desired. However, many applications nominal 9.961 volt full scale achieved sufficient accuracy simply inserting resistor series with analog input Typical full-scale calibration error will then within 0.8%. more precise calibration desired, trimmer should used instead. analog input 9.961 volts, trimmer that output code just transition between 111111 11111111. Each will then have weight 39.06 nominal full scale 10.24 volts desired (which makes have weight exactly 40.0 mV), resistor trimmer trimmer with good resolution) should used. course, larger full-scale ranges arranged using larger input resistor, linearity full-scale temperature coefficient compromised external resistor becomes sizeable percentage Figure illustrates connections required full-scale calibration.
Figure shows converter zero offset correct initial offset and/or input signal offsets. shown, circuit gives approximately symmetrical adjustment unipolar mode. Figure shows nominal transfer curve near zero AD673 unipolar mode. code transitions edges nominal weights. some applications will preferable offset code transitions that they fall between nominal weights, shown offset characteristics.
Figure AD673 Transfer Curve-Unipolar Operation (Approximate Weights Shown Illustration, Nominal Weights 39.06
Figure Standard AD673 Connections
Unipolar Offset Calibration
Since Unipolar Offset less than versions AD673, most applications will require trimming. Figure illustrates trimming methods which used greater accuracy necessary.
This offset easily accomplished shown Figure balance (after conversion) approximately flows into Analog Common terminal. resistor series with this terminal will result approximately desired offset transfer characteristics. nominal Analog Common current closely controlled manufacture. high accuracy required, potentiometer (connected rheostat) used Additional negative offset range obtained using larger values course, zero transition point changed, full-scale transition point will also move. Thus, offset introduced, full scale trimming described previous page should done with analog input 9.941 volts. NOTE: During conversion, transient currents from Analog Common terminal will disturb offset voltage. Capacitive decoupling should used around offset network. These transients will settle appropriately during conversion. Capacitive decoupling will "pump fail settle resulting conversion errors. Power supply decoupling, which returns analog signal common, should signal input side resistive offset network.
Figure Figure Figure Unipolar Offset Trimming
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AD673
BIPOLAR CONNECTION
obtain bipolar range with offset binary output code, bipolar offset control left open. -5.00 volt signal will give 8-bit code 00000000; input 0.00 volts results output code 10000000 +4.961 volts input yields 11111111 code. nominal transfer curve shown Figure
SAMPLE-HOLD AMPLIFIER CONNECTION AD673
Many situations high-speed acquisition systems digitizing rapidly changing signals require sample-hold amplifier (SHA) front converter. acquire hold signal faster than converter perform conversion. also used accurately define exact point time which signal sampled. AD673, also serve high input impedance buffer. Figure shows AD673 connected AD582 monolithic high speed signal acquisition. this configuration, AD582 will acquire volt signal less than with droop rate less than µV/ms. goes high after conversion initiated indicate that reset complete. Figure also used AD582 into hold mode while AD673 begins conversion cycle. (The AD582 settles final value well advance first comparator decision inside AD673).
Figure AD673 Transfer Curve-Bipolar Operation
Note that bipolar mode, code transitions offset such that input voltage volts yields code representing zero (10000000). Each output code then centered nominal input voltage.
Full-Scale Calibration
goes when conversion complete placing AD582 back sample mode. Configured shown Figure next conversion initiated after delay allow signal acquisition AD582. Observe carefully ground, supply, bypass capacitor connections between devices. This will minimize ground noise interference during conversion cycle.
Full-Scale Calibration accomplished same manner Unipolar operation except full-scale input voltage +4.61 volts.
Negative Full-Scale Calibration
circuit Figure also used Bipolar operation offset input voltage (nominally which results 000000 code. should omitted obtain symmetrical range. bipolar offset control input directly compatible interface logic control constructed shown Figure
Figure Sample-Hold Interface AD673
Figure Bipolar Offset Controlled Logic Gate Gate Output Unipolar V-10 Input Range Gate Output Bipolar Input Range
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AD673
GROUNDING CONSIDERATIONS TIMING SPECIFICATIONS
AD673 provides separate Analog Digital Common connections. circuit will operate properly with much common-mode voltage between commons. This permits more flexible control system common bussing digital analog returns. normal operation, Analog Common terminal generate transient currents during conversion. addition static current about will flow into Analog Common unipolar mode after conversion complete. Analog Common current will modulated variations input signal. absolute maximum voltage rating between commons volt. recommended that parallel pair back-to-back protection diodes connected between commons they connected locally.
CONTROL TIMING AD673
Parameter CONVERT Pulse Width Delay from CONVERT Conversion Time Data Access Time Data Valid after High Output Float Delay
Symbol Units tDSC
MICROPROCESSOR INTERFACE CONSIDERATIONS- GENERAL
operation AD673 controlled inputs: CONVERT DATA ENABLE.
Starting Conversion
When analog-to-digital converter like AD673 interfaced microprocessor, several details interface must considered. First, signal start converter must generated; then appropriate delay period must allowed pass before valid conversion data read. most applications, AD673 interface microprocessor system with little external logic. most popular control signal configuration consists decoding address assigned AD673, then gating this signal with system's signal generate CONVERT pulse, gating with enable output buffers. memory address memory signals denotes "memory-mapped" interfacing, while separate address space denotes "isolated I/O" interfacing. Figure shows generalized diagram control logic AD673 interfaced 8-bit data bus, where address ADDR been decoded. ADDR starts converter when written (the actual data being written converter does matter) contains high byte data during read operations.
conversion cycle initiated positive-going CONVERT pulse least wide. rising edge this pulse resets internal logic, clears result previous conversion, sets high. falling edge CONVERT begins conversion cycle. When conversion completed returns low. During conversion cycle, should held high. goes during conversion, data output buffers will enabled intermediate conversion results will present data output pins. This cause conflicts other devices system trying bus.
CONVERT
tDSC
Figure Convert Timing
Reading
three-state data output buffers enabled Access time these buffers typically (250 maximum). Data outputs remain valid until after enable signal returns high, completely into high-impedance state later.
HIGH IMPEDANCE
DATA VALID
DB0-DB7
HIGH IMPEDANCE
Figure General AD673 Interface 8-Bit Microprocessor
Figure Read Timing
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AD673
systems where this read-write interface used, least microseconds (the maximum conversion time) must allowed pass between starting conversion reading results. This delay "time-out" period implemented short software routine such countdown loop, enough dummy instructions consume microseconds, enough actual useful instructions consume required time. tightlytimed systems, line read through external three-state buffer determine precisely when conversion complete. Higher-speed systems choose signal interrupt processor conversion.
CONVERT Pulse Generation
AD673 tested with CONVERT pulse width will typically operate with pulse short However, some microprocessors produce active pulses which shorter than this. Either circuits shown Figure used generate adequate CONVERT pulse AD673. both circuits, short low-going pulse sets CONVERT line high through flip-flop. rising edge (which signifies that internal logic been reset) resets flip-flop brings CONVERT low, which starts conversion. Note that tDSC slightly longer when result previous conversion contains Logic LSB. This means that actual CONVERT pulse generated circuits Figure will vary slightly width.
Figure 13a. Using 74LS00
Figure 13b. Using 74LS74
Figure Typical AD673 Timing Diagram
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AD673
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
20-Pin Ceramic (D-20)
20-Pin Plastic (N-20)
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PRINTED U.S.A.
C853c-5-3/87
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