Description T7295-1 Integrated Line Receiver fully integrated rec
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T7295-1 Integrated Line Receiver
Description
T7295-1 Integrated Line Receiver fully integrated receive interface that terminates bipolar (34.368 Mbits/s) signal transmitted over coaxial cable. This device used with T7296 Integrated Line Transmitter. device provides functions receive equalization (optional), automatic-gain control (AGC), clock recovery data retiming, loss-of-signal loss-of-frequency-lock detection. digital system interface dual rail, with received positive negative appearing unipolar digital signals separate output leads. on-chip equalizer designed cable losses receive input variable input sensitivity control, providing three different sensitivity settings. High input sensitivity allows significant amounts flat loss within system. Figure shows block diagram device. T7295-1 device manufactured using linear CMOS technology packaged 20-pin, plastic 20-pin, plastic package surface mounting. Figure shows layout both package types.
Fully integrated receive interface signals Integrated equalization (optional) timing recovery Loss-of-signal loss-of-lock alarms Variable input sensitivity control Single power supply
Applications
Interface networks CSU/DSU equipment test equipment Fiber-optic terminals Companion device T7296 transmitter
T7295-1 Integrated Line Receiver
Description (continued)
REQB LPF1 LPF2 VDDA GNDA VDDD GNDD VDDC GNDC
ATTENUATOR
GAIN EQUALIZER
SLICERS
PHASE DETECTOR
LOOP FILTER
RCLK
PEAK DETECTOR RETIMER RPDATA RNDATA
LOSTHR
DIGITAL DETECTOR FREQUENCY/ PHASE ACQUISITION CIRCUIT ANALOG RLOS
ANALOG
EQUALIZER TUNING CIRCUIT
PACKAGE TMC1 TMC2 EXCLK RLOL
5-1240(C)r.7
Figure Block Diagram
Information
GNDA TMC1 LPF1 LPF2 TMC2 RLOS RLOL GNDD GNDC VDDA LOSTHR REQB RPDATA RNDATA RCLK EXCLK VDDC VDDD
5-1251(C).ar.1
T7295-1
Figure Assignment
Lucent Technologies Inc.
T7295-1 Integrated Line Receiver
Information (continued)
Table Descriptions Symbol GNDA TMC1, TMC2 LPF1, LPF2 Type Analog Ground. Receive Input. Single-ended analog receive input. This internally biased approximately series with Test Mode Control Internal test modes enabled within device using TMC1 TMC2. Users must these pins ground plane. Filter external capacitor (0.1 20%) connected between these pins. capacitor should mounted close pins possible (within recommended). Receive Loss Signal. This high loss data signal receive input. Receive Loss Lock. This high loss frequency lock. Digital Ground Clock. Ground lead circuitry running synchronously with clock. Digital Ground EXCLK. Ground lead circuitry running synchronously with EXCLK. Digital Supply (±10%) Clock. Power circuitry running synchronously with clock. Digital Supply (±10%) EXCLK. Power circuitry running synchronously with EXCLK. External Reference Clock. valid (34.368 ppm) clock must provided this input. EXCLK must independent clock guarantee device performance specifications. duty cycle EXCLK, referenced VDD/2 levels, must with maximum rise fall time (10% 90%) Receive Clock. Recovered clock signal terminal equipment. Receive Negative Data. Negative pulse data output terminal equipment. Receive Positive Data. Positive pulse data output terminal equipment. In-Circuit Test Control (Active-Low). forced low, digital output pins (RCLK, RPDATA, RNDATA, RLOS, RLOL) placed high-impedance state allow in-circuit testing. nominal pull-up provided this pin. Receive Equalization Bypass. high this bypasses internal equalizer. places equalizer data path. Loss-of-Signal Threshold Control. voltage forced this controls input loss-of-signal threshold. Three settings provided forcing GND, VDD/2, VDD. This must desired level upon powerup should changed during operation. Analog Supply (±10%). Name/Description
RLOS RLOL GNDD GNDC VDDD VDDC EXCLK
RCLK RNDATA RPDATA
REQB LOSTHR
VDDA
Lucent Technologies Inc.
T7295-1 Integrated Line Receiver
case external line equalizer network precedes T7295-1 device. this mode, signal already equalized, on-chip equalizer should bypassed setting REQB both case case signal must meet amplitude limits described Table recommended receive termination shown Figure resistor terminates coaxial cable with characteristic impedance. Figure case fixed equalizer includes line termination, resistor required. signal ac-coupled through 0.01 capacitor RIN. bias generated internally. input capacitance typically (SOJ package) (DIP package).
Overview
Receive Path Configuration
diagram Figure shows typical system application T7295-1 device. receive signal path (see Figure internal equalizer included setting REQB bypassed setting REQB equalizer bypass option allows easy interfacing T7295-1 device into systems already containing external equalizers. Figure illustrates receive path options separate cases. case signal from coaxial cable feeds directly into input. this mode, user should REQB engaging equalizer data path cable loss greater than cable loss less than equalizer bypassed setting REQB
SYSTEM dB-15 T7295-1 T7296 TRANSMITTER COAXIAL CABLE
SYSTEM
T7296 TRANSMITTER T7295-1
5-2635(C).ar.1
Figure Application Diagram
Lucent Technologies Inc.
T7295-1 Integrated Line Receiver
Overview (continued)
External Loop Filter Capacitor
Figure shows connection external capacitor LPF1/LPF2 pins. This capacitor part filter. nonpolarized, low-leakage capacitor should used.
CASE dB-15 CABLE LOSS CABLE LOSS
REQB 0.01 T7295-1 LPF2 LPF1
CASE dB-15 EXISTING OFF-CHIP NETWORKS
REQB FIXED EQUALIZER 0.01 T7295-1 LPF2 LPF1
5-2636(C).ar.1
Optional, Receive Path Configuration section.
Figure Receiver Configurations Table Receive Input Signal Amplitude Requirements Maximum input amplitude under conditions REQB LOSTHR VDD/2 VDD/2 Minimum Signal SOJ* Unit
device performance enhanced decreased package parasitics. Although system designers typically power describe input levels, T7295-1 responds peak input signal amplitude. Therefore, T7295-1 input signal limits given
Lucent Technologies Inc.
T7295-1 Integrated Line Receiver
Overview (continued)
Signal Requirements
T7295-1 designed recover pulses that conform ITU-T recommendation G.703. Figure shows pulse mask requirement recommended G.703, Table shows pulse specifications.
(14.55 2.45) 8.65 (14.55 5.90)
NOMINAL PULSE 14.55
12.1 (14.55 2.45)
24.5 (14.55 9.95)
29.1 (14.55 14.55)
5-2638(C)r.5
Figure Isolated Pulse Template Table Pulse Specification Parameter Pulse Shape (nominally rectangular) Test Load Impedance Nominal Peak Voltage Mark (pulse) Peak Voltage Space pulse) Nominal Pulse Width Ratio Amplitudes Positive Negative Pulses Center Pulse Interval Ratio Widths Positive Negative Pulses Nominal Half Amplitude Value marks valid signal must conform with mask (see Figure regardless sign. resistive. 14.55 0.95 1.05. 0.95 1.05.
Lucent Technologies Inc.
T7295-1 Integrated Line Receiver
Table Generated Jitter Jitter Transfer Characteristics Parameter Generated Jitter:* All-1s Pattern Repetitive 1000 Pattern Unit pk-to-pk pk-to-pk
Timing Recovery
Output Jitter
total jitter appearing RCLK output during normal operation consists components. First, some jitter appears RCLK because jitter incoming signal. (The next section discusses jitter transfer characteristic, which describes relationship between input output jitter.) Second, noise sources, both within T7295-1 device those that coupled into device through power supplies, create jitter RCLK. magnitude this internally generated jitter function bandwidth, which, turn, function input density. higher densities, amount generated jitter decreases. Generated jitter also depends quality power supply bypassing networks used. Table lists typical generated jitter performance achievable with suggested bypassing network shown Figure
Jitter Transfer Characteristic: Peaking 0.05 f3dB
Nominal levels with Repetitive 1000 input pattern nominal levels with
Jitter Accommodation
Under allowable operating conditions, jitter accommodation T7295-1 device exceeds system requirements error-free operation (BER 1e-9). typical (VDD nominal signal level) jitter accommodation T7295-1 also shown Figure
Jitter Transfer Characteristic
jitter transfer characteristic indicates fraction input jitter that reaches RCLK output function input jitter frequency. Table shows important jitter transfer characteristic parameters.
10.00
PEAK-TO-PEAK JITTER AMPLITUDE (UI)
ITU-T G.823 MASK 1.50 1.00 PRBS
1000 PATTERN 0.55 0.47 0.42
0.15 0.10
0.01 100k 200k 400k 800k
JITTER FREQUENCY (Hz)
5-2997(C)r.4
Figure Typical Jitter Accommodation T7295-1 Device Lucent Technologies Inc.
T7295-1 Integrated Line Receiver
allow varying levels noise crosstalk different applications, three loss-of-signal threshold settings available using LOSTHR pin. Setting LOSTHR provides lowest loss-of-signal threshold; LOSTHR VDD/2 (can produced using resistors voltage divider between VDDD GNDD) provides intermediate threshold; LOSTHR provides highest threshold. LOSTHR must desired value powerup must changed during operation. Table Analog Loss-of-Signal Thresholds
Timing Recovery (continued)
Acquisition Time
valid input signal already present input, maximum time between application device power error-free operation power already been applied, interval between application valid data error-free operation
False Lock Immunity
False lock defined condition where recovered clock obtains stable phase-lock frequency equal incoming data rate. T7295-1 device uses combination frequency/phase-lock architecture prevent false lock. acquisition circuitry monitors clock frequency relative EXCLK reference frequency. frequency difference between EXCLK clock exceeds approximately ±0.5%, correction circuitry forces reacquisition proper frequency phase.
Data Rate 34.368 Mbits/s
REQB LOSTHR VDD/2 VDD/2
Threshold
Unit
Loss-of-Lock Indication
RLOL alarm activated difference between clock EXCLK frequency exceeds approximately ±0.5%. high RLOL output indicates that acquisition circuit working bring into proper frequency lock. RLOL remains high until frequency lock occurred; however, minimum RLOL pulse width clock cycles.
Notes: RLOS alarm indication presence input signal, error rate indication. Table gives minimum input amplitude needed error-free operation (BER 1e-9). Independent RLOS state, device will attempt recover correct timing data. RLOS low-to-high transition typically occurs below highto-low transition.
Digital Detection addition signal amplitude monitoring analog detector, digital detector monitors recovered data density. RLOS alarm goes high more consecutive occur receive data stream. alarm goes when least eight occur string consecutive bits. This hysteresis minimizes RLOS chattering guarantees minimum RLOS pulse width clock cycles. Note, however, that RLOS chatter still occur. When REQB input signal levels above analog RLOS threshold still enough result high error rate. resultant data stream (containing errors) temporarily activate digital detector, RLOS chatter occur. Therefore, RLOS should used error rate monitor. RLOS chatter also occur when RLOL activated (high). T7295-1EL T7295-1PL devices meet digital detection requirements HDB3 encoding. This corrected version silicon that code marked T7295-1EL2 T7295-1PL2.
Loss-of-Signal Detection
Figure shows that analog digital methods lossof-signal (LOS) detection combined create RLOS alarm output. RLOS either analog digital detection circuitry indicates occurred. Analog Detection analog detector monitors peak input signal amplitude. RLOS makes high-to-low transition (input signal regained) when input signal amplitude exceeds loss-of-signal threshold defined Table RLOS low-to-high transition (input signal lost) occurs level typically below high-to-low transition level. This hysteresis prevents RLOS chattering. Once set, RLOS alarm remains high least clock cycles, allowing system detection lossof-signal condition without external latch.
Lucent Technologies Inc.
T7295-1 Integrated Line Receiver
digital supplies. analog supply VDDA bypassed using (C1) capacitor shield bead that removes significant amounts highfrequency noise generated system device logic. Good-quality, high-frequency (low lead inductance) capacitors should used. Finally, most important that ground connections made low-impedance ground plane.
Timing Recovery (continued)
Loss-of-Signal Detection (continued)
Phase Hits response degree phase input data, T7295-1 returns error-free operation less than During reacquisition time, RLOS temporarily indicated.
Interference Immunity
GNDA VDDA T7295-1 GNDD VDDC SENSITIVE NODE SHIELD BEAD*
T7295-1 complies with interference test detailed G.703 detailed Figure data generators asynchronous.
GNDC
PRBS
VDDD
PRBS
ATTENUATION
CABLE LOSS 12.0 17,184
5-2637(C).ar.1
Recommended shield beads FairRite 2643000101 FairRite 2743019446 (surface mount) equivalent. FairRite registered trademark FairRite Products Corporation.
ERROR DETECTOR
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LUCENT T7295-1
Figure Recommended Power Supply Bypassing Network
Figure Test Setup Interference Immunity
Receive Input
connections receive input must carefully considered. Noise coupling must minimized along path from signal entering board input pin. noise coupled into T7295-1 input directly degrades signal-to-noise ratio input signal degrade sensitivity.
In-Circuit Test Capability
When pulled low, forces digital outputs (RCLK, RPDATA, RNDATA, RLOS, RLOL pins) into high output impedance state. This feature allows incircuit testing done neighboring devices without concern T7295-1 device output damage. When forced high, does affect device operation. internal pull-up device (nominally provided this pin; therefore, users leave this unconnected normal operation. This only which internal pull-up/pull-down provided.
Filter Capacitor
filter capacitor between pins LPF1 LPF2 must placed close chip possible (within recommended). LPF1 LPF2 pins adjacent, allowing short-lead lengths with crossovers external capacitor. Noise coupling into LPF1 LPF2 pins degrade performance.
Board Layout Considerations
Power Supply Bypassing
Figure illustrates recommended power supply bypassing network. (C2) capacitor bypasses Lucent Technologies Inc.
T7295-1 Integrated Line Receiver
Absolute Maximum Ratings
Stresses excess absolute maximum ratings cause permanent damage device. These absolute stress ratings only. Functional operation device implied these other conditions excess those given operational sections data sheet. Exposure absolute maximum ratings extended periods adversely affect device reliability. External leads soldered safely temperatures Parameter Power Supply Power Dissipation, Package Limit Storage Temperature Maximum Voltage (any pin) with Respect Minimum Voltage (any pin) with Respect Maximum Allowable Voltages (RIN) with Respect Symbol Tstg -0.5 -0.5 -0.5 Unit
Handling Precautions
Although protection circuitry been designed into this device, proper precautions should taken avoid exposure electrostatic discharge (ESD) during handling mounting. Lucent Technologies Microelectronics Group employs human-body model (HBM) charged-device model (CDM) ESD-susceptibility testing protection design evaluation. industry-wide standard been adopted CDM. However, standard (resistance 1500 capacitance widely used and, therefore, used comparison purposes. threshold presented here obtained using these circuit parameters: Threshold Device T7295-1 Voltage >1000
Electrical Characteristics
Table Recommended Operating Conditions Parameter Ambient Temperature Power Supply Symbol Unit
Table Electrical Characteristics Typical values random data. Maximum values data. Parameter Power Supply Current: REQB REQB Symbol Unit
Lucent Technologies Inc.
T7295-1 Integrated Line Receiver
Electrical Characteristics (continued)
Table Logic Interface Characteristics Parameter Input Voltage: High Input Leakage Symbol Test Conditions -0.5 (all input pins except GNDD -5.0 GNDD 0.7VDDD GNDD VDDD VDDD VDDD Unit
Output Voltage High Input Capacitance Load Capacitance
Timing Characteristics
Recovered Clock Data Timing
Table Figure summarize timing relationships between high-speed logic signals RCLK, RPDATA, RNDATA. RPDATA RNDATA change rising edge RCLK valid during falling edge RCLK. positive pulse creates high level RPDATA level RNDATA. negative pulse creates high level RNDATA level RPDATA, received zero produces levels both RPDATA RNDATA. Table System Interface Timing Characteristics timing characteristics measured with loading. Symbol tRCH1RCH2 tRCL2RCL1 tRDVRCL tRCLRDX tRCHRDV Parameter Receive Clock Rise Time (10% 90%) Receive Clock Fall Time (90% 10%) Receive Data Setup Time Receive Data Hold Time Receive Propagation Delay Receive Clock Duty Cycle Unit
tRCHRDV RCLK (RC) tRDVRCL RPDATA RNDATA (RD)
tRCL2RCL1
tRCH1RCH2
tRCLRDX
5-1249(C)r.5
Figure Timing Diagram System Interface Lucent Technologies Inc.
T7295-1 Integrated Line Receiver
Outline Diagrams
20-Pin, Plastic
Dimensions millimeters.
IDENTIFIER ZONE
SEATING PLANE 0.10 1.27 0.020 0.64
5-4413(C).r1
Number Pins
Package Dimensions (SOJ) Maximum Length 12.95 Maximum Width Without Leads 7.62 Maximum Width Including Leads 8.81 Maximum Height Above Board 3.18
Lucent Technologies Inc.
T7295-1 Integrated Line Receiver
Outline Diagrams (continued)
20-Pin, Plastic
Dimensions millimeters.
IDENTIFIER ZONE
SEATING PLANE 0.38 2.54 0.023
5-4410(C)r.1
Number Pins
Package Dimensions (DIP) Maximum Length 26.42 Maximum Width Without Leads 6.48 Maximum Width Including Leads 7.87 Maximum Height Above Board 5.08
Ordering Information
Device Code 7295 1EL2 7295 1PL2 Package 20-Pin, Plastic 20-Pin, Plastic Temperature Comcode (Ordering Number) 107114464 107202186
Lucent Technologies Inc.
T7295-1 Integrated Line Receiver (MBA) Interactive Terminal Interface
Advance
additional information, contact your Microelectronics Group Account Manager following: INTERNET: http://www.lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 data requests Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 299, (44) 1734 technical inquiries Europe: CENTRAL EUROPE: (49) 95086 (Munich), NORTHERN EUROPE: (44) 1344 (Bracknell UK), FRANCE: (33) (Paris), SOUTHERN EUROPE: (39) 6601 1800 (Milan) (34) 1700 (Madrid)
Lucent Technologies Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. rights under patent accompany sale such product(s) information.
Copyright 1997 Lucent Technologies Inc. Rights Reserved Printed U.S.A.
February 1997 DS97-037TIC (Replaces DS92-152TIC)
Printed Recycled Paper
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