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MSC8101/D Rev. 7/2003 Networking Digital Signal Processor
(mask sets 2K42A 1K87M)
UART HDLC Transparent Ethernet Fast Ethernet UTOPIA Interface Interrupt Controller Timers Parallel Baud Rate Generators Dual Ported SDMA RISC
64-bit System MEMC System Protection Reset Control Clock Control SIC_EXT Interrupts Bridge 64/32-bit System
Serial Interface
Engine
TDMs
Motorola MSC8101 16-bit Digital Signal Processor (DSP) first member family DSPs based StarCore SC140 core. MSC8101 offered three core speed levels: 250, 275, MHz.
Other Peripherals Extended Core Program Sequencer SC140 Core JTAG Address Register File Address EOnCEClock/PLL Data Register File Data Q2PPC Bridge
64-bit Local
MEMC
128-bit QBus
Interrupts EFCOP 8/16-bit Host Interface
Boot HDI16 SRAM Interface
Power Management
128-bit P-Bus 64-bit Data 64-bit Data
Figure MSC8101 Block Diagram
What's New?
Rev. includes following changes: Table 2A-16 Table 2B-16 note Table 2A-18 Table 2B-18. Timing Table 2A-21 Table 2B-21. Table 2B-2 MHz. Table 2B-15 timings 15a, 15b. Table several FCC1 signal designations
Motorola MSC8101 very versatile device that integrates high-performance SC140 four-ALU (Arithmetic Logic Unit) core along with on-chip memory, Communications Processor Module (CPM), 64-bit bus, very flexible System Integration Unit (SIU), 16-channel engine single device. With four-ALU core, MSC8101 execute four multiply-accumulate (MAC) operations single clock cycle. MSC8101 32-bit RISC-based communications protocol engine that network Time-Division Multiplexed (TDM) highways, Ethernet,
Asynchronous Transfer mode (ATM) backbones. MSC8101 60x-compatible interface facilitates connection multi-master system architectures. very large on-chip memory, reduces need off-chip program data memories. MSC8101 offers 1500 MMACS (1200 core EFCOP) performance using internal clock with core independent input/output (I/O). Figure shows block diagram MSC8101 processor.
Note: This document contains information product. Specifications information herein subject change without notice.
Table Contents
MSC8101 Features Target Applications Product Documentation
Chapter
Signal/ Connection Descriptions
Signal Groupings Power Signals Clock Signals Reset, Configuration, EOnCE Event Signals. System Bus, HDI16, Interrupt Signals. Memory Controller Signals 1-16 Communications Processor Module (CPM) Ports. 1-18 JTAG Test Access Port Signals. 1-44 Reserved Signals. 1-45 Introduction. 2A-1 Absolute Maximum Ratings 2A-1 Recommended Operating Conditions. 2A-2 Thermal Characteristics 2A-2 Electrical Characteristics. 2A-3 Clock Configuration 2A-4 Timings. 2A-6 Introduction.2B-1 Absolute Maximum Ratings .2B-1 Recommended Operating Conditions.2B-2 Thermal Characteristics .2B-3 Electrical Characteristics.2B-3 Clock Configuration .2B-4 Timings.2B-8 Pin-Out Package Information. FC-PBGA Package Description. Lidded FC-PBGA Package Mechanical Drawings. 3-32 Thermal Design Considerations. Electrical Design Considerations. Power Considerations Layout Practices.
Chapter
Specifications (mask 2K42A)
2A.1 2A.2 2A.3 2A.4 2A.5 2A.6 2A.7
Chapter
Specifications (mask 1K87M)
2B.1 2B.2 2B.3 2B.4 2B.5 2B.6 2B.7
Chapter
Packaging
Chapter
Design Considerations
Index Ordering Contact Information Back Cover
Data Sheet Conventions
pin-out OVERBAR "asserted" "deasserted" Examples: Although device package does have pins, term pins pin-out used convenience indicate specific signal locations within ball-grid array. Used indicate signal that active when pulled (For example, RESET active when low.) Means that high true (active high) signal high that true (active low) signal Means that high true (active high) signal that true (active low) signal high Signal/Symbol Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Note: Values VOL, defined individual product specifications.
MSC8101 Features
SC140 Core Architecture optimized efficient C/C++ code compilation Four 16-bit ALUs 32-bit AGUs 1200 MMACS running Very power dissipation-less than 0.25 core running full speed Variable-Length Execution (VLES) execution model JTAG/Enhanced OnCE debug port Communications Processor Module (CPM) Programmable protocol machine using 32-bit RISC engine Mbps Ainterface (including 0/1/2/5) 10/100 Mbit Ethernet interface four E1/T1 interfaces E3/T3 interface E1/T1 interface HDLC support rates, channels 32-bit Wide Interface Support bursts high efficiency Glueless interface 60x-compatible systems Multi-master support Enhanced Filter Coprocessor (EFCOP) Independently concurrently executes long filters (such echo cancellation) Runs 250/275/300 provides 250/275/300 MMACS performance Programmable Memory Controller Control eight banks external memory User-programmable machines (UPM) allowing glueless interface various memory types (SRAM, DRAM, EPROM, Flash memory) other user-definable peripherals Dedicated pipelined SDRAM memory interface Large On-Chip SRAM 256K 16-bit words (512 Unified program data space configurable application Word byte addressable Controller channels, FIFO based, with burst capabilities Sophisticated addressing capabilities Small Foot Print Package lidded FC-PBGA package Very Power Consumption Separate power supply internal logic (1.6 (3.3 Enhanced 16-bit Parallel Host Interface (HDI16) Supports variety microcontroller, microprocessor, interfaces Phase-Lock Loops (PLLs) System DPLLs (SCC SCM) Process Technology Uses 0.13 micron copper interconnect process technology
Target Applications
MSC8101 targets applications requiring very high performance, very large amounts on-chip memory, such networking capabilities Third-generation wideband wireless infrastructure systems Packet Telephony systems Multi-channel modem banks Multi-channel xDSL
Product Documentation
documents listed Table required complete description MSC8101 necessary design properly with part. Documentation available from following sources (see back cover detailed information): local Motorola distributor Motorola semiconductor sales office Motorola Literature Distribution Center World Wide (WWW) Table MSC8101 Documentation
Name
MSC8101 Technical Data MSC8101 User's Guide MSC8101 Pocket Guide MSC8101 Reference Manual SC140 Core Reference Manual Application Notes
Description
MSC8101 features list physical, electrical, timing, package specifications Detailed functional description MSC8101 memory configuration, operation, register programming Quick reference information application development. Detailed description MSC8101 processor core instruction Detailed description SC140 family processor core instruction Documents describing specific applications optimized device operation including code examples
Order Number
MSC8101/D MSC8101UG/D MSC8101PG/D MSC8101RM/D MNSC140CORE/D MSC8101 product website
Chapter
Signal/ Connection Descriptions
Signal Groupings
MSC8101 external signals organized into functional groups, shown Table 1-1, Figure 1-1, Figure 1-2. Table lists functional groups, number signal connections each group, references table that gives detailed listing multiplexed signals within each group. Figure shows MSC8101 external signals organized function. Figure indicates parallel input/output (I/O) ports signals multiplexed. Because parallel design supported MSC8101 Communications Processor Module (CPM) subset parallel signals supported MPC8260 device, port pins numbered sequentially. Table 1-1. MSC8101 Functional Signal Groupings
Number Signal Connections
Port Port Port Port JTAG Test Access Port Reserved (denotes connections that always reserved)
Functional Group
Detailed Description
Power (VCC, VDD, GND) Clock Reset, Configuration, EOnCE System Bus, HDI16, Interrupts Memory Controller Communications Processor Module (CPM) Input/Output Parallel Ports
Table page Table page Table page Table page Table page 1-16 Table page 1-19 Table page 1-26 Table page 1-31 Table page 1-41 Table page 1-44 Table page 1-45
Signal Groupings
VDDH VCCSYN VCCSYN1 GNDSYN GNDSYN1
Port PA[31-6] signals multiplexed Ports A-D, Figure Port PB[31-18] Port PC[31-22, 15-12, 7-4] Port PD[31-29, 19-16,
A[0-31] TT[0-4] TSIZ[0-3] TBST IRQ1 Reserved AACK ARTRY D[0-31]
BADDR[29-31]
IRQ[2-3,
IRQ2
IRQ3 HDI16 Signals HD[0-15] HA[0-3] HCS1 Single Double HRD/HRD HDS/HDS HWR/HWR Single Double HREQ/HREQ HTRQ/HTRQ HACK/HACK HRRQ/HRRQ HDSP HDDS H8BIT HCS2 Reserved Reserved IRQ1 Reserved Reserved DREQ3 DREQ4 DACK3 DACK4 EXT_Br2 EXT_BG2 EXT_DBG2 EXT_BR3 EXT_BG3 EXT_DBG3 IRQ6 IRQ7
D[32-47] D[48-51] D[61-63]
TRST
Reserved IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 NMI_OUT PSDVAL IRQ7 CS[0-7] BCTL1 BADDR[27-28] BCTL0 PWE[0-7] PSDA10 PSDWE PSDCAS PGTA PSDAMUX
EOnCE Event EE[2-3] EE[4-5]
RESET Configuration DBREQ BTM[0-1] PORESET RSTCONF HRESET SRESET
INT_OUT
BNKSEL[0-2]
TC[0-2]
CLKIN MODCK[1-3] CLKOUT DLLIN
PSDDQM[0-7]
PSDRAS PUPMWAIT PPBS
TEST THERM[1-2] SPARE1, SPARE5
PBS[0-7] PGPL0 PGPL1 PGPL2 PGPL3 PGPL4 PGPL5
Note:
Refer System Interface Unit (SIU) chapter MCS8101 Reference Manual details configure these pins.
Figure 1-1. MSC8101 External Signals
Signal Groupings
FCC1 ATM/UTOPIA MPHY MPHY Master Master poll dir. poll Slave TXENB TXCLAV TXCLAV0 TXSOC (master) RXENB RXSOC (slave) RXCLAV RXCLAV0 TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 FCC1 HDLC/ Ethernet transp. Serial TX_ER TX_EN RX_DV RX_ER SDMA MSNUM0 MSNUM1
HDLC Nibble GPIO PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 BRGs Clocks Timers PB18 BRG1O CLK1 TGATE1 PC31 BRG2O CLK2 TOUT1 PC30 BRG3O CTS/CLSN Timer Input BRG4O CLK5 TMCLK DACK2 Ext. Req. EXT2 SCC1 LIST1 SMTXD CTS/CLSN CD/RENA LIST2 LIST4 LIST3 LIST1 LIST2 SMC1 SMTXD SMRXD RTS/TENA LIST3 LIST4 DRACK1/DONE1 DRACK2/DONE2 BRG1O SPISEL SPICLK SPIMOSI BRG2O SPIMISO SMSYN DREQ2 DACK1 DREQ1 BRG5O BRG6O BRG7O BRG8O CLK3 TIN2 PC29
TXD3 TXD2 TXD1 TXD0 RXD0 RXD1 RXD2 RXD3
TXD3 TXD2 TXD1 TXD0 RXD0 RXD1 RXD2 RXD3 TDMA1 Serial Nibble L1TXD L1TXD0 L1RXD L1RXD0 L1TSYNC L1RSYNC TDMB2 L1TXD L1RXD L1RSYNC L1TSYNC TDMC2 L1TXD L1RXD L1TSYNC L1RSYNC TDMD2 L1TXD L1RXD L1TSYNC L1RSYNC MSNUM2 MSNUM3 MSNUM4 MSNUM5
FCC2 HDLC/ HDLC Ethernet transp. Serial Nibble TX_ER RX_DV TX_EN RX_ER TXD3 TXD2 TXD1 TXD0 RXD0 RXD1 RXD2 RXD3 TXD3 TXD2 TXD1 TXD0 RXD0 RXD1 RXD2 RXD3 Ext. Req. EXT1 SCC1 CTS/CLSN
SMC2 SMTXD SMRXD SMSYN SCC2 RTS/TENA
L1TXD3 L1RXD3 L1RXD2 L1RXD1 L1TXD2 L1TXD1
TIN1/ CLK4 PC28 TOUT2 CLK5 TGATE2 PC27 CLK6 TOUT3 PC26 CLK7 CLK8 CLK9 CLK10 TIN4 TIN3/ TOUT4 PC25 PC24 PC23 PC22 PC15 PC14 PC13 PC12 PD31 PD30 PD29 PD19 PD18 PD17 PD16
TXADDR0 RXADDR0 TXADDR1 RXADDR1 TXADDR2/ TXADDR2 TXCLAV1 RXADDR2/ RXADDR2 RXCLAV1
CTS/CLSN CD/RENA FCC1 FCC2
RXADDR3 RXCLAV2 TXADDR4 TXCLAV3 RXADDR4 RXCLAV3 RXPRTY TXPRTY TXADDR3 TXCLAV2
Figure 1-2. Port Multiplexed Functionality
Power Signals
Power Signals
Table 1-1. Power Ground Signal Inputs
Power Name
Description
Internal Logic Power dedicated with device core. voltage should well-regulated input should provided with extremely impedance path power rail. Input/Output Power This source supplies power buffers. user must provide adequate external decoupling capacitors. System Power dedicated with system Phase Lock Loop (PLL). voltage should well-regulated input should provided with extremely impedance path power rail. SC140 Power dedicated with SC140 core PLL. voltage should well-regulated input should provided with extremely impedance path power rail. System Ground isolated ground internal processing logic. This connection must tied externally chip ground connections, except GNDSYN GNDSYN1. user must provide adequate external decoupling capacitors. System Ground Ground dedicated system use. connection should provided with extremely low-impedance path ground. SC140 Ground Ground dedicated SC140 core use. connection should provided with extremely low-impedance path ground.
VDDH
VCCSYN
VCCSYN1
GNDSYN
GNDSYN1
Clock Signals
Clock Signals
Table 1-2. Clock Signals
Signal Name
CLKIN MODCK1
Type
Input Input
Signal Description
Clock Primary clock input MSC8101 PLL. Clock Mode Input Defines operating mode internal clock circuits. Transfer Code Supplies information that useful debugging transactions initiated MSC8101. Bank Select Selects SDRAM bank when MSC8101 60x-compatible mode. Clock Mode Input Defines operating mode internal clock circuits. Transfer Code Supplies information that useful debugging transactions initiated MSC8101. Bank Select Selects SDRAM bank when MSC8101 60x-compatible mode. Clock Mode Input Defines operating mode internal clock circuits. Transfer Code Supplies information that useful debugging transactions initiated MSC8101. Bank Select Selects SDRAM bank when MSC8101 60x-compatible mode. Clock system clock. DLLIN Synchronizes with external device.
Output
BNKSEL0 MODCK2
Output Input
Output
BNKSEL1 MODCK3
Output Input
Output
BNKSEL2 CLKOUT DLLIN
Output Output Input
Reset, Configuration, EOnCE Event Signals
Reset, Configuration, EOnCE Event Signals
Table 1-3. Reset, Configuration, EOnCE Event Signals
Signal Name
DBREQ
Type
Input
Signal Description
Debug Request Determines whether into SC140 Debug mode when PORESET deasserted. Enhanced OnCE (EOnCE) Event After PORESET deasserted, configure input (default) output.
EE01
Input
Debug request, enable Address Event Detection Channel generate EOnCE events. Detection Address Event Detection Channel Used trigger external debugging equipment. Host Port Enable When this asserted during PORESET, Host port enabled, system data bits wide, Host must program reset configuration word. EOnCE Event After PORESET deasserted, configure input (default) output.
Output
Input
EE11
Input Output
Enable Address Event Detection Channel generate EOnCE events. Debug Acknowledge detection Address Event Detection Channel Used trigger external debugging equipment. EOnCE Event After PORESET deasserted, configure input (default) output.
EE21
Input
Enable Address Event Detection Channel generate EOnCE events enable Event Counter. Detection Address Event Detection Channel Used trigger external debugging equipment. EOnCE Event After PORESET deasserted, configure input (default) output. Emulation Debug chapter SC140 Core Reference Manual details ERCV Register.
Output
EE31
Input Output
Enable Address Event Detection Channel generate EOnCE events. EOnCE Receive Register (ERCV) read DSP. Used trigger external debugging equipment.
Reset, Configuration, EOnCE Event Signals
Table 1-3. Reset, Configuration, EOnCE Event Signals (Continued)
Signal Name
BTM[0-1]
Type
Input
Signal Description
Boot Mode Determines MSC8101 boot mode when PORESET deasserted. Emulation Debug chapter SC140 Core Reference Manual details these pins. EOnCE Event After PORESET deasserted, configure input (default) output. Emulation Debug chapter SC140 Core Reference Manual details ETRSMT Register.
EE41
Input Output
Enable Address Event Detection Channel generate EOnCE events EOnCE Transmit Register (ETRSMT) written DSP. Used trigger external debugging equipment. EOnCE Event After PORESET deasserted, configure input (default) output.
EE51
Input Output
Enable Address Event Detection Channel Detection Address Event Detection Channel Used trigger external debugging equipment. Enhanced OnCE (EOnCE) Event Detection After PORESET deasserted, configure input (default) output:
EED1
Input Output
Enable Data Event Detection Channel. Detection Data Event Detection Channel. Used trigger external debugging equipment. Power-On Reset When asserted, this line causes MSC8101 enter power-on reset state. Reset Configuration Used during reset configuration sequence chip. detailed explanation function provided "Power-On Reset Flow" "Hardware Reset Configuration" sections MSC8101 Reference Manual. Hard Reset When asserted, this open-drain line causes MSC8101 enter hard reset state. Soft Reset When asserted, this open-drain line causes MSC8101 enter soft reset state.
PORESET
Input
RSTCONF
Input
HRESET
Input
SRESET
Input
Note:
Emulation Debug chapter SC140 Core Reference Manual details configure these pins.
System Bus, HDI16, Interrupt Signals
System Bus, HDI16, Interrupt Signals
system bus, HDI16, interrupt signals grouped together because they common signal lines. Individual assignment signal specific signal line configured through registers System Interface Unit (SIU) Host Interface (HDI16). Table describes signals this group. Note: boot from host interface, HDI16 must enabled pulling signal line during PORESET. signal pulled configuration word must then loaded from host. configuration word must Internal Space Port Size Control Register (BCR[ISPS]) change system data width from bits bits reassign upper bits their HDI16 functions. Never Host Port Enable (HEN) Host Port Control Register (HPCR) enable HDI16, unless size first changed from bits bits setting BCR[ISPS] bit. Otherwise, unpredictable operation occur.
Although there eight interrupt request (IRQ) connections core processor, there multiple external lines that connect these internal signal lines. After reset, default configuration includes IRQ1 IRQ7 input lines. designer must select line each required interrupt reconfigure other external signal line lines alternate functions. Table 1-4.
Signal
A[0-31]
System Bus, HDI16, Interrupt Signals
Description
Data Flow
Input/Output
Address When MSC8101 external master mode, these pins function address bus. MSC8101 drives address internal masters responds addresses generated external masters. When MSC8101 Internal Master mode, these pins used address lines connected memory devices controlled MSC8101 memory controller. Transfer Type master drives these pins during address tenure specify type transaction. Transfer Size master drives these pins with value indicating number bytes transferred current transaction. Transfer Burst master asserts this indicate that current transaction burst transaction (transfers four quad words). Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. Global1 When master within chip initiates transaction, drives this pin. When external master initiates transaction, should drive this pin. Assertion this indicates that transfer global should snooped caches system.
TT[0-4]
Input/Output
TSIZ[0-3]
Input/Output
TBST
Input/Output
IRQ1
Input
Input/Output
System Bus, HDI16, Interrupt Signals
Table 1-4.
Signal
Reserved BADDR29
System Bus, HDI16, Interrupt Signals (Continued)
Description
primary configuration reserved. Burst Address five outputs memory controller. These pins connect directly memory devices controlled MSC8101 memory controller. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. primary configuration reserved. Burst Address five outputs memory controller. These pins connect directly memory devices controlled MSC8101 memory controller. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. primary configuration reserved. Burst Address five outputs memory controller. These pins connect directly memory devices controlled MSC8101 memory controller. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. Request output when external arbiter used. MSC8101 asserts this request ownership bus. input when internal arbiter used. external master should assert this request ownership from internal arbiter. Grant2 output when internal arbiter used. MSC8101 asserts this grant ownership external master. input when external arbiter used. external arbiter should assert this grant ownership MSC8101. Address Busy1 MSC8101 asserts this duration address tenure. Following address acknowledge (AACK) signal, which terminates address tenure, MSC8101 deasserts fraction cycle then stops driving this pin. MSC8101 does assume ownership long senses that this asserted external master. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core.
Data Flow
Output Output
IRQ2
Input
Reserved BADDR30
Output Output
IRQ3
Input
Reserved BADDR31
Output Output
IRQ5
Input
Input/Output Output
Input Input/Output Output
Input Input/Output Output
Input
IRQ2
Input
System Bus, HDI16, Interrupt Signals
Table 1-4.
Signal
System Bus, HDI16, Interrupt Signals (Continued)
Description
Transfer Start Signals beginning address tenure. MSC8101 asserts this signal when internal masters (SC140 core DMA) begins address tenure. When MSC8101 senses this being asserted external master, responds address tenure required (snoop enabled, access internal MSC8101 resources, memory controller support). Address Acknowledge slave asserts this signal indicate that identified address tenure. Assertion this signal terminates address tenure. Address Retry Assertion this signal indicates that transaction should retried master. MSC8101 asserts this signal enforce data coherency with internal cache prevent deadlock situations. Data Grant2 output when internal arbiter used. MSC8101 asserts this output grant data ownership external master. input when external arbiter used. external arbiter should assert this input grant data ownership MSC8101. Data Busy1 MSC8101 asserts this output duration data tenure. Following which terminates data tenure, MSC8101 deasserts fraction cycle then stops driving this pin. MSC8101 does assume data ownership long senses asserted external master. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. Data Most Significant Word write transactions master drives valid data this bus. read transactions slave drives valid data this bus. Host Port Disabled mode, these bits part 64-bit data bus. Host Port Enabled mode, these bits used 32-bit mode. Data Bits 32-47 write transactions master drives valid data this bus. read transactions slave drives valid data this bus. Host Data2 When HDI16 interface enabled, these signals lines 0-15 bidirectional tri-state data bus. Data Bits 48-51 write transactions master drives valid data these pins. read transactions slave drives valid data these pins. Host Address Line 0-33 When HDI16 interface enabled, these lines address internal host registers.
Data Flow
Input/Output
AACK
Input/Output
ARTRY
Input
Input/Output Output
Input Input/Output Output
Input
IRQ3
Input
D[0-31]
Input/Output
D[32-47]
Input/Output
HD[0-15]
Input/Output
D[48-51]
Input/Output
HA[0-3]
Input
1-10
System Bus, HDI16, Interrupt Signals
Table 1-4.
Signal
System Bus, HDI16, Interrupt Signals (Continued)
Description
Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Host Chip Select When HDI16 interface enabled, this chip-select pins. HDI16 chip select logical HCS1 HCS2. Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Host Read Write Select When HDI16 interface enabled Single Strobe mode, this read/write input (HRW). Host Read Strobe3 When HDI16 programmed interface with double data strobe host bus, this read data strobe Schmitt trigger input (HRD/HRD). polarity data strobe programmable. Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Host Data Strobe3 When HDI16 programmed interface with single data strobe host bus, this data strobe Schmitt trigger input (HDS/HDS). polarity data strobe programmable. Host Write Data Strobe3 When HDI16 programmed interface with double data strobe host bus, this write data strobe Schmitt trigger input (HWR/HWR). polarity data strobe programmable. Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Host Request When HDI16 programmed interface with single host request host bus, this host request output (HREQ/HREQ). polarity host request programmable. host request programmed driven open-drain output. Transmit Host Request When HDI16 programmed interface with double host request host bus, this transmit host request output (HTRQ/HTRQ). signal programmed driven open drain. polarity host request programmable.
Data Flow
Input/Output
HCS1
Input
Input/Output
Input
HRD/HRD
Input
Input/Output
HDS/HDS
Input
HWR/HWR
Input
Input/Output
HREQ/HREQ
Output
HTRQ/HTRQ
Output
1-11
System Bus, HDI16, Interrupt Signals
Table 1-4.
Signal
System Bus, HDI16, Interrupt Signals (Continued)
Description
Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Host Acknowledge3 When HDI16 programmed interface with single host request host bus, this host acknowledge Schmitt trigger input (HACK). polarity host acknowledge programmable. Receive Host Request3 When HDI16 programmed interface with double host request host bus, this receive host request output (HRRQ/HRRQ). signal programmed driven open drain. polarity host request programmable. Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Host Data Strobe Polarity3 When HDI16 interface enabled, this host data strobe polarity (HDSP). Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Host Dual Data Strobe3 When HDI16 interface enabled, this host dual data strobe (HDDS). Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. H8BIT3 When HDI16 interface enabled, this determines interface 8-bit 16-bit mode. Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Host Chip Select When HDI16 interface enabled, this chip-select pins. HDI16 chip select logical HCS1 HCS2. Data Bits 61-63 Used only 60x-mode-only mode. write transactions master drives valid data this bus. read transactions slave drives valid data this bus. These dedicated signals reserved when HDI16 enabled.3
Data Flow
Input/Output
HACK/HACK
Output
HRRQ/HRRQ
Output
Input/Output
HDSP
Input
Input/Output
HDDS
Input Input/Output
H8BIT
Input
Input/Output
HCS2
Input
D[61-63]
Input/Output
Reserved
1-12
System Bus, HDI16, Interrupt Signals
Table 1-4.
Signal
Reserved
System Bus, HDI16, Interrupt Signals (Continued)
Description
primary configuration reserved. Data Parity agent that drives data also drives data parity signals. value driven data parity zero should give parity (odd number ones) group signals that includes data parity D[0-7]. External Request 21,2 external master asserts this request ownership from internal arbiter. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. Data Parity agent that drives data also drives data parity signals. value driven data parity should give parity (odd number ones) group signals that includes data parity D[8-15]. External Grant 21,2 MSC8101 asserts this grant ownership external master. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. Data Parity agent that drives data also drives data parity signals. value driven data parity should give parity (odd number ones) group signals that includes data parity D[16-23]. External Data Grant 21,2 MSC8101 asserts this grant data ownership external master. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. Data Parity agent that drives data also drives data parity signals. value driven data parity three should give parity (odd number ones) group signals that includes data parity D[24-31]. External Request 31,2 external master asserts this request ownership from internal arbiter.
Data Flow
Input Input/Output
EXT_BR2
Input
IRQ1
Input
Input/Output
EXT_BG2 IRQ2
Output Input
Input/Output
EXT_DBG2
Output
IRQ3
Input
Input/Output
EXT_BR3
Input
1-13
System Bus, HDI16, Interrupt Signals
Table 1-4.
Signal
IRQ4
System Bus, HDI16, Interrupt Signals (Continued)
Description
Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. Data Parity agent that drives data also drives data parity signals. value driven data parity four should give parity (odd number ones) group signals that includes data parity D[32-39]. Request external peripheral uses this request service. External Grant 31,2 MSC8101 asserts this grant ownership external master. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. Data Parity agent that drives data also drives data parity signals. value driven data parity five should give parity (odd number ones) group signals that includes data parity D[40-47]. Request external peripheral uses this request service. External Data Grant 31,2 MSC8101 asserts this grant data ownership external master. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. Data Parity agent that drives data also drives data parity signals. value driven data parity should give parity (odd number ones) group signals that includes data parity D[48-55]. Acknowledge drives this output acknowledge transaction bus. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. Data Parity master slave that drives data also drives data parity signals. value driven data parity seven should give parity (odd number ones) group signals that includes data parity D[56-63]. Acknowledge1 drives this output acknowledge transaction bus. Transfer Acknowledge Indicates that data beat valid data bus. single beat transfers, assertion indicates termination transfer. burst transfers, asserted four times indicate transfer four data beats with last assertion indicating termination burst transfer.
Data Flow
Input
Input/Output
DREQ3
Input
EXT_BG3 IRQ5
Output Input
Input/Output
DREQ4
Input
EXT_DBG3
Output
IRQ6
Input
Input/Output
DACK3 IRQ7
Output Input
Input/Output
DACK4
Output Input/Output
1-14
System Bus, HDI16, Interrupt Signals
Table 1-4.
Signal
System Bus, HDI16, Interrupt Signals (Continued)
Description
Transfer Error Acknowledge Indicates error. masters within MSC8101 monitor state this pin. MSC8101 internal monitor assert this identifies transfer that hung. Non-Maskable Interrupt When external device asserts this line, MSC8101 input asserted. Non-Maskable Interrupt Driven from MSC8101 internal interrupt controller. Assertion this output indicates that non-maskable interrupt, pending MSC8101 internal interrupt controller, waiting handled external host. Data Valid Indicates that data beat valid data bus. difference between PSDVAL that asserted indicate data transfer terminations while PSDVAL signal asserted with each data beat movement. Thus, when asserted, PSDVAL asserted, when PSDVAL asserted, necessarily asserted. example when SDMA initiates double word (2x64 bits) transfer memory device that 32-bit port size, PSDVAL asserted three times without finally both pins asserted terminate transfer. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. Interrupt Output1 Driven from MSC8101 internal interrupt controller. Assertion this output indicates that unmasked interrupt pending MSC8101 internal interrupt controller.
Data Flow
Input/Output
NMI_OUT
Input Output
PSDVAL
Input/Output
IRQ7
Input
INT_OUT
Output
Notes:
System Interface Unit (SIU) chapter MCS8101 Reference Manual details configure these pins. When used control arbiter system bus, MSC8101 support three external masters. Each master uses Request, Grant, Data Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, EXT_BR3/EXT_BG3/EXT_DBG3). Each these signal sets must configured indicate whether external master MSC8101 master device. Configuration Register (BCR) description System Interface Unit (SIU) chapter MCS8101 Reference Manual details configure these pins. second third pins defined EXT_xxx indicate that they only used with external master devices. first pins (BR/BG/DBG) have dual function. When MSC8101 arbiter, these signals (BR/BG/DBG) used MSC8101 obtain master control bus. Host Interface (HDI16) chapter MCS8101 Reference Manual details configure these pins.
1-15
Memory Controller Signals
Memory Controller Signals
Refer Memory Controller chapter MSC8101 Reference Manual (MSC8101RM/D) detailed information about configuring these signals. Table 1-2. Memory Controller Signals
Signal
CS[0-7] BCTL1
Data Flow
Output Output
Description
Chip Select Enable specific memory devices peripherals connected MSC8101 buses. Buffer Control Controls buffers data bus. Usually used with BCTL0. exact function this defined value SIUMCR[BCTLC]. System Interface Unit (SIU) chapter MS8101 Technical Reference manual details. Burst Address 27-28 five outputs memory controller. These pins connect directly memory devices controlled MSC8101 memory controller. Address Latch Enable Controls external address latch used external master configuration. Buffer Control Controls buffers data bus. exact function this defined value SIUMCR[BCTLC]. System Interface Unit (SIU) chapter MS8101 Technical Reference manual details. Write Enable Outputs General-Purpose Chip-select Machine (GPCM). These pins select byte lanes write operations. SDRAM Outputs SDRAM control machine. These pins select specific byte lanes SDRAM devices. Byte Select Outputs User-Programmable Machine (UPM) memory controller. These pins select specific byte lanes during memory operations. timing these pins programmed UPM. actual driven value depends address size transaction port size accessed device. SDRAM Output from SDRAM controller. This part address when address driven. part command when column address driven. General-Purpose Line general-purpose output lines UPM. values timing this programmed UPM. SDRAM Write Enable Output from SDRAM controller. This should connect SDRAM input signal. General-Purpose Line general-purpose output lines from UPM. values timing this programmed UPM.
BADDR[27-28]
Output
BCTL0
Output Output
PWE[0-7]
Output
PSDDQM[0-7]
Output
PBS[0-7]
Output
PSDA10
Output
PGPL0
Output
PSDWE
Output
PGPL1
Output
1-16
Memory Controller Signals
Table 1-2. Memory Controller Signals (Continued)
Signal
Data Flow
Output
Description
Output Enable Output GPCM. Controls output buffer memory devices during read operations. SDRAM Output from SDRAM controller. This should connect SDRAM Address Strobe (RAS) input signal. General-Purpose Line general-purpose output lines from UPM. values timing this programmed UPM. SDRAM Output from SDRAM controller. This should connect SDRAM Column Address Strobe (CAS) input signal. General-Purpose Line general-purpose output lines from UPM. values timing this programmed UPM. GPCM Terminates transactions during GPCM operation. Requires external pull resistor proper operation. Wait Input UPM. external device hold this high force wait until device ready operation continue. Parity Byte Select systems which data parity stored separate chip, this output byte-select that chip. General-Purpose Line general-purpose output lines from UPM. values timing this programmed UPM. SDRAM Address Multiplexer Controls SDRAM address multiplexer when MSC8101 External Master mode. General-Purpose Line general-purpose output lines from UPM. values timing this programmed UPM.
PSDRAS
Output
PGPL2
Output
PSDCAS
Output
PGPL3
Output
PGTA
Input
PUPMWAIT
Input
PPBS
Output
PGPL4
Output
PSDAMUX
Output
PGPL5
Output
1-17
Communications Processor Module (CPM) Ports
Communications Processor Module (CPM) Ports
MSC8101 supports subset signals included MPC8260. following sections describe functionality signals MSC8101. MSC8101 includes following communication controllers: full-duplex Fast Serial Communications Controllers (FCCs) that support: Asynchronous Transfer Mode (ATM) through UTOPIA interface (FCC1 only)-The MSC8101 operate following: UTOPIA slave device UTOPIA multi-PHY master device using direct polling devices UTOPIA multi-PHY master device using multiplex polling that address devices addresses 0-30 (address reserved null port). IEEE 802.3/Fast Ethernet through Media-Independent Interface (MII) High-Level Data Link Control (HDLC) Protocol: Serial mode-Transfers data time Nibble mode-Transfers data four bits time Transparent mode serial operation that operates with only Multi-Channel Controllers (MCCs) that together handle HDLC/transparent channels Kbps each, multiplexed four interfaces full-duplex serial communications controllers (SCCs) that support following protocols: IEEE 802.3/Fast Ethernet through Media-Independent Interface (MII) HDLC Protocol: Serial mode-Transfers data time Nibble mode-Transfers data four bits time Synchronous Data Link Control (SDLC) LocalTalk (HDLC-based local area network protocol) Universal Asynchronous Receiver/Transmitter (UART) Synchronous UART clock mode) Binary Synchronous (BISYNC) communication Transparent mode serial operation additional SCCs that operate with only full-duplex Serial Management Controllers (SMCs) that support following protocols: General Circuit Interface (GCI)/Integrated Services Digital Network (ISDN) monitor channels (TSA only) UART Transparent mode serial operation Serial Peripheral Interface (SPI) support master slave operation Inter-Integrated Circuit (I2C) controller Time-Slot Assigner (TSA) that supports multiplexing from SCCs, FCCs, SMCs, MCCs onto four time-division multiplexed (TDM) interfaces. uses Serial Interfaces (SI1 SI2). uses TDMA1 which supports both serial nibble mode. does support nibble mode includes TDMB2, TDMC2, TDMD2 which operate only serial mode. individual sets externals signals associated with specific protocol data transfer mode multiplexed across ports, shown Figure 1-2. following sections provide detailed descriptions signals supported Ports A-Port
1-18
Communications Processor Module (CPM) Ports
1.7.1 Port Signals
Table 1-3. Port Signals
Name GeneralPurpose
PA31
Peripheral Controller: Dedicated Signal Protocol
FCC1: TXENB UTOPIA master
Dedicated Data Direction
Output
Description
FCC1: UTOPIA Master Transmit Enable AUTOPIA interface supported FCC1, TXENB asserted MSC8101 (UTOPIA master PHY) when there valid transmit cell data (TXD[0-7]). FCC1: UTOPIA Slave Transmit Enable AUTOPIA interface supported FCC1, TXENB asserted external UTOPIA master when there valid transmit cell data (TXD[0-7]). FCC1: Media Independent Interface Collision Detect interface supported FCC1, asserted external fast Ethernet PHY. FCC1: UTOPIA Slave Transmit Cell Available AUTOPIA interface supported FCC1, TXCLAV asserted MSC8101 (UTOPIA slave PHY) when MSC8101 accept complete Acell. FCC1: UTOPIA Master Transmit Cell Available AUTOPIA interface supported FCC1, TXCLAV asserted external UTOPIA slave indicate that accept complete Acell. FCC1: UTOPIA Master Transmit Cell Available Multi-PHY Direct Polling AUTOPIA interface supported FCC1, TXCLAV0 asserted external UTOPIA slave using direct polling indicate that accept complete Acell. FCC1: Request Send standard modem interface signals supported FCC1 (RTS, CTS, CD). asynchronous with data. typically used conjunction with MSC8101 FCC1 transmitter requests receiver send data asserting low. request accepted when returned low. FCC1: Media Independent Interface Carrier Sense interface supported FCC1. asserted external fast Ethernet PHY. indicates activity cable. FCC1: UTOPIA Transmit Start Cell AUTOPIA interface supported FCC1. TXSOC asserted MSC8101 (UTOPIA master PHY) when TXD[0-7] contains first valid byte cell. FCC1: Media Independent Interface Transmit Error interface supported FCC1. TX_ER asserted MSC8101 force propagation transmit errors.
FCC1: TXENB UTOPIA slave
Input
FCC1: PA30 FCC1: TXCLAV UTOPIA slave
Input
Output
FCC1: TXCLAV UTOPIA master,
Input
FCC1: TXCLAV0 UTOPIA master, Multi-PHY, direct polling
Input
FCC1: HDLC, Serial Nibble
Output
FCC1:
Input
PA29
FCC1: TXSOC UTOPIA master
Output
FCC1: TX_ER
Output
1-19
Communications Processor Module (CPM) Ports
Table 1-3. Port Signals (Continued)
Name GeneralPurpose
PA28
Peripheral Controller: Dedicated Signal Protocol
FCC1: RXENB UTOPIA master
Dedicated Data Direction
Output
Description
FCC1: UTOPIA Master Receive Enable AUTOPIA interface supported FCC1. (UTOPIA master) RXENB asserted MSC8101 (UTOPIA master PHY) indicate that RXD[0-7] RXSOC sampled next cycle. RXD[0-7] RXSOC enabled only cycles following those with RXENB asserted. FCC1: UTOPIA Master Receive Enable AUTOPIA interface supported FCC1. (UTOPIA slave) RXENB input asserted external indicate that RXD[0-7] RXSOC sampled next cycle. RXD[0-7] RXSOC enabled only cycles following those with RXENB asserted. FCC1: Media Independent Interface Transmit Enable interface supported FCC1. TX_EN asserted MSC8101 when transmitting data. FCC1: UTOPIA Receive Start Cell Asserted MSC8101 (UTOPIA slave) external when RXD[0-7] contains first valid byte cell. FCC1: Media Independent Interface Receive Data Valid interface supported FCC1. RX_DV input asserted external fast Ethernet PHY. RX_DV indicates that valid data being sent. presence carrier sense RX_DV indicates reception broken packet headers, probably wiring circuit. FCC1: UTOPIA Slave Receive Cell Available AUTOPIA interface supported FCC1. RXCLAV asserted MSC8101 (UTOPIA slave PHY) when complete Acell available transfer. FCC1: UTOPIA Master Receive Cell Available AUTOPIA interface supported FCC1. RXCLAV asserted external when complete Acell available transfer. FCC1: UTOPIA Master Receive Cell Available Direct Polling AUTOPIA interface supported FCC1, RXCLAV0 asserted external when complete Acell available transfer. FCC1: Media Independent Interface Receive Error interface supported FCC1. RX_ER asserted external fast Ethernet PHY. This signal indicates receive error, which often indicates wiring.
FCC1: RXENB UTOPIA slave
Input
FCC1: TX_EN PA27 FCC1: RXSOC UTOPIA slave
Output
Output
FCC1: RX_DV
Input
PA26
FCC1: RXCLAV UTOPIA slave
Output
FCC1: RXCLAV UTOPIA master,
Input
RXCLAV0 UTOPIA master, Multi-PHY, direct polling
Input
FCC1: RX_ER
Input
1-20
Communications Processor Module (CPM) Ports
Table 1-3. Port Signals (Continued)
Name GeneralPurpose
PA25
Peripheral Controller: Dedicated Signal Protocol
FCC1: TXD0 UTOPIA
Dedicated Data Direction
Output
Description
FCC1: UTOPIA Transmit Data AUTOPIA interface supported FCC1. MSC8101 outputs Acell octets (UTOPIA interface data) TXD[0-7]. TXD7 most significant bit. TXD0 least significant bit. When Adata available, idle cells inserted. cell bytes. Module Serial Number MSNUM[0-4] sub-block code current peripheral controller using SDMA. MSNUM5 indicates which section, transmit receive (1), active during transfer. FCC1: UTOPIA Transmit Data AUTOPIA interface supported FCC1. MSC8101 outputs Acell octets (UTOPIA interface data) TXD[0-7]. TXD7 most significant bit. TXD0 least significant bit. When Adata available, idle cells inserted. cell bytes. Module Serial Number MSNUM[0-4] sub-block code current peripheral controller using SDMA. MSNUM5 indicates which section, transmit receive (1), active during transfer. FCC1: UTOPIA Transmit Data TXD[0-7] part AUTOPIA interface supported FCC1. MSC8101 outputs Acell octets (UTOPIA interface data) TXD[0-7]. TXD7 most significant bit. TXD0 least significant bit. When Adata available, idle cells inserted. cell bytes. FCC1: UTOPIA Transmit Data TXD[0-7] part AUTOPIA interface supported FCC1. MSC8101 outputs Acell octets (UTOPIA interface data) TXD[0-7]. TXD7 most significant bit. TXD0 least significant bit. When Adata available, idle cells inserted. cell bytes. FCC1: UTOPIA Transmit Data TXD[0-7] part AUTOPIA interface supported FCC1. MSC8101 outputs Acell octets (UTOPIA interface data) TXD[0-7]. TXD7 most significant bit. TXD0 least significant bit. When Adata available, idle cells inserted. cell bytes. FCC1: HDLC Nibble Transmit Data TXD[3-0] supports HDLC nibble modes FCC1. TXD3 most significant bit. TXD0 least significant bit.
SDMA: MSNUM0
Output
PA24
FCC1: TXD1 UTOPIA
Output
SDMA: MSNUM1
Output
PA23
FCC1: TXD2 UTOPIA
Output
PA22
FCC1: TXD3 UTOPIA
Output
PA21
FCC1: TXD4 UTOPIA
Output
FCC1: TXD3 HDLC nibble
Output
1-21
Communications Processor Module (CPM) Ports
Table 1-3. Port Signals (Continued)
Name GeneralPurpose
PA20
Peripheral Controller: Dedicated Signal Protocol
FCC1: TXD5 UTOPIA
Dedicated Data Direction
Output
Description
FCC1: UTOPIA Transmit Data TXD[0-7] part AUTOPIA interface supported FCC1. MSC8101 outputs Acell octets (UTOPIA interface data) TXD[0-7]. TXD7 most significant bit. TXD0 least significant bit. When Adata available, idle cells inserted. cell bytes. FCC1: HDLC Nibble Transmit Data TXD[3-0] supported HDLC nibble modes FCC1. TXD3 most significant bit. TXD0 least significant bit. FCC1: UTOPIA Transmit Data TXD[0-7] part AUTOPIA interface supported FCC1. MSC8101 outputs Acell octets (UTOPIA interface data) TXD[0-7]. TXD7 most significant bit. TXD0 least significant bit. When Adata available, idle cells inserted. cell bytes. FCC1: HDLC Nibble Transmit Data TXD[3-0] supported HDLC transparent nibble modes FCC1. TXD3 most significant bit. TXD0 least significant bit. FCC1: UTOPIA Transmit Data TXD[0-7] part AUTOPIA interface supported FCC1. MSC8101 outputs Acell octets (UTOPIA interface data) TXD[0-7]. TXD7 most significant bit. TXD0 least significant bit. When Adata available, idle cells inserted. cell bytes. FCC1: HDLC Nibble Transmit Data TXD[3-0] supported HDLC nibble modes FCC1. TXD3 most significant bit. TXD0 least significant bit. FCC1: HDLC Serial Transparent Transmit Data serial supported HDLC serial transparent modes FCC1. FCC1: UTOPIA Receive Data RXD[0-7] part AUTOPIA interface supported FCC1. MSC8101 inputs Acell octets (UTOPIA interface data) RXD[0-7]. RXD7 most significant bit. RXD0 least significant bit. When Adata available, idle cells inserted. cell bytes. support Multi-PHY configurations, RXD[0-7] tri-stated, enabled only when RXENB asserted. FCC1: HDLC Nibble Receive Data RXD[3-0] supported HDLC nibble mode FCC1. RXD3 most significant bit. RXD0 least significant bit. FCC1: HDLC Serial Transparent Receive Data serial supported HDLC transparent FCC1.
FCC1: TXD2 HDLC nibble
Output
PA19
FCC1: TXD6 UTOPIA
Output
FCC1: TXD1 HDLC nibble
Output
PA18
FCC1: TXD7 UTOPIA
Output
FCC1: TXD0 HDLC nibble
Output
FCC1: HDLC serial transparent PA17 FCC1: RXD7 UTOPIA
Output
Input
FCC1: RXD0 HDLC nibble
Input
FCC1: HDLC serial transparent
Input
1-22
Communications Processor Module (CPM) Ports
Table 1-3. Port Signals (Continued)
Name GeneralPurpose
PA16
Peripheral Controller: Dedicated Signal Protocol
FCC1: RXD6 UTOPIA
Dedicated Data Direction
Input
Description
FCC1: UTOPIA Receive Data RXD[0-7] part AUTOPIA interface supported FCC1. MSC8101 inputs Acell octets (UTOPIA interface data) RXD[0-7]. RXD7 most significant bit. RXD0 least significant bit. When Adata available, idle cells inserted. cell bytes. support Multi-PHY configurations, RXD[0-7] tri-stated, enabled only when RXENB asserted. FCC1: HDLC Nibble Receive Data RXD[3-0] supported HDLC nibble mode FCC1. RXD3 most significant bit. RXD0 least significant bit. FCC1: UTOPIA Receive Data AUTOPIA interface supported FCC1. MSC8101 inputs Acell octets (UTOPIA interface data) RXD[0-7]. RXD7 most significant bit. RXD0 least significant bit. When Adata available, idle cells inserted. cell bytes. support Multi-PHY configurations, RXD[0-7] tri-stated, enabled only when RXENB asserted. FCC1: HDLC Nibble Receive Data RXD[3-0] supported HDLC nibble mode FCC1. RXD3 most significant bit. RXD0 least significant bit. FCC1: UTOPIA Receive Data AUTOPIA interface supported FCC1. MSC8101 inputs Acell octets (UTOPIA interface data) RXD[0-7]. RXD7 most significant bit. RXD0 least significant bit. When Adata available, idle cells inserted. cell bytes. support Multi-PHY configurations, RXD[0-7] tri-stated, enabled only when RXENB asserted. FCC1: HDLC Nibble Receive Data RXD[3-0] supported HDLC nibble mode FCC1. RXD3 most significant bit. RXD0 least significant bit. FCC1: UTOPIA Receive Data AUTOPIA interface supported FCC1. MSC8101 inputs Acell octets (UTOPIA interface data) RXD[0-7]. RXD7 most significant bit. RXD0 least significant bit. cell bytes. support Multi-PHY configurations, RXD[0-7] tri-stated, enabled only when RXENB asserted. Module Serial Number MSNUM[0-4] sub-block code current peripheral controller using SDMA. MSNUM5 indicates which section, transmit receive (1), active during transfer.
FCC1: RXD1 HDLC nibble
Input
PA15
FCC1: RXD5 UTOPIA
Input
RXD2 HDLC nibble
Input
PA14
FCC1: RXD4 UTOPIA
Input
FCC1: RXD3 HDLC nibble
Input
PA13
FCC1: RXD3 UTOPIA
Input
SDMA: MSNUM2
Output
1-23
Communications Processor Module (CPM) Ports
Table 1-3. Port Signals (Continued)
Name GeneralPurpose
PA12
Peripheral Controller: Dedicated Signal Protocol
FCC1: RXD2 UTOPIA
Dedicated Data Direction
Input
Description
FCC1: UTOPIA Receive Data AUTOPIA interface supported FCC1. MSC8101 inputs Acell octets (UTOPIA interface data) RXD[0-7]. RXD7 most significant bit. RXD0 least significant bit. cell bytes. support Multi-PHY configurations, RXD[0-7] tri-stated, enabled only when RXENB asserted. Module Serial Number MSNUM[0-4] sub-block code current peripheral controller using SDMA. MSNUM5 indicates which section, transmit receive (1), active during transfer. FCC1: UTOPIA Receive Data AUTOPIA interface supported FCC1. MSC8101 inputs Acell octets (UTOPIA interface data) RXD[0-7]. RXD7 most significant bit. RXD0 least significant bit. cell bytes. support Multi-PHY configurations, RXD[0-7] tri-stated, enabled only when RXENB asserted. Module Serial Number MSNUM[0-4] sub-block code current peripheral controller using SDMA. MSNUM5 indicates which section, transmit receive active during transfer. FCC1: UTOPIA Receive Data AUTOPIA interface supported FCC1. MSC8101 inputs Acell octets (UTOPIA interface data) RXD[0-7]. RXD7 most significant bit. RXD0 least significant bit. cell bytes. support Multi-PHY configurations, RXD[0-7] tri-stated, enabled only when RXENB asserted. Module Serial Number MSNUM[0-4] sub-block code current peripheral controller using SDMA. MSNUM5 indicates which section, transmit receive (1), active during transfer. SMC2: Serial Management Transmit Data Supported SMC2. interface consists SMTXD, SMRXD, SMSYN, clock. signals used applications. SMCs full-duplex ports that supports three protocols modes: UART, transparent, general-circuit interface (GCI). also PC15. Time-Division Multiplexing Layer Transmit Data TDMA1 interface supported SI1. L1TXD3 most significant bit. L1TXD0 least significant nibble mode. TDMA1 transmits nibble data L1TXD[0-3].
SDMA: MSNUM3
Output
PA11
FCC1: RXD1 UTOPIA
Input
SDMA: MSNUM4
Output
PA10
FCC1: RXD0 UTOPIA
Input
SDMA: MSNUM5
Output
SMC2: SMTXD
Output
TDMA1: L1TXD0 nibble
Output
1-24
Communications Processor Module (CPM) Ports
Table 1-3. Port Signals (Continued)
Name GeneralPurpose
Peripheral Controller: Dedicated Signal Protocol
SMC2: SMRXD
Dedicated Data Direction
Input
Description
SMC2: Serial Management Receive Data Supported SMC2. interface consists SMTXD, SMRXD, SMSYN, clock. signals used applications. SMCs full-duplex ports that supports three protocols modes: UART, transparent, general-circuit interface (GCI). Time-Division Multiplexing Layer Nibble Receive Data TDMA1 interface supported SI1. L1RXD3 most significant bit. L1RXD0 least significant nibble mode. TDMA1 receives nibble data from L1RXD[0-3]. Time-Division Multiplexing Layer Serial Receive Data TDMA1 interface supported SI1. TDMA1 receives serial data from L1RXD. SMC2: Serial Management Synchronization interface consists SMTXD, SMRXD, SMSYN, clock. signals used applications. SMCs full-duplex ports that supports three protocols modes: UART, transparent, general-circuit interface (GCI). Time-Division Multiplexing Layer Transmit Synchronization TDMA1 interface supported SI1, this synchronizing signal transmit channel. Serial Interface with Time-Slot Assigner chapter MSC8101 Technical Reference manual. Time-Division Multiplexing Layer Receive Synchronization. TDMA1 interface supported SI1, this synchronizing signal receive channel.
TDMA1: L1RXD0 nibble
Input
TDMA1: L1RXD serial
Input
SMC2: SMSYN
Input
TDMA1: L1TSYNC nibble serial
Input
TDMA1: L1RSYNC nibble serial
Input
1-25
Communications Processor Module (CPM) Ports
1.7.2 Port Signals
Table 1-4. Port Signals
Name GeneralPurpose
PB31
Peripheral Controller: Dedicated Protocol
FCC2: TX_ER
Dedicated Data Direction
Output
Description
FCC2: Media Independent Interface Transmit Error interface supported FCC2. TX_ER asserted MSC8101 force propagation transmit errors. SCC2: Receive Data Supported SCC2. SCC2 receives serial data from RXD. Time-Division Multiplexing Layer Transmit Data TDMB2 interface supported SI2. L1TXD supports serial mode. TDMB2 transmits serial data L1TXD. SCC2: Transmit Data. Supported SCC2. SCC2 transmits serial data TXD. FCC2: Media Independent Interface Receive Data Valid interface supported FCC2, RX_DV asserted external fast Ethernet PHY. RX_DV indicates that valid data being sent. presence carrier sense, RX_DV, indicates reception broken packet headers, probably wiring circuit. Time-Division Multiplexing Layer Receive Data TDMB2 interface supported SI2. L1RXD supports serial mode. TDMB2 receives serial data from L1RXD. FCC2: Media Independent Interface Transmit Enable interface supported FCC2. TX_EN asserted MSC8101 when transmitting data. Time-Division Multiplexing Layer Receive Synchronization TDMB2 interface supported SI2, this synchronizing signal receive channel.
SCC2:
Input
TDMB2: L1TXD serial PB30 SCC2:
Output
Output
FCC2: RX_DV
Input
TDMB2: L1RXD serial PB29 FCC2: TX_EN
Input Output
TDMB2: L1RSYNC serial
Input
1-26
Communications Processor Module (CPM) Ports
Table 1-4. Port Signals (Continued)
Name GeneralPurpose
PB28
Peripheral Controller: Dedicated Protocol
FCC2: HDLC serial, HDLC nibble, transparent
Dedicated Data Direction
Output
Description
FCC2: Request Send standard modem interface signals supported FCC2 (RTS, CTS, CD). asynchronous with data. typically used conjunction with MSC8101 FCC2 transmitter requests receiver send data asserting low. request accepted when returned low. FCC2: Media Independent Interface Receive Error interface supported FCC2, RX_ER asserted external fast Ethernet PHY. This signal indicates receive error, which often indicates wiring. SCC2: Request Send, Transmit Enable Typically used conjunction with supported SCC2. MSC8101 SCC2 transmitter requests receiver send data asserting low. request accepted when returned low. TENA signal used Ethernet mode. Time-Division Multiplexing Layer Transmit Synchronization TDMB2 interface supported SI2, this synchronizing signal transmit channel. Serial Interface with Time-Slot Assigner chapter MSC8101 Technical Reference manual. FCC2: Media Independent Interface Collision Detect interface supported FCC2. asserted external fast Ethernet PHY. Time-Division Multiplexing Layer Transmit Data TDMC2 interface supported SI2. L1TXD supports serial mode. TDMC2 transmits serial data L1TXD. FCC2: Media Independent Interface Carrier Sense Input interface, asserted external fast Ethernet PHY. This signal indicates activity cable. Time-Division Multiplexing Layer Receive Data TDMC2 interface supported SI2. L1RXD supports serial mode. TDMC2 receives serial data from L1RXD.
FCC2: RX_ER
Input
SCC2: RTS, TENA
Output
TDMB2: L1TSYNC serial
Input
PB27
FCC2:
Input
TDMC2: L1TXD serial PB26 FCC2:
Output
Input
TDMC2: L1RXD serial
Input
1-27
Communications Processor Module (CPM) Ports
Table 1-4. Port Signals (Continued)
Name GeneralPurpose
PB25
Peripheral Controller: Dedicated Protocol
FCC2: TXD3 HDLC nibble
Dedicated Data Direction
Output
Description
FCC2: HDLC Nibble Transmit Data Supported HDLC nibble mode FCC2. TXD3 most significant bit. TXD0 least significant bit. Time-Division Multiplexing Nibble Layer Transmit Data TDMA1 transmits nibble data L1TXD[0-3]. L1TXD3 most significant L1TXD0 least significant nibble mode. Time-Division Multiplexing Layer Transmit Synchronization TDMC2 interface supported SI2, this synchronizing signal transmit channel. Serial Interface with Time-Slot Assigner chapter MSC8101 Technical Reference manual. FCC2: HDLC Nibble: Transmit Data Supported HDLC nibble mode FCC2. TXD3 most significant bit. TXD0 least significant bit. Time-Division Multiplexing Nibble Layer Receive Data TDMA1 receives nibble data into L1RXD[0-3]. L1RXD3 most significant L1RXD0 least significant nibble mode. Time-Division Multiplexing Layer Receive Synchronization TDMC2 interface supported SI2, this synchronizing signal receive channel. FCC2: HDLC Nibble: Transmit Data Supported HDLC nibble mode FCC2. TXD3 most significant bit. TXD0 least significant bit. Time-Division Multiplexing Nibble Layer Receive Data TDMA1 interface supported SI1. TDMA1 supports nibble modes. L1RXD3 most significant bit. L1RXD0 least significant nibble mode. TDMA1 receives nibble data from L1RXD[0-3]. Time-Division Multiplexing Layer Transmit Data TDMD2 interface supported SI2. L1TXD supports serial mode. TDMA1 transmits serial data L1TXD.
TDMA1: L1TXD3 nibble
Output
TDMC2: L1TSYNC serial
Input
PB24
FCC2: TXD2 HDLC nibble
Output
TDMA1: L1RXD3 nibble
Input
TDMC2: L1RSYNC serial
Input
PB23
FCC2: TXD1 HDLC nibble
Output
TDMA1: L1RXD2 nibble
Input
TDMD2: L1TXD serial
Output
1-28
Communications Processor Module (CPM) Ports
Table 1-4. Port Signals (Continued)
Name GeneralPurpose
PB22
Peripheral Controller: Dedicated Protocol
FCC2: TXD0 HDLC nibble
Dedicated Data Direction
Output
Description
FCC2: HDLC Nibble Transmit Data TXD[0-3] supported HDLC nibble mode FCC2. TXD3 most significant bit. TXD0 least significant bit. FCC2: HDLC Serial Transparent Transmit Data supported HDLC serial mode transparent mode FCC2. Time-Division Multiplexing Nibble Layer Receive Data TDMA1 interface supported SI1. TDMA1 supports nibble modes. L1RXD3 most significant bit. L1RXD0 least significant nibble mode. TDMA1 receives nibble data from L1RXD[0-3]. Time-Division Multiplexing Layer Receive Data TDMD2 interface supported SI2. TDMD2 supports serial mode. TDMD2 receives serial data from L1RXD. FCC2: HDLC Nibble Receive Data RXD[0-3] supported HDLC nibble mode FCC2. RXD3 most significant bit. RXD0 least significant bit. FCC2: HDLC Serial Transparent Receive Data Supported HDLC serial mode transparent mode FCC2. Time-Division Multiplexing Nibble Layer Transmit Data TDMA1 interface supported SI1. TDMA1 supports nibble modes. L1TXD3 most significant bit. L1TXD0 least significant nibble mode. TDMA1 transmits nibble data L1TXD[0-3]. Time-Division Multiplexing Layer Transmit Synchronize Data TDMD2 interface supported SI2, this synchronizing signal transmit channel. Serial Interface with Time-Slot Assigner chapter MSC8101 Technical Reference manual.
FCC2: HDLC serial transparent
Output
TDMA1: L1RXD1 nibble
Input
TDMD2: L1RXD serial PB21 FCC2: RXD0 HDLC nibble
Input
Input
FCC2: HDLC serial transparent
Input
TDMA1: L1TXD2 nibble
Output
TDMD2: L1TSYNC serial
Input
1-29
Communications Processor Module (CPM) Ports
Table 1-4. Port Signals (Continued)
Name GeneralPurpose
PB20
Peripheral Controller: Dedicated Protocol
FCC2: RXD1 HDLC nibble
Dedicated Data Direction
Input
Description
FCC2: HDLC Nibble: Receive Data RXD[0-3] supported HDLC nibble mode FCC2. RXD3 most significant bit. RXD0 least significant bit. Time-Division Multiplexing Nibble Layer Transmit Data TDMA1 interface supported SI1. TDMA1 supports nibble modes. L1TXD3 most significant bit. L1TXD0 least significant nibble mode. TDMA1 transmits nibble data L1TXD[0-3]. Time-Division Multiplexing Layer Receive Synchronize Data TDMD2 interface supported SI2, this synchronizing signal receive channel. FCC2: HDLC Nibble Receive Data RXD[0-3] supported HDLC nibble mode FCC2. RXD3 most significant bit. RXD0 least significant bit. I2C: Inter-Integrated Circuit Serial Data interface comprises signals: serial data (SDA) serial clock (SDA). controller uses synchronous, multimaster that connect several integrated circuits board. Clock rates kHz@25 system clock. FCC2: HDLC Nibble Receive Data RXD[0-3] supported HDLC nibble mode FCC2. RXD3 most significant bit. RXD0 least significant bit. I2C: Inter-Integrated Circuit Serial Clock interface comprises signals: serial data (SDA) serial clock (SDA). controller uses synchronous, multimaster that connect several integrated circuits board. Clock rates kHz@25 system clock.
TDMA1: L1TXD1 nibble
Output
TDMD2: L1RSYNC serial
Input
PB19
FCC2: RXD2 HDLC nibble
Input
I2C:
Input/ Output
PB18
FCC2: RXD3 HDLC nibble
Input
I2C:
Input/ Output
1-30
Communications Processor Module (CPM) Ports
1.7.3 Port Signals
Table 1-5. Port Signals
Name GeneralPurpose
PC31
Peripheral Controller: Dedicated Protocol
BRG1O
Dedicated Data Direction
Output
Description
Baud-Rate Generator Output supports BRGs. BRGs used internally bank-of-clocks selection logic and/or provide output pins. BRG1O internal input timers. When CLK5 selected (see PC27 below), source BRG1O which default input timers. System Interface Unit (SIU) chapter MSC8101 Technical Reference manual additional information. CLK5 enabled, BRG1O uses internal input. TMCLK enabled (see PC26 below), BRG1O input timers disabled. Clock supports clock input pins. clocks sent bank-of-clocks selection logic, where they routed controllers. Timer 1/2: Timer Gate timers gated/restarted external gate signal. There gate signals: TGATE1 controls timer and/or TGATE2 controls timer and/or Baud-Rate Generator Output supports BRGs. BRGs used internally bank-of-clocks selection logic and/or provide output pins. Clock supports clock input pins. clocks sent bank-of-clocks selection logic, where they routed controllers. Timer Timer timers (Timer[1-4]) output signal timer output (TOUT[1-4]) when reference value reached. This signal active-low pulse toggle current output. output also connect internally input another timer, resulting 32-bit timer. External Request External request input line asserts internal request processor. signal programmed level- edge-sensitive, also programmable priority. Refer RISC Controller Configuration Register (RCCR) description Chapter MSC8101 Reference Manual programming information. There current microcode applications this request line. reserved future development.
CLK1
Input
TIMER1/2: TGATE1
Input
PC30
BRG2O
Output
CLK2
Input
Timer1: TOUT1
Output
EXT1
Input
1-31
Communications Processor Module (CPM) Ports
Table 1-5. Port Signals (Continued)
Name GeneralPurpose
PC29
Peripheral Controller: Dedicated Protocol
BRG3O
Dedicated Data Direction
Output
Description
Baud-Rate Generator Output supports BRGs. BRGs used internally bank-of-clocks selection logic and/or provide output pins. Clock supports clock input pins. clocks sent bank-of-clocks selection logic, where they routed controllers. Timer Input timer have following sources: another timer, system clock, system clock divided timer input. supports timer inputs. timer inputs captured rising, falling both edges. SCC1: Clear Send, Collision Typically used conjunction with RTS. MSC8101 SCC1 transmitter sends request send data signal (RTS). request accepted when returned low. CLSN signal used Ethernet mode. also PC15. Baud-Rate Generator Output supports BRGs. BRGs used internally bank-of-clocks selection logic and/or provide output pins. Clock supports clock input pins. clocks sent bank-of-clocks selection logic, where they routed controllers. Timer Input timer have following sources: another timer, system clock, system clock divided timer input. supports timer inputs. timer inputs captured rising, falling both edges. Timer Timer Output timers (Timer[1-4]) output signal timer output (TOUT[1-4]) when reference value reached. This signal active-low pulse toggle current output. output also connected internally input another timer, resulting 32-bit timer. SCC2: Clear Send, Collision Typically used conjunction with RTS. MSC8101 SCC2 transmitter sends request send data signal (RTS). request accepted when returned low. CLSN signal used Ethernet mode. also PC13.
CLK3
Input
TIN2
Input
SCC1: CTS, CLSN
Input
PC28
BRG4O
Output
CLK4
Input
TIN1
Input
Timer2: TOUT2
Output
SCC2: CTS, CLSN
Input
1-32
Communications Processor Module (CPM) Ports
Table 1-5. Port Signals (Continued)
Name GeneralPurpose
PC27
Peripheral Controller: Dedicated Protocol
BRG5O
Dedicated Data Direction
Output
Description
Baud-Rate Generator Output supports BRGs. BRGs used internally bank-of-clocks selection logic and/or provide output pins. Clock When selected, CLK5 source timers BRG1O. System Interface Unit (SIU) chapter MSC8101 Technical Reference manual additional information. CLK5 enabled, BRG1O uses internal input. TMCLK enabled (see PC26 below), BRG1O input timers disabled. Timer 3/4: Timer Gate timers gated/restarted external gate signal. There gate signals: TGATE1 controls timer and/or TGATE2 controls timer and/or Baud-Rate Generator Output supports BRGs. BRGs used internally bank-of-clocks selection logic and/or provide output pins. Clock supports clock input pins. clocks sent bank-of-clocks selection logic, where they routed controllers. Timer Timer timers (Timer[1-4]) output signal timer output (TOUT[1-4]) when reference value reached. This signal active-low pulse toggle current output. output also connect internally input another timer, resulting 32-bit timer. Timer Clock When selected, TMCLK designated input timers. When TMCLK configured input timers, BRG1O input disabled. System Interface Unit (SIU) chapter MSC8101 Technical Reference manual additional information.
CLK5
Input
TIMER3/4: TGATE2
Input
PC26
BRG6O
Output
CLK6
Input
Timer3: TOUT3
Output
TMCLK
Input
1-33
Communications Processor Module (CPM) Ports
Table 1-5. Port Signals (Continued)
Name GeneralPurpose
PC25
Peripheral Controller: Dedicated Protocol
BRG7O
Dedicated Data Direction
Output
Description
Baud-Rate Generator Output supports BRGs. BRGs used internally bank-of-clocks selection logic and/or provide output pins. Clock supports clock input pins. clocks sent bank-of-clocks selection logic, where they routed controllers. Timer Input timer have following sources: another timer, system clock, system clock divided timer input. supports timer inputs. timer inputs captured rising, falling both edges. DMA: Data Acknowledge DACK2, DREQ2, DRACK2 DONE2 belong DMA. DONE2 DRACK2 signals same therefore cannot used simultaneously. There sets pins associated with ports. Baud-Rate Generator Output supports BRGs. BRGs used internally bank-of-clocks selection logic and/or provide output pins. Clock supports clock input pins. clocks sent bank-of-clocks selection logic, where they routed controllers. Timer Input timer have following sources: another timer, system clock, system clock divided timer input. supports four timer inputs. timer inputs captured rising, falling, both edges. Timer Timer timers (Timer1-4]) output signal timer output (TOUT[1-4]) when reference value reached. This signal active-low pulse toggle current output. output also connected internally input another timer, resulting 32-bit timer. DMA: Data Request DACK2, DREQ2, DRACK2, DONE2 belong DMA. DONE2 DRACK2 signals same therefore cannot used simultaneously. There sets pins associated with ports.
CLK7
Input
TIN4
Input
DMA: DACK2
Output
PC24
BRG8O
Output
CLK8
Input
TIN3
Input
Timer4: TOUT4
Output
DMA: DREQ2
Input
1-34
Communications Processor Module (CPM) Ports
Table 1-5. Port Signals (Continued)
Name GeneralPurpose
PC23
Peripheral Controller: Dedicated Protocol
CLK9
Dedicated Data Direction
Input
Description
Clock supports clock input pins. clocks sent bank-of-clocks selection logic, where they routed controllers. DMA: Data Acknowledge DACK1, DREQ1, DRACK1, DONE1 belong DMA. DONE1 DRACK1 signals same therefore cannot used simultaneously. There sets pins associated with ports. External Request External request input line asserts internal request processor. signal programmed level- edge-sensitive, also programmable priority. Refer RISC Controller Configuration Register (RCCR) description Chapter MSC8101 Reference Manual programming information. There current microcode applications this request line. reserved future development. Serial Interface Layer Strobe time-slot assigner supported SI1. MSC8101 time-slot assigner supports four strobe outputs that asserted byte basis. strobe outputs useful interfacing other devices that support multiplexed interface enabling/disabling three-state buffers multiple-transmitter architecture. These strobes also generate output wave forms such applications stepper-motor control. Clock supports clock input pins. clocks sent bank-of-clocks selection logic, where they routed controllers. DMA: Request DACK1, DREQ1, DRACK1, DONE1 belong DMA. DONE1 DRACK1 signals same therefore cannot used simultaneously. There sets pins associated with ports.
DMA: DACK1
Output
EXT2
Input
PC22
SI1: L1ST1
Output
CLK10
Input
DMA: DREQ1
Input/ Output
1-35
Communications Processor Module (CPM) Ports
Table 1-5. Port Signals (Continued)
Name GeneralPurpose
PC15
Peripheral Controller: Dedicated Protocol
SMC2: SMTXD
Dedicated Data Direction
Output
Description
SMC2: Serial Management Transmit Data Supported SMC2. interface consists SMTXD, SMRXD, SMSYN, clock. signals used applications. SMCs full-duplex ports that support three protocols modes: UART, transparent, general-circuit interface (GCI). also PA9. SCC1: Clear Send, Collision Typically used conjunction with RTS. MSC8101 SCC1 transmitter sends request send data signal (RTS). request accepted when returned low. CLSN signal used Ethernet mode. also PC29. FCC1: UTOPIA Master Transmit Address AUTOPIA master interface supported FCC1, this transmit address FCC1: UTOPIA Slave Transmit Address AUTOPIA slave interface supported FCC1, this transmit address Serial Interface Layer Strobe time-slot assigner supported SI1. MSC8101 time-slot assigner supports four strobe outputs that asserted byte basis. strobe outputs useful interfacing other devices that support multiplexed interface enabling/disabling three-state buffers multiple-transmitter architecture. These strobes also generate output wave forms such applications stepper-motor control. SCC1: Carrier Detect, Receive Enable Typically used conjunction with supported SCC1. MSC8101 SCC1 transmitter requests receiver send data asserting low. request accepted when returned low. FCC1: UTOPIA Multi-PHY Master Receive Address AUTOPIA master interface supported FCC1, this receive address FCC1: UTOPIA Multi-PHY Slave Receive Address AUTOPIA slave interface supported FCC1, this receive address
SCC1: CTS/CLSN
Input
FCC1: TXADDR0 UTOPIA master
Output
FCC1: TXADDR0 UTOPIA slave PC14 SI1: L1ST2
Input
Output
SCC1: RENA
Input
FCC1: RXADDR0 UTOPIA master
Output
FCC1: RXADDR0 UTOPIA slave
Input
1-36
Communications Processor Module (CPM) Ports
Table 1-5. Port Signals (Continued)
Name GeneralPurpose
PC13
Peripheral Controller: Dedicated Protocol
SI1: L1ST4
Dedicated Data Direction
Output
Description
Serial Interface Layer Strobe time-slot assigner supported SI1. MSC8101 time-slot assigner supports four strobe outputs that asserted byte basis. strobe outputs useful interfacing other devices that support multiplexed interface enabling/disabling three-state buffers multiple-transmitter architecture. These strobes also generate output wave forms such applications stepper-motor control. SCC2: Clear Send, Collision Typically used conjunction with RTS. MSC8101 SCC2 transmitter sends request send data signal (RTS). request accepted when returned low. CLSN signal used Ethernet mode. also PC28. FCC1: UTOPIA Multi-PHY Master Transmit Address AUTOPIA master interface supported FCC1, this transmit address FCC1: UTOPIA Multi-PHY Slave Transmit Address AUTOPIA slave interface supported FCC1, this transmit address Serial Interface Layer Strobe time-slot assigner supported SI1. MSC8101 time-slot assigner supports four strobe outputs that asserted byte basis. strobe outputs useful interfacing other devices that support multiplexed interface enabling/disabling three-state buffers multiple-transmitter architecture. These strobes also generate output wave forms such applications stepper-motor control. SCC2: Carrier Detect, Request Enable Typically used conjunction with supported SCC2. MSC8101 SCC2 transmitter requests receiver that sends data asserting low. request accepted when returned low. FCC1: UTOPIA Multi-PHY Master Receive Address AUTOPIA master interface supported FCC1, this receive address FCC1: UTOPIA Multi-PHY Slave Receive Address AUTOPIA slave interface supported FCC1, this receive address
SCC2: CTS,CLSN
Input
FCC1:TXADDR1 UTOPIA master
Output
FCC1: TXADDR1 UTOPIA slave PC12 SI1: L1ST3
Input
Output
SCC2: RENA
Input
FCC1: RXADDR1 UTOPIA master
Output
FCC1: RXADDR1 UTOPIA slave
Input
1-37
Communications Processor Module (CPM) Ports
Table 1-5. Port Signals (Continued)
Name GeneralPurpose
Peripheral Controller: Dedicated Protocol
SI2: L1ST1
Dedicated Data Direction
Output
Description
Serial Interface Strobe time-slot assigner supported SI2. MSC8101 time-slot assigner supports four strobe outputs that asserted byte basis. strobe outputs useful interfacing other devices that support multiplexed interface enabling/disabling three-state buffers multiple-transmitter architecture. These strobes also generate output wave forms such applications stepper-motor control. FCC1: Clear Send standard modem interface signals supported FCC1 (RTS, CTS, CD). asynchronous with data. FCC1: UTOPIA Multi-PHY Master Transmit Address AUTOPIA master interface supported FCC1, this transmit address FCC1: UTOPIA Multi-PHY Slave Transmit Address AUTOPIA slave interface supported FCC1 using multiplexed polling, this transmit address FCC1: UTOPIA Multi-PHY Master Transmit Cell Available Direct Polling AUTOPIA master interface supported FCC1 using direct polling, TXCLAV1 asserted external UTOPIA slave indicate that accept complete Acell.
FCC1: HDLC serial, HDLC nibble, transparent FCC1: TXADDR2 UTOPIA master
Input
Output
FCC1: TXADDR2 UTOPIA slave
Input
FCC1: TXCLAV1 UTOPIA multi-PHY master, direct polling
Input
1-38
Communications Processor Module (CPM) Ports
Table 1-5. Port Signals (Continued)
Name GeneralPurpose
Peripheral Controller: Dedicated Protocol
SI2: L1ST2
Dedicated Data Direction
Output
Description
Serial Interface Layer Strobe time-slot assigner supported SI2. MSC8101 time-slot assigner supports four strobe outputs that asserted byte basis. strobe outputs useful interfacing other devices that support multiplexed interface enabling/disabling three-state buffers multiple-transmitter architecture. These strobes also generate output wave forms such applications stepper-motor control. FCC1: Carrier Detect standard modem interface signals supported FCC1 (RTS, CTS, CD). input asynchronous with data. FCC1: UTOPIA Multi-PHY Master Receive Address AUTOPIA master interface supported FCC1, this receive address FCC1: UTOPIA Slave Receive Address AUTOPIA slave interface supported FCC1 using multiplexed polling, this receive address FCC1: UTOPIA Multi-PHY Master Receive Cell Available Direct Polling AUTOPIA master interface supported FCC1 using direct polling, RXCLAV1 asserted external when complete Acell available transfer. SMC1: Transmit Data Supported SMC1. interface consists SMTXD, SMRXD, SMSYN, clock. signals used applications. SMCs full-duplex ports that supports three protocols modes: UART, transparent, general-circuit interface (GCI). Serial Interface Layer Strobe time-slot assigner supported SI2. MSC8101 time-slot assigner supports four strobe outputs that asserted byte basis. strobe outputs useful interfacing other devices that support multiplexed interface enabling/disabling three-state buffers multiple-transmitter architecture. These strobes also generate output wave forms such applications stepper-motor control. FCC2: Clear Send standard modem interface signals supported FCC2 (RTS, CTS, CD). asynchronous with data.
FCC1: HDLC serial, HDLC nibble, transparent
Input
FCC1: RXADDR2 UTOPIA master
Output
FCC1: RXADDR2 UTOPIA slave
Input
FCC1: RXCLAV1 UTOPIA multi-PHY master, direct polling
Input
SMC1: SMTXD
Output
SI2: L1ST3
Output
FCC2: HDLC serial, HDLC nibble, transparent
Input
1-39
Communications Processor Module (CPM) Ports
Table 1-5. Port Signals (Continued)
Name GeneralPurpose
Peripheral Controller: Dedicated Protocol
SMC1: SMRXD
Dedicated Data Direction
Input
Description
SMC1: Receive Data Supported SMC1. interface consists SMTXD, SMRXD, SMSYN, clock. signals used applications. SMCs full-duplex ports that supports three protocols modes: UART, transparent, general-circuit interface (GCI). Serial Interface Layer Strobe time-slot assigner supported SI2. MSC8101 time-slot assigner supports four strobe outputs that asserted byte basis. strobe outputs useful interfacing other devices that support multiplexed interface enabling/disabling three-state buffers multiple-transmitter architecture. These strobes also generate output wave forms such applications stepper-motor control. FCC2: Carrier Detect standard modem interface signals supported FCC2 (RTS, CD). asynchronous with data.
SI2: L1ST4
Output
FCC2: HDLC serial, HDLC nibble, transparent
Input
1-40
Communications Processor Module (CPM) Ports
1.7.4 Port Signals
Table 1-6. Port Signals
Name GeneralPurpose
PD31
Peripheral Controller: Dedicated Protocol
SCC1:
Dedicated Data Direction
Input
Description
SCC1: Receive Data Supported SCC1. SCC1 receives serial data from RXD. DMA: Data Request Acknowledge DACK1, DREQ1, DRACK1, DONE1 belong DMA. DONE1 DRACK1 signals same therefore cannot used simultaneously. There sets pins associated with ports. DMA: Done DACK1, DREQ1, DRACK1, DONE1 belong DMA. DONE1 DRACK1 signals same therefore cannot used simultaneously. There sets pins associated with ports. SCC1: Transmit Data Supported SCC1. SCC1 transmits serial data TXD. DMA: Data Request Acknowledge DACK2, DREQ2, DRACK2, DONE2 belong DMA. DONE2 DRACK2 signals same therefore cannot used simultaneously. There sets pins associated with ports. DMA: Done DACK2, DREQ2, DRACK2, DONE2 belong DMA. DONE2 DRACK2 signals same therefore cannot used simultaneously. There sets pins associated with ports. SCC1: Request Send, Transmit Enable Typically used conjunction with supported SCC2. MSC8101 SCC1 transmitter requests receiver send data asserting low. request accepted when returned low. TENA signal used Ethernet mode. FCC1: UTOPIA Multi-PHY Master Receive Address AUTOPIA master interface supported FCC1 using multiplexed polling, this receive address FCC1: UTOPIA Slave Receive Address AUTOPIA slave interface supported FCC1 using multiplexed polling, this receive address FCC1: UTOPIA Multi-PHY Master Receive Cell Available Direct Polling AUTOPIA master interface supported FCC1 using direct polling, RXCLAV2 asserted external when complete Acell available transfer.
DMA: DRACK1
Output
DMA: DONE1
Input/ Output
PD30
SCC1:
Output
DMA: DRACK2
Output
DMA: DONE2
Input/ Output
PD29
SCC1: RTS, TENA
Output
FCC1: RXADDR3 UTOPIA master
Output
FCC1: RXADDR3 UTOPIA slave
Input
FCC1: RXCLAV2 UTOPIA multi-PHY master, direct polling
Input
1-41
Communications Processor Module (CPM) Ports
Table 1-6. Port Signals (Continued)
Name GeneralPurpose
PD19
Peripheral Controller: Dedicated Protocol
FCC1: TXADDR4 UTOPIA master
Dedicated Data Direction
Output
Description
FCC1: Multi-PHY Master Transmit Address Multiplexed Polling AUTOPIA master interface supported FCC1 using multiplexed polling, this transmit address FCC1: UTOPIA Slave Transmit Address AUTOPIA slave interface supported FCC1 using multiplexed polling, this transmit address FCC1: UTOPIA Multi-PHY master Transmit Cell Available Direct Polling AUTOPIA master interface supported FCC1 using direct polling, TXCLAV3 asserted external UTOPIA slave indicate that accept complete Acell. Baud Rate Generator Output supports BRGs. BRGs used internally bank-of-clocks selection logic and/or provide output pins. BRG1O internal input timers. When CLK5 selected (see PC27 above), source BRG1O which default input timers. System Interface Unit (SIU) chapter MSC8101 Technical Reference manual additional information. CLK5 enabled, BRG1O uses internal input. TMCLK enabled (see PC26 above), BRG1O input timers disabled. SPI: Select interface comprises four signals: master slave (SPIMOSI), master slave (SPIMISO), clock (SPICLK) select (SPISEL). configured slave master single- multiple-master environments. SPISEL enable input slave. multimaster environment, SPISEL (always input) detects error when more than master operating. masters must output slave select signal enable slave devices using separate general-purpose signal. Assertion SPISEL while master causes error.
FCC1: TXADDR4 UTOPIA slave
Input
FCC1: TXCLAV3 UTOPIA multi-PHY master, direct polling
Input
BRG1O
Output
SPI: SPISEL
Input
1-42
Communications Processor Module (CPM) Ports
Table 1-6. Port Signals (Continued)
Name GeneralPurpose
PD18
Peripheral Controller: Dedicated Protocol
FCC1: RXADDR4 UTOPIA master
Dedicated Data Direction
Output
Description
FCC1: UTOPIA Master Receive Address AUTOPIA master interface supported FCC1 using multiplexed polling, this receive address FCC1: UTOPIA Slave Receive Address AUTOPIA slave interface supported FCC1, this receive address FCC1: UTOPIA Multi-PHY Master Receive Cell Available Direct Polling AUTOPIA master interface supported FCC1 using direct polling, RXCLAV3 asserted external when complete Acell available transfer. SPI: Clock interface comprises four signals: master slave (SPIMOSI), master slave (SPIMISO), clock (SPICLK) select (SPISEL). configured slave master single- multiple-master environments. SPICLK gated clock, active only during data transfers. Four combinations SPICLK phase polarity configured. When master, SPICLK clock output signal that shifts received data from SPIMISO transmitted data SPIMOSI. Baud Rate Generator Output supports BRGs. BRGs used internally MSC8101 and/or provide output pins. FCC1: UTOPIA Receive Parity AUTOPIA interface supported FCC1, this parity RXD[0-7]. SPI: Master Output Slave Input interface comprises signals: master slave (SPIMOSI), master slave (SPIMISO), clock (SPICLK) select (SPISEL). configured slave master single- multiple-master environments. When slave, SPICLK clock input that shifts received data from SPIMOSI transmitted data through SPIMISO. FCC1: UTOPIA Transmit Parity AUTOPIA interface supported FCC1, this parity TXD[0-7]. SPI: Master Input Slave Output interface comprises four signals: master slave (SPIMOSI), master slave (SPIMISO), clock (SPICLK), select (SPISEL). configured slave master single- multiple-master environments. When slave, SPICLK clock input that shifts received data from SPIMOSI transmitted data through SPIMISO.
FCC1: RXADDR4 UTOPIA slave
Input
FCC1: RXCLAV3 UTOPIA multi-PHY master, direct polling
Input
SPI: SPICLK
Input/ Output
PD17
BRG2O
Output
FCC1: RXPRTY UTOPIA
Input
SPI: SPIMOSI
Input/ Output
PD16
FCC1: TXPRTY UTOPIA
Output
SPI: SPIMISO
Input/ Output
1-43
JTAG Test Access Port Signals
Table 1-6. Port Signals (Continued)
Name GeneralPurpose
Peripheral Controller: Dedicated Protocol
SMC1: SMSYN
Dedicated Data Direction
Input
Description
SMC1: Serial Management Synchronization Supported SMC1. SMSYN input. interface consists SMTXD, SMRXD, SMSYN clock. signals used applications. SMCs full-duplex ports that supports three protocols modes: UART, transparent general-circuit interface (GCI). FCC1: UTOPIA Master Transmit Address AUTOPIA master interface supported FCC1 using multiplexed polling, this transmit address FCC1: UTOPIA Slave Transmit Cell Available AUTOPIA slave interface supported FCC1 using multiplexed polling, this transmit address FCC1: UTOPIA Multi-PHY Master Transmit Cell Available Direct Polling AUTOPIA master interface supported FCC1 using direct polling, TXCLAV2 asserted external UTOPIA slave indicate that accept complete Acell.
FCC1: TXADDR3 UTOPIA master
Output
FCC1: TXADDR3 UTOPIA slave
Input
FCC1: TXCLAV2 UTOPIA multi-PHY master, direct polling
Input
JTAG Test Access Port Signals
MSC8101 supports standard Test Access Port (TAP) signals defined IEEE 1149.1 Standard Test Access Port Boundary-Scan Architecture specification described Table 1-7. Table 1-7. JTAG Test Access Port Signals
Signal Name
Type
Input Input
Signal Description
Test Clock-A test clock signal synchronizing JTAG test logic. Test Data Input-A test data serial signal test instructions data. sampled rising edge internal pull-up resistor. Test Data Output-A test data serial signal test instructions data. tri-stated. signal actively driven shift-IR shift-DR controller states changes falling edge TCK. Test Mode Select-Sequences test controller's state machine, sampled rising edge TCK, internal pull-up resistor. Test Reset-Asynchronously initializes test controller, internal pull-up resistor, must asserted after power
Output
Input
TRST
Input
1-44
Reserved Signals
Reserved Signals
Table 1-8. Reserved Signals
Signal Name
TEST
Type
Input
Signal Description
Test Used manufacturing testing. must connect this input GND. Leave disconnected. Spare Pins Leave disconnected backward compatibility with future revisions this device.
THERM[1-2] SPARE1,
1-45
Reserved Signals
1-46
Chapter
Specifications (mask 2K42A)
2A.1 Introduction
This document contains detailed information power considerations, DC/AC electrical characteristics, timing specifications MSC8101 communications processor, mask 2K42A. additional information, MSC8101 Reference Manual.
2A.2 Absolute Maximum Ratings
CAUTION
This device contains circuitry protecting against damage high static voltage electrical fields; however, normal precautions should taken avoid exceeding maximum voltage ratings. Reliability enhanced unused inputs tied appropriate logic voltage level (for example, either VCC). calculating timing requirements, adding maximum value specification minimum value another specification does yield reasonable sum. maximum specification calculated using worst case variation process parameter values direction. minimum specification calculated using worst case same parameters opposite direction. Therefore, "maximum" value specification never occurs same device with "minimum" value another specification; adding maximum minimum represents condition that never exist.
2A-1
Recommended Operating Conditions
Table 2A-1 describes maximum electrical ratings MSC8101. Table 2A-1. Absolute Maximum Ratings2
Rating
Core supply voltage3 supply voltage3 supply Input voltage3
Symbol
VCCSYN
Value
-0.2 -0.2 -0.2 (GND 0.2) +150
Unit
voltage3 range4
Maximum operating temperature Storage temperature range Notes:
TSTG
Functional operating conditions given Table 2A-2. Absolute maximum ratings stress ratings only, functional operation maximum guaranteed. Stress beyond listed limits affect device reliability cause permanent damage. input voltage must exceed supply VDDH more than time, including during power-on reset. turn, VDDH exceed DD/V CCSYN more than during power-on reset, more than VDDH should exceed VDD/V CCSYN more than during normal operation. VDD/V CCSYN must exceed VDDH more than time, including during power-on reset. Section 4.2, Electrical Design Considerations, page more information. Section 4.1, Thermal Design Considerations, page includes formula computing chip junction temperature
2A.3 Recommended Operating Conditions
Table 2A-2 lists recommended operating conditions. Proper device operation outside these conditions guaranteed. Table 2A-2. Recommended Operating Conditions
Rating
SC140 Core supply voltage supply voltage supply voltage Input voltage Operating temperature range
Symbol
VCCSYN VDDH
Value
3.135 3.465 -0.2 VDDH
Unit
2A.4 Thermal Characteristics
Table 2A-3 describes thermal characteristics MSC8101. Table 2A-3. Thermal Characteristics
Characteristic
Junction-to-ambient1, Junction-to-board (bottom)3 Junction-to-case (top)
Symbol
Lidded FC-PBGA 17mm
Unit
°C/W °C/W °C/W
2A-2
Electrical Characteristics
Table 2A-3. Thermal Characteristics (Continued)
Characteristic
Notes:
Symbol
Lidded FC-PBGA 17mm
Unit
Junction temperature function on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, flow, power dissipation other components board, board thermal resistance. SEMI G38-87 EIA/JESD51-2 with single layer (1s) board horizontal. Thermal resistance between printed circuit board JESD 51-8. Indicates average thermal resistance between case surface measured cold plate method (MIL SPEC-883 Method 1012.1) with cold plate temperature used case temperature. Numbers based simulations. Actual values TBD.
Section 4.1, Thermal Design Considerations, page details these characteristics.
2A.5 Electrical Characteristics
This section describes electrical characteristics MSC8101. measurements Table 2A-4 assume following system conditions: VDDH leakage current measured nominal VDDH both VDDH must vary same direction (for example, both VDDH vary percent). Table 2A-4. Electrical Characteristics
Characteristic
Input high voltage, inputs except CLKIN Input voltage CLKIN input high voltage CLKIN input voltage1 Input leakage current, VDDH Tri-state (high impedance state) leakage current, VDDH Signal input current, Signal high input current, Output high voltage, except open drain pins Output voltage, IOL= Notes:
Note:
Symbol
VILC
3.465 3.465 -4.0
Unit
optimum CLKIN duty cycle obtained when: VILC VDDH VIHC
2A-3
Clock Configuration
Table 2A-5. Typical Power Dissipation
Characteristic
Core power dissipation power dissipation 137.5 power dissipation 68.75 Core leakage power leakage power leakage power
Symbol
PCORE PCPM PSIU PLCO PLSI
Typical
Unit
2A.6 Clock Configuration
following sections provide general description clock configuration.
2A.6.1 Valid Clock Modes
Table 2A-6 shows maximum frequency values each rated core frequency (250 MHz). user must ensure that maximum frequency values exceeded. Table 2A-6. Maximum Frequencies
Characteristic
Core Frequency Frequency (CPMCLK) Frequency (BCLK) Serial Communication Controller Clock Frequency (SCLK) Baud Rate Generator Clock Frequency (BRGCLK) External Clock Output Frequency (CLKOUT)
Maximum Frequency
62.5 62.5 137.5 68.75 68.75 68.75 68.75
values MSC8101 clocks valid configuration mode options. Each option determines CLKIN SC140 core, system bus, clock, CPM, CLKOUT frequencies. values derived from three dedicated input pins (MODCK[1-3]) three bits from reset configuration word (MODCK_H). configure SPLL pre-division factor, SPLL multiplication factor, frequencies SC140 core, clocks, parallel ports, system buses, MODCK[1-3] pins sampled combined with MODCK_H values when internal power-on reset (internal PORESET) deasserted. Clock configuration changes only when internal PORESET signal deasserted. following factors configured: SPLL pre-division factor (SPLL PDF) SPLL multiplication factor (SPLL post-division factor (Bus division factor (SCC fixed division factor (CPM fixed division factor (BRG configured through System Clock Control Register (SCCR) (default after reset), 256. Note: Refer AN2288/D Clock Mode Selection MSC8101 Mask 2K42A details clock configuration.
2A-4
Clock Configuration
2A.6.2 Clocks Programming Model
This section describes clock registers detail. registers discussed follows: System Clock Control Register (SCCR) System Clock Mode Register (SCMR)
2A.6.2.1 System Clock Control Register
TYPE RESET
TYPE RESET
DFBRG
Figure 2A-1. System Clock Control Register (SCCR)-0x10C80 SCCR memory-mapped into register MSC8101. Table 2A-7. SCCR Descriptions
Defaults Name
0-29 DFBRG 30-31
PORESET
Hard Reset
Reserved
Description
Settings
Unaffected Division Factor Clock Defines BRGCLK frequency. Changing this value does result loss lock condition.
Divide Divide (default value) Divide Divide
2A.6.2.2 System Clock Mode Register
TYPE RESET
COREPDF
COREMF
BUSDF
CPMDF
DLLDIS
SPLLPDF TYPE RESET
SPLLMF
Figure 2A-2. System Clock Mode Register (SCMR)-0x10C88 SCMR read-only register that updated during power-on reset (PORESET) provides mode control signals PLLs, DLL, clock logic. This register reflects currently defined configuration settings. details available setting options, AN2288. 2A-5
Timings
Table 2A-8. SCMR Descriptions
Defaults Name
PORESET
Hard Reset
Reserved
Description
Settings
COREPDF Configuration Unaffected Core Pre-Division Factor Pins
CPLL PDF= CPLL PDF= CPLL PDF= CPLL PDF=
COREMF BUSDF 8-11
Configuration Unaffected Core Multiplication Factor Pins Configuration Unaffected Division Factor Pins
0101 0110 other combinations used. 0010 0011 0100 other combinations used.
CPMDF 12-15 SPLLPDF 16-19
Configuration Unaffected Division Factor Pins Configuration Unaffected SPLL Pre-Division Factor Pins
0001 other combinations used. 0000 0001 0010 0011 other 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 other SPLL SPLL SPLL SPLL combinations used SPLL SPLL SPLL SPLL SPLL SPLL SPLL SPLL SPLL SPLL combinations used
SPLLMF 20-23
Configuration Unaffected SPLL Multiplication Factor Pins
DLLDIS 26-31
Reserved operation enabled disabled
Configuration Unaffected Disable Pins Reserved
2A.7 Timings
following sections include illustrations tables clock diagrams, signals, parallel outputs inputs. timings based load, except where noted otherwise, transmission line.
2A-6
Timings
2A.7.1 Clocking Timing Characteristics
Table 2A-9. System Clock Parameters
Characteristic
Phase Jitter between BCLK DLLIN CLKIN frequency1,2 CLKIN slope DLLIN slope CLKOUT frequency jitter Delay between CLKOUT DLLIN Notes:
Minimum
Maximum
(0.01/CLKOUT) CLKIN jitter
Unit
CLKIN frequency causes poor performance. Choose CLKIN frequency high enough keep frequency after predivider (SPLLMFCLK) higher than MHz. CLKIN should have duty cycle.
Table 2A-10. Clock Ranges
Maximum Rated Core Frequency Clock Symbol
Input Clock SPLL Clock Output Serial Communications Controller Communications Processor Module SC140 Core Baud Rate Generator (default) CLKIN SPLLMFCLK BCLK CLKOUT SCLK CPMCLK DSPCLK BRGCLK 2.25 562.5 62.5 15.63 3.91 976.6 68.75 17.19 4.30 1.07 43.2
Max. Values SC140 Clock Rating
62.5 20.83 62.5 62.5 62.5
68.75 22.9 68.75 68.75 68.75 137.5
2A-7
Timings
2A.7.2 Reset Timing
MSC8101 several inputs reset logic: Power-on reset (PORESET) External hard reset (HRESET) External soft reset (SRESET) Asserting external PORESET causes concurrent assertion internal PORESET signal, HRESET, SRESET. When external PORESET signal deasserted, MSC8101 samples several configuration pins:
RSTCONF-determines whether MSC8101 master slave device DBREQ -determines whether operate normal mode invoke SC140 debug mode HPE-disable enable host port (HDI16) BTM[0-1]-boot from external memory (00) HDI16 (01)
these reset sources into reset controller, which takes different actions depending source reset. reset status register indicates last sources cause reset. Table 2A-11 describes reset causes. Table 2A-11. Reset Causes
Name
Power-on reset (PORESET) Hard reset (HRESET) Soft reset (SRESET)
Direction
Input Input/Output
Description
PORESET initiates power-on reset flow that resets MSC8101s configures various attributes MSC8101, including clock mode. MSC8101 detect external assertion HRESET only occurs while MSC8101 asserting reset. During HRESET, SRESET asserted. HRESET open-drain pin. MSC8101 detect external assertion SRESET only occurs while MSC8101 asserting reset. SRESET open-drain pin.
Input/Output
2A.7.2.1 Reset Operation
reset control logic determines cause reset, synchronizes necessary, resets appropriate logic modules. memory controller, system protection logic, interrupt controller, parallel pins initialized only hard reset. Soft reset initializes internal logic while maintaining system configuration. MSC8101 mechanisms reset configuration: host reset configuration hardware reset configuration.
2A.7.2.2 Power-On Reset Flow
Asserting PORESET external initiates power-on reset flow. PORESET should asserted externally least input clock cycles after external power MSC8101 reaches least VCC. Table 2A-12 shows, MSC8101 five configuration pins, four which multiplexed with SC140 core EONCE Event (EE[0-1], EE[4-5]) pins fifth which RSTCONF pin. These pins sampled rising edge PORESET. addition these configuration pins, three (MODCK[1-3]) pins sampled MSC8101. signals these pins MODCK_H value Hard Reset Configuration Word determine locking mode, defining ratio between clock, clocks, clock frequencies.
2A-8
Timings
Table 2A-12. External Configuration Signals
RSTCONF
Description
Reset Configuration Input line sampled MSC8101 rising edge PORESET. EONCE Event Input line sampled after SC140 core locks. Holding high when PORESET deasserted puts SC140 core into Debug mode.
Settings
Reset Configuration Master. Reset Configuration Slave. SC140 core starts normal processing mode after reset. SC140 core enters Debug mode immediately after reset. Host port disabled (hardware reset configuration enabled). Host port enabled.
DBREQ/
HPE/EE1
Host Port Enable Input line sampled rising edge PORESET. asserted, Host port enabled, system data 32-bit wide, Host must program reset configuration word. Boot Mode Input lines sampled rising edge PORESET, which determine MSC8101 Boot mode.
BTM[0-1]/ EE[4-5]
MSC8101 boots from external memory. MSC8101 boots from HDI16. Reserved. Reserved.
Table 2A-13. Reset Timing
Characteristics
Required external PORESET duration minimum CLKIN CLKIN Delay from deassertion external PORESET deassertion internal PORESET CLKIN CLKIN Delay from deassertion internal PORESET SPLL lock SPLLMFCLK SPLLMFCLK Delay from SPLL lock lock enabled BCLK BCLK disabled Delay from SPLL lock HRESET deassertion enabled BCLK BCLK disabled BCLK BCLK Delay from SPLL lock SRESET deassertion enabled BCLK BCLK disabled BCLK BCLK
Expression
CLKIN
Unit
888.8 213.3 1024 CLKIN 56.89 13.65 SPLLMFCLK 44.4 32.0
3073 BLCK 170.72 40.97
3585 BLCK 199.17 47.5 BLCK 28.4 6.83
3588 BLCK 199.33 47.84 BLCK 28.61 6.87
Note:
Value given lowest possible CLKIN frequency ensure proper initialization reset sequence.
2A-9
Timings
2A.7.2.3 Host Reset Configuration
Host reset configuration allows host program reset configuration word Host port after PORESET deasserted, described MSC8101 Reference Manual. MSC8101 samples signals described Table 2A-12 rising edge PORESET when signal deasserted. sampled high, host port enabled. this mode RSTCONF must pulled device extends internal PORESET until host programs reset configuration word register. host must write four 8-bit half-words Host Reset Configuration Register address program reset configuration word, which bits wide. more information, MSC8101 Reference Manual. reset configuration word programmed before internal MSC8101 locked. host must program after rising edge PORESET input. this mode, host must have clock that does depend MSC8101 clock. After locked, HRESET remains asserted another clocks then released. SRESET released three clocks later (see Figure 2A-3).
PORESET Input PORESET Internal RSTCONF, HRM, Bpins sampled
asserted CLKIN.
time HRESET Output (I/O) Host programs Reset Configuration Word
MODCK[1-3] pins sampled. MODCK_H bits ready PLL. locked locked
SRESET Output (I/O)
locks after SPLLMFCLKs locks 3073 clocks after locked. When disabled, reset period shortened lock time.
HRESET/SRESET extended 512/515 clocks, respectively, from lock
Figure 2A-3. Host Reset Configuration Timing
2A.7.2.4 Hardware Reset Configuration
Hardware reset configuration enabled sampled rising edge PORESET. value driven RSTCONF while PORESET changes from assertion deassertion determines MSC8101 configuration. RSTCONF deasserted (driven high) while PORESET changes, MSC8101 acts configuration slave. RSTCONF asserted (driven low) while PORESET changes, MSC8101 acts configuration master. Section 2A.7.2.4, Hardware Reset Configuration, explains configuration sequence terms "configuration master" "configuration slave." Directly after deassertion PORESET choice reset operation mode configuration master configuration slave, MSC8101 starts configuration process. MSC8101 asserts HRESET SRESET throughout power-on reset process, including configuration. Configuration takes 1024 CLOCKIN cycles, after which MODCK[1-3] sampled determine MSC8101's working mode.
2A-10
Timings
Next, MSC8101 halts until SPLL locks. SPLL locks according MODCK[1-3], which sampled, MODCK_H taken from Reset Configuration Word. SPLL locking time reference clocks, which clock output SPLL Pre-divider. After SPLL locked, clocks MSC8101 enabled. DLLDIS reset configuration word reset, starts locking process after SPLL locked. During locking, HRESET SRESET asserted. HRESET remains asserted another clocks then released. SRESET released three clocks later. DLLDIS reset configuration word set, bypassed there locking process, thus saving locking time. Figure 2A-4 shows power-on reset flow.
PORESET Input PORESET Internal
asserted CLKIN.
RSTCONF sampled master/slave determination
MODCK[1-3] sampled. MODCK_H bits ready PLL. HRESET Output (I/O) locked SRESET Output (I/O) reset configuration mode: reset configuration sequence occurs this period. locked
HRESET/SRESET extended 512/515 clocks, respectively, from Lock time.
locks after SPLLMFCLKs. locks 3073 clocks after locked. When disabled, reset period shortened 3073 clocks.
Figure 2A-4. Hardware Reset Configuration Timing
2A.7.3 System Access Timing
2A.7.3.1 Core Data Transfers
Generally, MSC8101 system output signals driven from rising edge reference clock (REFCLK), which DLLIN disabled, CLKOUT. Memory controller signals, however, trigger four points within REFCLK cycle. Each cycle divided four internal ticks: always occurs rising edge REFCLK (and falling edge), spacing depends clock ratio selected, Table 2A-14 shows. Table 2A-14. Tick Spacing Memory Controller Signals
Tick Spacing Occurs Rising Edge REFCLK) Clock Ratio
1:2, 1:3, 1:4, 1:5, 1:2.5 1:3.5 REFCLK 3/10 REFCLK 4/14 REFCLK
REFCLK REFCLK REFCLK
REFCLK 8/10 REFCLK 11/14 REFCLK
2A-11
Timings
Figure 2A-5 graphical representation Table 2A-14.
REFCLK REFCLK REFCLK
1:2, 1:3, 1:4, 1:5,
1:2.5
1:3.5
Figure 2A-5. Internal Tick Spacing Memory Controller Signals Note: machine GPCM machine outputs change internal tick determined memory controller programming; specifications relative internal tick. SDRAM machine outputs change only REFCLK rising edge. Table 2A-15. Characteristics Inputs
Characteristic1
Hold time signals after level REFCLK rising edge AACK/ARTRY/TA/TEA/DBG/BG/BR setup time before level REFCLK rising edge Data setup time before level REFCLK rising edge Data setup time parity modes before level REFCLK rising edge setup time before level REFCLK rising edge Address setup time before level REFCLK rising edge TBST setup time before level REFCLK rising edge PSDVAL setup time before level REFCLK rising edge Setup time before level REFCLK rising edge other signals
Value
Units
Notes:
Input specifications measured from level signal level REFCLK rising edge. EXDD only. EXDD maximum speed MHz. TSIZ multicycle.
Table 2A-16. Characteristics Outputs
Characteristic
PSDVAL/
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