Centaur-P AN983 PCI/mini-PCI 10/100 Fast Ethernet Controller With
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Centaur-P
AN983 PCI/mini-PCI 10/100 Fast Ethernet Controller With Integrated
Specifications subject changed without notice
Revision
February 2000
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Centaur-P Specificatio Revision History Revision Revision Date August 1999 Descriptio Change AN985P AN983 CR12 [1:31](page Ratio (page CSR6[22] reserved (page change csr7[12,10] reserved (page csr17[29] added page csr17[15] description changed (page csr16[29] added (page csr15[19:16] removed (page explanation modified (page explanation chap 12.5 Centaur note page cr48 <24:22> description/value changed (page21) csr18<7> added (page AC/AD e2prom timing updated(page note modified (page CSR18<24> NEC_pmes_sticky added (page CSR18<25> Use_pci_pad_in_cardmode added (page CSR18<18> mode added (page
Oct. 1999
Dec. 1999 Feb. 2000
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Centaur-P Specificatio
General Descriptions Centaur-P (AN983A AN983A mini-PCI) high
performance Fast Ethernet controller with integrated physical layer interface 10BASE-T 100BASE-TX application. Centaur-P designed with advanced CMOS technology provide glueles 32-bit master interface PCI, boot interface, CSMA/CD protocol Fast Ethernet, well physical media interface 100BASE-TX IEEE802.3u 10BASE-T IEEE802.3. auto-negotiation function also supported speed duplex detection. Centaur-P programmed MAC-only controller. this mode, provides standard interface link external PHY. With this mode, connected HomePNA support HomePNA networking solution. Centaur-P provides both half-duplex full-duplex operation, well support full -duplex flow control. provides long FIFO buffers transmission receiving, early interrupt mechanism enhance performance. Centaur-P also supports ACPI compliant power management function Magic Packet wake-up event.
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Centaur-P Specificatio
System block diagram
Serial Serial EEPROM Serial EEPROM EEPROM Interface Interface Interface
Boot Boot Boot Transformer Transformer
25MHz 25MHz 25MHz Crystal Crystal Crystal LEDs LEDs
RJ45 RJ45 RJ45 10/100 10/100 10/100
Fig.1 System Diagram CENTAUR-P
Features Industry standard IEEE802.3u 100BAS IEEE802.3 10BASE-T compliant Support IEEE802.3x flow control IEEE802.3u Auto-Negotiation support 10BASE-T 100BASE-TX Specification compliant ACPI power management Ver.1.1 compliant Support PC99 wake
FIFO Provides independen long FIFOs with bytes each transmission
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Centaur-P Specificatio
receiving Pre-fetch transmit packets minimize inter frame gap(IFG) 0.96us Retransmits collided packet without reload from host memory within bytes Automatically retransmits FIFO under-run packet with maximum drain threshold until times retry failure that will influence registers transmit threshold next packet Provides 32-bit master data transfer Supports clock with frequency from 33MH Supports network operation with system clock from 20MHz 33MH Provides performance meter, master latency timer, tuning threshold enhance performance Provides burst transmit packet interrupt transmit/receive early interrupt reduce host utilization Supports memory-read, memory-read-line, memory-read-multiple, memor -write, memory-write-and-invalidate command while being maste Supports little endian byte ordering
EEPROM/Boot Provides write-able Flash EPROM boot with size 128kB Provides access boot byte, word, double word Re-writes Flash boot through port programming register Provides serial interface read/write 93C66 EEPROM Automatically loads device vendor subsystem subsystem vendor Maximum-Latency Minimum-Grand from byte contents 93C66 after reset de-asserted environment
MAC/Physical Integrates whole Physical layer functions 100BAS 10BASE-T Provides Full -duplex operation both 100Mbps 10Mbps modes Provides Auto-negotiation(NWAY) function full/half duplex operation both Mbps Provides transmit wave-shaper, receive filters, adaptive equalizer Provides MLT-3 transceiver with restoration Base-line wander compensation Provides Transceiver(TXCVR) loop-back modes diagnostic
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Centaur-P Specificatio
Builds Stream Cipher Scrambler/ De-scrambler 4B/5B encoder/decoder Supports external transmit transformer with turn ratio Supports external receive transformer with turn ratio
Displa LEDs displays scheme provided 100Mbps(on) Speed 10(off) Link(keeps when link Activity(will blinking with 10Hz receiving transmitting collision) FD(keeps when Full duplex mode) Collision(will blinking with 20Hz when colliding LEDs displayed scheme provided 100Mbps Link (keep when link 100Mpbs) 10Mbps Link (keep when link 10Mpbs) Activity(will blinking with 10Hz when receiving transmitting collision) FD(keeps when Full duplex mode) Collision(will blinking with 20Hz when colliding
Miscellaneous Provides -pin QFP/LQFP packages PCI/mini-PCI interfaces 3.3V power supply with 5V/3.3V tolerance
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Centaur-P Specificatio
Block diagram
iste
ntro
ntro
LEDs
ntro
ntro
ntro
sica
ator
Fig.2 Block Diagram Centaur-P
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Centaur-P Specificatio Assignment Diagram
BrWE#/Rxclk
BrD3/MrxD3
BrD2/MrxD2
BrD1/MrxD1
BrD0/MrxD0
BrOE#/Txclk
10/Mtxen
BrD4/Mrxdv
9/MtxD3
8/MtxD2
7/MtxD1
6/MtxD0
5/Mtxerr
16/LED
11/Mdc
BrD5/EDO
BrD7/ECK
BrD6/EDI
BrCS#
Vdd-3
EECS
Vss-3
TST3 RXIN RXIP GNDR TST0 TST1 TST2 GNDREEF RIBB XTLN XTLP GNDT TXOP TXON Vdd-IR INTA RST# s-IR pci_clk Vdd-pci gnt# req# pme# s-pci Vdd-pci
rxerr Vdd_5V_3V Vcc_detect Vaux clk-run s-pci Vdd-pci CBEB0 s-pci s-IR Vdd-pci Vdd-IR s-pci CBEB1 Vdd-pci SERR PERR
Centaur-P
(AN983)
FRAME#
TRDY#
Vdd-pci
Vdd-pci
CBEB3
CBEB2
Vdd-IR
DSEL#
Vss-pci
Vss-pci
Vss-pci
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STOP#
IRDY#
IDSEL
Vss-IR
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
Centaur-P Specificatio Description
Name
Type Description
Interface
INTA# interrupt request Centaur-P asserts this signal when interrupt events occur. signal initialize Centaur-P. active reset signal should sustained least 100µs guarantee that CENTAUR-P completed initializing activity. During reset period, output CENTAUR-P will tri-state pins floated. This clock inputs CENTAUR-P relative circuits synchronized timing base with bus. signals recognized rising edge PCI-CLK. order network operating properly, frequency range PCI-CLK limited between 20MHz 33MHz when network operating. Granted. This signal indicates that request CENTAUR-P have been accepted. Request. master device want access right Power Management Event signal open drain, active signal. When WOL-bit into "1", means that CENTAUR-P into Wake mode. this mode, when CENTAUR-P receives Magic Packet frame from network then CENTAUR-P will active this signal too. Wake mode, when -bit (bit CSR18 into means LAN-WAKE signal HP-style signal, otherwise -style signal
RST#
PCI-CLK
GNT#
REQ# PME#
33,34 35,36 38,39 40,41 46,47 49,50 51,53 54,56 70,72 73,75
AD-31,30 AD-29,28 AD-27,26 AD-25,24 AD-23,22 AD-21,20 AD-19,18 AD-17,16 AD-15,14 AD-13,12
Multipl address data
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76,78 79,81 84,85 86,88 89,90 93,94 AD-11,10 AD-9,8 AD-7, AD-5,4 AD-3,2 AD-1,0 C-BEB3 C-BEB2 C-BEB1 C-BEB0 IDSEL Initialization Device Select. This signal asserted when host issues configuration cycles CENTAUR-P. Begin duration access, driven master device Master device ready data transaction Slave device ready data transaction Device select, target driving indicate address decode Target device request master device stop current transaction Data parity error detected, driven agent receiving command byte enable
FRAME# IRDY TRDY#
DEVSEL# STOP# PERR SERR
Address parity error Parity, even parity (AD[31:0] C/BE[3:0]), master ives address write data phase, target drives read data phase
clk-run
Clock system. normal operation situation, Host should assert this signal indicate CENTAUR-P about normal situation. other hand, when Host will deassert this signal when clock going down nonoperating frequency. When CENTAUR-P recognizes deasserte status clk-run, then will assert -run request host maintain normal clock operation. When clk-run function disabled then CENTAUR-P will clik-run tri-state.
BootROM/EEPROM Interface
data Provides 128kB EPROM Flash-ROM application space.
98~101, BrA0 106,108 ~110, 112, 113,
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Centaur-P Specificatio
126, 127, 128, 1~3, 116~ 120, 121~ 123, BrD0~4 BrD5/ED BrD6/EDI BootROM data (0~7) EDO: Data Output serial EEPROM, Inputs data CENTAUR-P
EDI: Data Input serial EEPROM, CENTAUR-P outputs data EEPROM ECK: Clock input serial EEPROM, CENTAUR-P outputs clock signal BrD7/ECK EEPROM EECS BrCS# BrOE# BrWE# Chip Select serial EEPROM BootROM Chip Selec BootROM Read Enable flash application BootROM Write Enable flash application.
Interface (Program Centaur-P MAC-only mode, FCh[2:0] 100b)
Mtxen Management Data Clock Transmit Enable Transmit Data
109,110 MtxD0~3 112,113 Mtxerr Mdio Mrxdv Mcrs MrxD0~3
Transmit Error Management Data Receive Data Valid Carrier Sense Transmit Data
Mcol Mrxerr Rxclk Txclk
Collision Receive Error Receive Clock Transmit Clock
Physical Interface
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Centaur-P Specificatio
XTLP, XTLN RXIN, RXIP TXOP, TXON RIBB Crystal nputs. connected 25MHz crystal.
differential receive inputs 100BASE-TX 10BASE-T, these pins directly input from Magnetic. differential Transmit outputs 100BASE-TX 10BASE-T, these pins directly output Magnetic. Reference Bias Resistor. tied external 10.0K (1%) resistor which should connected analog ground other end. Test
20,21
9,10,11, TST0, TST1 12,13 TST2, TST3
display Miscellaneous
Led-Act 4Leds mode: display Activity status. This will driven with blinking frequency when either effective receiving transmitting detected. (3Led mode): display link activity status This will driven continually when good Link test detected. This will driven with blinking frequency when either effective receiving transmitting detected. 4Leds mode: display speed. This will driven continually when network operating speed detected. (3Leds mode): display Full Duplex Collision status. This will driven continually when full duplex configuration detected. This will driven with blinking frequency when collision status detected half duplex configuration.
(Led-lk/act)
Led-10Lnk (Led-fd/col)
Led-100Lnk (Led-speed)
4Leds mode: display 100Mb/s speed. This will driven continually when 100Mb/s network operating speed detected. (3Leds mode): display 100M speed. This
will driven continually when 100M network operating speed detected.
Led-Fd /Col 4Leds mode: display Full Duplex Collision tatus. This will driven continually when full duplex configuration detected. This will driven with blinking frequency when collision status detected half duplex configuration. (3Leds mode): None
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Centaur-P Specificatio
Vaux When this asserted, indicates auxiliary power source supported
Vcc-detect When this asserted, indicates power source supported.
Vdd_5V_3
I(A) &'#&
when 5Vaux support from 3-way switch. (D3cold mode
Digital Power
Vss-pci, Vss-IR, Vss-3 Vdd-pci Vdd-IR, Vdd-3 Connect 3.3V
Analog Power Pins
VAAR, VAAREF, VAAT 3.3V
4,16,22
8,14,1
GNDR, GNDREF,GNDT
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Centaur-P Specificatio
Registers Descriptors Description There three kinds registers designed CENTAUR-P. They CENTAUR-P configuration registers, control/status registers, Transceiver control/status registers. CENTAUR-P configuration registers used initialize configure CENTAUR-P identifying querying CENTAUR-P. control/status registers used communicate between host CENTAUR-P. Host initialize, control, read status CENTAUR-P through mapped memory address space. Regarding registers transceiver portion CENTAUR-P, there registers with 16bits supported CENTAUR-P. includes basic registers which defined according clause "Reconciliation -layer Media Independent Interface" clause "Physical Layer link signaling Mb/s Mb/s Auto -Negotiatio twisted pair" IEEE802.3u standard. Besides, there special registers advance chip controlling status reading CENTAUR-P also provides receive transmit descriptors packet buffering management. These descriptors described following section
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Centaur-P Specificatio
7.1. CENTAUR-P configuration registers With configuration registers software driver initialize configure AN983. contents configuration registers default value when there hardware reset occurs. other hand, there effect their value when software reset occurs. access these configuration registers AN983 provides byte, word double word data access length. 7.1.1. AN983 configuration registers list Offset
Index
Name IOBA CINT PMR0 PMR1
Descriptions Loaded device vendor Configuration Status Comman Class Code revision number Latency Timer Base Address Memory Base Address Card Information Structure(for Card bus) Subsystem vendor Boot Base Address (ROM size 256KB Capability Pointer Configuration Interrupt driver space special purpos Signature AN983 Power Management Register Power Management Register
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Centaur-P Specificatio 7.1.2. AN983 configuration registers table
offset 18h~ Reserved Max_Lat* Reserved Min_Gnt*
ROM-im*
-Device Status
-Vendor Command
Base Class Code
Subclass
-Latency timer
Revision
Step
cache line size
Base address Base memory address Reserved Address space offset Subsystem
Add-indi*
Subsystem vendor Boot base address
Reserved Reserved Interrupt
Driver Space
Cap_Ptr
Interrupt line Reserved
Signature AN98 Next_Item_Ptr PMCSR Cap_ID
Note:
automatically recalled EEPROM when reset deserted CIS(28h) read-only register DS(40h), bit1 read/write able register SIG(80h) hard wired register, read only.
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Centaur-P Specificatio 7.1.3. AN983 configuration registers descriptions
CR0(offset 00h), Loaded Identification number Device Vendor Name Descriptions Loaded Device device number loaded from serial EEPROM. Loaded Vendor vendor number loaded from seria EEPROM.
Default Type From EEPROM From EEPROM
31~16 LDID
15~0
LVID
From EEPROM: Loaded from EEPROM CR1(offset 04h), Configuration command status Name Descriptions Status Parity Error means that AN983 detected parity error. This will this condition, even parity error response(bit CR1) disabled. Status System Error. means that AN983 asserted system error pin. Status Master Abort. means that AN983 received master abort terminated master transaction. Status Target Abort. means that AN983 received target abort terminated master transaction. -SDST reserved. Status Device Select Timing. timing assertion device select. means medium assertion DEVSEL SDPR Status Data Parity Report. when three conditions met: SFBB AN983 asserted parity error PERR# detected parity error asserted other device. AN983 operating master. AN983's parity error response bit(bit CR1) enabled. Default Type
Status Fast Back-to-Back Always since AN983 ability accept fast back back transactions.
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Centaur-P Specificatio
22~21 reserved. Capabilities. This indicates that whether AN983 provides list extended capabilities, such power management. AN983 provides management function AN983 doesn't provides Capabilities. -CSE reserved. Command System Error Respons enable system error response. AN983 will assert SERR When find parity error address phase. -CPE reserved. Command Parity Error Respons disable parity error response. AN983 will ignore detected parity error keep operating. Default value enable parity error response. AN983 will assert system error(bit CSR5) when parity error detected. -CMO reserved. Command Master Operation Ability disable master ability. enable master ability. Default value normal operation. CMSA Command Memory Space Access disable memory space access ability. enable memory space access ability. CIOSA Command Space Access enable space access ability. disable space access ability. R/W: Read Write able. Read able only. CR2(offset 08h), Class Code Revision Number Name Descriptions Base Class Code. means AN983 network controller. Subclass Code. means AN983 Fast Ethernet Controller. reserved. Revision Number, identifies revision number AN983. Step Number, identifies AN983 steps within current revision. Same CSR18
Default Type
31~24 23~16
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Read Only CR3(offset 0ch), Latency Time Name Descriptions reserved. Latency Timer. This value specifies latency timer AN983 units clock. Once AN983 asserts FRAME#, latency timer starts count. latency timer expires AN983 still asserted FRAME#, then AN983 will terminate data transaction soon GNT# removed. Cache Line Size. This value specifies system cache line size units 32-bit double words(DW). AN983 supports cache line size. This value used AN983 driver program cache ignment bits(bit CSR0). cache alignment bits used cache oriented commands, memory-read-line, memory-read-multiple, memory-write-and-invalidate.
Default Type
31~16 -15~
CR4(offset 10h), IOBA Base Address Name IOBA -IOSI Descriptions Base Address. This value indicate base address control status register(CSR0~28 reserved. Space Indicator. means that configuration registers into space. CR5(offset 14h), Memory Base Address Name Descriptions Memory Base Address. This value indicate base address control status register(CSR0~28) reserved. Memory Space Indicator. means that configuration registers into space. CR11(offset 2ch), Subsystem Name Descriptions Subsystem This value loaded from EEPROM after power hardware reset. Default Type From EEPROM Default Type Default Type
-IOSI
31~16
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Centaur-P Specificatio
SVID Subsystem Vendor This value loaded from EEPROM after power hardware reset From EEPROM
CR12(offset 30h), BRBA Boot Base Address. This register should initialized before accessing boot space. (write 32'hffffffff return 32'h fffe0001) Name Descriptions Boot Base Address. This value indicates address mapping boot field. Besides, also defines size. value 17~10 AN98 supports 256KB boot ROM. Reserved Boot Enable. AN983 really enables boot access only both memory space access bit(bit CR1) this enable Boot ROM. (Combines with CR1) CR13(offset 34h), Capabilities Pointer. 31~8 Name Descriptions Reserved Capabilities Pointer. Default Type Default Type b31~18 b17~10
31~17 BRBA
-BRE
CR15(offset 3ch), Configuration Interrupt Name Descriptions Max_Lat register This value indicates "how often" AN983 needs access units 250ns. This value loaded from serial EEPROM after power hardware reset. Min_Gnt register This value indicates long AN983 needs retain ownership whenever initiate transaction, units 250ns. This value loaded from serial EEPROM after power hardware reset. Interrupt Pin. This value indicates which four interrupt request pins that AN983 connected. Always 01h: means AN983 connects INTA# Interrupt Line. This value indicates which system interrupt request lines INTA# AN983 routed BIOS will fill this field when initializes configures system. AN983 driver this value determin priority vector information. Default Type From EEPROM
31~24
23~16
From EEPROM
CR16(offset 40h), Driver Space special purpose. Name Descriptions Default Type
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31~16 -15~8 reserved Driver Space special purpose. Since this area won't cleared software reset. AN983 driver this area special purpose. Reserved
CR32(offset 80h), Signature AN983 31~16 15~0 Name Descriptions Device device number AN983 Vendor vendor number Technology Default Type 0985h 1317h
CR48(offset c0h), PMR0, Power Management Register0. Name Descriptions PME_Support. AN983 will assert PME# signal while power state. AN983 supports Wake-up from above states. D2_Support. AN983 supports Power Management State. D1_Support. AN983 supports Power Management State. Current. Thest three bits report maximum Vaux current requirements CENTAUR-P. PMR0 `1', default value 0101b, means CENTAUR-P need support remote wake-up D3cold power state. Device Specific Initialization indicates whethe special initialization this function required before generic class device driver able indicates that function does require devic specific initialization sequence following transition un-initialized state. -PMEC Reserved. Clock. When indicates that AN983 relies presence clock PME# operation. While indicates clock required AN983 generate PME#. Version. value 010b indicates that AN983 complies with Revision Power Management Interface Specification. Next Item Pointer. This value always indicates that there additional items Capabilities List. 010b Default Type 11111b
31~27 PMES
24~22 AUXC
18~16
010b
15~8
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Centaur-P Specificatio
CAPID Capability Identifier. This always 01h, indicates link list item being Power Management Registers.
CR49(offset c4h), PMR1, Power Management Register Name Descriptions reserved PME_Status, This when AN983 would normally assert PME# signal wake-up event, this independent state bit. Writing this will clear cause AN983 stop asserting PME# enabled). Writing effect. 14,13 DSCAL Data_Scale, indicates scaling factor used when interpreting value Data register. This field required function that implements Data register. Otherwise, it's optional AN983 doesn't support Data register Data_Scale. 12~9 DSEL Data_Select, This four field used select which data reported through Data register Data_Scale field. This field required function that implements Data register. AN983 doesn't support Data_select. PME_En PME_En, enables AN983 assert PME#. When disables PME# assertion. Magic packet default enable When Csr18<18> csr18<19> than magic packet wake event will default enabled (csr13<9> set) doesn't matter PME_En not. -PWRS Reserved. PowerState, This field used both determine current power state AN983 AN983 into power definition this field given below. D3hot This field auto cleared when power resumed 000000 0000b R/W* Default Type
31~16 PMES
R/W*: Read Write clear
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Centaur-P Specificatio 7.2. Control/Status registers 7.2.1. Control/Status registers list
offset from base address
Index CSR0 CSR1 CSR2 CSR3 CSR4 CSR5 CSR6 CSR7 CSR8 CSR9 CSR10 CSR11 CSR12 CSR13 CSR14 CSR15 CSR16 CSR17 CSR18 CSR19 CSR20 CSR21 CSR22 CSR23 CSR24 CSR25 CSR26 CSR27 CSR28
Name -TMR -WTMR ACSR5 ACSR7 PCIC PMCSR WTDP WRDP TXBR FROM PAR0 PAR1 MAR0 MAR1
Descriptions access register Transmit demand register Receive demand register Receive descriptor base address Transmit descriptor base address Status register Network access register Interrupt enable register Lost packet counter Serial port register Reserved Timer Reserved Reserved Reserved Watchdog time Status register Interrupt enable register Command register performance counter Power Management Command Status Current transmit descriptor point Current receive descriptor point Transmit burst counter/time-out register Flash(boot) port Physical address register Physical address register Multicast address hash table register Multicast address hash table register
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Centaur-P Specificatio Operation Mode register
7.2.2. Control/Status register description
CSR0(offset 00h), Access Register Name Descriptions Reserved Memory Write Invalidate Enable. enable AN983 generate memory write invalidate command. AN983 will generate this command while writing full ache lines. disable AN983 generate memory write invalidat command memory write commands instead. Memory Read Line Enable. enable AN983 generate memory read line command while read access instruction reach cache line boundary. read access instruction doesn't reach cache boundary then AN983 uses memory read command instead. Reserved Memory Read Multiple Enable. enable AN983 generate memory read multiple command while reading full cache line. memory cache aligned, AN983 uses memory read command instead. Reserved Transmit auto-polling transmit suspended state, disable auto-polling (default) polling own-bit very polling own-bit every polling own-bit every 1600 -CAL Reserved Cache alignment, address boundary data burst, after reset reserved (default) boundary alignment boundary alignment boundary alignment Programmable Burst Length. This value defines maximum number transferred transaction. value: (unlimited), 16(default), Little Endian selection. little endian (e.g. INTEL) ADMtek Incorporated. No.9, Industry Rd., SBIP, HsinChu Tel: 886-3-5788879 Fax: -578887 2000/3/23 Rev: 010000 R/W* R/W* R/W* R/W* R/W* Default Type
31~25 MWIE
MRLE
R/W*
-MRME
20~19 -18,17
R/W*
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Centaur-P Specificatio
endian (only data buffer) Descriptor Skip Length. Defines between descriptions units arbitration receive higher priorit transmit higher priorit R/W* R/W*
Software reset reset internal hardware, except configuration registers. This signal will cleared AN983 itself after completed reset process. R/W* Before writing transmit receive operations should stopped. CSR1(offset 08h), Transmit demand register Name TPDM Descriptions
R/W*
Default Type ffffffffh R/W*
Transmit poll demand When written value suspended state, trigger read-tx-descriptor process check own-bit, own-bit then start transmit process R/W* Before writing transmit process should suspended state. CSR2(offset 10h), Receive demand register Name Descriptions Receive poll demand
Default Type ffffffffh R/W*
RPDM
When written value suspended state, trigger read-rx-descriptor process check own-bit, own-bit then start move data buffer from FIFO R/W* Before writing receive process should suspended state. CSR3(offset 18h), Receive descriptor base address Name Descriptions Start address receive descriptor Default Type xxxxxxx R/W*
RBND must boundary R/W* Before writing receive process should topped. CSR4(offset 20h), Transmit descriptor base address Name Descriptions Start address transmit descriptor
Default Type xxxxxx R/W*
TBND must boundary R/W* Before writing transmit process should stopped. CSR5(offset 28h), Status register Name Descriptions reserved Error Type. This field valid only when CSR5(fatal error) set. There interrupt generat this field.
Default Type
-25~
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Centaur-P Specificatio
000: parity error, 011, 1xx: reserve 001: master abort, 010: target abort
Transmit State. Report current transmission state only, interrupt will generated. 000: stop 001: read descriptor 010: transmitting 011: FIFO fill, read data from memory into FIFO 100: reserved 101: reserved 110: suspended, unavailable transmit descriptor FIFO overflow 111: write descriptor
19~17
Receive State. Report current receive state only, interru will generated. 000: stop 001: read descriptor 010: check this packet pre-fetch next descriptor 011: wait receiving data 100: suspended 101: write descriptor 110: flush current FIFO 111: FIFO drain, move data from receiving FIFO into memory Normal Interrupt Status Summary. It's below bits CSR5 asserted.(combines with ACSR5) bit0, transmit completed interrupt bit2, transmit descriptor unavailabl bit6, receive descriptor interrupt Abnormal Interrupt Status Summary. It's below bits CSR5 asserted.(combines with ACSR5) bit1, transmit process stopped bit3, transmit jabber timer time-out bit5, transmit unde -flow bit7, receive descriptor unavailable bit8, receive processor stopped bit9, receive watchdog time-out bit11, general purpose timer time-out bit13, fatal error
NISS
RO/LH*
AISS
RO/LH*
-FBE
reserved Fatal Error. while parity error,master abort, target abort occurred(see bits 25~23 CSR5). AN983 will disable RO/LH*
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access. recover parity error setting software reset. -GPTT -RWT reserved General Purpose Timer -out, base CSR11 timer register reserved Receive Watchdog Time-out, based CSR15 watchdog timer register Receive Process Stopped, receive state stop Receive Descriptor Unavailable while next receive descriptor can't applied AN983. receive process suspended this situation. restart receive process, ownership next receive descriptor should AN983 receiv poll demand command should issued(or recognized frame received, receive poll demand issued). Receive Completed Interrupt while frame reception completed Transmit Unde -Flow while transmit FIFO under-flow condition happened during transmitting. transmit process enter suspended state report unde -flow errror bit1 TDES0. Reserved Transmit Jabber Timer Time-out while transmit jabber timer expired. transmit processor will enter stop state transmit jabber time-out flag TDES0 will asserted Transmit Descriptor Unavailable while next transmit descriptor can't applied AN983. transmission process suspended this situation. restart transmission process, ownership next transmit descriptor should AN983 transmit automatic polling enabled then transmit poll demand command should issued. Transmit Process Stopped. while transmit state stop
RO/LH*
RO/LH* RO/LH* RO/LH*
RO/LH* RO/LH*
-TJT
RO/LH*
RO/LH*
RO/LH* RO/LH*
Transmit Completed Interrupt. means frame transmission completed while TDES1 asserted first transmit descriptor frame. High Latching cleared writing CSR6(offset 30h), Network access register Name Descriptions
Default Type
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31~22 Reserved Store forward transmit disable enable, ignore transmit threshold setting Reserved Disable enable function 10BAS operation. AN983 provides test function 10BASE half duplex operation. disable function. Reserved transmit threshold control 128-byte (100Mbps), 256-byte (100Mbps), 512-byte (100Mbps), -byte (100Mbps), Stop transmit stop (default) start Force collision mode
disable
R/W*
-SQE
R/W*
18~16 -15~14
-byte (10Mbps) -byte (10Mbps) 128-byte (10Mbps) 160-byte (10Mbps)
R/W*
R/W**
generate collision when transmit (for test loop -back mode) Operating Mode norma loop-back 10,11: reserved Reserved Multicast receive multicast packets Promiscuous Mode receive good packet. receive only right destination address packets Stop Back-off Counte back-off counter stop when carrier active, resume when carrier drop. back-off counter effected carrier Reserved Pass packe receives packets, pass address filter, including runt packets, error, truncated packets. receiving packets, CSR6 should R/W*** R/W** R/W*** R/W*** R/W**
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filters packets Reserved Start/Stop Receive receive processor will enter stop state after current reception frame completed. This value effective when receive processor running suspending state. Notice: "Stop Receive" tate, PAUSE packet Remote Wake packet won't effected received corresponding function enabled. receive processor will enter running state.
-Reserved only write when transmit processor stopped. only write when transmit receive processor both stopped. W*** only write when receive processor stopped.
CSR7(offset 38h), Interrupt Enable Register Name -FBEIE Descriptions (Refer CSR5) Reserved Normal Interrupt Enable enable normal interrupt bits( bit16 CSR5) Abnormal Interrupt Enable enable abnormal interrupt bits(see CSR5) Reserved Fatal Error Interrupt Enabl combine this CSR7 enable fatal error interrupt General Purpose Timer Interrupt Enabl combine this CSR7 enable general purpose timer expired interrupt. Receive Watchdog Time-out Interrupt Enable combine this CSR7 enable receiv watchdog time-out interrupt. Receive Stopped Interrupt Enable combine this CSR7 enable receiv stopped interrupt. Receive Descriptor Unavailable Interrupt Enable combine this CSR7 enable receiv descriptor unavailable interrupt. Receive Completed Interrupt Enable combine this CSR7 enable receive completed interrupt. Transmit Unde -flow Interrupt Enable Default Type 31~17
GPTIE
RWTIE
RSIE
RUIE
RCIE
TUIE
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combine this CSR7 enable transmit under-flow interrupt. -TJTTIE Reserved Transmit Jabber Timer Time-out Interrupt Enable combine this CSR7 enable transmit jabber timer -out interrupt. Transmit Descriptor Unavailable Interrupt Enable combine this CSR7 enable transmit descriptor unavailable interrupt. TPSIE Transmit Processor Stopped Interrupt Enable combine this CSR7 enable transmit processor stopped interrupt. Transmit Completed Interrupt Enabl combine this CSR7 enable transmit completed interrupt.
TDUIE
TCIE
CSR8(offset 40h), Lost packet counter 15~0 Name LPCO Descriptions Reserved Lost Packet Counter Overflow while lost packet counter overflowed. Cleared after read Lost Packet Counter Increment counter while packet discarded since there host receive descriptors available. Cleared after read RO/L RO/L Default Type 31~17
CSR9(offset 48h), Serial port registe Name Descriptions Reserved Management Data Input Specified read data from external Management Control Write operation external Read operation from external Management Data Output Specified Write Data external Management Clock Management Clock output reference clock external -SRC Reserved Serial EEPROM Read Control together with CSR9 bit11 enable read operation from EEPROM Serial PROM Write Control Default Type 31~20
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together with CSR9 bit11 enable write operation EEPROM -SRS Reserved Serial EEPROM Select together with CSR9 bit14 enable EEPROM access Reserved Serial EEPROM data This serially shifts data from EEPROM AN983. Serial EEPROM data This serially shifts data from AN983 EEPROM. SCLK Serial EEPROM clock High/Low this provide clock signal EEPROM. Serial EEPROM chip select selects serial EEPROM chip. CSR11(offset 58h), -General-purpose Timer Name Descriptions Reserved Continuous Operation Mode sets general-purpose timer continuous operating mode. General-purpose Timer Value Sets counter value. This count -down counter with cycle time 204us.
10~4
-SDO
Default Type
31~17
15~0
CSR13(offset 68h), WCSR -Wake-up Control/Status Register Name -CRCT Descriptions Reserved CRC-16 Type Initial contents 0000h Initial contents FFFFh 24-18 WP1E WP2E WP3E WP4E WP5E -Wake-up Pattern Matched Enable. Wake-up Pattern Matched Enable. Wake-up Pattern Three Matched Enable. Wake-up Pattern Four Matched Enable. Wake-up Pattern Five Matched Enable. Reserved Default Type
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LinkOFF Link Detect Enable. AN983 will CSR13 after detected that link status from OFF. LinkON Link Detect Enable. AN983 will CSR13 after detected that link status from Reserved Wake-up Frame Received Enable. AN983 will include "Wak Frame Received" event into wake-up events. this set, AN983 will assert PMES PMR1 after AN983 received matched wake-up frame. Magic Packet Received Enable. AN983 will include "Magic Packet Received" event into events. this set, AN983 will assert PMES PMR1 after AN983 received Magic packet. Link Status Changed Enable. AN983 will include "Link Status Changed" event into wake-up events. this set, AN983 will assert PMES PMR1 after AN983 detected link status changed event Reserved Wake-up Frame Received, Indicates AN983 received frame. cleared write upon power-up reset. affected hardware software reset. Magic Packet Received, Indicates AN983 received magic packet. cleared write upon power-up reset. affected hardware software reset. Link Status Changed, Indicates AN983 detected link status change event. cleared write upon power-up reset. affected hardware software reset. R/W1C*, Read Only Write cleared.
15-11
-WFRE
00001
MPRE
LSCE
-WFR
R/W1C*
R/W1C*
R/W1C*
CSR14(offset 70h), WPDR -Wake-up Pattern Data Register patterns filtering information programmed through WPDR register. filtering information follows,
Offset 0000h 0004h
Wake-up pattern mask bits 31:0 Wake-up pattern mask bits 63:32
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0008h 000ch 0010h 0014h 0018h 001ch 0020h 0024h 0028h 002ch 0030h 0034h 0038h 003ch 0040h 0044h 0048h 004ch 0050h 0054h 0058h 005ch 0060h Wake-up pattern mask bits 95:64 Wake-up pattern mask bits 127:96 CRC16 pattern Reserved Wake-up pattern mask bits 31:0 Wake-up pattern mask bits 63:32 Wake-up pattern mask bits 95:64 Wake-up pattern mask bits 127:96 CRC16 pattern Reserved Wake-up pattern mask bits 31:0 Wake-up pattern mask bits 63:32 Wake-up pattern mask bits 95:64 Wake-up pattern mask bits 127:96 CRC16 pattern Reserved Wake-up pattern mask bits 31:0 Wake-up pattern mask bits 63:32 Wake-up pattern mask bits 95:64 Wake-up patt mask bits 127:96 CRC16 pattern Reserved Wake-up pattern mask bits 31:0 Wake-up pattern mask bits 63:32 Wake-up pattern mask bits 95:64 Wake-up pattern mask bits 127:96 CRC16 pattern Reserved
Wake-up pattern offset
Wake-up pattern offset
Wake-up pattern offset
Wake-up pattern offset
Wake-up pattern offset
Offset value from 0-255 (8-bit width). load whole wake-up frame filtering information, consecutive long words write operation CSR14 should done.
CSR15(offset 78h), WTMR Watchdog timer 31~6 Name -RWR Descriptions Reserved Receive Watchdog Release, time releas watchdog timer from last carrier deserted
bit-time
Default Type
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Receive Watchdog Disable receiving packet`s length longer than 2560 bytes, watchdog timer will expired. disable receive watchdog. Reserved Jabber clock transmission after (100Mbps) (10Mbps).
transmission after byte-time.
-JCLK
Non-Jabber jabber expired, -enable transmit function after (100Mbps) 420ms (10Mbps) immediately -enable transmit function after jabber expire Jabber disable disable transmit jabber function
CSR16(offset 80h), ACSR5 Assistant CSR5(Status register Name TEIS Descriptions Transmit Early Interrupt status Transmit early interrupt status when Transmit early interrupt function enabled(set CSR17 transmitted packet moved completed from descriptors TX-FIFO buffer. This cleared written with Receive Early Interrupt Status. Receive early interrupt status when Receive interrupt function enabled(set CSR17 received packet fill first receive descriptor. This cleared written with Status Link status change Transmit Deferred Interrupt Status. Reserved PAUSE Frame Received Interrupt Status indicates PAUSE frame received when PAUSE function enabled. Reserved Added normal interrupt status summary. added normal interrupt happened. Added Abnormal Interrupt Status Summary. added abnormal interrupt happened. RO/LH* RO/LH* RO/LH* RO/LH* Default Type RO/LH*
REIS
RO/LH*
TDIS -PFR
RO/LH* RO/LH*
25~17 14~0 ANISS AAIS
These bits same status register CSR5. access those status bits through either CSR5 CSR16. High Latching cleared writing
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CSR17(offset 84h), ACSR7- Assistant CSR7(Interrupt enable register Name TEIE REIE LCIE TDIE -PFRIE ANISE Descriptions Transmit Early Interrupt Enable Receive Early Interrupt Enable Link Status Change Interrupt Enable Transmit Deferred Interrupt Enabl Reserved PAUSE Frame Received Interrupt Enabl Reserved Added Normal Interrupt Summary Enable adds interrupts ACSR7 normal interrupt summary(bit CSR5). Added Abnormal Interrupt Summary Enable. adds interrupt ACSR7 abnormal interrupt summ ary. These bits same interrupt enable register CSR7. access those interrupt enable bits through either CSR7 CSR16.
Default Type
25~17
AAIE
14~0
CSR18(offset 88h), Command Register, bit31 bit16 automatically recall from EEPRO Name D3CS Descriptions D3cold support, mapped CR48<31> Default Type from EEPROM 30-28 010b AUXCL Current. Thest three bits report maximum Vaux current requirements CENTAUR PMR0 from `1', default value 0101b, means CENTAUR-P need support remote wake-up D3cold power state. EEPROM Reserved Pci_pad effect mode from EEPROM Pmes_stic pmez sticky: While pmez signal asserted wake event, auto de-asserted. software should clear CR49<15> PMES -assert pmez signal. pmez auto de-asserted: While pmez signal asserted wake event, will de-sasserted power automati-cally. 4_3LED this reset, mode selected, LEDs definition 100/10 speed Link/Activit Full Duplex/Collision this set, mode selected, LEDs definitio Link
27-26
from EEPROM
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Link Activity Full Duplex/Collision
Receive FIFO size control 01,00: reserved Clock Run(clk-run pin) disable disables function clock supports PCI. Power Management, enables AN983 whether vate Power Management abilities. When this into AN983 will Cap_Ptr register zero, indicating compliant power management capabilities. value this will mapped NC-bit CR1. Power Management mode, events include "Wake-up Frame Received", "Magic Packe Received" "Link Status Changed" depends CSR13 settings mode this effective when (csr18[19]) Magic Packet wake event default enable Magic Packet wake event default disable Should from EEPROM from EEPROM from EEPROM
from EEPROM from EEPROM
16~8
reserved
D3_APM D3_cold APM_mode_en PC99 certificati doesn't matter status PEM_EN, pmez signal asserted programming this Assert pmez signal de-assert pmez signa Reset Wake-up Pattern Data Register Pointer Normal Reset PAUSE function control disable enable PAUSE function flow control. default value PAUSE decided result Auto-Negotiation. Driver force enable disable after Auto-Negotiation completed. PAUSE function disabled. PAUSE function enabled Receive Threshold Enable FIFO threshold enabled. disable receive FIFO threshold selection this register, receive threshold -byte.
PAUSE
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Drain Receive Threshol bytes bytes store-and -forward reserved SINT ATUR Software interrupt. enable automatically transmit-underrun recovery.
CSR19(offset 8ch) PCIC, performance counter Name Descriptions Default Type
31~16 CLKCNT number clock from read request asserted access completed. This clock number accumulated read command cycles from last CSR19 read current CSR1 read. 15~8 -reserved
DWCNT number double word accessed last master. This double word number accumulated master data transactions from last CSR19 read current CSR19 read.
Read only cleared reading. CSR20(offset 90h) PMCSR, Power Management Command Status.(The same register value mapping CR49-PMR1.) Name Descriptions reserved PME_Status, This when AN983 would normally assert PME# signal wakeup event, this independent state bit. Writing this will clear cause AN983 stop asserting PME#(if enabled). Writing effect. Since AN983 doesn't supports PME# from D3cold, this defaulted 14,13 DSCAL Data_Scale, indicates factor used when interpreting value Data register. This field required function that implements Data register. Otherwise, it's optional AN983 doesn't support Data register Data_Scale. 12~9 DSEL Data_Select, This four field used select which data reported through Data register Data_Scale field. This field required function that implements Data register. 0000b Default Type
31~16 PMES
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AN983 doesn't support Data_select. PME_En PME_En, enables AN983 assert PME#. When disables PME# assertion. This defaults function does support PME# generation from D3cold. -PWRS reserved. PowerState, This field used both determine current power state AN983 AN983 into power state. definition this field given below. D3hot software attempts write unsupported, optional state this field, write operation must complete normally bus, however data discarded state change occurs. CSR21(offset 94h) WTDP, current working transmit descriptor pointer 31~0 Name WTDP Descriptions current working transmit descriptor pointer driver's double checking other special purpose. 000000
Default Type XXXX
CSR22(offset 98h) WRDP, current working receive descriptor pointer 31~0 Name WRDP Descriptions current working receive descriptor pointer driver's double checking other special purpose. Default Type XXXX
CSR23(offset 9ch) TXBR, transmit burst count time-out Name Descriptions reserved Transmit Burst Count After this number consecutive successful transmit, transmi completed interrupt will generated. Continuously this function reset. Transmit Time-Out (deferred time back-off time). When TDIE(bit28 ACSR7) set, timer decreased unit 2.56us(100M) 25.6us(10M). timer expires before another packet transmit begin, then TDIE interrupt will generated Default Type
31~21 -20~16 TBCNT
11~0
CSR24(offset a0h) FROM, Flash ROM(also boot ROM) port ADMtek Incorporated. No.9, Industry Rd., SBIP, HsinChu Tel: 886-3-5788879 Fax: -578887 2000/3/23 Rev:
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Name Bra16_ Descriptions This only effective while mode selected (bit CSR18 set) When mode selected, this set, then defined brA16, else defined fd/col. 30~28 25~8 ADDR DATA reserved read enable, clear read data ready DATA, bit7-0 FROM. Write enable, cleared write completed Flash address Read/Write data flash
Default Type
CSR25(offset a4h) PAR0, physical address register automatically recall from EEPROM Name Descriptions physical address byte physical address byte physical address byte physical address byte Default Type From EEPROM From EEPROM From EEPROM From EEPROM
31~24 PAB3 23~16 PAB2 15~8 PAB1 PAB0
CSR26(offset a8h) PAR1, physical address register automatically recall from EEPROM Name Descriptions reserved reserved physical address byte physical address byte From EEPROM From EEPROM Default Type
31~24 -23~16 -15~8 PAB5 PAB4
example, physical address -00-e8-11-22-33 PAR0= PAR1= PAR0 PAR1 readable, written only receive state opped(CSR5 bit1 -17=000). CSR27(offset ach) MAR0, multicast address register Name Descriptions Default Type
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31~24 MAB3 23~16 MAB2 15~8 MAB1 MAB0 multicast address byte (hash table 31:24) multicast address byte (hash table 23:16) multicast address byte (hash table 15:8) multicast address byte (hash table 7:0)
CSR28(offset b0h) MAR1, multicast address register Name Descriptions multicast address byte (hash table 63:56) multicast address byte (hash table 55:48) multicast address byte (hash table 47:40) multicast address byte (hash table 39:32) Default Type
31~24 MAB7 23~16 MAB6 15~8 MAB5 MAB4
MAR0 MAR1 readable, written only receive state stopped(CSR5 bit1 -17=000). Operation Mode Register (Memory base offset 0FCh) Name SPEE Descriptions Network Speed Status 100M Full/Half Duplex Status Full duplex Half duplex Network Link Status Link Link Default Type
LINK
28~27 Reserved EERLOD Write this will cause AN983 reload data from EEPROM. After reload completed, this will cleared automatically. Reserved OpMode These three bits used configure AN983's operation mode: 111b: Single Chip mode (Normal operation) this mode, AN983 configured single chip provide Ethernet controller. 100b: MAC-only mode AN983 configured only controller, provide standard interface link external PHY. interface pins multiplexed with BootROM interface. 111b
25~3
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Others: diagnostic purpose.
7.3. Transceiver(XCVR) Registers accessed csr9 MDI/MMC/MDO/MDC) 7.3.1. Transceiver registers Register 8-15 25-31 Control Register Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiatio Link Partner Ability Register Auto-Negotiation Expansion Register Next Page Advertisement Registe Reserved specific Register Interrupt Control/Status Register Diagnostic Register Power Management Loopback Register Loopback Power management Register Mode Control Registe Reserved Lock Register Receive Error Counter Register Reserved Descriptio Default 1000 7849 0022 5513 01E1 0001 0004 2001 XXXX 0540 0000 0000 0020 XXFX 0304 XXXX 0000 0000 XXXX
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Centaur-P Specificatio 7.3.2. Transceiver registers Descriptions
Legend: Type Description Readable writable Self Cleari Latch until clear Type Description Read Only Cleared read operation Latch high until clear
Register Control Register
Reg.bit 0.15
Name Reset
Description reset. This -clearing. Enable loopback mode. This will loopback RXD, thus will ignore activity cable media. Normal operation. 100Mbps, 10Mbps. This will ignored Auto Negotiation enabled (0.12=1). Enable auto-negotiate process (overrides 0.13 0.8) Disable -negotiate process.
Mode RW/SC
Default
0.14
Loopbac
0.13
Speed Select
0.12
Auto-Neg. Enable
0.11
Power Down
Power down. CENTAU will shut blocks except MDIO/MDC interface. Normal operation.
0.10
Isolate
Electrically isolate from MII. However, still able response MDC/MDIO. Normal operation.
Restart Auto-Negot iation
Restart Auto-Negotiation process. Normal operation.
RW/SC
Duplex Mode
Full duplex. Half duplex.
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Reg.bit Name Description Auto-Neg. enabled: This writable will ignored. Collision Test Enable collision test, which issues signal response assertion TX_EN signal disable test. 0.[6:0] Reserved Mode
Default
000000
Register Status Register
Reg.bit 1.15
Name 100Base-T4
Description Permanently tied zero indicates 100BaseT4 capability.
Mode
Default
1.14
100Base-T Full Duplex
100BaseTX with full duplex 100BaseTX full duplex ability.
1.13
100Base-T Half Duplex
100BaseTX with half duplex. half-duplex ability. 10BaseT with full duplex. 10BaseT full duplex ability. 10BaseT with half duplex. 10BaseT half duplex ability.
1.12
10Base-T Full Duplex
1.11
10Base-T Half Duplex
1.[10:6]
Reserved Auto-Negot iate Complete Auto-negotiate process completed. Reg. valid after this set. Auto-negotiate process completed. Remote fault condition detected. remote fault. This will remain until cleared reading register management interface.
00000
Remote Fault
RO/L
Auto-Negot iate Abilit
Able perform Auto-Negotiation function, value determined ANEGA pin.
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Unable perform Auto-Negotiation function. Link Status Link established. This Latched bit. Therefore, CENTAUR-P link failed, this will cleared remain until register again management interface. link down. Jabber Detect Extende Capabilit Jabber condition detect. Jabber condition detected. Extended register capable. This tied permanently one. RO/L RO/L
Register Identifier Register
Reg.bit 2.[15:0]
Name
Description Composed through 18th bits Organizationally Unique Identifier (OUI), respectively.
Mode
Default 0382(H)
Register Identifier Register
Reg.bit 3.[15:10] 3.[9:4]
Name Mode Number
Description Assigned 19th through 24th bits OUI. manufacturer's model number.
Mode
Default 010010 000001
3.[3:0]
Revision Number
Four manufacturer's revision number.
0000
Register Auto-Negotiation Advertisement Register
Reg.bit 4.15
Name Next Page
Description Next Page enabled. Next Page disabled.
Mode
Default
4.14
Acknowle
This will internally after receiving
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4.13 Remote Fault consecutive consistent bursts. Advertises that this device detected Remote Fault. remote fault detected. 4.[12:10] Reserved 100Base-T 100Base-T Full Duplex future technology CENTAUR-P doesn't support 100BaseT4 function, i.e., this ties zero. 100BaseTX full duplex supported Local device. 100BaseTX full duplex supported Loca device. Default Reg. 1.14. 100Base-T 100BaseTX supported Local device. 100BaseTX supported Local device. Default Reg. 1.13. 10Base-T Full Duplex 10Mbps full duplex supported Local device. 10Mbps full duplex supported Local device. Default Reg. 1.12. 10Base-T 10Mbps supported Local device. 10Mbps supported Local device. Default Reg. 1.11. 4.[4:0] Selector Field Protocol Selection [00001] IEEE 802.3.
00001
Register Auto-Negotiation Link Partner Ability Register
Reg.bit 5.15
Name Next Page
Description Link partner desires Next Page transfer. Link partner does desire Next Page transfer.
Mode
Default
5.14
Acknowle
Link Partner acknowledges reception words. acknowledged Link Partner.
5.13
Remote
Remote Fault indicated Link Partner.
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Fault 5.[12:10] Reserved 100Base-T 100Base-T Full Duplex remote fault detected Link Partner. future technology 100BaseT4 supported Link Partner. 100BaseT4 supported Link Partner. 100BaseTX full duplex supported Link Partner. 100BaseTX full duplex supported Link Partner. 100Base-T 10Base-T Full Duplex 10Base-T 100BaseTX supported Link Partner. 100BaseTX supported Link Partner. 10Mbps full duplex supported Link Partner. 10Mbps full duplex supported Link Partner. 10Mbps supported Link Partner. 10Mbps supported Link Partner. 5.[4:0] Selector Field Protocol Selection [00001] IEEE 802.3.
00001
Register Auto Negotiation Expansion Registe
Reg.bit 6.[15:5]
Name Reserved Parallel Detection Fault
Description
Mode
Default
Fault detected parallel detection logic, this fault more than technology detecting concurrent link condition. This only cleared reading this register using management interface. fault detected paralleldetection logic
RO/L
Link Partne Next Page Able
Link partner support next page function Link partner does support next page function.
Next Page Able
Next page supported, i.e., this permanently ties
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Reg.bit Name Page Received Description when link code word been received into Auto-Negotiation Link Partne Ability Register. This cleared upon read this register. Link Partne Auto-Nego tiation Link partner Auto-Negotiat capable Link partner Auto-Negotiation capable. Mode
Default
Register Auto Negotiation Next Page Transmit Register (ANNPTR)
Reg.bit 7.15
Name
Description Next page indication: Another Next Page desired. other Next Page Transfer desired.
Mode
Default
7.14 7.13
Reserved
Message page: Message page. Un-formatted page.
7.12
ACK2
Acknowledge Will comply with message comply with message.
7.11
TOG_T
Toggle: Previous value transmitted link code word equals Previous value transmitted link code word equals
7.[10:0]
CODE
Message/Un-formatted Code Field.
Register ADMTEK Specific Register
Reg.bit
Name
Description
Mode
Default
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Reg.bit 16.15 Name Repeater Description Repeater mode, -duplex will inactive, only responses receive activity. test function also abled. 16.14 INTR_LE INTR will active high this register INTR will active register 16.[13:12] 16.11 Reserved Test Inhibi Disable 10BaseT testing. Enable 10BaseT testing, which generate pulse following completion packet transmission. 16.10 10BaseT Loopback Enable normal loopback 10BaseT mode. Disable normal loopback 10BaseT mode. Disable auto polarity detection correction. Enable auto polarity detection correction. Mode
Default RPTR
16.[9:6] 16.5
Reserved Auto polarit Disable
0000
16.4
Reverse Polarity
Reg. 16.5 Reverse polarity detected media, this will Reg. 16.5 writing this will reverse polarity transmitter. Note: reverse polarity detected either through inverted through burst inverted FLP.
16.[3:1] 16.0
Reserved Receive Clock Control
Write this will shut RX_CLK when incoming data present. RX_CLK will resume active clock cycle prior RX_DV goes high, shut clock cycles after RX_DV goes low. However, loopback bypassed modes, writing this does affect RX_CLK.
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Reg.bit Name Description Receive clock will active time Mode
Default
Register Interrupt Control/Status Register
Reg.bit 17.15 17.14 17.13
Name Jabber_IE Rx_Er_IE Page_Rx_I
Description Jabber Interrupt Enable Receive Error Interrupt Enable. Page Received Interrupt Enable. Parallel Detection Fault Inter rupt Enable.
Mode
Default
17.12
PD_Fault_I
17.11
LP_Ack_I
Link Partner Acknowledge Interrupt Enable.
17.10
Link_Not_
Link Status Interrupt Enable.
17.9 17.8
R_Fault_IE ANeg_Co mp_IE
Remote Fault Interrupt Enable Auto-Negotiation Complete Interrupt Enable.
17.7 17.6 17.5
Jabber_Int Rx_Er_In Page_Rx_I
This when jabber event detected. This when RX_ER transitions high This when page received from link partner during Auto-Neg. This when parallel detect fault detected.
17.4
PD_Fault_I
17.3
LP_Ack_In
This when with acknowledge received. This when link status switches from status Non-OK status (Fail Ready). This when remote fault detected.
17.2
Link_Not_
17.1
R_Fault_In
17.0
A_Neg_Co
This when Auto-Neg complete.
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Interrupt Source Table assignments
Register Diagnostic Registe
Reg.bit 18.[15:12] 18.11
Name Reserved DPLX
Description
Mode
Default 0000
This indicates result Auto-Neg duplex arbitration. This indicates result Auto-Neg data speed arbitration. 10BT mode, this indicates that Manchester data been detected. 100BT mode, indicates valid signal been received necessarily locked
18.10 18.9
Speed RX_PASS
18.8
RX_LOCK
Indicates receive locked onto received signal selected speed operation (10Bas 100Base-TX). This whenever cycl -slip occurs, will remain until read.
RO/SC
18.[7:0]
Reserved
Register Power/Loopback Registe
Reg.bit 19.[14:7] 19.6
Name Reserved TP12
Description
Mode
Default
Transmit transformer ratio selection 1.25:1 Enable advanced power saving mode. disable advanced power saving mode. Enable test loopback. Data will transmitted from interface clock recovery loopback
19.5
Power Mode
19.4
Test Loopbac
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received data. 19.3 Digital loopback 19.2 LP_LPBK Enable loopback. Normal operation. Enable link pulse loopback. Normal operation. 19.1 Link Integrity Test 19.0 Reduc Timer Auto-Neg test mode, send instead order test receive integrity. Sending Auto-Neg test mode. Reduce time constant Auto -Negotiation timer. Normal operation.
Register Loopback Power Management Register
Reg.bit 20.[15:8] 20.[7:4]
Name Reserved Cable measureme capability
Description
Mode
Default
These bits used cable length indicator. bits incremented from 0000 1111, with increment approximately meters. equivalent with increment 100MHz. value read back from equalizer, measured value absolute.
20.[3:0]
Reserved
Register Mode Control Register
Reg.bit 21.15 21.14
Name Reserved Disable
Description
Mode
Default
Force 10B-T link without checking NLP. Normal Operation. force link auto negotiation must disabled this
21.13
Force_link
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Reg.bit 21.12 Name Jabber Disable 21.11 10BT_Sel Description Disable Jabber function PHY. Enable Jabber function PHY. Enable 7-wire interface 10Base-T operation. This useful only when chip bypass mode Normal operation. 21.[10:9] 21.8 Reserved FEF_Disab Enable far-end-fault generation detection function. Disable -end-fault. Mode
Default
TECH FX_SEL ANEGA
21.7
Force Transmit
This force transmit Faul (FEF) pattern. When Receive Error Counter full, this will one. Disable Receive Error Counter. Enable Receive Error Counter. Disable watchdog timer decipher. Enable watchdog timer.
21.6
Rx_Er_Cnt Full
21.5
Disable Rx_Er_Cnt
21.4
Dis_WDT
21.3
En_RPB
Enable remote loopback. Disable remote loopback.
21.2
Dis_Scrm
Enable data scrambling. Disable data scrambling. When mode selected, this will forced
21.[1:0]
Reserved
Register Lock Registe
Reg.bit 23.[15:0]
Name DLOCK drop
Description Count lock drop events.
Mode
Default 0000
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counter
Register Receive Error Counter Register
Reg.bit 24.[15:0]
Name RX_ER counter
Description Count receive events.
Mode
Default 0000
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7.4. Descriptors Buffer Management CENTAUR-P provides receive transmit descriptors packet buffering management. 7.4.1. Receive descriptor 7.4.1.1. Receive Descriptor Table
RDES0 RDES1 RDES2 RDES3 -Contro Status Buffer2 byte-count Buffer1 address boundary) Buffer2 address boundary) Buffer1 byte-count
Descriptors receive buffers addresses must longword alignment
7.4.1.2. Receive Descriptor Descriptions
RDES0 Name Descriptions indicate receiving data into this descriptor Host does move receiving data yet. 30-16 Frame length, including CRC. This field valid only last descriptor Error summary, following overflow erro late collision frame long runt packet descriptor error This field valid only last descriptor. Descriptor error. This valid only last descriptor current receiving packet able into current valid descriptor. This packet truncated. 13-12 Data type. normal
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loop-back Transceiver loop-back remote loop-back These bits valid only last descripto Runt frame (packet length bytes). This valid only last descriptor Multicast frame. This valid only last descripto First descriptor. Last descriptor. long packet (packet length 1518 bytes). valid only last descriptor Late collision. when collision active after bytes. This valid only last descriptor Frame type. This valid only last descriptor. Ethernet type 802.3 type RDES1 31~26 Name -RER Descriptions reserved Receive ring indicates this descriptor last, return base address descripto Second address chain chain structure. Indicates buffer2 address next descriptor address. Ring mode takes precedence over chained 23~22 21~11 RDES2 31~0 RDES3 Name RBA1 Descriptions Receive Buffer Address This buffer address should double word aligned -RBS2 RBS1 reserved Buffer size boundary Buffer size boundary reserved Receive watchdog (refer CSR15, This valid only last descriptor. Default Dribble bit. This valid only last descripto Packet length integer multiple -bit. error. This valid only last descriptor Overflow. This valid only last descripto
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31~0 Name RBA2 Descriptions Receive Buffer Address This buffer address should double word aligned
7.4.2. Transmit Descriptor 7.4.2.1. Transmit Descriptor Table
TDES0 TDES1 TDES2 TDES3 Descriptor addresses must longword alignment Contro Status Buffer2 byte-count Buffer1 address Buffer2 address Buffer1 byte-count
7.4.2.2. Transmit Descriptor Descriptions
TDES0 Name Descriptions Indicate this descriptor ready transmit transmit data this descriptor transmission 30-24 23-22 21-16 Reserved Under-run count Reserved Error summary, following under-run error excessive collision late collision carrier loss carrier jabber time-out 13-12 Transmit jabber time-out Reserved Loss carrier carrier
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Late collision Excessive collision Heartbeat fail Collision count Reserved Under-run error Deferred
TDES1 28,27 Name Descriptions Interrupt completed Last descriptor First descriptor Reserved Disable function Ring address chain Indicate buffer2 address next descriptor address 21-11 10-0 TDES2 31~0 TDES3 31~0 Name Descriptions Buffer Address Without limitation transmission buffer address. Name Descriptions Buffer Address Without limitation transmission buffer address. -TBS2 TBS1 Disable padding functi Reserved Buffer size Buffer size
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Functional Descriptions 8.1. Initialization Flow flow initialize AN983 shown below.
Search
base address value
Reset (CSR0) Reset (XR0)
Need media type?
(Force Media)
Program media type
Read EEPROM from CSR9
Physical adress (CSR25,
Need Multicast
Multicast address table (CSR27,
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Prepare Transmit descriptor buffer
Install function
Open interrupt Enable functions
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8.2. Network Packet Buffer Managemen 8.2.1 Descriptor Structure Types networking operation, CENTAUR-P transmits data packet from transmit buffers host memory CENTAUR-P's transmit FIFO receives data packet from CENTAUR-P's receive FIFO receive buffers host memory. descriptors that CENTAUR-P supports build host memory used pointers thes transmit receive buffers. There structure types descriptor Ring Chain, supported CENTAUR-P shown below. type selection controlled bit24 RDES1 bit24 TDES1. transmit receive buffers physically built host memory. buffer contain either whole packet just part packet. can't contain more than packet.
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Ring structure: There buffers descriptor inthe ring structure. Support receive early interrupt.
Descriptor CSR3 CSR4 Descriptor Pointer
Length Length
Data Buffe Data Length
Buffer1 pointe Buffer2 pointe Ring
Data
Length
Fig.3 Ring structure frame buffer
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Chain structure: There only buffer descriptor chain structure.
CSR3 CSR4 Descriptor Pointer
Descriptor -Length
Data Buffer Data Length
Buffer1 pointer Next pointer
-Length
Buffer1 pointer Next pointer
Data
Length
-Length
Buffer1 pointer Next pointer
Data
Length
Fig.4 Chain structure frame buffer
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8.2.2. point descriptor management ready network side access ready host side access
Transmit Descriptor Pointers
Descriptor
Length Length
next packet transmitted bit=1, packet1 packet2 ready transmit
buffer1 pointer buffer2 pointer
Data Buffer
packet1
data
packet1
data
packet2
empty descriptor pointer
ring
Fig.5 Transmit pointers descriptor management
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Receive Descriptor Pointers
packet2
bit=1, next descriptor ready incoming packet
Data Buffer
filled descriptor pointer
packet1
ring
packet2
Fig.6 Receive pointers descriptor managemen
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8.3. Transmit Scheme Transmit Early Interrupt 8.3.1. Transmit flow flow packet transmit shown below. Initial Program descriptor, place data into host memory
Change
Write demand poll
CENTAUR-P read descriptor available descriptor(own=1) read data into fifo own=0
deferring greater than threshold TRANSMIT read rest data Back-off collision? write descriptor generate interrupt rrors
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Centaur-P Specificatio 8.3.2 Transmit pre-fetch data flow Transmit FIFO size=2K-byte packets FIFO same time meet transmit min. back-to-back
place packet data into host memory issue transmit demand FIFO-to-host memory operation (1st packet) Transmit enable place packet data into host memory check point FIFO-to-host memory operation (2nd packet) place packet data into host memory check point FIFO-to-host memory operation (3rd packet)
packet transmitted, check packet packet check next packet packet transmit threshold
time
handled driver
handled CENTAUR-P
Fig.7 Transmit data flow pre-fetch data 8.3.3. Transmit early interrupt Schem
Host TX-FIFO Memory Operation Transmit data from FIFO Media Normal Interrupt after Transmit Completed Driver return buffer upper layer Early Interrupt after Host TXFIFO Operation Completed Driver return buffer upper layer time saved time when transmit early interrupt implemented
handled driver
handled CENTAUR-P
Fig.8 Transmit normal interrup early interrupt comparison
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Receive scheme Receive early interrupt scheme following figure shows difference timing without early interrupt early interrupt.
incoming packet receive FIFO operation FIFO-to-host memory operation interrupt driver read header higher layer proces driver read rest data receive early interrup driver read header(early) higher layer process(early) driver read rest data finish time finish time
time
without early interrupt
with interrupt
Fig.9 Receive data flow (without early interrupt with early interrupt)
size descriptor program header size advance
FIFO-to-host operation
descriptor descriptor full
packet issue second interrupt
receive early interrupt driver read header(early) higher layer process(early) driver read rest data finish time
Fig.10 Detailed Receive Early interrupt flow
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8.5. Network Operation 8.5.1.MAC Operation (Media Access Control) portion CENTAUR-P, incorporates essential protocol requirements operating IEEE802.3 Ethernet compliant node.
Format Description 7-byte field (10101010b) 1-byte field (10101011b) 6-byte field 6-byte field 2-byte field indicated frame IEEE802.3 format Ethernet format. IEEE802.3 format: 0000H 05DCH Length field Ethernet format: 05DD FFFFH Type fiel 1500 bytes data information 32-bit cyclic redundant code error detection
Field Preamble Start Frame Delimiter Destination Address Source Address Length/Typ
Data
*Note: padding disabled(TDES1 bit23), data field shorter than bytes.
Transmit Data Encapsulatio differences between encapsulation frame while operating 100BASE-TX mode listed follow first byte preamble replaced code according IEE802.3u, clause After field frame, CENTAUR-P insert code according IEE802.3u, clause
Receive Data Decapsulation When operate 100BAS mode CENTAUR-P detects code
preamble well code packet end. code detected, CENTAUR-P will abort this frame receiving wait code detection.
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Centaur-P Specificatio code detected, CENTAUR-P will report error.
Deferring Inter-Frame (IFG) time divided into parts IFG1 time (64-bit time): carrier detected medium during this time, CENTAUR-P will reset IFG1 time counter restart monitor channel idle again. IFG2 time (32-bit time): After counting IFG2 time CENTAUR-P will access channel even though carrier been sensed network.
Collision Handling scheduling re-transmissions determined controlled randomization process called "truncated binary exponential back -off". enforcing collision (jamming), CENTAUR-P delays before attempting re-transmit packet
delay integer multiple slot time. number slot times delay before re-transmission attempt chosen uniform distributed integer range:
where min(n,
8.5.2. Transceiver Operatio transceiver portion CENTAUR-P, integrates IEEE802.3u
compliant functions PCS(physical coding -layer), PMA(physical medium attachment) sub-layer, PMD(physical dependent) sub-layer 100BASE-TX, IEEE802.3 compliant functions Manchester encoding/decoding transceiver 10BASE-T. functions operation schemes described following sections.
100BASE-TX Transmit Operation Regarding 100BASE-TX transmission, transceiver provides transmission functions PCS, PMA, encoding data nibbles -bit code-groups (4B/5B), scrambling, serialization scrambled code -groups, converting serial code into NRZI code, converting NRZI code into MLT3 code, then driving MLT3 code into category Unshielded Twisted Pair cable through isolation transformer with turns ratio
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Data code-groups Encoder normal mode application, transceiver receives nibble type data TxD0~3 inputs MII. These inputs sampled transceiver rising edge -clk passed 4B/5B encoder generate -group used 100BAS -TX. Idle code-groups: order establish maintain clock synchronization, transceiver need keep transmitting signals medium. transceiver generate Idle code-groups transmission when there real data want sent MAC. Start-of-Stream Delimiter-SSD (/J/K/): transmission stream, first nibbles preamble. order partner delineate boundary data transmission sequence authenticate carrier events, transceiver will replace first nibbles preamble with /J/K/ code-groups. End-of-Stream Delimiter-ESD (/T/R/) order indicate termination normal data transmissions, transceiver will insert nibbles /T/R/ code-group after last nibble FCS. Scrambling: encoded data(including idle, SSD, code-groups) passed data scrambler reduce spread power spectrum using 10-bit scrambler seed loaded beginning. Data conversion Parallel Serial, NRZI, NRZI MLT3 After scrambled, transmission data with type 25MHz will converted serial stream 125HMz parallel serial function. After serialized, transmission serial stream will further converted from NRZI format. After NRZI converted, NRZI stream passed through MLT3 encoder generate TP-PMD specified MLT3 code. With this MLT3 code, lowers frequency reduces energy transmission signal cable also makes system easily meet specification EMI. -Shaper Media Signal Driver: order reduce energy
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harmonic frequency transmission signals, transceiver provides wave-shaper prior line driver smooth keep symmetric rising/falling edge transmission signals. wave -shaped signals include 100BASE-TX 10BAS both passed same media signal driver. This design simplify external magnetic connection with single one.
100BASE-TX Receiving Operation Regarding 100BASE-TX receiving operation, transceiver provides receiving functions PMD, PMA, receiving incoming data signals through category cable isolation transformer with turns ratio ncludes adaptive equalizer baseline wander, data conversions MLT3 NRZI, NRZI serial parallel, clock data recovery, -scrambler, decoder 5B/4B.
Adaptive Equalizer Baseline Wander Since high speed signals over unshielded shielded) twisted Pair cable will induce amplitude attenuation phase shifting. Furthermore, these effects depends signal frequency, cable type, cable length connectors cabling. reliable adaptive equalizer baseline wander compensate amplitud attenuation phase shifting necessary. transceiver, provides robust circuits perform these functions MLT3 NRZI Decoder Data Recovery: After receiving proper MLT3 signals, transceiver converts MLT3 NRZI code further processing. After adaptive equalizer, baseline wander, MLT3 NRZI decoder, compensated signals with NRZI type 125MHz passed Phase Lock Loop circuits extract original data synchronous clock. Data Conversions NRZI Serial Parallel After data recovered, signals will passed NRZI converter generate 125MHz serial stream. This serial stream will packed parallel type further processing De-scrambling Decoding 5B/4B: parallel type data passed
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Centaur-P Specificatio de-scrambler 5B/4B decoder return their original nibble type data.
Carrier sensing: Carrier Sense(CRS) signal asserted when transceiver detects non-contiguous zeros within 10bit boundary receiving stream. de-asserted when code-group Idle code-group detected. half duplex mode, asserted during packet transmission receive. full duplex mode, asserted only during packet reception.
10BASE-T Transmission Operation includes parallel serial converter, Manchester Encoder, Link test function, Jabber function transmit wave-shaper line driver described section "Wave-Shaper Media Signal Driver" "100BASE-T Transmission Operation". also provides Collision detection test half duplex application.
10BASE-T Receive Operation includes carrier sense function, receiving filter, clock data recovering, Manchester decoder, serial parallel converter Loop-back Operation transceiver transceiver provides internal loop -back(also called transceiver -back) operation both 100BASE-TX 10BASE-T operations. -back operation enabled setting register this -back operation, lines isolated from media. transceiver also provides remote -back operation 100BASE-TX operation. remote loop -back operation enabled setting register 100BASE-TX internal loop-back operation, data comes from transmi output NRZI converter then loop-back receive path into input NRZI converter. 100BASE-TX remote loop-back operation, data received from pins through receive path output data clock recover then loop-back input NRZI MLT3 converter transmit path then transmit medium transmit line drivers. 10BASE-T loop-back operation, data through transmit path -back from output Manchester encoder into input Phase Lock Loop circuit receive path.
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Full Duplex Half Duplex Operation Transceiver transceiver operate either full duplex half duplex network application. full duplex, both transmit receive operated simultaneously. Under full duplex mode, collision(COL) signal ignored carrier sense(CRS) signal asserted only when transceiver receiving. half duplex mode, either transmit receive operated time. Under half duplex mode, collision signal asserted when transmit receive signals collided carrier sense asserted during transmission reception.
Auto-Negotiation Operation Auto-Negotiation function designed provide means exchange information between transceiver network partner automatically configure both take maximum advantage their abilities, both setup accordingly. Auto-Negotiation function controlled through register Auto-Negotiation exchanges information with network partner using Fast Link Pulses(FLPs) burst link pulses. There bits signaling information contained burst pulses advertise remote partner's capabilities which determined register According this information they find their highest common capability following priority sequence below 100BASE-TX full duplex 100BASE-TX half duplex 10BASE-T full duplex 10BASE-T half duplex During powe reset, Auto-Negotiation found enabled then FLPs will transmitted -Negotiation function will process. Otherwise, Auto-Negotiation will occur until register When Auto-Negotiation disabled, then Network Speed Duplex Mode selected programming register
Power Down Operation reduce power consumption transceiver designed with power down feature which save power consumption significantly. Since power supply 100BASE-TX 10BASE-T circuits separated, transceiver turn circuit either 100BASE-TX 10BASE-T when other them operating
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8.5.3. Flow Control Full Duplex Application PAUSE function operation used inhibit transmission data frames specified period time. CENTAUR-P supports full duplex protocol IEEE802.3x. support PAUSE function, CENTAUR-P implements Control -layer functions decode Control frames received from control clients execute relative requests accordingly. When Full Duplex mode PAUSE function selected after Auto-Negotiation completed, then CENTAUR-P enables PAUSE function flow control full duplex application. this section will describe CENTAUR-P implements PAUSE function.
Control Frame PAUSE Fram
Octets Octets Octets Octets (minFrameSize 160) Octets
Destination Address Source Address Length/Type 88-08h Control Opcode Control Parameter Reserved(pads with zeroes)
Fig.11 Control Frame Format Control frame distinguished from other frames only their Length/Type field identifier. Control Opcode defined Control Frame format PAUSE function 0001h. Besides, PAUSE time specified Control Parameters field with Octets, unsigned integer, units Slot-Times. range possible PAUSE time 65535 Slot-Times. valid PAUSE frame issued control client(could switch bridge) will contains destination address equal globally assigned mulitcast address -80-C2-00-00-01, equal unicast address which control client wishes inhibit transmission data frames. Filled Control Opcode field with 0001h. Octets PAUSE time specified Control parameter field
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indicate length time which destination wished inhibit data frame transmission.
Receive Operation PAUSE functio Upon reception valid Control frame, CENTAUR-P will start timer
length time specified Control Parameters field. When timer value reaches zero then CENTAUR-P ends PAUSE state. However, PAUSE frame should affect transmission frame that been submitted MAC(started Transmit can't interrupted). other hand, CENTAUR-P shall begin transmit frame more than Slot -Times after received valid PAUSE frame with -zero PAUSE time. CENTAUR-P receives PAUSE frame with zero PAUSE time value, then CENTAUR-P ends PAUSE stat immediately.
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Opcode PAUSE Function
Wait Transmission Completed
transmission_in_progress false (01-80-C2-00-00-01 Phys-address)
(01-80-C2-00-00-01 Phys-address)
PAUSE FUNCTION
n_slots_rx data [17:32] Start pause_timer (n_slots_rx slot_time
PAUSE
Fig.12 PAUSE operation receive state diagram 8.6. Display Operation Centaur-P provides kinds display mode, detail descriptions about operation described Description section.
First mode displays 100Mbps(on) 10Mbps(off) Link(Keeps when link Activity(Blink with 10Hz when receiving transmitting collision FD(Keeps when Full duplex mode) Collision(Bl with 20Hz when colliding Second displays Link(On when 100M link Link(On when link
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Activity (Blink with 10Hz when receiving transmitting) FD(Keeps when Full duplex mode) Collision(Blink with 20Hz when colliding)
8.7. Reset Operation 8.7.1. Reset whole chip There ways reset CENTAU First, hardware reset, CENTAUR-P reset RST# pin. ensuring proper reset operation, least 100µs active Reset input signal required. Second, software reset, when CSR0 register CENTAUR-P will reset entire circuits register default value then clear CSR0 8.7.2. Reset Transceiver only When register transceiver will reset entire circuits register contains default value then clear register 8.8. Wake Function CENTAUR-P assert signal wake system when received Magic Packet from network. Wake operation described follow.
Magic Packet format: Valid destination address that pass address filter CENTAUR-P payload frame must include least contiguous `FF' followed immediately repetitions IEEE dress. frame contain multiple `six sixteen IEEE address' pattern.
Wake operatio Wake enable function controlled CSR18, loaded from EEPROM after reset programmed driver enable Wake function. CSR18 CENTAUR-P receive Magic Packet, will assert PME# signal (drive low) indicate receiving wake frame well status (the CSR20). 8.9. ACPI Power Management Function
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Centaur-P Specificatio CENTAUR-P built-in capability Power Management (PM) whic controlled host system
CENTAUR-P will provide Compatibility with Device Class Power Management Reference Specification, Rev1.09 Compatibility with ACPI specification, Compatibility with Power Management Interface Specification, Compatibility with Magic PacketTechnology. Compatibility with CLKRUN scheme.
8.9.1. Power States (Fully this state CENTAUR-P operates full functionality consumes normal power. While state, clock lower than 16MHz, CENTAUR-P receive transmit frames properly. this state CENTAUR-P doesn't response accesses except configuration space full function context place. only network operation CENTAUR-P initiate wake-up event.
this state CENTAUR-P only respond access configuration space full function context place. CENTAUR-P can't transmit receive even frame. D3cold (Power Removed this state function context lost. When power restored, function will return
D3hot (Software Visible When CENTAUR-P brought back from D3hot software must perfor
full initialization.
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Centaur-P Specificatio
CENTAUR-P D3hot state respond configurations cycles long power clock supplied. This requires device perform internal reset return power-up reset condition without RST# asserted. Device State State Function Context Full function context place Clock Power Supported Actions Function Supported Actions from Function transaction interrupt Only wake-up events
Full speed Full power transaction configuration access configuratio access(B0, configuratio access(B0, Power-on reset power
Configuration Stopped maintained. Full speed except wake-up events Configuration Stopped maintained. Full speed Configuration lost, Stopped full initialization Full speed required upon return configuratio lost. Power-on defaults place return clock
D3hot
D3cold
Table Power state
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Centaur-P Specificatio General EEPROM Format Descriptio Offset Length Description AN983 Signature: 0x85, 0x09 Format major version 0x02. Format minor version 0x00 Reserved IEEE network address ID1,ID2,ID3,ID4,ID5,ID6 Reserved, should zero. Reserved, should zero. Phytype Reserved, should zero. Reserved, should zero. Default Connection Type, Table Reserved, should zero. Reserved, should zero. Device ID.:0x0985(PCI), 0x1985(Cardbus) Vendor ID.:0x1317 Subsystem Subsystem Vendor MIN_GNT value. MAX_LAT value. Load configuration register offset 0x28 CSR18 (CR) 31-16 recall data. Reserved, should zero. Cardbus length Reserved, should zero.
CheckSum, least significant bytes data stored offset 0.7D EEPROM Cardbus
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Table Connection Type Definition 0xFFFF 0x0100 0x0200 0x0400 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0010 0x0013 0x0015 Software Driver Default Auto-Negotiatio Power-on Auto-detection Auto Sense 10BaseT 100BaseTx 100BaseT4 100BaseFx 10BaseT Full Duplex 100BaseTx Full Duplex 100BaseFx Full Duplex
Electrical Specifications Timings 10.1 Absolute Maximum Ratings Supply Voltage(Vcc) -0.5V 3.6V Input Voltag -0.5V VCC+0.5 Output Voltage -0.5V VCC+0.5 Storage Temperature degree degree Ambient Temperature degree degree Protection 2000V 10.2 Specifications
General Specifications Parameter Description Supply Voltag Power Supply Condition Typical Units
Interface Specfications Parameter Description Condition
Typical
Units
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Vilp Vihp Iilp Volp Vohp Cinp Cclkp Input Voltag Input HIGH Voltage Input Leakage Current Output Voltag Output HIGH Voltag Input Capacitance Capacitance 0<Vin <Vcc Iout=700uA Iout -150uA 0.9Vcc -0.5 0.475vcc 0.325vcc Vcc+0.5 0.1Vcc
Flash/EEPROM Interface Specifications Parameter Description Vilf Vihf Volf Vohf Cinf Input Voltag Input HIGH Voltage Input Leakage Current Output Voltag Output HIGH Voltag Input Capacitance Condition 0.7Vcc Typical 0.3Vcc Units
10.3 Specifications
Signaling Specifications 3.3V Parameter Description Ioh(AC) Iol(AC) Switching Current High Switching Current Slew Rate Unloaded Output Rise Unloaded Output Fall Time 0.2vcc~0.6vcc 0.6vcc~0.2vcc 0.25 Condition Typical Units V/ns V/ns V/ns
10.4 Timing Specifications
Clock Specification Parameter Description Tcyc Thigh Tlow Clock Cycle Time Clock High Time Clock Time Condition Typical Units
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Clock Slew Rate V/ns
0.6vcc Thigh 0.4Vcc Tlow 0.2Vcc
Tcyc
Figure Clock Waveform
Timings Parameter Description Tval Tval(ptp) Toff access time bused signals access time -point point Float Active Delay Active Float Delay Input Time Clock bused signals Tsu(ptp) Input Time Clock point point Trst Input Hold Time from Clock Reset Active Time after Power Stable Trst-clk Reset Active Time after Stable ADMtek Incorporated. No.9, Industry Rd., SBIP, HsinChu Tel: 886-3-5788879 Fax: -578887 2000/3/23 Rev: 10,12 Condition Typical Units
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Centaur-P Specificatio
Trst-off Reset Active Output Float delay
Figure Timings
1.5Vcc
Vth=2.4Vc Vtl=0.4Vcc Tval(max=11ns)
OUTPUT Dela
Tri-state OUTPUT
Toff
INPUT
1.5V
1.5V
Flash Interface Timings Parameter Description Tclz Tolz Tchz Tohz Read cycle time Chip enable access Address access time Output enable access time active output active output high active output high active output Output hold from address change Condition Typical Units
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Toes Toeh Twph Tblc Tblco Write cycle time Address setup time Address hold time setup time hold time high setup time high hold time pulse width pulse width high width Data setup Data hold time Byte load cycle Byte laod cycle time 0.22
Figure Flash write timings
ADDRESS Tfasc
Twph
DATA
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Figure Flash read timings
ADDRESS
DATA
EEPROM Interface Timings (AC/AD) Parameter Description Serial Clock Frequency Condition 2.7V<Vcc<5.5V Typical 0.4M/ 0.1M Tecss Delay from High High Tecsh Delay from Tedts Tedth Setup Time Hold Time after 2.7V<Vcc<5.5V 1120 /4480 2.7V<Vcc<5.5V 160/640 2.7V<Vcc<5.5V 2320 /9280 Tecsl Time 2.7V<Vcc<5.5V 7400/ 29600 2.7V<Vcc<5.5V 160/640 Units
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Figure Serial EEPROM timing
Tecss Tecsh Tecsl
Tedts Tedth
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Centaur-P Specificatio Package
Fig.20 Package outline Centaur-P Symbol Description Overall Height Stand Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Angl Coplanarity Minimum 0.25mm 0.17mm 0.13mm 23.0mm 19.9mm 17.0mm 13.9mm 0.50mm 0.65mm Maximum 3.4mm 0.27mm 0.23mm 23.4mm 20.1mm 17.4mm 14.1mm 0.95mm
0.076mm
Table2 Dimensions -pin PQFP Package
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Centaur-P Specificatio Symbol Description Overall Height Stand Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Angl Coplanarity Minimum 0.05mm 0.17mm 0.13mm 21.9.0mm 19.9mm 15.9.0mm 13.9mm 0.50mm 0.45mm Maximum 1.6mm 0.15mm 0.27mm 0.23mm 22.1mm 20.1mm 16.1mm 14.1mm 0.75mm 0.076mm
Table3 Dimensions -pin LQFP Package
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