+2.7 +5.5 Serial Input, Dual Voltage Output 8-Bit AD7303 AD7303
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FEATURES 8-Bit DACs Package 8-Pin DIP/SOIC microSOIC Packages +2.7 +5.5 Operation Internal External Reference Capability Individual Power-Down Function Three-Wire Serial Interface QSPITM, SPIand MicrowireCompatible On-Chip Output Buffer Rail-to-Rail Operation On-Chip Control Register Power Operation: Full Power-Down max, typically APPLICATIONS Portable Battery Powered Instruments Digital Gain Offset Adjustment Programmable Voltage Current Sources Programmable Attenuators
+2.7 +5.5 Serial Input, Dual Voltage Output 8-Bit AD7303
AD7303
INPUT REGISTER REGISTER VOUT
INPUT REGISTER
REGISTER
VOUT
DATA SCLK SYNC
CONTROL
POWER RESET
16-BIT SHIFT REGISTER
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
AD7303 dual, 8-bit voltage that operates from single +2.7 +5.5 supply. on-chip precision output buffers allow outputs swing rail rail. This device uses versatile 3-wire serial interface that operates clock rates MHz, compatible with QSPI, SPI, microwire digital signal processor interface standards. serial input register sixteen bits wide; bits data bits DACs, remaining eight bits make control register. on-chip control register used address relevant DAC, power down complete device individual DAC, select internal external reference provide synchronous loading facility simultaneous update outputs with software LDAC function. power consumption this part makes ideally suited portable battery operated equipment. power consumption reducing less than full power-down mode. AD7303 available 8-pin plastic dual in-line package, 8-lead SOIC microSOIC packages.
QSPI trademarks Motorola. Microwire trademark National Semiconductor.
power, single supply operation. This part operates from single +2.7 +5.5 supply consumes typically making ideal battery powered applications. on-chip output buffer amplifiers allow outputs DACs swing rail rail with settling time typically Internal external reference capability. High speed serial interface with clock rates MHz. Individual power-down each provided. When completely powered down, consumes typically
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 1997
+5.5 AD7303-SPECIFICATIONS GND;+2.7specificationsInternal TReference; otherwise noted) unless
GND;
Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error +25°C Full-Scale Error Gain Error3 Zero-Code Temperature Coefficient REFERENCE INPUT REFIN Input Range REFIN Input Impedance Internal Voltage Reference Error OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Slew Rate Digital Analog Glitch Impulse Digital Feedthrough Digital Crosstalk Analog Crosstalk Output Impedance Short Circuit Current Power Supply Rejection Ratio LOGIC INPUTS Input Current VINL, Input Voltage VINH, Input High Voltage Capacitance POWER REQUIREMENTS (Normal Mode) +25°C TMIN TMAX +25°C TMIN TMAX (Full Power-Down) +25°C TMIN TMAX
Versions1 -0.5 VDD/2 0.0001 2.7/5.5
Units Bits µV/°C V/µs nV-s nV-s nV-s min/max
Conditions/Comments
Note Guaranteed Monotonic Zeros Loaded Register Ones Loaded Register
Typically Change Around Major Carry
Both DACs Active Excluding Load Currents, VDD, Figure
VDD, Figure
NOTES Temperature ranges follows: Version, -40°C +105°C. Relative Accuracy calculated using reduced digital code range 245. Gain Error specified between Codes 245. actual error Code typically LSB. Internal Voltage Reference Error (Actual Ideal VREF/Ideal REF) 100. Ideal VDD/2, actual VREF voltage reference when internal reference selected. Specifications subject change without notice.
ORDERING GUIDE
Model AD7303BN AD7303BR AD7303BRM
Temperature Range -40°C +105°C -40°C +105°C -40°C +105°C
Package Options* SO-8 RM-8
Plastic DIP; SOIC; microSOIC.
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AD7303 TIMING CHARACTERISTICS1,
Parameter
(VDD +2.7 +5.5 Reference Internal Reference; specifications TMIN TMAX unless otherwise noted)
Units Conditions/Comments SCLK Cycle Time SCLK High Time SCLK Time SYNC Setup Time Data Setup Time Data Hold Time SYNC Hold Time Minimum SYNC High Time
Limit TMIN, TMAX Version)
NOTES Sample tested +25°C ensure compliance. input signals specified with (10% timed from voltage level VIH)/2, should exceed input. Figures
SCLK
SYNC
DB15
Figure Timing Diagram Continuous 16-Bit Write
SCLK
SYNC
DB15
Figure Timing Diagram 8-Bit Writes
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AD7303
ABSOLUTE MAXIMUM RATINGS*
+25°C unless otherwise noted)
-0.3 Reference Input Voltage -0.3 Digital Input Voltage -0.3 VOUT VOUT -0.3 Operating Temperature Range Commercial Version) -40°C +105°C Storage Temperature Range -65°C +150°C Junction Temperature +150°C Plastic Package, Power Dissipation Thermal Impedance 117°C/W Lead Temperature (Soldering, sec) +260°C
SOIC Package, Power Dissipation Thermal Impedance 157°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared sec) +220°C MicroSOIC Package, Power Dissipation Thermal Impedance 206°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared sec) +220°C
*Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7303 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
CONFIGURATIONS (DIP, SOIC microSOIC)
VOUT VOUT
AD7303
SYNC
VIEW (Not Scale) SCLK
FUNCTION DESCRIPTIONS
Mnemonic VOUT
Function Analog Output Voltage from output amplifier swings rail rail output. Power Supply Input. These parts operated from +2.7 +5.5 should decoupled GND. Ground reference point circuitry part. External Reference Input. This used reference both DACs, selected setting INT/EXT control register logic one. range this reference input VDD/2. When internal reference selected, this voltage will appear output decoupling purposes Pin. When using internal reference, external voltages should connected Pin, Figure Serial Clock. Logic Input. Data clocked into input shift register rising edge serial clock input. Data transferred rates MHz. Serial Data Input. This device 16-bit shift register, bits data bits control. Data clocked into register rising edge clock input. Level Triggered Control Input (active low). This frame synchronization signal input data. When SYNC goes low, enables input shift register data transferred rising edges following clocks. rising edge SYNC causes relevant registers updated. Analog output voltage from output amplifier swings rail rail output.
SCLK SYNC
VOUT
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AD7303
TERMINOLOGY
INTEGRAL NONLINEARITY DIGITAL-TO-ANALOG GLITCH IMPULSE
DACs, relative accuracy endpoint nonlinearity measure maximum deviation, LSBs, from straight line passing through endpoints transfer function. graphical representation transfer curve shown Figure
DIFFERENTIAL NONLINEARITY
Digital-to-analog glitch impulse impulse injected into analog output when digital inputs change state with selected software LDAC used update DAC. normally specified area glitch nV-s measured when digital input code changed major carry transition.
DIGITAL FEEDTHROUGH
Differential nonlinearity difference between measured change ideal change adjacent codes. specified differential nonlinearity maximum ensures monotonicity.
ZERO CODE ERROR
Digital feedthrough measure impulse injected into analog output from digital inputs same DAC, measured when updated. specified nV-s measured with full-scale code change data bus, i.e., from vice versa.
DIGITAL CROSSTALK
Zero code error measured output voltage from VOUT either when zero code (all zeros) loaded latch. combination offset errors output amplifier. Zero-scale error expressed LSBs.
GAIN ERROR
Digital crosstalk glitch impulse transferred output converter digital code change another DAC. specified nV-s.
ANALOG CROSSTALK
This measure span error DAC. deviation slope transfer characteristic from ideal expressed percent full-scale value. Gain error calculated between Codes 245.
FULL-SCALE ERROR
Analog crosstalk change output response change output other DAC. measured LSBs.
POWER SUPPLY REJECTION RATIO (PSRR)
Full-Scale Error measure output error when latch loaded with Hex. Full-scale error includes offset error.
This specification indicates output affected changes power supply voltage. Power supply rejection ratio quoted terms change output change full-scale output DAC. varied 10%. This specification applies external reference only because output voltage will track voltage when internal reference selected.
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AD7303-Typical Performance Characteristics
INTERNAL REFERENCE LOADED WITH 00HEX
4.92 4.84 4.76
3.25 2.75
VOUT
VOUT Volts
SINK CURRENT
4.68 4.52 4.44 4.36 INTERNAL REFERENCE REGISTER LOADED WITH FFHEX 4.28 25°C SOURCE CURRENT
VOUT Volts
2.25 1.75 1.25 INTERNAL REFERENCE REGISTER LOADED WITH FFHEX 25°C
SOURCE CURRENT
Figure Output Sink Current Capability with
Figure Output Source Current Capability with
Figure Output Source Current Capability with
0.45 0.35
LOGIC INPUTS
INTERNAL REFERENCE 25°C LOGIC INPUTS
ERROR LSBs
0.25 0.15
ERROR
INTERNAL REFERENCE
ERROR
0.05 REFERENCE VOLTAGE Volts
LOGIC INPUTS
LOGIC INPUTS
TEMPERATURE
Volts
Figure Relative Accuracy External Reference
Figure Supply Current Temperature
Figure Supply Current Supply Voltage
SYNC
ATTENUATION
INTERNAL VOLTAGE REFERENCE FULL SCALE CODE CHANGE 00H-FFH 25°C VOUT
POWER TIME INTERNAL REFERENCE BOTH DACS POWER DOWN INITIALLY
SYNC
EXTERNAL SINE WAVE REFERENCE REGISTER LOADED WITH FFHEX 25°C
VOUT VOUT
1000 FREQUENCY 10000
20mV TIME BASE 200ns/div
2V/div, 5V/div, TIME BASE 2µs/div
Figure Large Scale Signal Frequency Response
Figure Full-Scale Settling Time
Figure Exiting Power-Down (Full Power-Down)
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AD7303
INTERNAL REFERENCE NORMAL OPERATION INITIALLY POWER DOWN
SYNC
SYNC
INTERNAL VOLTAGE REFERENCE STEP CHANGE
VOUT
EXITING POWER DOWN
VOUT
500ns
5.00V, 50.0mV, 250ns
Figure Exiting Power-Down (Partial Power-Down)
Figure Supply Current Logic Input Voltage
Figure Small Scale Settling Time
ERROR
INTERNAL REFERENCE 100pF LOAD LIMITED CODE RANGE (10-245) 25°C
ERROR
-0.1 -0.2 -0.3 -0.4 -0.5 TEMPERATURE INTERNAL REFERENCE
ERROR
-0.1
-0.1 -0.2 -0.3 -0.4 INTERNAL REFERENCE
-0.2 -0.3 -0.4 -0.5
Input Code 245)
-0.5 TEMPERATURE
Figure Integral Linearity Plot
Figure Typical Temperature
Figure Typical Temperature
POWER-DOWN CURRENT
+5.5V
REFERENCE ERROR
TEMPERATURE
TEMPERATURE
Figure Typical Internal Reference Error Temperature
Figure Power-Down Current Temperature
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AD7303
GENERAL DESCRIPTION Section
AD7303 dual 8-bit voltage output digital-to-analog converter. architecture consists reference amplifier current source DAC, followed current-to-voltage converter capable generating rail-to-rail voltages output DAC. Figure shows block diagram basic architecture.
CURRENT 11.7k OUTPUT AMPLIFIER REFERENCE AMPLIFIER
reference appears reference output voltage decoupling purposes. When using internal reference, external references should connected pin. external reference selected, both switches open externally applied voltage applied reference amplifier. Decoupling capacitors applied decouple both internal reference external reference. noisy environments recommended that capacitor connected provide added decoupling even when internal reference selected.
Analog Outputs
AD7303
11.7k
AD7303 contains independent voltage output DACs with 8-bit resolution rail-to-rail operation. output buffer provides gain output. Figures show sink source capabilities output amplifier. slew rate output amplifier typically V/µs full-scale settling bits with capacitive load typically input coding straight binary. Table shows binary transfer function AD7303. Figure shows transfer function binary coding. output voltage ideally expressed
VOUT VREF (N/256)
Figure Architecture
Both outputs internally buffered these output buffer amplifiers have rail-to-rail output characteristics. output amplifier capable driving load both ground ground. reference selection either internally generated from externally applied through pin. Reference selection control register. range external reference input from VDD/2. output voltage from either given VREF (N/256) where: VREF voltage applied external VDD/2 when internal reference selected. decimal equivalent code loaded register ranges from 255.
Reference
where: VREF decimal equivalent binary input code. ranges from 255. voltage applied external when external reference selected VDD/2 internal reference used.
Table Binary Code Table AD7303
AD7303 facility either external reference applied through internal reference generated from VDD. Figure shows reference input arrangement where internal VDD/2 been selected.
Digital Input 1111 1111 1111 1110 1000 0001 1000 0000 0111 1111 0000 0001 0000 0000
2.VREF
Analog Output 255/256 VREF 254/256 VREF 129/256 VREF VREF 127/256 VREF VREF/256
AD7303
INT/EXT
0.1µF REFERENCE AMPLIFIER
OUTPUT VOLTAGE
VREF
Figure Reference Input
When internal reference selected during write DAC, both switches closed VDD/2 generated applied reference amplifier. This internal VDD/2 reference appears reference output voltage decoupling purposes. When using internal reference, external references should connected Pin. This internal VDD/2
INPUT CODE
Figure Transfer Function
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AD7303
SERIAL INTERFACE
AD7303 contains versatile 3-wire serial interface that compatible with SPI, QSPI Microwire interface standards well host digital signal processors. active SYNC enables shift register receive data from serial data input DIN. Data clocked into shift register rising edge serial clock. serial clock frequency high MHz. This shift register bits wide shown Figures first eight bits control bits second eight bits data bits DACs. Each transfer must consist 16-bit transfer. Data sent first transmitted 16-bit write 8-bit writes. Microwire interfaces output data 8-bit bytes thus require 8-bit transfers. this case SYNC input should remain until sixteen bits have been transferred shift register. QSPI interfaces pro-
grammed transfer data 16-bit words. After clocking sixteen bits shift register, rising edge SYNC executes programmed function. DACs double buffered which allows their outputs simultaneously updated.
INPUT SHIFT REGISTER DESCRIPTION
input shift register bits wide. first eight bits consist control bits last eight bits data bits. Figure shows block diagram logic interface AD7303 DAC. seven bits control word taken from input shift register latch sequencer that decodes this data provides output signals that control data transfers input data registers selected DAC, well output updating various power-down features associated with control section. description bits contained input shift register given below.
INT/EXT LDAC
SYNC LATCH SEQUENCER
POWER-DOWN POWER-DOWN BANDGAP POWER-DOWN SELECTOR LATCH DRIVERS REFERENCE CURRENT SWITCH RESISTOR SWITCH BIAS BANDGAP BIAS BIAS
16-BIT SHIFT REGISTER
CLOCK
INPUT REGISTER
DECODER
REGISTER
VOUT
INPUT REGISTER
DECODER
REGISTER
VOUT
SYNC SCLK
Figure Logic Interface AD7303
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AD7303
DB15 (MSB) INT/EXT LDAC (LSB) |------------------------- Control Bits Data Bits -------------------------|
Figure Input Shift Register Contents
Location DB15 DB14 DB13 DB12 DB11 DB10 DB7-DB0
Mnemonic INT/EXT LDAC
Description Selects between internal external reference. Uncommitted bit. Load synchronous update outputs. Power-down Power-down Address select either Control used conjunction with implement various data loading functions. Control used conjunction with implement various data loading functions. These bits contain data used update output DACs. 8-bit data word.
CONTROL BITS
LDAC
Function Implemented Both registers loaded from shift register. Update input register from shift register. Update input register from shift register. Update register from input register. Update register from input register. Update register from shift register. Update register from shift register. Load input register from shift register update both registers. Load input register from shift register update both registers outputs.
INT/EXT
Function Internal VDD/2 reference selected. External reference selected; this external reference applied ranges from VDD/2. Function Both DACs active. active power-down mode. power-down mode active. Both DACs powered down.
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AD7303
POWER-ON RESET AD7303 68HC11/68L11 Interface
AD7303 power-on reset circuit designed allow output stability during power-up. This circuit holds DACs reset state until write takes place DAC. reset state zeros latched into input registers each DAC, registers transparent mode. Thus output both DACs held ground potential until write takes place DAC.
POWER-DOWN FEATURES
bits control section 16-bit input word used AD7303 into power mode. powered down separately. When both DACs powered down, current consumption device reduced less than making device suitable portable battery powered equipment. reference bias servo loop, output amplifiers associated linear circuitry shut down when powerdown activated. output sees load approximately when power-down mode shown Figure contents data registers unaffected when power-down mode. time exit power-down determined nature power-down, device fully powered down bias generator also powered down device takes typically exit power-down mode. device only partially powered down, i.e., only channel powered down, this case bias generator active time required power-down channel exit this mode typically Figures
11.7k
Figure shows serial interface between AD7303 68HC11/68L11 microcontroller. 68HC11/68L11 drives CLKIN AD7303, while MOSI output drives serial data line DAC. SYNC signal derived from port line (PC7). setup conditions correct operation this interface follows: 68HC11/ 68L11 should configured that CPOL CPHA When data being transmitted DAC, SYNC line taken (PC7). When 68HC11/68L11 configured above, data appearing MOSI output valid rising edge SCK. Serial data from 68HC11/ 68L11 transmitted 8-bit bytes with only eight falling clock edges occurring transmit cycle. Data transmitted first. order load data AD7303, left after first eight bits transferred, second serial write operation performed taken high this procedure.
68HC11/68L11*
MOSI
AD7303*
SYNC SCLK
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7303 68HC11/68L11 Interface
AD7303 80C51/80L51 Interface
IDAC 11.7k VREF
Figure Output Stage During Power-Down
MICROPROCESSOR INTERFACING AD7303 ADSP-2101/ADSP-2103 Interface
Figure shows serial interface between AD7303 ADSP-2101/ADSP-2103. ADSP-2101/ADSP-2103 should operate SPORT Transmit Alternate Framing Mode. ADSP-2101/ADSP-2103 SPORT programmed through SPORT control register should configured follows: Internal Clock Operation, Active Framing, 16-Bit Word Length. Transmission initiated writing word register after SPORT been enabled. data clocked each falling edge serial clock clocked into AD7303 rising edge SCLK.
ADSP-2101/ ADSP-2103*
SCLK
Figure shows serial interface between AD7303 80C51/80L51 microcontroller. setup interface follows: 80C51/80L51 drives SCLK AD7303, while drives serial data line part. SYNC signal again derived from programmable port. this case port line P3.3 used. When data transmitted AD7303, P3.3 taken low. 80C51/80L51 transmits data only 8-bit bytes; thus only eight falling clock edges occur transmit cycle. load data DAC, P3.3 left after first eight bits transmitted, second write cycle initiated transmit second byte data. P3.3 taken high following completion this cycle. 80C51/ 80L51 outputs serial data format which first. AD7303 requires data with first received. 80C51/80L51 transmit routine should take this into account.
80C51/80L51*
P3.3
AD7303*
SYNC SCLK SDIN
AD7303*
SYNC SCLK
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7303 80C51/80L51 Interface
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7303 ADSP-2101/ADSP-2103 Interface
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AD7303
AD7303 Microwire Interface Bipolar Operation Using AD7303
Figure shows interface between AD7303 microwire compatible device. Serial data shifted falling edge serial clock clocked into AD7303 rising edge
AD7303 been designed single supply operation, bipolar operation achievable using circuit shown Figure circuit shown been configured achieve output voltage range Rail-to-rail operation amplifier output achievable using AD820 OP295 output amplifier.
0.1µF 10µF
MICROWIRE*
AD7303*
SYNC SCLK
VOUT 0.1µF
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7303 Microwire Interface
APPLICATIONS Typical Application Circuit
AD7303
SCLK VOUTA
Figure shows typical setup AD7303 when using external reference. reference range AD7303 from VDD/2 Higher values reference incorporated will saturate output both bottom transfer function. From input output AD7303 there gain two. Suitable references operation AD780 REF192. operation, suitable external reference would AD589, 1.23 bandgap reference.
AD780/ REF192 WITH AD589 WITH SERIAL INTERFACE
SYNC
Figure Bipolar Operation Using AD7303
output voltage input code calculated follows:
R4*VREF/R3
0.1µF
10µF
where decimal equivalent code loaded VREF reference voltage input.
VOUTA
VOUT 0.1µF
AD7303
SCLK AD780/ REF192 WITH AD589 WITH SERIAL INTERFACE SYNC VOUTB
With VREF VOUT D/256)
Opto-Isolated Interface Process Control Applications
Figure AD7303 Using External Reference
AD7303 also used with internally derived VDD/2 reference. Reference selection through INT/EXT 16-bit input word. internal reference, when selected, also provided output decoupled this point with capacitor noise reduction purposes. references also applied external references AD7303. AD7303 limited multiplying capability, multiplying bandwidth achievable.
AD7303 versatile 3-wire serial interface making ideal generating accurate voltages process control industrial applications. noise, safety requirements distance, necessary isolate AD7303 from controller. This easily achieved using opto-isolators, which will provide isolation excess serial loading structure AD7303 makes ideally suited optoisolated applications. Figure shows opto-isolated interface AD7303 where DIN, SCLK SYNC driven from opto-couplers. this application reference AD7303 internal VDD/2 reference. being decoupled with ceramic capacitor noise reduction purposes.
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AD7303
REGULATOR POWER 10µF 0.1µF
AD7303 Digitally Programmable Window Detector
SCLK SCLK 0.1µF SYNC SYNC VOUTA
digitally programmable upper/lower limit detector using DACs AD7303 shown Figure upper lower limits test loaded DACs which, turn, limits CMP04. signal input within programmed window, will indicate fail condition.
0.1µF 10µF FAIL 0.1µF VOUTA PASS
AD7303
DATA AGND
VOUTB
SYNC SCLK SYNC SCLK
AD7303
CMP04
PASS/FAIL
VOUTB
74HC05
Figure AD7303 Opto-Isolated Interface
Decoding Multiple AD7303
Figure Window Detector Using AD7303
Programmable Current Source
SYNC AD7303 used applications decode number DACs. this application, DACs system receive same serial clock serial data, only SYNC DACs will active time allowing access channels this eight-channel system. 74HC139 used 4-line decoder address DACs system. prevent timing errors from occurring, enable input should brought inactive state while coded address inputs changing state. Figure shows diagram typical setup decoding multiple AD7303 devices system.
AD7303
SYNC ENABLE CODED ADDRESS SCLK
Figure shows AD7303 used control element programmable current source. this circuit, full-scale current output voltage from applied across current setting resistor series with full-scale setting resistor Suitable transistors place feedback loop amplifier include BC107 2N3904, which enable current source operate from VSOURCE operating range determined operating characteristics transistor. Suitable amplifiers include AD820 OP295, both having rail-to-rail operation their outputs. current digital input code calculated follows: VREF D/(5E 256)
SCLK
0.1µF
10µF
AD7303
SYNC SCLK
VSOURCE LOAD
VOUT 0.1µF
VOUTA
74HC139
DGND
AD7303
SCLK SYNC
AD820/ OP295 4.7k
AD7303
SYNC SCLK
AD780/ REF192 WITH
SERIAL INTERFACE
AD7303
SYNC SCLK
Figure Programmable Current Source
Figure Decoding Multiple AD7303 Devices System
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AD7303
Power Supply Bypassing Grounding
circuit where accuracy important, careful consideration power supply ground return layout helps ensure rated performance. printed circuit board which AD7303 mounted should designed that analog digital sections separated, confined certain areas board. AD7303 system where multiple devices require AGND DGND connection, connection should made point only. star ground point should established closely possible AD7303. AD7303 should have ample supply bypassing parallel with supply located closely package possible, ideally right against device. capacitors tantalum bead type. capacitor should have Effective Series Resistance (ESR) Effective Series
Inductance (ESI), like common ceramic types that provide impedance path ground high frequencies handle transient currents internal logic switching. power supply lines AD7303 should large trace possible provide impedance paths reduce effects glitches power supply line. Fast switching signals such clocks should shielded with digital ground avoid radiating noise other parts board, should never near reference inputs. Avoid crossover digital analog signals. Traces opposite sides board should right angles each other. This reduces effects feedthrough through board. microstrip technique best, always possible with double-sided board. this technique, component side board dedicated ground plane while signal traces placed solder side.
AD7303 68HC11 Interface Program Source Code
PORTC DDRC PORTD DDRD SPCR SPSR SPDR Variables: eight MSBs, Control BYTE eight LSBs, Data BYTE requires 2*8-bit Writes DIN1 DIN2 INIT LDAA STAA LDAA STAA LDAA STAA PORTD #$00 SCLK low, Initialize Port outputs -14- REV. PORTC #$80 DDRC #$80 SYNC High Initialize Port Outputs SYNC enabled output $C000 #$CFFF Start users page BYTE INT/EXT, LDAC, PDB, PBA, A/B, CR1, CR0" BYTE DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0" $102A $1029 $1009 $1028 $1007 $1008 $1003 Port Control Register "SYNC, Port Data Direction Port Data Register SCLK, DIN, Port Data Direction Control Register "SPIE, SPE, DWOM, MSTR, CPOL, CPHA, SPR1, SPR0" Status Register "SPIF, WCOL, MODF, Data Register, Read Buffer, Write Shifter
AD7303
LDAA LDAA STAA UPDATE PSHX PSHY PSHA LDAA STAA LDAA STAA BCLR TRANSFER WAIT LDAA *Execute instruction BSET PULA PULY PULX Return main program. PORTC,Y Bring SYNC back high. Restore registers. #DIN TRANSFER Increment counter transfer second byte. bits transferred? not, transfer second BYTE. SPSR WAIT Wait SPIF indicate that transfer been completed. SPIF SPCR. SPIF automatically reset state when status register read. LDAA STAA PORTC,Y SPDR Assert SYNC. BYTE transfer SPI. Write register start transfer. #DIN1 #$1000 Stack pointer first first byte send Stack pointer chip registers. #$00 #$AA Control Word Load both registers from shift register with internal reference selected. Data Word Save relevant registers. UPDATE #$E000 Update AD7303 output. Restart. #$53 SPCR Master mode, CPOL=0, CPHA=0, Clock rate =E/32 #$18 SCLK enabled outputs
REV.
-15-
AD7303
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
8-Pin Plastic (N-8)
C2224-12-1/97
0.195 (4.95) 0.115 (2.93)
0.028 (0.71) 0.016 (0.41)
0.430 (10.92) 0.348 (8.84)
0.280 (7.11) 0.240 (6.10)
0.210 (5.33) 0.160 (4.06) 0.115 (2.93)
0.060 (1.52) 0.015 (0.38) 0.130 (3.30) SEATING PLANE
0.325 (8.25) 0.300 (7.62)
0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15)
0.015 (0.381) 0.008 (0.204)
8-Lead SOIC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
SEATING PLANE
0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35)
0.0098 (0.25) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
8-Lead microSOIC (RM-8)
0.122 (3.10) 0.114 (2.90)
0.122 (3.10) 0.114 (2.90)
0.199 (5.05) 0.187 (4.75)
0.0256 (0.65) 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84)
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PRINTED U.S.A.
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