Parallel Input Dual Voltage Output 8-Bit AD7302 AD7302 INPUT

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Parallel Input Dual Voltage Output 8-Bit AD7302 AD7302 INPUT

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FEATURES 8-Bit DACs Package 20-Lead DIP/SOIC/TSSOP Package +2.7 +5.5 Operation Internal External Reference Capability Power-Down Function Parallel Interface On-Chip Output Buffer Rail-to-Rail Operation Power Operation Power-Down APPLICATIONS Portable Battery Powered Instruments Digital Gain Offset Adjustment Programmable Voltage Current Sources Programmable Attenuators
Parallel Input Dual Voltage Output 8-Bit AD7302
AD7302
INPUT REGISTER REGISTER VOUTA
INPUT REGISTER
REGISTER
VOUTB
CONTROL LOGIC
POWER RESET AGND
LDAC
REFIN
DGND
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
AD7302 dual, 8-bit voltage that operates from single +2.7 +5.5 supply. on-chip precision output buffers allow outputs swing rail rail. AD7302 parallel microprocessor DSP-compatible interface with high speed registers double buffered interface logic. Data loaded registers rising edge selects either Reference selection AD7302 either internal reference derived from external reference applied REFIN pin. Both DACs simultaneously updated using asynchronous LDAC input cleared using asynchronous input. power consumption this part makes ideally suited portable battery operated equipment. power consumption less than reducing powerdown mode. AD7302 available 20-pin plastic dual-in-line package, 20-lead SOIC 20-lead TSSOP package.
Power, Single Supply Operation. This part operates from single +2.7 +5.5 supply typically consumes making ideal battery powered applications. on-chip output buffer amplifiers allow outputs DACs swing rail rail with settling time typically Internal external reference capability. High speed parallel interface. Power-Down Capability. When powered down consumes less than 25°C. Packaged 20-lead DIP, SOIC TSSOP packages.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 1997
AD7302-SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Full-Scale Error Zero Code Error 25°C Gain Error3 Zero Code Temperature Coefficient REFERENCE INPUT REFIN Input Range REFIN Input Impedance OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Slew Rate Digital Analog Glitch Impulse Digital Feedthrough Digital Crosstalk Analog Crosstalk Output Impedance Short Circuit Current Power Supply Rejection Ratio4 LOGIC INPUTS Input Current VINL, Input Voltage VINL, Input Voltage VINH, Input High Voltage VINH, Input High Voltage Capacitance POWER REQUIREMENTS 25°C TMIN TMAX 25°C TMIN TMAX (Full Power-Down) 25°C TMIN TMAX -0.75
(VDD +2.7 +5.5 Internal Reference; unless otherwise noted)
Units Bits µV/°C V/µs nV-s nV-s nV-s min/max Conditions/Comments
GND;
Versions1
Note Guaranteed Monotonic Zeroes Loaded Register
VDD/2 0.0003 2.7/5.5
Typically Change Around Major Carry
Both DACs Active Excluding Load Currents Typically Figures Typically Figures Figure
NOTES Temperature ranges follows: Version: -40°C +105°C. Relative Accuracy calculated using reduced code range 245. Gain error specified between Codes 245. actual error Code typically LSB. Guaranteed characterization product release, production tested. Specifications subject change without notice.
REV.
AD7302 TIMING CHARACTERISTICS1, specifications
Parameter Limit TMIN, Version)
(VDD +2.7 +5.5 Reference Internal VDD/2 Reference; unless otherwise noted)
Units Conditions/Comments Address Write Setup Time Address Valid Write Hold Time Chip Select Write Setup Time Chip Select Write Hold Time Write Pulse Width Data Setup Time Data Hold Time Write LDAC Setup Time LDAC Pulse Width Pulse Width
NOTES Sample tested +25°C ensure compliance. input signals specified with (10% timed from voltage level (VIL )/2. should exceed digital input. Figure
D7-D0
LDAC
Figure Timing Diagram Parallel Data Write
REV.
AD7302
ABSOLUTE MAXIMUM RATINGS*
+25°C unless otherwise noted)
-0.3 Reference Input Voltage AGND .-0.3 Digital Input Voltage DGND -0.3 AGND DGND -0.3 VOUTA, VOUTB AGND -0.3 Operating Temperature Range Commercial Version) -40°C +105°C Storage Temperature Range -65°C +150°C Junction Temperature .+150°C Plastic Package, Power Dissipation Thermal Impedance 102°C/W Lead Temperature (Soldering, sec) +260°C
TSSOP Package, Power Dissipation Thermal Impedance 143°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared sec) .+220°C SOIC Package, Power Dissipation Thermal Impedance 74°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared sec) .+220°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7302 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
ORDERING GUIDE
Model AD7302BN AD7302BR AD7302BRU
Temperature Range -40°C +105°C -40°C +105°C -40°C +105°C
Package Options* N-20 R-20 RU-20
Plastic DIP; Small Outline; =Thin Shrink Small Outline.
REV.
AD7302
FUNCTION DESCRIPTIONS
Mnemonic Function D7-D0 LDAC Parallel Data Inputs. Eight-bit data loaded input register AD7302 under control Chip Select. Active logic input. Write Input. active logic input used conjunction with write data selected register. Select. Address used select writing either Active input used part into power mode reducing current consumption less than Load Logic Input. When this logic input taken both outputs simultaneously updated with contents their registers. LDAC permanently tied low, DACs updated rising edge Asynchronous Clear Input (Active Low). When this input taken registers loaded with zeroes outputs cleared zero volts. Power Supply Input. These parts operated from should decoupled AGND. External Reference Input. This used reference both DACs. range this reference input REFIN directly tied internal reference selected. Analog Ground reference point return point analog current part. Analog output voltage from output amplifier swing rail rail output. Analog output voltage from output amplifier swing rail rail output. Digital Ground reference point return point digital current part.
CONFIGURATION
REFIN AGND VOUTB VOUTA DGND
(MSB)
DGND VOUTA VOUTB AGND
AD7302
REFIN
VIEW (Not Scale) (LSB) LDAC
REV.
AD7302
TERMINOLOGY
INTEGRAL NONLINEARITY DIGITAL FEEDTHROUGH
DACs, relative accuracy endpoint nonlinearity measure maximum deviation, LSBs, from straight line passing through endpoints transfer function. graphical representation transfer curve shown Figure
DIFFERENTIAL NONLINEARITY
Digital Feedthrough measure impulse injected into analog output from digital inputs same DAC, measured when updated. specified nV-s measured with full-scale code change data bus, i.e., from vice versa.
DIGITAL CROSSTALK
Differential Nonlinearity difference between measured change ideal change between adjacent codes. specified differential nonlinearity maximum ensures monotonicity.
ZERO CODE ERROR
Digital Crosstalk glitch impulse transferred output converter digital code change another DAC. specified nV-s.
ANALOG CROSSTALK
Analog Crosstalk change output response change output other DAC. measured LSBs.
POWER SUPPLY REJECTION RATIO (PSRR)
Zero Code Error measured output voltage from VOUT either when zero code (all zeros) loaded latch. combination offset errors output amplifier. Zero scale error expressed LSBs.
GAIN ERROR
This measure span error DAC. deviation slope transfer characteristic from ideal, expressed percent full-scale value. includes full-scale errors offset errors.
DIGITAL-TO-ANALOG GLITCH IMPULSE
This specification indicates output affected changes power supply voltage. Power supply rejection ratio quoted terms change output change full-scale output DAC. varied 10%.
Digital-to-Analog Glitch Impulse impulse injected into analog output when digital inputs change state with selected LDAC used update DAC. normally specified area glitch nV-s measured when digital input code changed major carry transition.
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Typical Performance Characteristics-AD7302
VOUT SINK CURRENT INTERNAL REFERENCE LOADED WITH 00HEX 4.92 4.84 4.76 VOUT Volts VOUT Volts 4.68 4.52 4.44 4.36 4.28 INTERNAL REFERENCE REGISTER LOADED WITH FFHEX +25°C SOURCE CURRENT 3.25 2.75 2.25 1.75 1.25 INTERNAL REFERENCE REGISTER LOADED WITH FFHex +25°C SOURCE CURRENT
Figure Output Sink Current Capability with
Figure Output Source Current Capability with
Figure Output Source Current Capability with
0.45 0.35
BOTH DACS ACTIVE INTERNAL REFERENCE USED +25°C
ERROR
5.5V
ERROR LSBs
0.25 0.15
3.3V INTERNAL REFERENCE LOGIC INPUTS BOTH DACS ACTIVE
LOGIC INPUTS
ERROR 0.05 REFERENCE VOLTAGE Volts
LOGIC INPUTS Volts
TEMPERATURE
Figure Relative Accuracy External Reference
Figure Typical Supply Current Temperature
Figure Typical Supply Current Supply Voltage
ATTENUATION EXTERNAL SINEWAVE REFERENCE REGISTER LOADED WITH FFHEX +25°C FREQUENCY
VOUT VOUT VOUT AD7302 POWER-UP TIME INTERNAL REFERENCE POWER-DOWN INITIALLY 2V/div, 5V/Div, TIME BASE µs/Div
INTERNAL VOLTAGE REFERENCE FULL SCALE CODE CHANGE 00H-FFH +25°C 20mV TIME BASE ns/Div
Figure Large Scale Signal Frequency Response
Figure Full-Scale Settling Time
Figure Exiting Power-Down (Full Power-Down)
REV.
AD7302
ZERO CODE ERROR
5.5V LOADED WITH ZEROES INTERNAL REFERENCE
INTERNAL VOLTAGE REFERENCE STEP CHANGE
VOUT
5.00V 5.00V
5.00V M20.0ms
5.00V, 50.0mV, 250ns
TEMPERATURE
Figure Power-On-RESET
Figure Zero Code Error Temperature
Figure Small-Scale Settling Time
ERROR -0.1 -0.2 -0.3 -0.4 -0.5 INPUT CODE 245) INTERNAL REFERENCE 100pf. LOAD LIMITED CODE RANGE (10-245) +25°C
ERROR INTERNAL REFERENCE -0.1 -0.2 -0.3 -0.4 TEMPERATURE -0.5 TEMPERATURE INTERNAL REFERENCE
ERROR
-0.1 -0.2 -0.3 -0.4
-0.5
Figure Integral Linearity Plot
Figure Typical Temperature
Figure Typical Temperature
POWER-DOWN CURRENT
1000
LOGIC INPUTS
REFERENCE ERROR
TEMPERATURE
TEMPERATURE
Figure Typical Internal Reference Error Temperature
Figure Power-Down Current Temperature
REV.
AD7302
GENERAL DESCRIPTION
Section AD7302 dual 8-bit voltage output digital-to-analog converter. architecture consists reference amplifier, current source followed current-to-voltage converter capable generating rail-to-rail voltages output DAC. Figure shows block diagram basic architecture.
AD7302
REFIN REFERENCE AMPLIFIER CURRENT 11.7k 11.7k
internal reference selected tying REFIN VDD. external reference used, this directly applied REFIN pin; this below internal circuitry will select this externally applied reference reference source DAC.
Digital Interface
AD7302 contains fast parallel interface allowing this dual interface industry standard microprocessors, microcontrollers machines. There modes which this parallel interface configured update outputs. simultaneous update mode allows simultaneous updating both outputs. automatic update mode allows each individually updated following write cycle. Figure shows internal logic associated with digital interface. STRB signal internally generated from power reset circuitry during poweron reset phase power-up procedure.
Figure Architecture
Both outputs internally buffered these output buffer amplifiers have rail-to-rail output characteristics. output amplifier capable driving load both ground parallel with ground. reference selection either internally generated from externally applied through REFIN pin. comparator REFIN detects whether required reference internally generated reference externally applied voltage REFIN pin. REFIN connected VDD, reference selected internally generated VDD/2 reference. When externally applied voltage more than volt below VDD, comparator selection switches externally applied voltage REFIN pin. range external reference input from VDD/2. output voltage from either given VREF (N/256) where: VREF voltage applied external REFIN VDD/2 when internal reference selected. decimal equivalent code loaded register ranges from 255.
STRB CLEAR LDAC LDAC ENABLE CONTROL LOGIC
CLEAR LDAC ENABLE
CONTROL LOGIC
Figure Logic Interface
AD7302 double buffered interface, which allows simultaneous updating outputs. Figure shows block diagram register arrangement within AD7302.
DB7-DB0
INPUT REGISTER DECODER LDAC REGISTER DRIVERS DECODER REGISTER DRIVERS
Reference
AD7302 facility either external reference applied through REFIN internal reference generated from Figure shows reference input arrangement where either internal reference externally applied reference selected.
PMOS COMPARATOR REFIN
CONTROL LOGIC
LOWER NIBBLE
UPPER NIBBLE
Figure Register Arrangement
SELECTED REFERENCE OUTPUT
Figure Reference Selection Circuitry
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AD7302
Automatic Update Mode POWER-ON RESET
this mode operation LDAC signal permanently tied low. state LDAC sampled rising edge LDAC being allows selected register automatically updated rising edge output update occurs rising edge Figure shows timing associated with automatic update mode operation also status various registers during this frame.
AD7302 power-on reset circuit designed allow output stability during power-up. This circuit holds DACs reset state until write takes place DAC. reset state zeros latched into input registers each registers transparent mode, thus output both DACs held ground potential until write takes place DAC. power-on reset circuitry generates STRB signal, which gating signal used within logic identify power-on condition.
POWER-DOWN FEATURES
D7-D0 LDAC (MLE) HOLD TRACK HOLD
(SLE)
TRACK
HOLD
TRACK
VOUT
Figure Timing Register Arrangement Automatic Update Mode
Simultaneous Update Mode
AD7302 power-down feature. This implemented exercising external pin; active signal puts complete into power-down mode. When power-down current consumption device reduced 25°C over temperature, making device suitable portable battery powered equipment. When power-down activated, reference bias servo loop output amplifiers with their associated linear circuitry powered down, reference resistors open circuited further reduce power consumption. output sees load approximately when power-down mode shown Figure contents data registers unaffected when power-down mode. device comes power-down typically (see Figure 10).
11.7k IDAC 11.7k VREF
this mode operation LDAC signal used update both outputs simultaneously. state LDAC sampled rising edge LDAC high, automatic update mode disabled both latches updated time after write taking LDAC low. output update occurs falling edge LDAC. LDAC must taken back high again before next data transfer takes place. Figure shows timing associated with simultaneous update mode operation also status various registers during this frame.
Figure Output Stage During Power-Down
Analog Outputs
D7-D0 LDAC
AD7302 contains independent voltage output DACs with 8-bit resolution rail-to-rail operation. output buffer provides gain output. Figures show source sink capabilities output amplifier. slew rate output amplifier typically V/µs fullscale settling bits with capacitive load typically input coding straight binary. Table shows binary transfer function AD7302. Figure shows transfer function binary coding. output voltage expressed
TRACK HOLD
(MLE)
HOLD
TRACK
HOLD
(SLE)
HOLD
VOUT VREF (N/256) where: decimal equivalent binary input code. ranges from 255.
VOUT
Figure Timing Register Arrangement Simultaneous Update Mode
-10-
REV.
AD7302
VREF voltage applied external REFIN when external reference selected VDD/2 internal reference used.
Table Output Voltage Selected Input Codes
0.1µF 10µF
Digital Input 1111 1111 1111 1110 1000 0001 1000 0000 0111 1111 0000 0001 0000 0000
AGND DGND VOUTA
VOUTA
Analog Output 255/256 VREF 254/256 VREF 129/256 VREF VREF 127/256 VREF VREF/256
AD7302
D7-D0 DATA CONTROL INPUTS VOUTB LDAC VOUTB
Figure Typical Configuration Selecting Internal Reference
2.VREF
OUTPUT VOLTAGE
VREF
Figure shows typical setup AD7302 when using external reference. reference range AD7302 from Higher values reference incorporated, will saturate output both bottom transfer function. There gain from input output AD7302. Suitable references operation AD780 REF192. operation suitable external reference would AD589 1.23 bandgap reference.
0.1µF 10µF
INPUT CODE
VOUT 0.1µF
AGND DGND VOUTA
VOUTA
Figure Transfer Function
AD780/REF192 WITH AD589 WITH D7-D0 DATA
AD7302
VOUTB LDAC VOUTB
Figure shows typical setup AD7302 when using internal reference. internal reference selected tying REFIN Internally reference section there reference detect circuit that will select internal based voltage connected REFIN pin. REFIN within threshold voltage PMOS device (approximately internal reference selected. When REFIN voltage more than below externally applied voltage this used reference DAC. internal reference AD7302 VDD/2, output current voltage converter within AD7302 provides gain two. Thus output range from VDD, based Table
CONTROL INPUTS
Figure Typical Configuration Using External Reference
REV.
-11-
AD7302
MICROPROCESSOR INTERFACING AD7302-ADSP-2101/ADSP-2103 Interface
ADDRESS ADDR DECODE A+1**
Figure shows interface between AD7302 ADSP-2101/ADSP-2103. fast interface timing associated with AD7302 allows easy interface ADSP-2101/ ADSP-2103.
DMA14 ADDRESS DMA0 ADDR DECODE A+1**
TMS32020
STRB
AD7302*
LDAC
ADSP-2101*/ ADSP-2103*
AD7302*
DMD15 DATA DMD0 **ADDITIONAL CIRCUITRY OMITTED CLARITY. DECODED ADDRESS **A+1 DECODED ADDRESS
LDAC
Figure AD7302-TMS32020 Interface
DMD15 DATA DMD0 **ADDITIONAL CIRCUITRY OMITTED CLARITY. DECODED ADDRESS **A+1 DECODED ADDRESS
Figure AD7302-ADSP-2101/ADSP-2103 Interface
addresses decoded select loading data either LDAC permanently tied this circuit, selected output updated rising edge signal. Data loaded AD7302 input register using following ADSP-21xx instruction: (DAC) ADSP-21xx Register. Decoded Address.
AD7302-TMS32020 Interface
circuit shown LDAC hardwired low, thus selected output updated rising edge Some applications require simultaneous updating both DACs AD7302. this case LDAC signal driven from external timer controlled microprocessor. option simultaneous updating decode LDAC from address that write operation this address will simultaneously update both outputs. simple gate with input driven from decoded address second input from signal will implement this function.
AD7302-8051/8088 Interface
Figure shows serial interface between AD7302 8051/8088 processors. address decoder used decode addresses
ADDRESS ADDR DECODE A+1**
Figure shows interface between AD7302 TMS32020. address decoder used decode addresses Data loaded AD7302 using following instruction: DAC, Decoded Address. Data Memory Address.
AD7302*
8051/8088
OCTAL LATCH ADDRESS/DATA **ADDITIONAL CIRCUITRY OMITTED CLARITY. DECODED ADDRESS **A+1 DECODED ADDRESS
Figure AD7302-8051//8088 Interface
-12-
REV.
AD7302
APPLICATIONS Bipolar Operation Using AD7302
DATA
AD7302
VOUTA
AD7302 been designed single supply operation, bipolar operation achievable using circuit shown Figure circuit shown been configured achieve output voltage range Rail-to-rail operation amplifier output achievable using AD820 OP295 output amplifier. output voltage input code calculated follows:
[(1+R4/R3) (R2/(R1+R2) VREF D/256)] VREF/R3
VOUTB
ENABLE CODED ADDRESS
AD7302
VOUTA
74HC139
DGND
VOUTB
where decimal equivalent code loaded VREF reference voltage input. With VREF VOUT D/256)
0.1µF 10µF VOUT 0.1µF AD820/ OP295 VOUTA
AD7302
VOUTA
VOUTB
AD7302
VOUTA
VOUTB
Figure Decoding Multiple AD7302 DACs System
AD7302 Digitally Programmable Window Detector
AD7302
AD780/REF192 WITH AD589 WITH
AGND
DGND
digitally programmable upper/lower limit detector using DACs AD7302 shown Figure upper lower limits test loaded DACs which turn limits CMP04. signal input within programmed window will indicate fail condition.
0.1µF 10µF FAIL PASS
Figure Bipolar Operation Using AD7302
Decoding Multiple AD7302 System
DVDD LDAC
REFIN
AD7302
VOUTA PASS/FAIL
AD7302 used applications decode number DACs. this application DACs system receive same input data, only DACs will active time allowing access channels system. 74HC139 used two-to-four line decoder address DACs system. prevent timing errors from occurring, enable input should brought inactive state while coded address inputs changing state. Figure shows diagram typical setup decoding multiple AD7302 devices system. built-in power-on reset circuit AD7302 ensures that outputs DACs system power with zero volts their outputs.
VOUTB 74HC05
CMP04 DGND AGND
Figure Programmable Window Detector
REV.
-13-
AD7302
Programmable Current Source
0.1µF 10µF 51.2k VOUT 0.1µF VOUTA VOUTB AD780/REF192 WITH AD589 WITH AGND DGND 51.2k AD820/ OP295 VOUT
Figure shows AD7302 used control element programmable current source. this circuit full-scale current output voltage from applied across current setting resistor series with full-scale setting resistor Transistors suitable place feedback loop amplifier include BC107 2N3904, which enable current source operate from VSOURCE operating range determined operating characteristics transistor. Suitable amplifiers include AD820 OP295 both having railto-rail operation their outputs. current digital input code calculated follows:
AD7302
VREF D/(5E 256)
0.1µF 10µF
Figure Coarse/Fine Adjust Circuit
Power Supply Bypassing Grounding
VOUT 0.1µF VOUTA AD820/ OP295
VSOURCE
LOAD
AD7302
AD780/REF192 WITH
AGND DGND 4.7k
circuit where accuracy important, careful consideration power supply ground return layout helps ensure rated performance. printed circuit board which AD7302 mounted should designed analog digital sections separated confined certain areas board. AD7302 system where multiple devices require AGND DGND connection, connection should made point only, star ground point that should established closely possible AD7302. AD7302 should have ample supply bypassing parallel with supply located close package possible, ideally right against device. capacitors tantalum bead type. capacitor should have Effective Series Resistance (ESR) Effective Series Inductance (ESI), such common ceramic types, which provide impedance path ground high frequencies handle transient currents internal logic switching. power supply lines AD7302 should large trace possible provide impedance paths reduce effects glitches power supply line. Fast switching signals like clocks should shielded with digital ground avoid radiating noise other parts board should never near reference inputs. Avoid crossover digital analog signals. Traces opposite sides board should right angles each other. This reduces effects feedthrough through board. microstrip technique best, always possible with double-sided board. this technique, component side board dedicated ground plane while signal traces placed solder side.
Figure Programmable Current Source
Coarse Fine Adjustment Using AD7302
DACs AD7302 paired together form coarse fine adjustment function shown Figure this circuit used provide coarse function while used provide fine adjustment. Varying ratio will vary relative effect coarse fine tune elements circuit. resistor values shown resolution giving fine tune range approximately LSBs operation with reference amplifiers shown allow rail-to-rail output voltage achieved output. typical application such circuit would setpoint controller.
-14-
REV.
AD7302
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
20-Lead Plastic (N-20)
1.060 (26.90) 0.925 (23.50)
0.280 (7.11) 0.240 (6.10)
0.210 (5.33) 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54)
0.060 (1.52) 0.015 (0.38) 0.130 (3.30) 0.070 (1.77) SEATING 0.045 (1.15) PLANE
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.015 (0.381) 0.008 (0.204)
20-Lead (R-20)
0.5118 (13.00) 0.4961 (12.60)
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.0291 (0.74) 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
20-Lead TSSOP (RU-20)
0.260 (6.60) 0.252 (6.40)
0.177 (4.50) 0.169 (4.30)
0.006 (0.15) 0.002 (0.05)
0.0433 (1.10) 0.0256 (0.65) 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
0.256 (6.50) 0.246 (6.25)
SEATING PLANE
0.028 (0.70) 0.020 (0.50)
REV.
-15-
-16-
C2990-12-4/97
PRINTED U.S.A.

Parallel Input Dual Voltage Output 8-Bit AD7302 AD7302 INPUT

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