AGND DGND REFB VREF FEATURES Four 12-Bit DACs Package 4-Quadrant
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LC2MOS +3.3 V/+5 Power, Quad 12-Bit AD7564
AGND DGND REFB VREF
FEATURES Four 12-Bit DACs Package 4-Quadrant Multiplication Separate References Single Supply Operation Guaranteed Specifications with +3.3 V/+5 Supply Power Versatile Serial Interface Simultaneous Update Capability Reset Function 28-Pin SOIC, SSOP Packages APPLICATIONS Process Control Portable Instrumentation General Purpose Test Equipment
FSIN CLKIN SDIN
INPUT LATCH
LATCH
IOUT1 IOUT2
INPUT LATCH
LATCH
IOUT1 IOUT2
INPUT LATCH
LATCH
IOUT1 IOUT2
INPUT LATCH
LATCH
IOUT1 IOUT2
CONTROL LOGIC INPUT SHIFT REGISTER
LDAC
AD7564
SDOUT
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
AD7564 contains four 12-bit DACs monolithic device. DACs standard current output with separate VREF, IOUT1, IOUT2 terminals. These DACs operate from single +3.3 supply. AD7564 serial input device. Data loaded using FSIN, CLKIN SDIN. address pins device address, this feature used simplify device loading multi-DAC environment. Alternatively, ignored serial capability used configure daisy-chained system. DACs simultaneously updated using asynchronous LDAC input, they cleared asserting asynchronous input. device packaged 28-pin SOIC, SSOP packages.
AD7564 contains four 12-bit current output DACs with separate VREF inputs. AD7564 operated from single +3.3 supply. Simultaneous update capability reset function available. AD7564 features fast, versatile serial interface compatible with modern microprocessors microcomputers. power,
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood. 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7564-SPECIFICATIONSA +4.75 +5.25
Normal Mode
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Gain Error +25°C TMIN TMAX Gain Temperature Coefficient2 Output Leakage Current IOUT1 +25°C TMIN TMAX REFERENCE INPUT Input Resistance Ladder Resistance Mismatch DIGITAL INPUTS VINH, Input High Voltage VINL, Input Voltage IINH, Input Current CIN, Input Capacitance2 DIGITAL OUTPUT (SDOUT) Output Voltage (VOL) Output High Voltage (VOH) POWER REQUIREMENTS Range Power Supply Rejection2 Gain/VDD
OUT1
OUT1D
IOUT2A IOUT2D AGND VREF TMIN TMAX,
Test Conditions/Comments VREF/212 2.44 when VREF Grades Guaranteed Monotonic Over Temperature
unless otherwise noted)
Grade1 Units Bits LSBs LSBs FSR/°C FSR/°C
4.75/5.25
min/V Load Circuit Figure Typical Input Resistance Typically 0.6%
Part Functions from 5.25
VINH VDD, VINL Input Levels Typically
NOTES Temperature range follows: Version: -40°C +85°C. production tested. Guaranteed characterization initial product release. Specifications subject change without notice.
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AD7564 Biased Mode1
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Gain Error +25°C TMIN TMAX Gain Temperature Coefficient3 Output Leakage Current IOUT1 +25°C TMIN TMAX Input Resistance IOUT2 Pins DIGITAL INPUTS VINH, Input High Voltage VINH, Input High Voltage +3.3 VINL, Input Voltage VINL, Input Voltage +3.3 IINH, Input Current CIN, Input Capacitance3 DIGITAL OUTPUT (SDOUT) Output Voltage (VOL) Output Voltage (VOL) Output High Voltage (VOH) Output High Voltage (VOH) POWER REQUIREMENTS Range Power Supply Sensitivity3 Gain/VDD
(VDD +5.5 VIOUT1 VIOUT2 1.23 AGND VREF 2.45 TMIN TMAX, unless otherwise noted)
Grade2 Units Bits Test Conditions/Comments (VIOUT2 VREF)/212 when VIOUT2 1.23 VREF Grades Guaranteed Monotonic Over Temperature
LSBs LSBs FSR/°C FSR/°C Terminology Section
3/5.5
min/V Load Circuit Figure +3.3 +3.3 This Varies with Input Code
VINH min, VINL max; SDOUT Open Circuit typically with VINH min, VINL max; SDOUT Open Circuit
NOTES These specifications apply with devices biased 1.23 single supply applications. model numbering reflects this means "-B" suffix (for example: AD7564AR-B). Figure example Biased Mode Operation. Temperature ranges follows: Version: -40°C +85°C. production tested. Guaranteed characterization initial product release. Specifications subject change without notice.
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AD7564 Performance Characteristics Normal Mode
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Channel-to-Channel Isolation Digital Crosstalk Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density
(VDD +4.75 +5.25 VIOUT1 VIOUT2 AGND VREF rms, sine wave; output AD843; TMIN TMAX, unless otherwise noted. These characteristics included Design Guidance subject test.)
Grade Units nV-s nV-s nV-s nV/Hz Test Conditions/Comments 0.01% Full-Scale Range. Latch Alternately Loaded with Measured with VREF Register Alternately Loaded with VREF p-p, Sine Wave. Latch Loaded with Loaded Loaded Feedthrough from Reference Others with p-p, Sine Wave Applied Effect Code Transition Nonselected DACs Feedthrough Output with FSIN High Square Wave Applied SDIN SCLK VREF rms, Sine Wave Loaded DAC. VREF Output ADOP07
Performance Characteristics Biased Mode
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time Digital Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density
(VDD +5.5 VIOUT1 VIOUT2 1.23 AGND VREF kHz, 2.45 p-p, sine wave biased 1.23 output AD820; TMIN TMAX, unless otherwise noted. These characteristics included Design Guidance subject test.)
Grade Units nV-s nV-s nV/Hz Loaded DAC. VIOUT2 VREF Test Conditions/Comments 0.01% Full-Scale Range. VREF Latch Alternately Loaded with Measured with VIOUT2 VREF Register Alternately Loaded with Latch Loaded with Loaded Loaded Feedthrough Output with FSIN HIGH Square Wave Applied SDIN CLKIN
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AD7564 Timing Specifications1
Parameter
TMIN TMAX unless otherwise noted)
Units Description CLKIN Cycle Time CLKIN High Time CLKIN Time FSIN Setup Time Data Setup Time Data Hold Time FSIN Hold Time SDOUT Valid After CLKIN Falling Edge LDAC, Pulse Width
Limit Limit +3.6 +4.75 +5.25
NOTES production tested. Guaranteed characterization initial product release. input signals specified with (10% VDD) timed from voltage level from voltage level 1.35 measured with load circuit Figure defined time required output cross with
CLKIN(I)
FSIN(I)
SDIN(I) DB15
SDOUT(O) DB15
LDAC,
Figure Timing Diagram
1.6mA
OUTPUT +1.6V 50pF
200µA
Figure Load Circuit Digital Output Timing Specifications
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AD7564
ABSOLUTE MAXIMUM RATINGS +25°C unless otherwise noted) CONFIGURATION DIP, SOIC SSOP Packages
DGND IOUT2 IOUT1 VREF IOUT2 IOUT1 VREF SDOUT LDAC FSIN IOUT2 AGND IOUT1 VREF
DGND -0.3 IOUT1 DGND -0.3 IOUT2 DGND -0.3 AGND DGND -0.3 Digital Input Voltage DGND -0.3 VRFB, VREF DGND Input Current Except Supplies2 Operating Temperature Range Commercial Plastic Versions). -40°C +85°C Storage Temperature Range -65°C +150°C Junction Temperature +150°C Package, Power Dissipation Thermal Impedance 75°C/W Lead Temperature, Soldering sec) 260°C SOIC Package, Power Dissipation Thermal Impedance 75°C/W Lead Temperature, Soldering sec) 260°C Vapor Phase sec) +215°C Infrared sec) +220°C SSOP Package, Power Dissipation Thermal Impedance 100°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared sec) +220°C
NOTES Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Transient currents will cause latch-up.
IOUT2 VIEW IOUT1 (Not Scale) VREF OLKIN SDIN
AD7564
CONNECT
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7564 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
ORDERING GUIDE
Model AD7564BN AD7564BR AD7564BRS AD7564AR-B AD7564ARS-B
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
Linearity Nominal Error (LSBs) Supply Voltage +3.3 +3.3
Package Option* N-28 R-28 RS-28 R-28 RS-28
DIP; SOIC; SSOP.
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AD7564
DESCRIPTIONS
Number
Mnemonic DGND IOUT2C IOUT1C RFBC VREFC IOUT2D IOUT1D RFBD VREFD SDOUT LDAC FSIN
Description Digital Ground. IOUT2 terminal This should normally connect signal ground system. Positive power supply. This IOUT1 terminal Feedback resistor reference input. IOUT2 terminal This should normally connect signal ground system. IOUT1 terminal Feedback resistor reference input. This shift register output allows multiple devices connected daisy chain configuration. Asynchronous input. When this input taken low, latches loaded with Asynchronous LDAC input. When this input taken low, latches simultaneously updated with contents input latches. Level-triggered control input (active low). This frame synchronization signal input data. When FSIN goes low, enables input shift register, data transferred falling edges CLKIN. address bits valid, 12-bit data transferred appropriate input latch sixteenth falling edge after FSIN goes low. Serial data input. device accepts 16-bit word. select bits. device address bits. DB15 contain 12-bit data loaded selected DAC. Clock Input. Data clocked into input shift register falling edges CLKIN. Device address pin. This input association with gives device address. serial input stream correspond this address, data which follows ignored loaded input latch. However, will appear SDOUT irrespective this. Device address pin. This input association with gives device address. reference input. Feedback resistor IOUT1 terminal IOUT2 terminal This should normally connect signal ground system. reference input. Feedback resistor IOUT1 terminal Connect pin. This connects back gates current steering switches. should connected signal ground system. IOUT2 terminal This should normally connect signal ground system.
SDIN
CLKIN
VREFA RFBA IOUT1A IOUT2A VREFB RFBB IOUT1B AGND IOUT2B
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AD7564
TERMINOLOGY Relative Accuracy Output Voltage Settling Time
Relative accuracy endpoint linearity measure maximum deviation from straight line passing through endpoints transfer function. measured after adjusting zero error full-scale error normally expressed Least Significant Bits percentage full-scale reading.
Differential Nonlinearity
This amount time takes output settle specified level full-scale input change. AD7564, specified with AD843 output amp.
Digital Analog Glitch Impulse
Differential nonlinearity difference between measured change ideal change between adjacent codes. specified differential nonlinearity maximum ensures monotonicity.
Gain Error
This amount charge injected into analog output when inputs change state. normally specified area glitch either pA-secs nV-secs, depending upon whether glitch measured current voltage signal. measured with reference input connected AGND digital inputs toggled between
Feedthrough Error
Gain error measure output error between ideal actual device output. measured with after offset error been adjusted expressed Least Significant Bits. Gain error adjustable zero with external potentiometer.
Output Leakage Current
This error capacitive feedthrough from reference input IOUT terminal, when loaded DAC.
Channel-to-Channel Isolation
Channel-to-channel isolation refers proportion input signal from DAC's reference input which appears output other device expressed dBs.
Digital Crosstalk
Output leakage current current which flows ladder switches when these turned off. IOUT1 terminal, measured loading measured loading measuring IOUT1 current. Minimum current will flow IOUT2 line when loaded with This combination switch leakage current ladder termination resistor current. IOUT2 leakage current typically equal that IOUT1.
Output Capacitance
glitch impulse transferred output converter change digital input code other converter defined Digital Crosstalk specified nV-secs.
Digital Feedthrough
When device selected, high frequency logic activity device digital inputs capacitively coupled through device show IOUT subsequently output. This noise digital feedthrough.
This capacitance from IOUT1 AGND.
Table AD7564 Loading Sequence
DB15 DB11 DB10
Table Selection
Function Selected Selected Selected Selected
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Typical Performance Curves-AD7564
NORMAL MODE OPERATION +25°C NORMAL MODE OPERATION +25°C
LSBs
LSBs
VREF Volts
VREF Volts
Figure Differential Nonlinearity Error VREF (Normal Mode)
Figure Integral Nonlinearity Error VREF (Normal Mode)
VREFC SINE WAVE OTHER REFERENCE INPUTS LOADED WITH OTHER DACs LOADED WITH
VOUTB/VOUTC
VREFB OTHER REFERENCE INPUTS SINE WAVE LOADED WITH OTHER DACs LOADED WITH
VOUTB/VOUTC
FREQUENCY
FREQUENCY
Figure Channel-to-Channel Isolation DAC)
Figure Channel-to-Channel Isolation Other DACs)
NORMAL MODE OPERATION AD713 +25°C
GAIN
LOADED WITH +25°C AD711
LOADED WITH
-100
-100
FREQUENCY
100k FREQUENCY
Figure Total Harmonic Distortion Frequency (Normal Mode)
Figure Multiplying Frequency Response Digital Code (Normal Mode)
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AD7564
LSBs +3.3V +25°C AD820 VREF +1.23V (AD589) +3.3V +25°C AD820 VREF +1.23V (AD589)
LSBs
|VREF VBIAS| Volts
|VREF VBIAS| Volts
Figure Integral Nonlinearity Error VREF (Biased Mode)
Figure Differential Nonlinearity Error VREF (Biased Mode)
LSBs
LSBs
+25°C AD820 VBIAS +1.23V (AD589)
+25°C AD820 VBIAS +1.23V (AD589)
|VREF VBIAS| Volts
|VREF VBIAS| Volts
Figure Integral Nonlinearity Error VREF (Biased Mode)
Figure Differential Nonlinearity Error VREF (Biased Mode)
LINEARITY ERROR LSBs
NORMAL MODE +25°C VREF
LINEARITY ERROR LSBs
-0.1
-0.2 -0.3 +3.3V +25°C VBIAS 1.23V VREF 1024 2048 CODE LSBs 3072 4095
-0.4 -0.5
-0.1 1024 2048 CODE LSBs 3072 4095
Figure Codes Linearity Plot (Biased Mode)
Figure Codes Linearity Plot (Normal Mode)
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AD7564
GENERAL DESCRIPTION Section
AD7564 contains four 12-bit current output converters. simplified circuit diagram converters shown Figure
Bringing line resets latches input latches affected that user revert previous analog output desired.
CLKIN FSIN SDIN 16-BIT INPUT SHIFT REGISTER SDOUT
OUT1 OUT2
Figure Input Logic
UNIPOLAR BINARY OPERATION (2-Quadrant Multiplication)
SHOWN
Figure Simplified Circuit Diagram
Figure shows standard unipolar binary connection diagram DACs AD7564. When signal, circuit performs 2-quadrant multiplication. Resistors allow user adjust gain error. Offset removed adjusting output amplifier offset voltage.
RFBA VREFA IOUT1A IOUT2A AD707 AD711 AD843 AD845 VOUT
segmented scheme used whereby MSBs 12-bit data word decoded drive three switches remaining bits data word drive switches standard R-2R ladder configuration. Each switches steers total reference current with remaining current passing through R-2R section. DACs have separate VREF, IOUT1, IOUT2 pins. When output amplifier connected standard configuration Figure output voltage given
AD7564
SIGNAL
NOTES ONLY SHOWN CLARITY. DIGITAL INPUT CONNECTIONS OMITTED. PHASE COMPENSATION (5-15pF) REQUIRED WHEN USING HIGH SPEED AMPLIFIER.
where fractional representation digital word loaded DAC. Thus, AD7564, from 4095/4096.
Interface Section
Figure Unipolar Binary Operation
AD7564 serial input device. Three input signals control serial interface. These FSIN, CLKIN SDIN. timing diagram shown Figure Data applied SDIN clocked into input shift register each falling edge CLKIN. SDOUT shift register output. allows multiple devices connected daisy chain fashion with SDOUT device connected SDIN next device. FSIN frame synchronization device. When sixteen bits have been received input shift register, checked they correspond state pins does, then word accepted. Otherwise, disregarded. This allows user address number AD7564s very simple fashion. 16-bit word determine which four input latches loaded. When LDAC line goes low, four latches device simultaneously loaded with contents their respective input latches outputs change accordingly.
should chosen suit application. example, AD707 ideal very bandwidth applications while AD843 AD845 offer very fast settling time wide bandwidth applications. Appropriate multiple versions these amplifiers used with AD7564 reduce board space requirements. code table Figure shown Table III.
Table III. Unipolar Binary Code Table
Digital Input 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
Analog Output (VOUT Shown Figure -VREF (4095/4096) -VREF (2049/4096) -VREF (2048/4096) -VREF (2047/4096) -VREF (1/4096) -VREF (0/4096)
NOTE Nominal size circuit Figure given (1/4096).
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AD7564
BIPOLAR OPERATION 4-Quadrant Multiplication)
Figure shows standard connection diagram bipolar operation DACs AD7564. coding offset binary shown Table When signal, circuit performs 4-quadrant multiplication. maintain gain error specifications, resistors should ratio matched 0.01%.
RFBA VREFA IOUT1A IOUT2A VOUT
current mode circuit Figure IOUT2 hence IOUT1, biased positive amount VBIAS. circuit operate correctly, ladder termination resistor must connected internally IOUT2. This case with AD7564. output voltage given
RDAC
BIAS
BIAS
varies from 4095/4096, output voltage varies from VOUT VBIAS VOUT VBIAS VIN. VBIAS should impedance source capable sinking sourcing possible variations current IOUT2 terminal without problems.
Voltage Mode Circuit
AD7564
NOTES: SIGNAL
ONLY SHOWN CLARITY. DIGITAL INPUT CONNECTIONS OMITTED. PHASE COMPENSATION (5-15pF) REQUIRED WHEN USING HIGH SPEED AMPLIFIER,
Figure Bipolar Operation (4-Quadrant Multiplication)
Table Bipolar (Offset Binary) Code Table
Digital Input 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
Analog Output (VOUT Shown Figure -VREF (2047/2048) -VREF (1/2048) -VREF (0/2048 -VREF (1/2048) -VREF (2047/2048) -VREF (2048/2048) -VREF
Figure shows AD7564 operating voltage-switching mode. reference voltage, applied IOUT1 pin, IOUT2 connected AGND output voltage available VREF terminal. this configuration, positive reference voltage results positive output voltage; making single supply operation possible. output from voltage constant impedance (the ladder resistance). Thus, necessary buffer output voltage. reference voltage input longer sees constant input impedance, which varies with code. voltage input should driven from impedance source. important note that limited voltages because switches longer have same sourcedrain voltage. result, their on-resistance differs this degrades integral linearity DAC. Also, must negative more than volts internal diode will turn causing possible damage device. This means that full-range multiplying capability lost.
RFBA
NOTE Nominal size circuit Figure given (1/2048).
SINGLE SUPPLY APPLICATIONS
"-B" versions AD7564 specified tested single supply applications. Figure shows typical circuit operation with single +3.3 supply.
RFBA IOUT1A VREFA IOUT2A VOUT
IOUT1A IOUT2A VREFA
VOUT
AD7564
NOTES ONLY SHOWN CLARITY. DIGITAL INPUT CONNECTIONS OMITTED. PHASE COMPENSATION (5-15pF) REQUIRED WHEN USING HIGH SPEED AMPLIFIER.
AD7564
Figure Single Supply Voltage Switching Mode Operation
VBIAS NOTES: ONLY SHOWN CLARITY. DIGITAL INPUT CONNECTIONS OMITTED. PHASE COMPENSATION (5-15pF) REQUIRED WHEN USING HIGH SPEED AMPLIFIER,
Figure Single Supply Current Mode Operation
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AD7564
MICROPROCESSOR INTERFACING AD7564 80C51 Interface AD7564 68HC11 Interface
serial interface between AD7564 80C51 microcontroller shown Figure 80C51 drives SCLK AD7564 while drives serial data line part. FSIN signal derived from port line P3.3. 80C51 provides SBUF register first serial data stream. Therefore, user will have ensure that data SBUF register arranged correctly that data word transmitted AD7564 corresponds loading sequence shown Table When data transmitted part, P3.3 taken low. Data valid falling edge TXD. 80C51 transmits serial data 8-bit bytes with only eight falling clock edges occurring transmit cycle. load data AD7564, P3.3 left after first eight bits transferred second byte data then transferred serially AD7564. When second serial transfer complete, P3.3 line taken high. Note that 80C51 outputs serial data byte format which first. AD7564 expects first. 80C51 transmit routine should take this into account.
Figure shows serial interface between AD7564 68HC11 microcontroller. 68HC11 drives SCLK AD7564 while MOSI output drives serial data line AD7564. FSIN signal derived from port line (PC7 shown). correct operation this interface, 68HC11 should configured such that CPOL CPHA When data transmitted part, taken low. When 68HC11 configured like this, data MOSI valid falling edge SCK. 68HC11 transmits serial data 8-bit bytes (MSB first), with only eight falling clock edges occurring transmit cycle. load data AD7564 left after first eight bits transferred second byte data then transferred serially AD7564. When second serial transfer complete, line taken high.
AD7564*
64HC11*
LDAC FSIN SCLK SDIN
AD7564*
80C51*
P3.5 P3.4 P3.3 LDAC FSIN SCLK
MOSI
*ADDITIONAL PINS OMMITTED CLARITY
SDIN
Figure AD7564 64HC11 Interface
*ADDITIONAL PINS OMMITTED CLARITY
Figure AD7564 80C51 Interface
LDAC AD7564 also controlled 80C51 port outputs. user bring LDAC after every bytes have been transmitted update which been programmed. Alternatively, possible wait until input registers have been loaded (sixteen byte transmits) then update outputs.
Figure LDAC controlled port outputs. with 80C51, each AD7564 updated after each two-byte transfer, else DACs simultaneously updated. This interface suitable both versions 68HC11 microcontroller.
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AD7564
AD7564 ADSP-2101/ADSP-2103 Interface
Figure shows serial interface between AD7564 ADSP-2101/ADSP-2103 digital signal processors. ADSP2101 operates from while ADSP-2103 operates from supplies. These processors operate SPORT Transmit Alternate Framing Mode. following conditions recommended: Internal SCLK; Active Framing Signal; 16-bit word length. Transmission initiated writing word register after SPORT been enabled. data then clocked every rising edge SCLK after goes low. stays until next data transfer.
AD7564*
TMS320C25*
CLKX LDAC FSIN SDIN CLKIN
CLOCK GENERATION *ADDITIONAL PINS OMMITTED CLARITY
AD7564*
ADSP-2101/ ADSP-2103
Figure AD7564 TMS320C25 Interface
APPLICATION HINTS Output Offset
SCLK
LDAC FSIN SDIN CLKIN
*ADDITIONAL PINS OMMITTED CLARITY
Figure AD7564 ADSP-2101/ADSP-2103 Interface
AD7564 TMS320C25 Interface
Figure shows interface circuit TMS320C25 digital signal processor. data clocked processor's Transmit Shift Register CLKX signal. Sixteen-bit transmit format should chosen setting register transmit operation begins when data written into data transmit register TMS320C25. This data will transmitted when line goes while CLKX high going high. data, starting with MSB, then shifted rising edge CLKX. When bits have been transmitted, user update outputs bringing output flag low.
CMOS converters circuits such Figures exhibit code dependent output resistance which turn cause code dependent error voltage output amplifier. maximum amplitude this error, which adds converter nonlinearity, depends VOS, where amplifier input offset voltage. AD7564 maintain specified accuracy with VREF recommended that greater than 10-6) (VREF), over temperature range operation. Suitable amplifiers include ADOP-07, ADOP-27, AD711, AD845 multiple versions these.
Temperature Coefficients
gain temperature coefficient AD7564 maximum value ppm/°C typical value ppm/°C. This corresponds gain shifts LSBs LSBs respectively over 100°C temperature range. When trim resistors used adjust full scale Figures their temperature coefficients should taken into account. further information "Gain Error Gain Temperature Coefficient CMOS Multiplying DACs," Application Note, Publication Number E630c-5-3/86, available from Analog Devices.
High Frequency Considerations
output capacitances AD7564 DACs work conjunction with amplifier feedback resistance pole open loop response. This cause ringing oscillation. Stability restored adding phase compensation capacitor parallel with feedback resistor. This shown Figures
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AD7564
APPLICATIONS Programmable State Variable Filter
circuit Figure (i.e., same code loaded each DAC). Resonant Frequency, 1/(2 R3C1) Quality Factor, (R6/R8) (R2/R5) Bandpass Gain, -R2/R1 Using values shown Figure range range kHz.
AD7564 with multiplying capability fast settling time ideal many types signal conditioning applications. circuit Figure shows state variable filter design. This type filter three outputs: pass, high pass bandpass. particular version shown Figure uses AD7564 control critical parameters Instead several fixed resistors, circuit uses equivalent resistances circuit elements. Thus, Figure controlled 12-bit digital word loaded AD7564. This also case with fixed resistor feedback resistor, RFBB. Equivalent Resistance, (RLADDER 4096)/N where: RLADDER ladder resistance Digital Code Decimal 4096)
10pF
1000pF
1000pF
HIGH PASS OUTPUT
PASS OUTPUT
IOUT1A
IOUT1B
RFBB
VREFB
VREFC
IOUT1C
VREFD
IOUT1D
BAND PASS OUTPUT
VREFA
(R1)
(R2)
(R3)
(R4)
AD7564
IOUT2A IOUT2B AGND IOUT2C IOUT2D
NOTES AD713. DIGITAL INPUT CONNECTIONS OMITTED. COMPENSATION CAPACITOR ELIMINATE GAIN VARIATIONS CAUSED AMPLIFIER GAIN BANDWIDTH LIMITATIONS.
Figure Programmable Order State Variable Filter
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AD7564
MECHANICAL INFORMATION
Dimensions shown inches (mm).
28-Pin (N-28)
C1977-18-10/94
0.042 (1.067) 0.018 (0.457)
0.550 (13.97) 0.530 (13.462) 0.200 (5.080) 1.450 (36.83) 1.440 (36.576) 0.606 (15.39) 0.594 (15.09) 0.160 (4.07) 0.140 (3.56) 0.020 (0.508) 0.015 (0.381) 0.105 (2.67) 0.095 (2.41) 0.065 (1.65) 0.045 (1.14) 0.175 (4.45) 0.120 (3.05) 0.012 (0.305) 0.008 (0.203)
LEADS SOLDER DIPPED TIN-PLATED ALLOY COPPER.
28-Lead SOIC (R-28)
0.299 (7.60) 0.291 (7.39)
0.414 (10.52) 0.398 (10.10)
0.708 (18.02) 0.696 (17.67) 0.096 (2.44) 0.089 (2.26) 0.01 (0.254) 0.006 (0.15)
0.03 (0.76) 0.02 (0.51)
0.050 (1.27)
0.019 (0.49) 0.014 (0.35)
0.013 (0.32) 0.009 (0.23)
LEAD IDENTIFIED DOT. SOIC LEADS WILL EITHER PLATED SOLDER DIPPED ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
28-Lead SSOP (RS-28)
0.212 (5.38) 0.205 (5.207) 0.311 (7.9) 0.301 (7.64)
0.407 (10.34) 0.397 (10.08)
0.07 (1.78) 0.066 (1.67)
0.008 (0.203) 0.002 (0.050)
0.009 (0.229) 0.005 (0.127) LEAD IDENTIFIED DOT. LEADS WILL EITHER PLATED SOLDER DIPPED ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 0.0256 (0.65)
0.03 (0.762) 0.022 (0.558)
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PRINTED U.S.A.
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