CMOS Dual 8-Bit Buffered Multiplying AD7628 GENERAL DESCRIPTION

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CMOS Dual 8-Bit Buffered Multiplying AD7628 GENERAL DESCRIPTION

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FEATURES On-Chip Latches Both DACs Operation DACs Matched Four Quadrant Multiplication TTL/CMOS Compatible from Latch Free (Protection Schottkys Required) APPLICATIONS Disk Drives Programmable Filters Graphics Gain/Attenuation
CMOS Dual 8-Bit Buffered Multiplying AD7628
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
AD7628 monolithic dual 8-bit digital/analog converter featuring excellent DAC-to-DAC matching. available small 0.3" wide 20-pin DIPs 20-terminal surface mount packages. Separate on-chip latches provided each allow easy microprocessor interface. Data transferred into either data latches common 8-bit TTL/CMOS compatible input port. Control input A/DAC determines which loaded. AD7628's load cycle similar write cycle random access memory, device compatible with most 8-bit microprocessors, including 6502, 6809, 8085, Z80. device operates from power supply TTL-compatible over this range. Power dissipation Both DACs offer excellent four quadrant multiplication characteristics with separate reference input feedback resistor each DAC.
matching: since both AD7628 DACs fabricated same time same chip, precise matching tracking between inherent. AD7628's matched CMOS DACs make whole range applications circuits possible, particularly audio, graphics process control areas. Small package size: combining inputs on-chip latches into common data adding select line allowed AD7628 packaged small 20-pin 0.3" wide DIP, 20-pin SOIC, 20-terminal PLCC 20-terminal LCC. TTL-Compatibility: digital inputs TTL-compatible over power supply range.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 1996
AD7628-SPECIFICATIONS +10.8 +15.75 otherwise noted)
VREF unless
Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Gain Error
+125
Units Bits
Test Conditions/Comments
This Endpoint Linearity Specification Grades Guaranteed Monotonic Over Full Operating Temperature Range Measured Using Internal Both Latches Loaded with 11111111. Gain Error Adjustable Using Circuits Figures
Gain Temperature Coefficient Gain/Temperature Output Leakage Current (Pin (Pin Input Resistance REFA, VREFB) VREFA/VREFB Input Resistance Match DIGITAL INPUTS Input High Voltage Input Voltage Input Current (IIN) Input Capacitance DB0-DB7 DACA/DACB SWITCHING CHARACTERISTICS Timing Diagram Chip Select Write Time Chip Select Write Hold Time Select Write Time Select Write Hold Time Data Valid Write Time Data Valid Write Hold Time Write Pulse Width POWER SUPPLY IDD, Grade Grades Grades
0.0035
0.0035
%/°C Latches Loaded with 00000000 Input Resistance -300 ppm/°C, Typical Input Resistance
Figure Digital Inputs Digital Inputs Digital Inputs
Specifications subject change without notice.
These characteristics included Design Guidance only subject test. +10.8 +15.75 (Measured Using Recommended Board Layout (Figure AD644 Output Amplifiers)
Parameter SUPPLY REJECTION (GAIN/VDD) CURRENT SETTLING TIME 0.01 0.02 +125 0.02 Units Test Conditions/Comments
PERFORMANCE CHARACTERISTICS
OutA/OutB Load DB0-DB7 Code Transition 00000000 11111111 Latches Loaded with 00000000 Latches Loaded with 11111111
DIGITAL-TO-ANALOG GLITCH IMPULSE OUTPUT CAPACITANCE COUTA COUTB COUTA COUTB FEEDTHROUGH VREFA VREFB
VREFA, REFB Sine Wave Both Latches Loaded with 11111111. VREFA Sine Wave VREFB Figure VREFB Sine Wave VREFA Figure Measured Code Transition 00000000 11111111
CHANNEL-TO-CHANNEL ISOLATION VREFA VREFB OUTA DIGITAL CROSSTALK HARMONIC DISTORTION
NOTES Temperature Ranges Version; -40°C +85°C; Version; -40°C +85°C; Version; -55°C +125°C. Specification applies both DACs AD7628. Guaranteed design production tested. Logic inputs Gates. Typical input current (+25°C) less than Specifications subject change without notice.
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AD7628
ABSOLUTE MAXIMUM RATINGS
+25°C unless otherwise noted)
TERMINOLOGY Relative Accuracy:
AGND DGND AGND DGND DGND AGND Digital Input Voltage DGND -0.3 VPIN2, VPIN20 AGND -0.3 VREF VREF AGND VRFB VRFB AGND Power Dissipation (Any Package) +75°C Derates above +75°C mW/°C Operating Temperature Range Commercial Grades -40°C +85°C Industrial Grades -40°C +85°C Extended Grades -55°C +125°C Storage Temperature -65°C +150°C Lead Temperature (Soldering, sec) +300°C
ORDERING GUIDE Model1 AD7628KN AD7628KP AD7628KR AD7628BQ AD7628TQ AD7628TE Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -55°C +125°C Relative Gain Accuracy Error Package Option2 N-20 P-20A R-20 Q-20 Q-20 E-20A
Relative accuracy endpoint nonlinearity measure maximum deviation from straight line passing through endpoints transfer function. measured after adjusting zero full-scale, normally expressed LSBs percentage full-scale reading.
Differential Nonlinearity:
Differential nonlinearity difference between measured change ideal change between adjacent codes. specified differential nonlinearity over operating temperature range ensures monotonicity.
Gain Error:
Gain error measure output error between ideal actual device output. measured with latches after offset error been adjusted out. Gain error both DACs adjustable zero with external resistance.
Output Capacitance:
Capacitance from AGND.
Digital-to-Analog Glitch Impulse:
amount charge injected from digital inputs analog output when inputs change state. This normally specified area glitch either pA-secs nV-secs, depending upon whether glitch measured current voltage signal. Glitch impulse measured with VREF VREF AGND.
Channel-to-Channel Isolation:
NOTES order MIL-STD-883, Class process parts, /883B part number. Contact your local sales office military data sheet. Leadless Ceramic Chip Carrier; Plastic DIP; Plastic Leaded Chip Carrier; Cerdip; SOIC.
proportion input signal from DAC's reference input that appears output other DAC, expressed ratio
Digital Crosstalk:
glitch energy transferred output converter change digital input code other converter. Specified secs.
CONFIGURATIONS DIP, SOIC
LCCC
AGND
PLCC
VREF (LSB) AGND
AGND VREF DGND A/DAC (MSB)
VREF VIEW (Not Scale) (LSB)
VREF DGND /DAC (MSB)
VREF
VREF DGND A/DAC (MSB)
AD7628
AD7628
VIEW (Not Scale)
(LSB)
AD7628
VIEW (Not Scale)
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7628 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD7628
INTERFACE LOGIC INFORMATION Selection
Both latches share common 8-bit input port. control input A/DAC selects which accept data from input port.
Mode Selection
weighted currents switched between output AGND, thus maintaining fixed currents each ladder independent switch state.
EQUIVALENT CIRCUIT ANALYSIS
Inputs control operating mode selected DAC. Mode Selection Table below.
Write Mode
Figure shows approximate equivalent circuit AD7628's converters, this case similar equivalent circuit drawn Note that AGND (Pin common both current source ILEAKAGE composed surface junction leakages and, with most semiconductor devices, approximately doubles every 10°C. resistor shown Figure equivalent output resistance device, which varies with input code (excluding code) from 0.8R typically COUT capacitance N-channel switches varies from about depending digital input. g(VREF Thevenin equivalent voltage generator reference input voltage VREF transfer function R-2R ladder. further information CMOS multiplying converters, refer "CMOS Application Guide, Edition" available from Analog Devices, Publication Number G872a-15-4/86.
When both low, selected write mode. input data latches selected transparent analog output responds activity DB0-DB7.
Hold Mode
selected latch retains data that present DB0-DB7 just prior assuming high state. Both analog outputs remain values corresponding data their respective latches.
Mode Selection Table
WRITE HOLD HOLD HOLD HOLD WRITE HOLD HOLD
State, High State, Don't Care
WRITE CYCLE TIMING DIAGRAM
Figure Equivalent Analog Output Circuit
CIRCUIT INFORMATION-DIGITAL SECTION
input buffers simple CMOS level-shifters designed that when AD7628 operated with from 10.8 15.75 buffer converts input levels (2.4 into CMOS logic levels. When region volt volts, input buffers operate their linear region pass quiescent current (see Figure minimize power supply currents, recommended that digital input voltages close supply rails (VDD DGND) practicably possible. AD7628 operated with supply voltage range 10.8 15.75 volts.
CIRCUIT INFORMATION-D/A SECTION
AD7628 contains identical 8-bit multiplying converters, Each consists highly stable thin film R-2R ladder eight N-channel current steering switches. simplified circuit shown Figure inverted R-2R ladder structure used; that binary
Figure Simplified Functional Circuit
Figure Typical Plot Supply Current, Logic Input Voltage
REV.
AD7628
Figure Dual Unipolar Binary Operation Quadrant Multiplication). Table
Figure Dual Bipolar Operation Quadrant Multiplication). Table
Table Unipolar Binary Code Table Latch Contents 11111111 10000001 10000000 01111111 00000001 00000000 NOTE: (2-8)(VIN)
Table Bipolar (Offset Binary) Code Table Latch Contents 11111111 10000001 10000000 01111111 00000001 00000000
Analog Output (DAC
Analog Output (DAC
Trim Resistor
NOTE: -7)(VIN)
Table III. Recommended Trim Resistor Values
K/B/T
REV.
AD7628
APPLICATIONS INFORMATION Application Hints
Figure shows printed circuit layout AD7628 AD644 dual amp, which minimizes feedthrough crosstalk.
SINGLE SUPPLY APPLICATIONS
ensure system performance consistent with AD7628 specifications, careful attention must given following points: GENERAL GROUND MANAGEMENT: transient voltages between AD7628 AGND DGND cause noise injection into analog output. simplest method ensuring that voltages AGND DGND equal AGND DGND together AD7628. more omplex systems where AGND-DGND intertie backplane, recommended that diodes connected inverse parallel between AD7628 AGND DGND pins (1N914 equivalent). OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit code-dependent output resistance which, turn, causes code-dependent amplifier noise gain. effect codedependent differential nonlinearity term amplifier output that depends (VOS amplifier input offset voltage). This differential nonlinearity term adds R/2R differential nonlinearity. maintain monotonic operation, recommended that amplifier greater than over temperature range interest. HIGH FREQUENCY CONSIDERATIONS: output capacitance CMOS works conjunction with amplifier feedback resistance pole open loop response. This cause ringing oscillation. Stability restored adding phase compensation capacitor parallel with feedback resistor.
DYNAMIC PERFORMANCE
AD7628 R-2R ladder termination resistors connected AGND within device. This arrangement particularly convenient single supply operation because AGND biased voltage between DGND VDD. Figure shows circuit that provides analog outputs biasing AGND from DGND. reference inputs tied together reference input voltage obtained without buffer amplifier making constant matched impedances reference inputs. Current flows through R-2R ladders into adjusted until VREF VREF inputs analog output voltages range from codes 00000000
Figure AD7628 Single Supply Operation
dynamic performance DACs AD7628 will depend gain phase characteristics output amplifiers, together with optimum choice board layout decoupling components. Figure shows relationship between input frequency channel-to-channel isolation.
Figure shows AD7628 connected positive reference, voltage switching mode. This configuration useful because VOUT same polarity VIN, allowing single supply operation. However, retain specified linearity, must range +2.5 output buffered loaded with high impedance (see Figure 10). Note that input voltage connected output voltage taken from VREF pin.
Figure Channel-to-Channel Isolation Figure AD7628 Single Supply, Voltage Switching Mode
Figure Suggested Board Layout AD7628 with AD644 Dual
Figure Typical AD7628 Performance Single Supply Voltage Switching Mode REV.
AD7628
MICROPROCESSOR INTERFACE
Figure AD7628 Dual 6800 Interface
PROGRAMMABLE WINDOW COMPARATOR
Figure AD7628 Dual 8085 Interface
circuit Figure AD7628 used implement programmable window comparator. DACs loaded with required upper lower voltage limits test, respectively. test input within programmed limits, pass/fail output will indicate fail (logic zero).
Figure Digitally Programmable Window Comparator (Upper Lower Limit Detector)
PROGRAMMABLE STATE VARIABLE FILTER
CIRCUIT EQUATIONS
RFBB1
NOTE equivalent resistance equals
Ladder resistance Digital Code
Figure Digitally Controlled State Variable Filter
this state, variable universal filter configuration (Figure DACs control gain filter characteristic, while DACs control cutoff frequency, DACs must track accurately simple expression hold. This readily accomplished AD7628. amps AD644. compensates effects gain-bandwidth limitations. REV.
filter provides pass, high pass band pass outputs ideally suited applications where microprocessor control filter parameters required, e.g., equalizer, tone controls, etc. Programmable range component values shown 4.5.
AD7628
DIGITALLY CONTROLLED DUAL TELEPHONE ATTENUATOR MECHANICAL INFORMATION OUTLINE DIMENSIONS
Dimensions shown inches (mm).
this configuration, AD7628 functions 2-channel digitally controlled attenuator; ideal stereo audio telephone signal level control applications. Table gives input codes attenuation 15.5 range.
Attenuation,
20-Pin Cerdip Suffix)
C1029a-8-3/88
Input Code
20-Pin Plastic Suffix)
Figure Digitally Controlled Dual Telephone Attenuator
Table Attenuation Code Circuit Figure
Input Attn. Code Code Input Decimal Attn. Code Code Decimal
20-Terminal Leadless Chip Carrier Suffix)
REV.
PRINTED U.S.A.
11111111 11110010 11100100 11010111 11001011 11000000 10110101 10101011 10100010 10011000 10010000 10001000 10000000 0111001 01110010 01101100
10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5
01100110 01100000 01011011 01010110 01010001 01001100 01001000 01000100 01000000 00111101 00111001 00110110 0011001 00110000 00101110 00101011
20-Terminal Plastic Leaded Chip Carrier Suffix)

CMOS Dual 8-Bit Buffered Multiplying AD7628 GENERAL DESCRIPTION

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