MC68332 User's Manual Motorola reserves right make changes w
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M68300 Family
MC68332
User's Manual
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. MOTOROLA registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
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SECTION INTRODUCTION SECTION 2NOMENCLATURE Symbols Operators CPU32 Registers Signal Mnemonics Register Mnemonics Conventions SECTION 3OVERVIEW 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.6.1 3.6.2 3.7.1 3.7.2 MC68332 Features System Integration Module (SIM) Central Processing Unit (CPU) Time Processor Unit (TPU) Queued Serial Module (QSM) Static Module with Emulation Capability (TPURAM) System Block Diagram Assignment Diagrams Descriptions Signal Descriptions Intermodule System Memory Internal Register 3-10 Address Space Maps 3-10 System Reset 3-15 Reset Mode Selection 3-15 Module Function During Reset 3-16 SECTION SYSTEM INTEGRATION MODULE 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 General System Configuration Protection Module Mapping Interrupt Arbitration Show Internal Cycles Factory Test Mode Register Access Reset Status Monitor Halt Monitor Spurious Interrupt Monitor
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4.2.10 Software Watchdog 4.2.11 Periodic Interrupt Timer 4.2.12 Low-Power Stop Operation 4.2.13 Freeze Operation System Clock 4.3.1 Clock Sources 4-10 4.3.2 Clock Synthesizer Operation 4-10 4.3.3 External Clock 4-15 4.3.4 Low-Power Operation 4-15 4.3.5 Loss Reference Signal 4-16 External Interface 4-17 4.4.1 Signals 4-18 4.4.1.1 Address 4-18 4.4.1.2 Address Strobe 4-18 4.4.1.3 Data 4-18 4.4.1.4 Data Strobe 4-18 4.4.1.5 Read/Write Signal 4-18 4.4.1.6 Size Signals 4-19 4.4.1.7 Function Codes 4-19 4.4.1.8 Data Size Acknowledge Signals 4-19 4.4.1.9 Error Signal 4-20 4.4.1.10 Halt Signal 4-20 4.4.1.11 Autovector Signal 4-20 4.4.2 Dynamic Sizing 4-20 4.4.3 Operand Alignment 4-21 4.4.4 Misaligned Operands 4-22 4.4.5 Operand Transfer Cases 4-22 Operation 4-22 4.5.1 Synchronization CLKOUT 4-23 4.5.2 Regular Cycles 4-23 4.5.2.1 Read Cycle 4-24 4.5.2.2 Write Cycle 4-25 4.5.3 Fast Termination Cycles 4-26 4.5.4 Space Cycles 4-27 4.5.4.1 Breakpoint Acknowledge Cycle 4-28 4.5.4.2 LPSTOP Broadcast Cycle 4-31 4.5.5 Exception Control Cycles 4-31 4.5.5.1 Errors 4-33 4.5.5.2 Double Faults 4-33 4.5.5.3 Retry Operation 4-34 4.5.5.4 Halt Operation 4-34
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Paragraph 4.5.6 4.5.6.1 4.5.6.2 4.6.1 4.6.2 4.6.3 4.6.3.1 4.6.3.2 4.6.3.3 4.6.4 4.6.5 4.6.5.1 4.6.5.2 4.6.6 4.6.7 4.6.8 4.6.9 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.8.1 4.8.1.1 4.8.1.2 4.8.1.3 4.8.1.4 4.8.2 4.8.3 4.8.4 4.9.1 4.9.2 4.9.3 4.10 (Continued) Title Page
External Arbitration 4-35 Slave (Factory Test) Mode Arbitration 4-36 Show Cycles 4-36 Reset 4-37 Reset Exception Processing 4-37 Reset Control Logic 4-38 Reset Mode Selection 4-38 Data Mode Selection 4-39 Clock Mode Selection 4-41 Breakpoint Mode Selection 4-41 Module Function During Reset 4-41 State During Reset 4-42 Reset States Pins 4-42 Reset States Pins Assigned Other Modules 4-43 Reset Timing 4-43 Power-On Reset 4-44 Reset Processing Summary 4-45 Reset Status Register 4-46 Interrupts 4-46 Interrupt Exception Processing 4-46 Interrupt Priority Recognition 4-46 Interrupt Acknowledge Arbitration 4-47 Interrupt Processing Summary 4-48 Interrupt Acknowledge Cycles 4-49 Chip Selects 4-49 Chip-Select Registers 4-51 Chip-Select Assignment Registers 4-52 Chip-Select Base Address Registers 4-53 Chip-Select Option Registers 4-53 PORTC Data Register 4-55 Chip-Select Operation 4-55 Using Chip-Select Signals Interrupt Acknowledge 4-55 Chip-Select Reset Operation 4-56 Parallel Input/Output Ports 4-58 Assignment Registers 4-58 Data Direction Registers 4-58 Data Registers 4-58 Factory Test 4-58 SECTION CENTRAL PROCESSING UNIT
General
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CPU32 Registers 5.2.1 Data Registers 5.2.2 Address Registers 5.2.3 Program Counter 5.2.4 Control Registers 5.2.4.1 Status Register 5.2.4.2 Alternate Function Code Registers 5.2.5 Vector Base Register (VBR) Memory Organization Virtual Memory Addressing Modes Processing States Privilege Levels Instructions 5.8.1 M68000 Family Compatibility 5-12 5.8.2 Special Control Instructions 5-13 5.8.2.1 Power Stop (LPSTOP) 5-13 5.8.2.2 Table Lookup Interpolate (TBL) 5-13 Exception Processing 5-13 5.9.1 Exception Vectors 5-13 5.9.2 Types Exceptions 5-14 5.9.3 Exception Processing Sequence 5-15 5.10 Development Support 5-15 5.10.1 M68000 Family Development Support 5-15 5.10.2 Background Debugging Mode 5-16 5.10.2.1 Enabling 5-17 5.10.2.2 Sources 5-17 5.10.2.3 Entering 5-18 5.10.2.4 Commands 5-19 5.10.2.5 Background Mode Registers 5-20 5.10.2.6 Returning from 5-20 5.10.2.7 Serial Interface 5-20 5.10.3 Recommended Connection 5-22 5.10.4 Deterministic Opcode Tracking 5-22 5.10.5 On-Chip Breakpoint Hardware 5-23 5.11 Loop Mode Instruction Execution 5-23 SECTION 6QUEUED SERIAL MODULE 6.2.1 General Registers Address Global Registers
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6.2.1.1 Low-Power Stop Operation 6.2.1.2 Freeze Operation 6.2.1.3 Interrupts 6.2.2 Control Registers Queued Serial Peripheral Interface 6.3.1 QSPI Registers 6.3.1.1 Control Registers 6.3.1.2 Status Register 6.3.2 QSPI 6.3.2.1 Receive 6.3.2.2 Transmit 6.3.2.3 Command 6.3.3 QSPI Pins 6.3.4 QSPI Operation 6.3.5 QSPI Operating Modes 6-10 6.3.5.1 Master Mode 6-17 6.3.5.2 Master Wraparound Mode 6-20 6.3.5.3 Slave Mode 6-20 6.3.5.4 Slave Wraparound Mode 6-22 6.3.6 Peripheral Chip Selects 6-22 Serial Communication Interface 6-22 6.4.1 Registers 6-22 6.4.1.1 Control Registers 6-22 6.4.1.2 Status Register 6-25 6.4.1.3 Data Register 6-25 6.4.2 Pins 6-25 6.4.3 Operation 6-25 6.4.3.1 Definition Terms 6-25 6.4.3.2 Serial Formats 6-26 6.4.3.3 Baud Clock 6-26 6.4.3.4 Parity Checking 6-27 6.4.3.5 Transmitter Operation 6-27 6.4.3.6 Receiver Operation 6-28 6.4.3.7 Idle-Line Detection 6-29 6.4.3.8 Receiver Wakeup 6-30 6.4.3.9 Internal Loop 6-30 Initialization 6-31 SECTION 7TIME PROCESSOR UNIT General Components
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Paragraph 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.11 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.6.1 7.6.1.1 7.6.1.2 (Continued) Title Page
Time Bases Timer Channels Scheduler Microengine Host Interface Parameter Operation Event Timing Channel Orthogonality Interchannel Communication Programmable Channel Service Priority Coherency Emulation Support Interrupts Standard Enhanced Standard Time Functions Discrete Input/Output (DIO) Input Capture/Input Transition Counter (ITC) Output Compare (OC) Pulse-Width Modulation (PWM) Synchronized Pulse-Width Modulation (SPWM) Period Measurement with Additional Transition Detect (PMA) Period Measurement with Missing Transition Detect (PMM) Position-Synchronized Pulse Generator (PSP) Stepper Motor (SM) Period/Pulse-Width Accumulator (PPWA) Quadrature Decode (QDEC) Motion Control Time Functions Table Stepper Motor (TSM) Input Capture/Transition Counter (NITC) Queued Output Match (QOM) 7-10 Programmable Time Accumulator (PTA) 7-10 Multichannel Pulse-Width Modulation (MCPWM) 7-10 Fast Quadrature Decode (FQD) 7-10 Universal Asynchronous Receiver/Transmitter (UART) 7-11 Brushless Motor Commutation (COMM) 7-11 Frequency Measurement (FQM) 7-11 Hall Effect Decode (HALLD) 7-11 Host Interface Registers 7-11 System Configuration Registers 7-12 Prescaler Control TCR1 7-12 Prescaler Control TCR2 7-12
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Paragraph 7.6.1.3 7.6.1.4 7.6.2 7.6.2.1 7.6.2.2 7.6.2.3 7.6.2.4 7.6.2.5 7.6.3 (Continued) Title Page
Emulation Control 7-13 Low-Power Stop Control 7-13 Channel Control Registers 7-14 Channel Interrupt Enable Status Registers 7-14 Channel Function Select Registers 7-14 Host Sequence Registers 7-14 Host Service Registers 7-14 Channel Priority Registers 7-14 Development Support Test Registers 7-15 SECTION 8STANDBY WITH EMULATION
General TPURAM Register Block TPURAM Array Address Mapping TPURAM Privilege Level Normal Operation Standby Operation Low-Power Stop Operation Reset Microcode Emulation APPENDIX ELECTRICAL CHARACTERISTICS APPENDIX MECHANICAL DATA ORDERING INFORMATION APPENDIX CDEVELOPMENT SUPPORT
M68MMDS1632 Modular Development System M68MEVB1632 Modular Evaluation Board APPENDIX REGISTER SUMMARY
D.1.1 D.1.2 D.2.1 D.2.2 D.2.3 D.2.4 D.2.5 D.2.6
Central Processing Unit CPU32 Register Model Status Register System Integration Module SIMCR Module Configuration Register $YFFA00 SIMTR System Integration Test Register $YFFA02 SYNCR Clock Synthesizer Control Register $YFFA04 Reset Status Register $YFFA07 SIMTRE System Integration Test Register (ECLK) $YFFA08 PORTE0/PORTE1 Port Data Register $YFFA11, $YFFA13
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D.2.7 DDRE Port Data Direction Register $YFFA15 D.2.8 PEPAR Port Assignment Register $YFFA17 D.2.9 PORTF0/PORTF1 Port Data Register.$YFFA19, $YFFA1B D.2.10 DDRF Port Data Direction Register.$YFFA1D D.2.11 PFPAR Port Assignment Register. $YFFA1F D.2.12 SYPCR System Protection Control Register $YFFA21 D-10 D.2.13 PICR Periodic Interrupt Control Register. $YFFA22 D-11 D.2.14 PITR Periodic Interrupt Timer Register $YFFA24 D-11 D.2.15 SWSR Software Service Register $YFFA27 D-11 D.2.16 TSTMSRA Master Shift Register $YFFA30 D-11 D.2.17 TSTMSRB Master Shift Register $YFFA32 D-11 D.2.18 TSTSC Test Module Shift Count $YFFA34 D-12 D.2.19 TSTRC Test Module Repetition Count $YFFA36 D-12 D.2.20 CREG Test Submodule Control Register $YFFA38 D-12 D.2.21 DREG Distributed Register.$YFFA3A D-12 D.2.22 PORTC Port Data Register $YFFA41 D-12 D.2.23 CSPAR0 Chip Select Assignment Register $YFFA44 D-12 D.2.24 CSPAR1 Chip Select Assignment Register $YFFA46 D-13 D.2.25 CSBARBT Chip Select Base Address Register Boot $YFFA48 D.2.26 CSBAR[0:10] Chip Select Base Address Registers $YFFA4C-$YFFA74 D-13 D.2.27 CSORBT Chip Select Option Register Boot ROM.$YFFA4A D-14 D.2.28 CSOR[0:10] Chip Select Option Registers .$YFFA4E-$YFFA76 D-14 Standby Module with Emulation D-16 D.3.1 TRAMMCR TPURAM Module Configuration Register. $YFFB00 D-16 D.3.2 TRAMTST TPURAM Test Register $YFFB02 D-16 D.3.3 TRAMBAR TPURAM Base Address Status Register $YFFB04 D-16 Queued Serial Module D-18 D.4.1 QSMCR Configuration Register $YFFC00 D-18 D.4.2 QTEST Test Register $YFFC02 D-19 D.4.3 QILR Interrupt Level Register.$YFFC04 QIVR Interrupt Vector Register$YFFC05 D-19 D.4.4 SCCR0 Control Register $YFFC08 D-20 D.4.5 SCCR1 Control Register 1.$YFFC0A D-20 D.4.6 SCSR Status Register $YFFC0C D-22 D.4.7 SCDR Data Register.$YFFC0E D-23 D.4.8 PORTQS Port Data Register. $YFFC15 D-23 D.4.9 PQSPAR PORT Assignment Register .$YFFC16 DDRQS PORT Data Direction Register$YFFC17 D-23 D.4.10 SPCR0 QSPI Control Register $YFFC18 D-25
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D.4.11 SPCR1 QSPI Control Register .$YFFC1A D-26 D.4.12 SPCR2 QSPI Control Register $YFFC1C D-27 D.4.13 SPCR3 QSPI Control Register $YFFC1E SPSR QSPI Status Register $YFFC1F D-27 D.4.14 RR[0:F] Receive Data RAM. $YFFD00-$YFFD0E D-28 D.4.15 TR[0:F] Transmit Data $YFFD20-$YFFD3E D-28 D.4.16 CR[0:F] Command RAM. $YFFD40-$YFFD4F D-29 D.5.1 TPUMCR Module Configuration Register. $YFFE00 D-30 D.5.2 Test Configuration Register. $YFFE02 D-32 D.5.3 DSCR Development Support Control Register. $YFFE04 D-32 D.5.4 DSSR Development Support Status Register $YFFE06 D-33 D.5.5 TICR Interrupt Configuration Register $YFFE08 D-33 D.5.6 CIER Channel Interrupt Enable Register.$YFFE0A D-34 D.5.7 CFSR0 Channel Function Select Register .$YFFE0C D-34 D.5.8 CFSR1 Channel Function Select Register .$YFFE0E D-34 D.5.9 CFSR2 Channel Function Select Register $YFFE10 D-34 D.5.10 CFSR3 Channel Function Select Register $YFFE12 D-34 D.5.11 HSQR0 Host Sequence Register $YFFE14 D-35 D.5.12 HSQR1 Host Sequence Register $YFFE16 D-35 D.5.13 HSRR0 Host Service Request Register $YFFE18 D-35 D.5.15 CPR0 Channel Priority Register .$YFFE1C D-36 D.5.16 CPR1 Channel Priority Register $YFFE1E D-36 D.5.17 CISR Channel Interrupt Status Register. $YFFE20 D-36 D.5.18 Link Register $YFFE22 D-36 D.5.19 SGLR Service Grant Latch Register. $YFFE24 D-36 D.5.20 DCNR Decoded Channel Number Register $YFFE26 D-37 D.5.21 Parameter D-37 SUMMARY CHANGES
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4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 5-10 5-11 5-12
Block Diagram Assignments 132-Pin Package Assignments 144-Pin Package Internal Register Memory 3-10 Overall Memory 3-11 Separate Supervisor User Space 3-12 Supervisor Space (Separate Program/Data Space) 3-13 User Space (Separate Program/Data Space) 3-14 System Integration Module Block Diagram System Configuration Protection Periodic Interrupt Timer Software Watchdog Timer System Clock Block Diagram System Clock Oscillator Circuit 4-10 System Clock Filter Networks 4-11 Basic System 4-17 Operand Byte Order 4-21 Word Read Cycle Flowchart 4-25 Write Cycle Flowchart 4-26 Space Address Encoding 4-27 Breakpoint Operation Flowchart 4-30 LPSTOP Interrupt Mask Level 4-31 Arbitration Flowchart Single Request 4-36 Data Mode Select Conditioning 4-40 Power-On Reset 4-45 Basic System 4-50 Chip-Select Circuit Block Diagram 4-51 Space Encoding Interrupt Acknowledge 4-56 CPU32 Block Diagram User Programming Model Supervisor Programming Model Supplement Data Organization Data Registers Address Organization Address Registers Memory Operand Addressing Common in-Circuit Emulator Diagram 5-16 State Analyzer Configuration 5-17 Debug Serial Block Diagram 5-21 Serial Data Word 5-22 Connector Pinout 5-22 Loop Mode Instruction Sequence 5-23 Block Diagram QSPI Block Diagram
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Figure A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 A-18 A-19 A-20 (Continued) Title Page
QSPI Flowchart QSPI Initialization Operation 6-11 Flowchart QSPI Master Operation (Part 6-12 Flowchart QSPI Master Operation (Part 6-13 Flowchart QSPI Master Operation (Part 6-14 Flowchart QSPI Slave Operation (Part 6-15 Flowchart QSPI Slave Operation (Part 6-16 Transmitter Block Diagram 6-23 Receiver Block Diagram 6-24 Block Diagram TCR1 Prescaler Control 7-12 TCR2 Prescaler Control 7-13 CLKOUT Output Timing Diagram A-14 External Clock Input Timing Diagram A-14 ECLK Output Timing Diagram A-14 Read Cycle Timing Diagram A-15 Write Cycle Timing Diagram A-16 Fast Termination Read Cycle Timing Diagram A-17 Fast Termination Write Cycle Timing Diagram A-18 Arbitration Timing Diagram -Active Case A-19 Arbitration Timing Diagram Idle Case A-20 Show Cycle Timing Diagram A-20 Chip Select Timing Diagram A-21 Reset Mode Select Timing Diagram A-21 Background Debugging Mode Timing Diagram Serial Communication A-23 Background Debugging Mode Timing Diagram Freeze Assertion A-23 ECLK Timing Diagram A-25 QSPI Timing Master, CPHA A-27 QSPI Timing Master, CPHA A-27 QSPI Timing Slave, CPHA A-28 QSPI Timing Slave, CPHA A-28 Timing Diagram A-29 132-Pin Plastic Surface Mount Package Assignments 144-Pin Plastic Surface Mount Package Assignments User Programming Model .D-2 Supervisor Programming Model Supplement .D-2
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4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24
Driver Types. Characteristics Power Connections Signal Characteristics Signal Function Reset Mode Selection. 3-15 Module Functions. 3-16 Show Cycle Enable Bits Monitor Period. MODCLK During Reset Software Watchdog Ratio. MODCLK Reset Periodic Interrupt Priority. Clock Control Multipliers. 4-12 System Frequencies from 32.768-kHz Reference. 4-14 Clock Control. 4-16 Size Signal Encoding 4-19 Address Space Encoding 4-19 Effect DSACK Signals 4-21 Operand Transfer Cases. 4-22 DSACK, BERR, HALT Assertion Results 4-32 Reset Source Summary 4-38 Reset Mode Selection 4-39 Module Functions. 4-42 Reset States 4-43 Chip-Select Functions 4-52 Assignment Field Encoding. 4-52 Block Size Encoding. 4-53 Option Register Function Summary 4-54 Chip Select Base Option Register Reset Values 4-57 CSBOOT Base Option Register Reset Values. 4-58 Instruction Summary 5-10 Exception Vector Assignments. 5-14 Source Summary. 5-17 Polling Entry Source. 5-18 Background Mode Command Summary 5-19 Generated Message Encoding 5-22 Function QSPI Function. BITS Encoding 6-19 Function 6-25
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Serial Frame Formats. 6-26 Effect Parity Checking Data Size 6-27 TCR1 Prescaler Control 7-12 TCR2 Prescaler Control 7-13 Channel Priority Encodings 7-15 Maximum Ratings. Typical Ratings, 16.78 Operation. Typical Ratings, 20.97 Operation. Thermal Characteristics 16.78 Clock Control Timing. 20.97 Clock Control Timing. 16.78 Characteristics 20.97 Characteristics 16.78 Timing 20.97 Timing A-11 Background Debugging Mode Timing A-22 16.78 ECLK Timing. A-24 20.97 ECLK Timing. A-24 QSPI Timing A-26 16.78 Time Processor Unit Timing. A-29 20.97 Time Processor Unit Timing. A-29 Ordering Information Quantity Order Suffix. MC68332 Development Tools.C-1 Module Address .D-1 Address Map.D-4 TPURAM Address .D-16 Address .D-18 Address .D-30 Parameter Address .D-37 MC68332 Module Address Map.D-38 Register Field Mnemonics.D-41
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SECTION INTRODUCTION
MC68332, highly-integrated 32-bit microcontroller, combines high-performance data manipulation capabilities with powerful peripheral subsystems. built from standard modules that interface through common intermodule (IMB). Standardization facilitates rapid development devices tailored specific applications. incorporates 32-bit (CPU32), system integration module (SIM), time processor unit (TPU), queued serial module (QSM), 2-Kbyte static module with emulation capability (TPURAM). either synthesize internal clock signal from external reference external clock input directly. Operation with 32.768-kHz reference frequency standard. System hardware software allow changes clock rate during operation. Because operation fully static, register memory contents affected clock rate changes. High-density complementary metal-oxide semiconductor (HCMOS) architecture makes basic power consumption low. Power consumption minimized stopping system clock. CPU32 instruction includes low-power stop (LPSTOP) command that efficiently implements this capability. Documentation Modular Microcontroller Family follows modular construction devices product line. Each microcontroller comprehensive user's manual that provides sufficient information normal operation device. user's manual supplemented module reference manuals that provide detailed information about module operation applications. Refer Motorola publication Advanced Microcontroller Unit (AMCU) Literature (BR1116/D) complete listing documentation.
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SECTION NOMENCLATURE
following nomenclature used throughout manual. Nomenclature used only certain sections, such register mnemonics, defined those sections. Symbols Operators Addition Subtraction negation (two's complement) Multiplication Division Greater Less Equal Equal greater Equal less equal Inclusive (OR) Exclusive (EOR) Complementation Concatenation Transferred Exchanged Sign bit; also used show tolerance Sign extension Binary value Hexadecimal value
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CPU32 Registers A6-A0 (SSP) (USP) D7-D0 Address registers (Index registers) Supervisor Stack Pointer User Stack Pointer Condition code register (user portion Data Registers (Index registers) Alternate function code register Program counter Alternate function code register Status register Vector base register Extend indicator Negative indicator Zero indicator Two's complement overflow indicator Carry/borrow indicator
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Signal Mnemonics ADDR[23:0] AVEC BERR BGACK BKPT CLKOUT CS[10:0] CSBOOT DATA[15:0] DSACK[1:0] DSCLK EXTAL FC[2:0] FREEZE HALT IFETCH IPIPE IRQ[7:1] MISO MODCLK MOSI PC[6:0] PCS[3:0] PE[7:0] PF[7:0] PQS[7:0] QUOT RESET SIZ[1:0] T2CLK TPUCH[15:0] XTAL Address Address Strobe Autovector Error Grant Grant Acknowledge Breakpoint Request System Clock Chip Selects Boot Chip Select Data Data Strobe Data Size Acknowledge Development Serial Clock Development Serial Input Development Serial Output External Crystal Oscillator Connection Function Codes Freeze Halt Instruction Fetch Instruction Pipeline Interrupt Request Master Slave Clock Mode Select Master Slave Port Peripheral Chip Selects Port Port Port Quotient Read/Write Reset Read-Modify-Write Cycle Receive Data QSPI Serial Clock Size Slave Select Clock Channel Signals Three-State Control Transmit Data External Filter Capacitor External Crystal Oscillator Connection
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Register Mnemonics CFSR[0:3] CIER CISR CPR[0:1] CREG CR[0:F] CSBARBT CSBAR[0:10] CSORBT CSOR[0:10] CSPAR[0:1] DCNR DDRE DDRF DDRQS DREG DSCR DSSR HSQR[0:1] HSRR[0:1] PEPAR PFPAR PICR PITR PORTC PORTE PORTF PORTQS PQSPAR QILR QIVR QSMCR QTEST RR[0:F] SCCR[0:1] SCDR SCSR SGLR SIMCR SIMTR SIMTRE SPCR[0:3] SPSR Channel Function Select Registers [0:3] Channel Interrupt Enable Register Channel Interrupt Status Register Channel Priority Registers [0:1] Test Control Register Command Chip-Select Base Address Register Boot Chip-Select Base Address Registers [0:10] Chip-Select Option Register Boot Chip-Select Option Registers [0:10] Chip-Select Assignment Registers [0:1] Decoded Channel Number Register Port Data Direction Register Port Data Direction Register Port Data Direction Register Test Module Distributed Register Development Support Control Register Development Support Status Register Host Sequence Registers [0:1] Host Service Request Registers [0:1] Link Register Port Assignment Register Port Assignment Register Periodic Interrupt Control Register Periodic Interrupt Timer Register Port Data Register Port Data Register Port Data Register Port Data Register Port Assignment Register Interrupt Level Register Interrupt Vector Register Configuration Register Test Register Receive Data Reset Status Register Control Registers [0:1] Data Register Status Register Service Grant Latch Register Module Configuration Register System Integration Test Register System Integration Test Register (ECLK) QSPI Control Registers [0:3] QSPI Status Register
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SWSR SYNCR SYPCR TICR TPUMCR TRAMBAR TRAMMCR TRAMTST TR[0:F] TSTMSRA TSTMSRB TSTRC TSTSC
Software Watchdog Service Register Clock Synthesizer Control Register System Protection Control Register Test Configuration Register Interrupt Configuration Register Module Configuration Register TPURAM Base Address/Status Register TPURAM Module Configuration Register TPURAM Test Register Transmit Data Test Module Master Shift Register Test Module Master Shift Register Test Module Repetition Counter Test Module Shift Count Register
Conventions Logic level voltage that corresponds Boolean true state. Logic level zero voltage that corresponds Boolean false state. refers specifically establishing logic level bits. Clear refers specifically establishing logic level zero bits. Asserted means that signal active logic state. active signal changes from logic level logic level zero when asserted, active high signal changes from logic level zero logic level one. Negated means that asserted signal changes logic state. active signal changes from logic level zero logic level when negated, active high signal changes from logic level logic level zero. specific mnemonic within range referred mnemonic number. accumulator ADDR7 line address bus; CSOR0 chip-select option register range mnemonics referred mnemonic numbers that define range. AM[35:30] bits accumulator CSOR[0:5] first option registers Parentheses used indicate content register memory location, rather than register memory location itself. content accumulator content word address means least significant bits. means most significant bits. References high bytes spelled out. means least significant word words. means most significant word words. ADDR address bus. ADDR[7:0] eight address bus. DATA data bus. DATA[15:8] eight data bus.
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This section contains information about entire modular microcontroller. lists features each module, shows device functional divisions assignments, summarizes signal functions, discusses intermodule bus, provides system memory maps. Timing electrical specifications entire microcontroller individual modules provided APPENDIX ELECTRICAL CHARACTERISTICS. Comprehensive module register descriptions memory maps provided APPENDIX REGISTER SUMMARY. MC68332 Features following paragraphs highlight capabilities each microcontroller modules. Each module discussed separately subsequent section this user's manual. 3.1.1 System Integration Module (SIM) External Support Programmable Chip-Select Outputs System Protection Logic Watchdog Timer, Clock Monitor, Monitor System Protection Logic System Clock Based 32.768-kHz Crystal Power Operation Test/Debug Submodule Factory/User Test Development 3.1.2 Central Processing Unit (CPU) Upward Object Code Compatible Instructions Controller Applications 32-Bit Architecture Virtual Memory Implementation Loop Mode Instruction Execution Table Lookup Interpolate Instruction Improved Exception Handling Controller Applications Trace Change Flow Hardware Breakpoint Signal, Background Mode Fully Static Operation 3.1.3 Time Processor Unit (TPU) Dedicated Microengine Operating Independently CPU32 Independent, Programmable Channels Pins Channel Perform Time Function Timer Count Registers with Programmable Prescalers Selectable Channel Priority Levels
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3.1.4 Queued Serial Module (QSM) Enhanced Serial Communication Interface (SCI), Universal Asynchronous Receiver Transmitter (UART): Modulus Baud Rate, Parity Queued Serial Peripheral Interface (SPI): 80-Byte RAM, Automatic Transfers Dual Function Ports Continuous Cycling, 8-16 Bits Transfer 3.1.5 Static Module with Emulation Capability (TPURAM) 2-Kbytes Static Used Normal Microcode Emulation System Block Diagram Assignment Diagrams Figure functional diagram MCU. Although diagram blocks represent relative size physical modules, there one-to-one correspondence between location size blocks diagram location size integratedcircuit modules. Figure shows assignments 132-pin plastic surfacemount package. Figure shows assignments 144-pin plastic surfacemount package. Refer APPENDIX MECHANICAL DATA ORDERING INFORMATION package dimensions. functions signal names shown this drawing. Refer subsequent paragraphs this section signal descriptions.
MOTOROLA
OVERVIEW
MC68332 USER'S MANUAL
VSTBY
TPUCH[15:0] T2CLK
TPUCH[15:0] T2CLK KBYTES
ADDR[23:0] SIZ1 SIZ0 AVEC DSACK1 DSACK0
ADDR[23:19]
CONTROL PORT
CHIP SELECTS BGACK CS[10:0]
CSBOOT ADDR23/CS10 PC6/ADDR22/CS9 PC5/ADDR21/CS8 PC4/ADDR20/CS7 PC3/ADDR19/CS6 PC2/FC2/CS5 PC1/FC1/CS4 PC0/FC0/CS3 BGACK/CS2 BG/CS1 BR/CS0
ADDR[18:0] PE7/SIZ1 PE6/SIZ0 PE5/DS PE4/AS PE3/RMC PE2/AVEC PE1/DSACK1 PE0/DSACK0
PQS7/TXD PQS6/PCS3 PQS5/PCS2 PQS4/PCS1 PQS3/PCS0/SS PQS2/SCK PQS1/MOSI PQS0/MISO
PCS3 PCS2 PCS1 PCS0/SS MOSI MISO
PORT CONTROL
DATA[15:0]
CONTROL PORT
DATA[15:0] RESET HALT BERR PF7/IRQ7 PF6/IRQ6 PF5/IRQ5 PF4/IRQ4 PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 PF0/MODCLK CLKOUT XTAL EXTAL VDDSYN CONTROL FREEZE/QUOT
IRQ[7:1] CONTROL PORT MODCLK CLOCK BKPT IFETCH IPIPE DSCLK FREEZE TEST QUOT
CONTROL
BKPT/DSCLK IFETCH/DSI IPIPE/DSO
BLOCK
Figure Block Diagram
MC68332 USER'S MANUAL
OVERVIEW
MOTOROLA
ADDR23/CS10 PC6/ADDR22/CS9 PC5/ADDR21/CS8 PC4/ADDR20/CS7 PC3/ADDR19/CS6 PC2/FC2/CS5 PC1/FC1/CS4 PC0/FC0/CS3
TPUCH8 TPUCH9 TPUCH10 TPUCH11
TPUCH12 TPUCH13 TPUCH14 TPUCH15 T2CLK
TPUCH0 TPUCH1 TPUCH2 TPUCH3 TPUCH4 TPUCH5 TPUCH6 TPUCH7
VSTBY ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 PQS0/MISO PQS1/MOSI PQS2/SCK PQS3/PCS0/SS PQS4/PCS1 PQS5/PCS2 PQS6/PCS3
MC68332
BGACK/CS2 BG/CS1 BR/CS0 CSBOOT DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 ADDR0 PE0/DSACK0 PE1/DSACK1 PE2/AVEC PE3/RMC PE5/DS
PQS7/TXD IPIPE/DSO IFETCH/DSI BKPT/DSCLK FREEZE/QUOT XTAL VDDSYN EXTAL CLKOUT RESET HALT BERR PF7/IRQ7 PF6/IRQ6 PF5/IRQ5 PF4/IRQ4 PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 PF0/MODCLK PE7/SIZ1 PE6/SIZ0
132-PIN
Figure Assignments 132-Pin Package
MOTOROLA
OVERVIEW
MC68332 USER'S MANUAL
FC0/CS3 FC1/CS4 FC2/CS5 ADDR19/CS6 ADDR20/CS7 ADDR21/CS8 ADDR22/CS9 ADDR23/CS10 T2CLK TPUCH15 TPUCH14 TPUCH13 TPUCH12 TPUCH11 TPUCH10 TPUCH9 TPUCH8 VDDE VSSE TPUCH7 TPUCH6 TPUCH5 TPUCH4 TPUCH3 TPUCH2 TPUCH1 TPUCH0
BGACK/CS2 BG/CS1 BR/CS0 CSBOOT DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 ADDR0 PE0/DSACK0 PE1/DSACK1 PE2/AVEC PE3/RMC PE5/DS
MC68332
PE4/AS PE6/SIZ0 PE7/SIZ1 PF0/MODCLK PF1/IRQ1 PF2/IRQ2 PF3/IRQ3 PF4/IRQ4 PF5/IRQ5 PF6/IRQ6 PF7/IRQ7 BERR HALT RESET CLKOUT EXTAL XTAL FREEZE/QUOT BKPT/DSCLK IFETCH/DSI IPIPE/DSO PQS7/TXD
VSTBY ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 PQS0/MISO PQS1/MOSI PQS2/SCK PQS3/PCS0/SS PQS4/PCS1 PQS5/PCS2 PQS6/PCS3
144-PIN
Figure Assignments 144-Pin Package Descriptions following tables summarize functional characteristics pins. Table shows types output drivers. Table shows inputs outputs. Digital inputs outputs CMOS logic levels. entry Discrete column indicates that also used general-purpose input, output, both. port designation given when applies. Table shows characteristics power pins. Refer Figure port organization.
MC68332 USER'S MANUAL
OVERVIEW
MOTOROLA
Table Driver Types
Type Description Output-only signals that always driven; external pull-up required Type output with weak P-channel pull-up during reset Three-state output that includes circuitry pull output before high impedance established, ensure rapid rise time. external holding resistor required maintain logic level while high-impedance state. Type output that operated open-drain mode
Table Characteristics
Mnemonic ADDR23/CS10/ECLK ADDR[22:19]/CS[9:6] ADDR[18:0] AVEC BERR BG/CS1 BGACK/CS2 BKPT/DSCLK BR/CS0 CLKOUT CSBOOT DATA[15:0]1 DSACK1 DSACK0 DSI/IFETCH DSO/IPIPE EXTAL2 FC[2:0]/CS[5:3] FREEZE/QUOT HALT IRQ[7:1] MISO MODCLK1 MOSI PCS0/SS PCS[3:1] RESET SIZ[1:0] T2CLK TPUCH[15:0] Output Driver Input Synchronized Input Hysteresis Special Discrete Port Designation PC[6:3] PC[2:0] PF[7:1] PQS0 PQS1 PQS3 PQS[6:4] PQS2 PE[7:6]
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MC68332 USER'S MANUAL
Table Characteristics (Continued)
Mnemonic XFC2 XTAL2 Output Driver Input Synchronized Input Hysteresis Discrete Special Special Port Designation PQS7
NOTES: DATA[15:0] synchronized during reset only. MODCLK synchronized only when used input port pin. EXTAL, XFC, XTAL clock reference connections.
Table Power Connections
Mnemonic VSTBY VDDSYN VSSE/VDDE VSSI/VDDI Description Standby Power Clock Synthesizer Power External Periphery Power (Source Drain) Internal Module Power (Source Drain)
Signal Descriptions following tables define signals. Table shows signal origin, type, active state. Table describes signal functions. Both tables sorted alphabetically mnemonic. pins often have multiple functions. More than description apply pin. Table Signal Characteristics
Signal Name ADDR[23:0] AVEC BERR BGACK BKPT CLKOUT CS[10:0] CSBOOT DATA[15:0] DSACK[1:0] DSCLK EXTAL FC[2:0] FREEZE HALT Module CPU32 CPU32 CPU32 CPU32 Signal Type Output Input Input Output Input Input Input Output Output Output Output Input Input Input Output Input Output Output Input/Output Active State Serial Clock (Serial Data) (Serial Data)
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MOTOROLA
Table Signal Characteristics (Continued)
Signal Name IFETCH IPIPE IRQ[7:1] MISO MODCLK MOSI PC[6:0] PCS[3:0] PE[7:0] PF[7:0] PQS[7:0] QUOT RESET SIZ[1:0] T2CLK TPUCH[15:0] XTAL Module CPU32 CPU32 Signal Type Output Output Input Input/Output Input Input/Output Output Input/Output Input/Output Input/Output Input/Output Output Input/Output Output Output Input Input/Output Output Input Input Input/Output Input Output Input Output Active State (Port) (Port) (Port) (Port)
Table Signal Function
Signal Name Address Address Strobe Autovector Error Grant Grant Acknowledge Breakpoint Request System Clockout Chip Selects Boot Chip Select Data Data Strobe Mnemonic ADDR[23:0] AVEC BERR BGACK BKPT CLKOUT CS[10:0] CSBOOT DATA[15:0] Function 24-bit address Indicates that valid address address Requests automatic vector during interrupt acknowledge Indicates that error occurred Indicates that relinquished Indicates that external device assumed mastership Signals hardware breakpoint Indicates that external device requires mastership System clock output Select external devices programmed addresses Chip select external boot start-up 16-bit data During read cycle, indicates when possible external device place data data bus. During write cycle, indicates that valid data data bus. Provide asynchronous data transfers dynamic sizing Serial clock background debugging mode
Data Size Acknowledge Development Serial Out, Clock Crystal Oscillator
DSACK[1:0] DSI, DSO, DSCLK EXTAL, XTAL Connections clock synthesizer circuit reference; crystal external oscillator used
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MC68332 USER'S MANUAL
Table Signal Function (Continued)
Signal Name Function Codes Freeze Halt Instruction Pipeline Interrupt Request Level Master Slave Clock Mode Select Master Slave Port Auxiliary Timer Clock Input Peripheral Chip Select Port Port Port Quotient Reset Read-Modify-Write Cycle Read/Write Receive Data QSPI Serial Clock Size Slave Select TCR2 Clock Channel Pins Three-State Control Transmit Data External Filter Capacitor Mnemonic FC[2:0] FREEZE HALT IPIPE, IFETCH IRQ[7:1] MISO MODCLK MOSI PC[6:0] PCLK PCS[3:0] PE[7:0] PF[7:0] PQS[7:0] QUOT RESET SIZ[1:0] T2CLK TPUCH[15:0] Function Identify processor state current address space Indicates that entered background mode Suspend external activity Indicate instruction pipeline activity Provides interrupt priority level Serial input QSPI master mode; serial output from QSPI slave mode Selects source type system clock Serial output from QSPI master mode; serial input QSPI slave mode digital output port signals External clock dedicated QSPI peripheral chip selects digital port signals digital port signals digital port signals Provides quotient polynomial divider System reset Indicates indivisible read-modify-write instruction Indicates direction data transfer Serial input Clock output from QSPI master mode; clock input QSPI slave mode Indicates number bytes transferred during cycle Causes serial transmission when QSPI slave mode; causes mode fault master mode External clock source TCR2 counter Bidirectional pins associated with channels Places output drivers high-impedance state Serial output from Connection external phase-locked loop filter capacitor
Intermodule intermodule (IMB) standardized developed facilitate both design operation modular microcontrollers. contains circuitry support exception processing, address space partitioning, multiple interrupt levels, vectored interrupts. standardized modules communicate with another with external components through IMB. uses address data lines. System Memory Figure through Figure memory maps. Figure shows addresses internal registers. Figure through Figure show system memory maps that different external decoding schemes.
MC68332 USER'S MANUAL
OVERVIEW
MOTOROLA
3.6.1 Internal Register Figure 3-4, ADDR[23:20] represented letter value represented determines base address module control registers. M68300 microcontrollers, equal M111, where logic state module mapping (MM) system integration module configuration register (SIMCR).
$YFF000
$YFFA00 $YFFA80 $YFFB00 $YFFB40 $YFFC00
RESERVED TPURAM CONTROL RESERVED 2-KBYTE TPURAM ARRAY
$YFFE00
$YFFFFF
ADDRESS
Figure Internal Register Memory 3.6.2 Address Space Maps Figure shows single memory space. Function codes FC[2:0] decoded externally that separate user/supervisor program/data spaces provided. Figure 3-6, decoded, resulting separate supervisor user spaces. FC[1:0] decoded, that separate program data spaces provided. Figure Figure 3-8, FC[2:0] decoded, resulting four separate memory spaces: supervisor/program, supervisor/data, user/program user/data. exception vectors located supervisor data space, except reset vector, which located supervisor program space. Only initial reset vector fixed processor's memory map. Once initialization complete, there fixed assignments. Since vector base register (VBR) provides base address vector table, vector table located anywhere memory. Refer SECTION CENTRAL PROCESSING UNIT more information concerning memory management, extended addressing, exception processing. Refer SECTION SYSTEM INTEGRATION MODULE more information concerning function codes address space types.
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MC68332 USER'S MANUAL
$000000
COMBINED SUPERVISOR USER SPACE
VECTOR VECTOR OFFSET NUMBER 0000 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 002C 0030 0034 0038 003C 0040-005C 16-23 006C 0064 0068 006C 0070 0074 0078 007C 0080-00BC 32-47 00C0-00EB 48-58 00EC-00FC 59-63 0100-03FC 64-255
TYPE EXCEPTION RESET INITIAL STACK POINTER RESET INITIAL ERROR ADDRESS ERROR ILLEGAL INSTRUCTION ZERO DIVISION CHK, CHK2 INSTRUCTIONS TRAPcc, TRAPV INSTRUCTIONS PRIVILEGE VIOLATION TRACE LINE 1010 EMULATOR LINE 1111 EMULATOR HARDWARE BREAKPOINT (RESERVED COPROCESSOR PROTOCOL VIOLATION) FORMAT ERROR UNINITIALIZED INTERRUPT FORMAT ERROR UNINITIALIZED INTERRUPT (UNASSIGNED, RESERVED) SPURIOUS INTERRUPT LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR INSTRUCTION VECTORS (0-15) (RESERVED, COPROCESSOR) (UNASSIGNED, RESERVED) USER-DEFINED VECTORS
$XX0000
$XX03FC
$YFF000
$YFFA00 $7FF000
INTERNAL REGISTERS
RESERVED TPURAM RESERVED $YFFA80 $YFFB00 $YFFB40 $YFFC00 $YFFE00
$FF0000 $FFFFFF NOTES:
INTERNAL REGISTERS
$YFFFFF
Location exception vector table determined vector base register. vector address vector base register vector offset. Location module control registers determined state module mapping (MM) configure register. M111, where state bit. Unused addresses within internal register block mapped externally. "RESERVED" blocks mapped externally.
COMB
Figure Overall Memory
MC68332 USER'S MANUAL
OVERVIEW
MOTOROLA 3-11
$000000
SUPERVISOR SPACE
VECTOR VECTOR OFFSET NUMBER 0000 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 002C 0030 0034 0038 003C 0040-005C 16-23 006C 0064 0068 006C 0070 0074 0078 007C 0080-00BC 32-47 00C0-00EB 48-58 00EC-00FC 59-63 0100-03FC 64-255
TYPE EXCEPTION RESET INITIAL STACK POINTER RESET INITIAL ERROR ADDRESS ERROR ILLEGAL INSTRUCTION ZERO DIVISION CHK, CHK2 INSTRUCTIONS TRAPcc, TRAPV INSTRUCTIONS PRIVILEGE VIOLATION TRACE LINE 1010 EMULATOR LINE 1111 EMULATOR HARDWARE BREAKPOINT (RESERVED COPROCESSOR PROTOCOL VIOLATION) FORMAT ERROR UNINITIALIZED INTERRUPT FORMAT ERROR UNINITIALIZED INTERRUPT (UNASSIGNED, RESERVED) SPURIOUS INTERRUPT LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR INSTRUCTION VECTORS (0-15) (RESERVED, COPROCESSOR) (UNASSIGNED, RESERVED) USER-DEFINED VECTORS
$000000
$XX0000
USER SPACE
$XX03FC
$YFF000
$YFFA00 $7FF000
INTERNAL REGISTERS
INTERNAL REGISTERS
$7FF0004
RESERVED TPURAM RESERVED
$YFFA80 $YFFB00 $YFFB40 $YFFC00
$YFFE00 $FF0000 $FFFFFF NOTES:
Location exception vector table determined vector base register. vector address vector base register vector offset. Location module control registers determined state module mapping (MM) configure register. M111, where state bit. Unused addresses within internal register block mapped externally. "RESERVED" blocks mapped externally. Some internal registers available user space.
INTERNAL REGISTERS
$YFFFFF
INTERNAL REGISTERS
$FF00004 $FFFFFF
Figure Separate Supervisor User Space
MOTOROLA 3-12
OVERVIEW
MC68332 USER'S MANUAL
$000000
VECTOR OFFSET 0000 0004
VECTOR NUMBER
EXCEPTION VECTORS LOCATED SUPERVISOR PROGRAM SPACE RESET INITIAL STACK POINTER RESET INITIAL
$000000
$XX0000 $XX0004
SUPERVISOR DATA SPACE
VECTOR VECTOR OFFSET NUMBER 0000 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 002C 0030 0034 0038 003C 0040-005C 16-23 006C 0064 0068 006C 0070 0074 0078 007C 0080-00BC 32-47 00C0-00EB 48-58 00EC-00FC 59-63 0100-03FC 64-255
EXCEPTION VECTORS LOCATED SUPERVISOR DATA SPACE RESET INITIAL STACK POINTER RESET INITIAL ERROR ADDRESS ERROR ILLEGAL INSTRUCTION ZERO DIVISION CHK, CHK2 INSTRUCTIONS TRAPcc, TRAPV INSTRUCTIONS PRIVILEGE VIOLATION TRACE LINE 1010 EMULATOR LINE 1111 EMULATOR HARDWARE BREAKPOINT (RESERVED COPROCESSOR PROTOCOL VIOLATION) FORMAT ERROR UNINITIALIZED INTERRUPT FORMAT ERROR UNINITIALIZED INTERRUPT (UNASSIGNED, RESERVED) SPURIOUS INTERRUPT LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR INSTRUCTION VECTORS (0-15) (RESERVED, COPROCESSOR) (UNASSIGNED, RESERVED) USER-DEFINED VECTORS
$XX0000
SUPERVISOR PROGRAM SPACE
$XX03FC
$YFF000
$YFFA00 $7FF000
INTERNAL REGISTERS
RESERVED TPURAM RESERVED $YFFA80 $YFFB00 $YFFB40 $YFFC00 $YFFE00
$FF0000 $FFFFFF NOTES:
INTERNAL REGISTERS
$YFFFFF
$FFFFFF
Location exception vector table determined vector base register. vector address vector base register vector offset. Location module control registers determined state module mapping (MM) configure register. M111, where state bit. Unused addresses within internal register block mapped externally. "RESERVED" blocks mapped externally. Some internal registers available user space.
SUPER
Figure Supervisor Space (Separate Program/Data Space)
MC68332 USER'S MANUAL
OVERVIEW
MOTOROLA 3-13
$000000
$000000
USER PROGRAM SPACE
USER DATA SPACE
$YFF000
$YFFA00 $7FF000
INTERNAL REGISTERS
RESERVED TPURAM RESERVED $YFFA80 $YFFB00 $YFFB40 $YFFC00 $YFFE00
$FF0000 $FFFFFF NOTES: $FFFFFF
INTERNAL REGISTERS
$YFFFFF
Location exception vector table determined vector base register. vector address vector base register vector offset. Unused addresses within internal register block mapped externally. "RESERVED" blocks mapped externally. Some internal registers available user space.
USER
Figure User Space (Separate Program/Data Space)
MOTOROLA 3-14
OVERVIEW
MC68332 USER'S MANUAL
System Reset following information concise reference only. MC68332 system reset complex operation. understand operation during after reset, refer SECTION SYSTEM INTEGRATION MODULE, paragraph Reset more complete discussion reset function. 3.7.1 Reset Mode Selection logic states certain data pins during reset determine operating configuration. addition, state MODCLK determines system clock source state BKPT determines what happens during subsequent breakpoint assertions. Table summary reset mode selection options. Table Reset Mode Selection
Mode Select DATA0 DATA1 Default Function (Pin Left High) CSBOOT 16-Bit CS[7:6] CS[8:6] CS[9:6] CS[10:6] DSACK0, DSACK1, AVEC, SIZ[1:0] IRQ[7:1] MODCLK Test Mode Disabled System Clock Background Mode Disabled Alternate Function (Pin Pulled Low) CSBOOT 8-Bit BGACK ADDR19 ADDR[20:19] ADDR[21:19] ADDR[22:19] ADDR[23:19] PORTE
DATA2
DATA3 DATA4 DATA5 DATA6 DATA7 DATA8
DATA9 DATA11 MODCLK BKPT
PORTF Test Mode Enabled EXTAL System Clock Background Mode Enabled
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MOTOROLA 3-15
3.7.2 Module Function During Reset Generally, pins associated with modules other than default port functions, input/output ports input state. This accomplished disabling functions appropriate control registers, clearing appropriate port data direction registers. Refer individual module sections this manual more information. Table summary module function reset. Table Module Functions
Module CPU32 Mnemonic DSI/IFETCH DSO/IPIPE BKPT/DSCLK TPUCH[15:0] T2CLK PQS7/TXD PQS[6:4]/PCS[3:1] PQS3/PCS0/SS PQS2/SCK PQS1/MOSI PQS0/MISO Function DSI/IFETCH DSO/IPIPE BKPT/DSCLK Input TCR2 Clock Discrete Input Discrete Input Discrete Input Discrete Input Discrete Input Discrete Input
MOTOROLA 3-16
OVERVIEW
MC68332 USER'S MANUAL
SECTION SYSTEM INTEGRATION MODULE
This section overview function. Refer Reference Manual (SIMRM/AD) comprehensive discussion capabilities. Refer APPENDIX REGISTER SUMMARY information concerning address register structure. General system integration module (SIM) consists five functional blocks. Figure block diagram SIM. system configuration protection block controls configuration parameters provides software watchdog monitors. addition, provides periodic interrupt generator support execution time-critical control routines. system clock generates clock signals used SIM, other modules, external devices. external interface handles transfer information between modules external address space. pins also configured general-purpose ports chip-select block provides chip-select signals. Each chip-select signal associated base register option register that contain programmable characteristics that chip select. Chip-select pins also configured generalpurpose output port system test block incorporates hardware necessary testing MCU. used perform factory tests, normal applications supported.
MC68332 USER'S MANUAL
SYSTEM INTEGRATION MODULE
MOTOROLA
SYSTEM CONFIGURATION PROTECTION
CLOCK SYNTHESIZER
CLKOUT EXTAL MODCLK
CHIP SELECTS
CHIP SELECTS
EXTERNAL EXTERNAL INTERFACE RESET
FACTORY TEST
FREEZE/QUOT
S(C)IM BLOCK
Figure System Integration Module Block Diagram System Configuration Protection system configuration protection functional block controls module configuration, preserves reset status, monitors internal activity, provides periodic interrupt generation. Figure block diagram submodule.
MOTOROLA
SYSTEM INTEGRATION MODULE
MC68332 USER'S MANUAL
MODULE CONFIGURATION TEST
RESET STATUS
HALT MONITOR
RESET REQUEST
MONITOR
BERR
SPURIOUS INTERRUPT MONITOR
CLOCK PRESCALER
SOFTWARE WATCHDOG TIMER
RESET REQUEST
PERIODIC INTERRUPT TIMER
[7:1]
PROTECT BLOCK
Figure System Configuration Protection 4.2.1 Module Mapping Control registers modules microcontroller mapped into 4-Kbyte block. state module mapping (MM) configuration register (SIMCR) determines where control register block located system memory map. When register addresses range from $7FF000 $7FFFFF; when register addresses range from $FFF000 $FFFFFF. 4.2.2 Interrupt Arbitration Each module that generate interrupt requests interrupt arbitration (IARB) field. Arbitration between interrupt requests same priority performed serial contention between IARB field values. Contention must take place whenever inMC68332 USER'S MANUAL SYSTEM INTEGRATION MODULE MOTOROLA
terrupt request acknowledged, even when there only single request pending. interrupt serviced, appropriate IARB field must have non-zero value. interrupt request from module with IARB field value %0000 recognized, CPU32 processes spurious interrupt exception. Because routes external interrupt requests CPU32, IARB field value used arbitration between internal external interrupts same priority. reset value IARB %1111, reset IARB value other modules %0000, which prevents interrupts from being discarded during initialization. Refer Interrupts discussion interrupt arbitration. 4.2.3 Show Internal Cycles show cycle allows internal transfers monitored externally. SHEN field SIMCR determines what external interface does during internal transfer operations. Table shows whether data driven externally, whether external arbitration occur. Refer 4.5.6.2 Show Cycles more information. Table Show Cycle Enable Bits
SHEN Action Show cycles disabled, external arbitration enabled Show cycles enabled, external arbitration disabled Show cycles enabled, external arbitration enabled Show cycles enabled, external arbitration enabled; internal activity halted grant
4.2.4 Factory Test Mode internal serve slave external master direct module testing. This test mode reserved factory test. Slave mode enabled holding DATA11 during reset. slave enabled (SLVEN) read-only that shows reset state DATA11. 4.2.5 Register Access CPU32 operate either privilege levels. Supervisor level more privileged than user level instructions system resources available supervisor level, access restricted user level. Effective privilege level protect system resources from uncontrolled access. state status register determines access level, whether user supervisor stack pointer used stacking operations. SUPV places global registers either supervisor user data space. When SUPV registers with controlled access accessible from either user supervisor privilege level; when SUPV registers with controlled access restricted supervisor access only. 4.2.6 Reset Status reset status register (RSR) latches internal status during reset. Refer 4.6.9 Reset Status Register more information.
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MC68332 USER'S MANUAL
4.2.7 Monitor internal monitor checks data size acknowledge (DSACK) autovector (AVEC) signal response times during normal cycles. monitor asserts internal error (BERR) signal when response time excessively long. DSACK AVEC response times measured clock cycles. Maximum allowable response time selected setting monitor timing (BMT) field system protection control register (SYPCR). Table shows periods allowed. Table Monitor Period
Monitor Time-out Period System Clocks System Clocks System Clocks System Clocks
monitor does check DSACK response external unless CPU32 initiates cycle. SYPCR enables internal monitor internal external cycles. system contains external masters, external monitor must implemented internal-to-external monitor option must disabled. When monitoring transfers 8-bit port, monitor does reset until both byte accesses word transfer completed. Monitor time-out period must least twice number clocks that single byte access requires. 4.2.8 Halt Monitor halt monitor responds assertion HALT signal internal bus. Refer 4.5.5.2 Double Faults more information. Halt monitor reset inhibited halt monitor (HME) SYPCR. 4.2.9 Spurious Interrupt Monitor During interrupt exception processing, CPU32 normally acknowledges interrupt request, recognizes highest priority source, then acquires vector responds request autovectoring. spurious interrupt monitor asserts internal error signal (BERR) interrupt arbitration occurs during interrupt exception processing. assertion BERR causes CPU32 load spurious interrupt exception vector into program counter. spurious interrupt monitor cannot disabled. Refer Interrupts further information. detailed information about interrupt exception processing, refer SECTION CENTRAL PROCESSING UNIT. 4.2.10 Software Watchdog software watchdog controlled software watchdog enable (SWE) SYPCR. When enabled, watchdog requires that service sequence written software service register SWSR periodic basis. servicing does take place, watchdog times asserts reset signal.
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MOTOROLA
Perform software watchdog service sequence follows: Write SWSR. Write SWSR. Both writes must occur before time-out order listed, number instructions executed between writes. Watchdog clock rate affected software watchdog prescale (SWP) software watchdog timing (SWT) fields SYPCR. determines system clock prescaling watchdog timer determines that options, either prescaling prescaling factor 512, selected. value affected state MODCLK during reset, shown Table 4-3. System software change value. Table MODCLK During Reset
MODCLK (External Clock) (Internal Clock) 512)
field selects divide ratio used establish software watchdog time-out period. Time-out period given following equations. Time-out Period -EXTAL Frequency Divide Ratio Divide Ratio Time-out Period -EXTAL Frequency Table shows ratio each combination bits. When SWT[1:0] modified, watchdog service sequence must performed before timeout period take effect. Table Software Watchdog Ratio
Ratio
Figure block diagram watchdog timer clock control periodic interrupt timer.
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MC68332 USER'S MANUAL
PITR FREEZE CLOCK PRECLK PITCLK 8-BIT MODULUS COUNTER INTERRUPT
EXTAL
CLOCK DISABLE
PRESCALER (29)
RESET SWCLK LPSTOP SWT1 SWT0 STAGE DIVIDER CHAIN (215)
BLOCK
Figure Periodic Interrupt Timer Software Watchdog Timer 4.2.11 Periodic Interrupt Timer periodic interrupt timer allows generation interrupts specific priority predetermined intervals. This capability often used schedule control system tasks that must performed within time constraints. timer consists prescaler, modulus counter, registers that determine interrupt timing, priority vector assignment. Refer SECTION CENTRAL PROCESSING UNIT further information about interrupt exception processing. periodic interrupt modulus counter clocked signal derived from buffered crystal oscillator (EXTAL) input unless external frequency source used. value periodic timer prescaler (PTP) periodic interrupt timer register (PITR) determines system clock prescaling watchdog timer. options, either prescaling, prescaling factor 512, selected. value affected state MODCLK during reset, shown Table System software change value. Table MODCLK Reset
MODCLK (External Clock) (Internal Clock) 512)
Either clock signal (EXTAL EXTAL 512) divided four before driving modulus counter (PITCLK). modulus counter initialized writing value periodic timer modulus (PITM) field PITR. zero value turns periodic timer. When modulus counter value reaches zero, interrupt generated. modulus counter then reloaded with value PIand counting repeats. value written PITR, loaded into modulus counter when current count completed.
MC68332 USER'S MANUAL SYSTEM INTEGRATION MODULE MOTOROLA
following expression calculate timer period. Modulus Prescaler Value Period -EXTAL Frequency Interrupt priority vectoring determined values periodic interrupt request level (PIRQL) periodic interrupt vector (PIV) fields periodic interrupt control register (PICR). Content PIRQL compared CPU32 interrupt priority mask determine whether interrupt recognized. Table shows priority PIRQL values. Because hardware prioritization, interrupt serviced before external interrupt request same priority. periodic timer continues when interrupt disabled. Table Periodic Interrupt Priority
PIRQL Priority Level Periodic Interrupt Disabled Interrupt Priority Level Interrupt Priority Level Interrupt Priority Level Interrupt Priority Level Interrupt Priority Level Interrupt Priority Level Interrupt Priority Level
field contains periodic interrupt vector. vector placed when interrupt request made. vector number used calculate address appropriate exception vector exception vector table. Reset value field $0F, which corresponds uninitialized interrupt exception vector. 4.2.12 Low-Power Stop Operation When CPU32 executes LPSTOP instruction, current interrupt priority mask stored clock control logic, internal clocks disabled according state STSIM SIMCR, enters low-power stop mode. monitor, halt monitor, spurious interrupt monitor inactive during low-power stop. During low-power stop, clock input software watchdog timer disabled timer stops. software watchdog begins again first rising clock edge after low-power stop ends. watchdog reset low-power stop. service sequence must performed reset timer. periodic interrupt timer does respond LPSTOP instruction, continues during LPSTOP. stop periodic interrupt timer, PITR must loaded with zero value before LPSTOP instruction executed. interrupt, external interrupt request, bring low-power stop condition higher priority than interrupt mask value stored clock control logic when lowpower stop initiated. LPSTOP terminated reset.
MOTOROLA SYSTEM INTEGRATION MODULE MC68332 USER'S MANUAL
4.2.13 Freeze Operation FREEZE signal halts operations during debugging. FREEZE asserted internally CPU32 breakpoint occurs while background mode enabled. When FREEZE asserted, only monitor, software watchdog, periodic interrupt timer affected. halt monitor spurious interrupt monitor continue operate normally. Setting freeze monitor (FRZBM) SIMCR disables monitor when FREEZE asserted, setting freeze software watchdog (FRZSW) disables software watchdog periodic interrupt timer when FREEZE asserted. When FRZSW set, FREEZE assertion must least times clock source period ensure accurate number counts. System Clock system clock provides timing signals modules external peripheral bus. Because fully static design, register memory contents affected when clock rate changes. System hardware software support changes clock rate during operation. system clock signal generated three ways. internal phaselocked loop synthesize clock from either internal reference external reference, clock signal input from external frequency source. Keep these clock sources mind while reading rest this section. Figure block diagram system clock. Refer APPENDIX ELECTRICAL CHARACTERISTICS clock specifications.
EXTAL
XTAL
VDDSYN
CLKOUT
CRYSTAL OSCILLATOR
PHASE COMPARATOR
LOW-PASS FILTER
FEEDBACK DIVIDER
SYSTEM CLOCK CONTROL
SYSTEM CLOCK
BLOCK
Figure System Clock Block Diagram
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MOTOROLA
4.3.1 Clock Sources state clock mode (MODCLK) during reset determines clock source. When MODCLK held high during reset, clock synthesizer generates clock signal from either internal external reference frequency clock synthesizer control register (SYNCR) determines operating frequency mode operation. When MODCLK held during reset, clock synthesizer disabled external system clock signal must applied SYNCR control bits have effect. generate reference frequency using internal oscillator reference crystal must connected between EXTAL XTAL pins. Figure shows recommended circuit.
330k XTAL
VSSI
EXTAL
Resistance capacitance based test circuit constructed with DAISHINKU DMX-38 32.768-kHz crystal.
Specific components must based crystal type. Contact crystal vendor exact circuit.
OSCILLATOR
Figure System Clock Oscillator Circuit external reference signal external system clock signal applied EXTAL pin, XTAL must left floating. External reference signal frequency must less than equal maximum specified reference frequency. External system clock signal frequency must less than equal maximum specified system clock frequency. When external system clock signal applied (PLL disabled, MODCLK during reset), duty cycle input critical, especially operating frequencies close maximum. relationship between clock signal duty cycle clock signal period expressed: Minimum External Clock Period Minimum External Clock High Time -50% Percentage Variation External Clock Input Duty Cycle 4.3.2 Clock Synthesizer Operation VDDSYN used power clock circuits when either internal external reference frequency applied. separate power source increases noise immunity used clock when powered down. quiet power supMOTOROLA 4-10 SYSTEM INTEGRATION MODULE MC68332 USER'S MANUAL
must used VDDSYN source. Adequate external bypass capacitors should placed close possible VDDSYN assure stable operating frequency. When external system clock signal applied disabled, VDDSYN should connected supply. Refer Reference Manual (SIMRM/ more information regarding system clock power supply conditioning. voltage controlled oscillator (VCO) generates system clock signal. maintain clock duty cycle, frequency either four times system clock frequency, depending state SYNCR. portion clock signal back divider/counter. divider controls frequency input phase comparator. other phase comparator input reference signal, either from crystal oscillator from external source. comparator generates control signal proportional difference phase between inputs. signal lowpass filtered used correct output frequency. Filter geometry vary, depending upon external environment required clock stability. Figure shows recommended filters. leakage must specified APPENDIX ELECTRICAL CHARACTERISTICS maintain optimum stability performance. external filter network connected required when external system clock signal applied disabled. must left floating this case.
0.1µF
0.1µF XFC1 VDDSYN
0.1µF
0.1µF
XFC1,
VSSI
0.01µF
VSSI NORMAL OPERATING ENVIRONMENT
0.01µF
0.01µF VDDSYN
HIGH-STABILITY OPERATING ENVIRONMENT
Maintain low-leakage node. Appendix electrical characteristics more information. Recommended loop filter reduced sensitivity low-frequency noise.
16/32 CONN
Figure System Clock Filter Networks synthesizer locks when frequency equal EXTAL frequency. Lock time affected filter time constant amount difference between comparator inputs. Whenever comparator input changes, synthesizer must relock. Lock status shown SLOCK SYNCR. During power-up, does come reset state until synthesizer locks. Crystal type, characteristic frequency, layout external oscillator circuitry affect lock time.
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When clock synthesizer used, control register SYNCR determines operating frequency various modes operation. SYNCR controls three-bit prescaler feedback divider. Setting increases speed factor four. SYNCR field determines count modulus modulo down counter, causing divide value When values change, frequency changes, there relock delay. SYNCR controls divide-by-two circuit that synthesizer feedback loop. When (reset state), divider enabled, system clock frequency one-fourth frequency; setting disables divider, doubling clock speed without changing speed. There relock delay when clock speed changed bit. Clock frequency determined SYNCR settings follows: SYSTEM REFERENCE
reset state SYNCR ($3F00) produces modulus-64 count. device perform correctly, system clock frequencies selected bits must within limits specified MCU. combination values that selects either operating frequency frequency greater than maximum specified values APPENDIX ELECTRICAL CHARACTERISTICS. Table shows clock control multipliers possible combinations SYNCR bits. Table shows clock frequencies available with 32.768-kHz reference maximum specified clock frequency 20.97 MHz. Table Clock Control Multipliers
obtain clock frequency kilohertz, find counter modulus left column, then multiply reference frequency value appropriate prescaler cell. Modulus 000000 000001 000010 011111 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 Prescalers [W:X] [W:X]
[W:X]
[W:X]
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Table Clock Control Multipliers (Continued)
obtain clock frequency kilohertz, find counter modulus left column, then multiply reference frequency value appropriate prescaler cell. Modulus 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Prescalers [W:X] [W:X] 1008 1024
[W:X]
[W:X] 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 1824 1856 1888 1920 1952 1984 2016 2048
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Table System Frequencies from 32.768-kHz Reference
obtain clock frequency kilohertz, find counter modulus left column, then multiply reference frequency value appropriate prescaler cell. Modulus 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 Prescaler [W:X] 1049 1180 1311 1442 1573 1704 1835 1966 2097 2228 2359 2490 2621 2753 2884 3015 3146 3277 3408 3539 3670 3801 3932 4063 4194 4325 4456 4588 4719 4850 4981 5112 5243 5374 5505 5636 5767 5898 [W:X] 1049 1311 1573 1835 2097 2359 2621 2884 3146 3408 3670 3932 4194 4456 4719 4981 5243 5505 5767 6029 6291 6554 6816 7078 7340 7602 7864 8126 8389 8651 8913 9175 9437 9699 9961 10224 10486 10748 11010 11272 11534 11796 [W:X] 1049 1573 2097 2621 3146 3670 4194 4719 5243 5767 6291 6816 7340 7864 8389 8913 9437 9961 10486 11010 11534 12059 12583 13107 13631 14156 14680 15204 15729 16253 16777 17302 17826 18350 18874 19399 19923 20447 20972 21496 22020 22544 23069 23593 [W:X] 1049 2097 3146 4194 5243 6291 7340 8389 9437 10486 11534 12583 13631 14680 15729 16777 17826 18874 19923 20972 22020 23069 24117 25166 26214 27263 28312 29360 30409 31457 32506 33554 34603 35652 36700 37749 38797 39846 40894 41943 42992 44040 45089 46137 47186
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Table System Frequencies from 32.768-kHz Reference (Continued)
obtain clock frequency kilohertz, find counter modulus left column, then multiply reference frequency value appropriate prescaler cell. Modulus 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Prescaler [W:X] 6029 6160 6291 6423 6554 6685 6816 6947 7078 7209 7340 7471 7602 7733 7864 7995 8126 8258 8389 [W:X] 12059 12321 12583 12845 13107 13369 13631 13894 14156 14418 14680 14942 15204 15466 15729 15991 16253 16515 16777 [W:X] 24117 24642 25166 25690 26214 26739 27263 27787 28312 28836 29360 2988 30409 30933 31457 31982 32506 33030 33554 [W:X] 48234 49283 50332 51380 52428 53477 54526 55575 56623 57672 58720 59769 60817 61866 62915 63963 65011 66060 67109
4.3.3 External Clock state external clock division (EDIV) SYNCR determines clock rate external clock signal (ECLK) available ADDR23. ECLK clock MC6800 devices peripherals. ECLK frequency system clock frequency divided eight system clock frequency divided sixteen. clock enabled CS10 field chip select assignment register (CSPAR1). ECLK operation during low-power stop described following paragraph. Refer Chip Selects more information about external clock. 4.3.4 Low-Power Operation Low-power operation initiated CPU32. reduce power consumption selectively, STOP bits each module configuration register. minimize overall microcontroller power consumption, execute LPSTOP instruction, which causes turn system clock. When individual module STOP bits set, clock signals inside each module turned off, module registers still accessible. When executes LPSTOP, special space cycle writes copy current interrupt mask into clock control logic. brings low-power operation when either interrupt higher priority than stored mask reset occurs. Refer 4.5.4.2 LPSTOP Broadcast Cycle SECTION CENTRAL PROCESSING UNIT more information.
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During low-power stop, unless system clock signal supplied external source that source removed, clock control logic clock signal (SIMCLK) continue operate. periodic interrupt timer input logic RESET pins clocked SIMCLK. also continue generate CLKOUT signal while low-power mode. stop mode system integration module clock (STSIM) stop mode external clock (STEXT) bits SYNCR determine clock operation during low-power stop. Table summary effects STSIM STEXT. MODCLK value logic level MODCLK during last reset before LPSTOP execution. clock state held low. synthesizer turned during LPSTOP, there relock delay after turned back Table Clock Control
Mode LPSTOP Pins MODCLK EXTAL External Clock External Clock External Clock External Clock External Clock Crystal Reference Crystal Reference Crystal Reference Crystal Reference Crystal Reference SYNCR Bits STSIM STEXT SIMCLK External Clock External Clock External Clock External Clock External Clock Crystal Reference Crystal Reference Clock Status CLKOUT External Clock External Clock External Clock Crystal/ Reference ECLK External Clock External Clock External Clock
4.3.5 Loss Reference Signal state reset enable (RSTEN) SYNCR determines what happens when clock logic detects reference failure. When RSTEN cleared (default state reset), clock synthesizer forced into operating condition referred limp mode. Limp mode frequency varies from device device, maximum limp frequency does exceed half maximum system clock when maximum system clock frequency when When RSTEN set, resets MCU. limp status (SLIMP) SYNCR indicates whether synthesizer reference signal. when reference failure detected.
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External Interface external interface (EBI) transfers information between internal external devices. Figure shows basic system with external memory peripherals.
ASYNC PERIPHERAL
DSACK IACK ADDR[15:0] DATA[15:0]
CLKOUT DSACK ADDR[23:0] DATA[15:0]
MEMORY
ADDR[23:0] DATA[15:8]
CSBOOT
MEMORY
ADDR[23:0] DATA[7:0]
decoded provide additional address space. Varies depending upon peripheral memory size.
EXAMPLE BLOCK
Figure Basic System external address lines data lines. provides dynamic sizing between 8-bit 16-bit data accesses. supports byte, word, long-word transfers. Ports accessed through asynchronous cycles controlled data transfer (SIZ1 SIZ0) data size acknowledge pins (DSACK1 DSACK0). Multiple cycles required transfer from 8-bit port. maximum number bits transferred during access referred port width. Widths eight sixteen bits accessed asynchronous cycles controlled data size (SIZ[1:0]) data size acknowledge (DSACK[1:0]) signals. Multiple cycles required dynamically-sized transfer. flexibility minimize necessity external logic, chip-select logic synchronized with transfers. Refer Chip Selects more information.
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4.4.1 Signals address provides addressing information external devices. data transfers 8-bit 16-bit data between external devices. Strobe signals, address another data bus, indicate validity address provide timing information data. Control signals indicate beginning each cycle, address space take place size transfer, type cycle. External devices decode these signals respond transfer data terminate cycle. operates asynchronous mode port width. 4.4.1.1 Address signals ADDR[23:0] define address byte most significant byte) transferred during cycle. places address beginning cycle. address valid while asserted. 4.4.1.2 Address Strobe Address strobe (AS) timing signal that indicates validity address address many control signals. asserted one-half clock after beginning cycle. 4.4.1.3 Data Signals DATA[15:0] form bidirectional, nonmultiplexed parallel that transfers data from MCU. read write operation transfer eight sixteen bits data cycle. During read cycle, data latched last falling edge clock that cycle. write cycle, bits data driven, regardless port width operand size. places data data one-half clock cycle after asserted write cycle. 4.4.1.4 Data Strobe Data strobe (DS) timing signal. read cycle, asserts signal external device place data bus. asserted same time during read cycle. write cycle, signals external device that data valid. asserts full clock cycle after assertion during write cycle. 4.4.1.5 Read/Write Signal read/write signal (R/W) determines direction transfer during cycle. This signal changes state, when required, beginning cycle, valid while asserted. only transitions when write cycle preceded read cycle vice versa. signal remain consecutive write cycles.
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4.4.1.6 Size Signals Size signals (SIZ[1:0]) indicate number bytes remaining transferred during operand cycle. They valid while address strobe (AS) asserted. Table shows SIZ0 SIZ1 encoding. Table 4-10 Size Signal Encoding
SIZ1 SIZ0 Transfer Size Byte Word Byte Long Word
4.4.1.7 Function Codes generates function code output signals FC[2:0] indicate type activity occurring data address bus. These signals considered address extensions that externally decoded determine which eight external address spaces accessed during cycle. Address space designated space. space used control information normally associated with read write cycles. Function codes valid while asserted. Table 4-11 shows address space encoding. Table 4-11 Address Space Encoding
Address Space Reserved User Data Space User Program Space Reserved Reserved Supervisor Data Space Supervisor Program Space Space
supervisor status register determines whether operating supervisor user mode. Addressing mode instruction being executed determine whether memory access program data space. 4.4.1.8 Data Size Acknowledge Signals During normal transfers, external devices assert data size acknowledge signals (DSACK[1:0]) indicate port width MCU. During read cycle, these signals tell terminate cycle latch data. During write cycle, signals indicate that external device successfully stored data that cycle terminate. DSACK[1:0] also supplied internally chip-select logic. Refer Chip Selects more information.
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4.4.1.9 Error Signal error signal (BERR) asserted when cycle properly terminated DSACK AVEC assertion. BERR also asserted same time DSACK, provided appropriate timing requirements met. Refer 4.5.5 Exception Control Cycles more information. internal monitor generate BERR signal internal internal-to-external transfers. external master must provide BERR generation drive BERR pin, because internal BERR monitor information about transfers initiated external master. Refer 4.5.6 External Arbitration more information. 4.4.1.10 Halt Signal halt signa (HALT) asserted external device debugging purposes cause single cycle operation combination with BERR) retry cycle error. HALT signal affects external cycles only, program requiring external continue executing, unaffected HALT signal. When completes cycle with HALT signal asserted, DATA[15:0] placed high-impedance state, control signals driven inactive; address, function code, size, read/write signals remain same state. HALT still asserted once mastership returned MCU, address, function code, size, read/write signals again driven their previous states. does service interrupt requests while halted. Refer 4.5.5 Exception Control Cycles further information. 4.4.1.11 Autovector Signal autovector signal (AVEC) used terminate external interrupt acknowledge cycles. Assertion AVEC causes CPU32 generate vector numbers locate interrupt handler routine. continuously asserted, autovectors generated external interrupt requests. AVEC ignored during other cycles. Refer Interrupts more information. AVEC external interrupt requests also supplied internally chip-select logic. Refer Chip Selects more information. autovector function disabled when there external master. Refer 4.5.6 External Arbitration more information. 4.4.2 Dynamic Sizing dynamically interprets port size addressed device during each cycle, allowing operand transfers from 8-bit 16-bit ports. During operand transfer cycle, external device signals port size indicates completion cycle through DSACK inputs, shown Table 4-12. Chip-select logic generate data size acknowledge signals external device. Refer Chip Selects further information.
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Table 4-12 Effect DSACK Signals
DSACK1 DSACK0 Result Insert Wait States Current Cycle Complete Cycle Data Port Size Bits Complete Cycle Data Port Size Bits Reserved
executing instruction that reads long-word operand from 16-bit port, latches bits valid data then runs another cycle obtain other bits. operation 8-bit port similar, requires four read cycles. addressed device uses DSACK signals indicate port width. instance, 16-bit device always returns DSACK 16-bit port (regardless whether cycle byte word operation). Dynamic sizing requires that portion data used transfer from particular port size fixed. 16-bit port must reside data bits [15:0], 8-bit port must reside data bits [15:8]. This minimizes number cycles needed transfer data ensures that transfers valid data. always attempts transfer maximum amount data cycles. word operation, assumed that port bits wide when cycle begins. Operand bytes designated shown Figure 4-8. OP[0:3] represent order access. instance, most significant byte long-word operand, accessed first, while OP3, least significant byte, accessed last. bytes word-length operand (most significant) OP1. single byte bytelength operand OP0.
Operand Long Word Three Byte Word Byte Byte Order
Figure Operand Byte Order 4.4.3 Operand Alignment data multiplexer establishes necessary connections different combinations address data sizes. multiplexer takes bytes 16-bit routes them their required positions. Positioning bytes determined size address outputs. SIZ1 SIZ0 indicate remaining number bytes transferred during current cycle. number bytes transferred equal less than size indicated SIZ1 SIZ0, depending port width. ADDR0 also affects operation data multiplexer. During operand transfer, ADDR[23:1] indicate word base address portion operand accessed, ADDR0 indicates byte offset from base.
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4.4.4 Misaligned Operands CPU32 architecture uses basic operand size bits. operand misaligned when overlaps word boundary. This determined value ADDR0. When ADDR0 even address), address word byte boundary. When ADDR0 address), address byte boundary only. byte operand aligned address; word long-word operand misaligned address. largest amount data that transferred single cycle aligned word. transfers long-word operand through 16-bit port, most significant operand word transferred first cycle least significant operand word transferred following cycle. 4.4.5 Operand Transfer Cases Table 4-13 summary operands aligned various types transfers. entries portions requested operand that read written during cycle defined SIZ1, SIZ0, ADDR0 that cycle. following paragraphs discuss allowable transfer cases detail. Table 4-13 Operand Transfer Cases
Transfer Case Byte 8-Bit Port (Even/Odd) Byte 16-Bit Port (Even) Byte 16-Bit Port (Odd) Word 8-Bit Port (Aligned) Word 8-Bit Port (Misaligned)1 Word 16-Bit Port (Aligned) Word 16-Bit Port (Misaligned)1 Long Word 8-Bit Port (Aligned) Long Word 8-Bit Port (Misaligned)1 Long Word 16-Bit Port (Aligned) Long Word 16-Bit Port (Misaligned)1 Byte 8-Bit Port (Aligned)2 Byte 8-Bit Port (Misaligned)2 [1:0] Read Cycles ADDR0 DSACK DATA DATA [1:0] [15:8] [7:0] Write Cycles DATA DATA Next [15:8] [7:0] Cycle (OP0) (OP0) (OP0) (OP1) (OP0) (OP0) (OP1) (OP0) (OP0) (OP1) (OP0)
NOTES: CPU32 does support misaligned transfers. Three-byte transfer cases occur only result long word byte transfer.
Operation Internal microcontroller modules typically accessed system clock cycles, with wait states. Regular external cycles handshaking between external peripherals manage transfer size data. These accesses take three system clock cycles, again with wait states. During regular cycles, wait states inserted needed control logic. Refer 4.5.2 Regular Cycles more information.
MOTOROLA 4-22 SYSTEM INTEGRATION MODULE MC68332 USER'S MANUAL
Fast-termination cycles, which two-cycle external accesses with wait states, chip-select logic generate handshaking signals internally. Chip-select logic also used insert wait states before internal generation handshaking signals. Refer 4.5.3 Fast Termination Cycles Chip Selects more information. control signal timing, well chip-select signal timing, specified APPENDIX ELECTRICAL CHARACTERISTICS. Refer Reference Manual (SIMRM/AD) more information about each type cycle. responsible de-skewing signals issues both start cycle. addition, responsible de-skewing acknowledge data signals from peripheral devices. 4.5.1 Synchronization CLKOUT External devices connected operate clock frequency different from frequencies long external devices satisfy interface signal timing constraints. Although cycles classified asynchronous, they interpreted relative system clock output (CLKOUT). Descriptions made terms individual system clock states, labeled {S0, S2,., SN}. designation "state" refers logic level clock signal, does correspond implemented machine state. clock cycle consists successive states. Refer APPENDIX ELECTRICAL CHARACTERISTICS more information. cycles terminated DSACK assertion normally require minimum three CLKOUT cycles. support systems that CLKOUT generate DSACK other inputs, asynchronous input setup time asynchronous input hold times specified. When these specifications met, guaranteed recognize appropriate signal specific edge CLKOUT signal. read cycle, when assertion DSACK recognized particular falling edge clock, valid data latched into next falling clock edge, provided that data meets data setup time. this case, parameter asynchronous operation ignored. When system asserts DSACK required window around falling edge obeys protocol maintaining DSACK BERR HALT until throughout clock edge that negates wait states inserted. cycle runs maximum speed three clocks cycle. ensure proper operation system synchronized CLKOUT, when either BERR, BERR HALT asserted after DSACK, BERR BERR HALT) assertion must satisfy appropriate data-in setup hold times before falling edge clock cycle after DSACK recognized. 4.5.2 Regular Cycles following paragraphs contain discussion cycles that external control logic. Refer 4.5.3 Fast Termination Cycles information about fast cycles.
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initiate transfer, asserts address SIZ[1:0] signals. signals ADDR0 externally decoded select active portion data (refer 4.4.2 Dynamic Sizing). When valid, peripheral device either places data (read cycle) latches data from (write cycle), then asserts DSACK[1:0] combination that indicates port size. DSACK[1:0] signals asserted before data from peripheral device valid read cycle. ensure valid data latched into MCU, maximum period between DSACK assertion assertion specified. There specified maximum period between assertion DSACK. Although transfer data minimum three clock cycles when cycle terminated with DSACK, inserts wait cycles clock period increments until either DSACK signal goes low. NOTE monitor asserts BERR when response time exceeds predetermined limit. monitor period determined field SYPCR. monitor cannot disabled; maximum monitor period system clock cycles. peripheral responds access, access invalid, external logic should assert BERR HALT signals abort cycle (when BERR HALT asserted simultaneously, CPU32 acts though only BERR asserted). termination signals asserted within specified period, monitor terminates cycle. 4.5.2.1 Read Cycle During read cycle, transfers data from external memory peripheral device. instruction specifies long-word word operation, attempts read bytes once. byte operation, reads byte. portion data from which each byte read depends operand size, peripheral address, peripheral port size. Figure flowchart word read cycle. Refer 4.4.2 Dynamic Sizing, 4.4.4 Misaligned Operands, Reference Manual (SIMRM/AD) more information.
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ADDRESS DEVICE (S0) READ DRIVE ADDRESS ADDR[23:0] DRIVE FUNCTION CODE FC[2:0] DRIVE SIZ[1:0] OPERAND SIZE
PERIPHERAL
ASSERT (S1)
PRESENT DATA (S2) DECODE ADDR, R/W, SIZ[1:0], PLACE DATA DATA[15:0] DATA[15:8] 8-BIT DATA DRIVE DSACK SIGNALS
DECODE DSACK (S3)
LATCH DATA (S4)
NEGATE (S5)
TERMINATE CYCLE (S5) REMOVE DATA FROM DATA NEGATE DSACK
START NEXT CYCLE (S0)
FLOW
Figure Word Read Cycle Flowchart 4.5.2.2 Write Cycle During write cycle, transfers data external memory peripheral device. instruction specifies long-word word operation, attempts write bytes once. byte operation, writes byte. portion data upon which each byte written depends operand size, peripheral address, peripheral port size. Refer 4.4.2 Dynamic Sizing 4.4.4 Misaligned Operands more information. Figure 4-10 flowchart write-cycle operation word transfer. Refer Reference Manual (SIMRM/AD) more information.
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ADDRESS DEVICE (S0) WRITE DRIVE ADDRESS ADDR[23:0] DRIVE FUNCTION CODE FC[2:0] DRIVE SIZ[1:0] OPERAND SIZE
PERIPHERAL
ASSERT (S1)
PLACE DATA DATA[15:0] (S2)
ASSERT WAIT DSACK (S3)
ACCEPT DATA DECODE ADDRESS LATCH DATA FROM DATA ASSERT DSACK SIGNALS
OPTIONAL STATE (S4)
CHANGE
TERMINATE OUTPUT TRANSFER (S5) NEGATE REMOVE DATA FROM DATA
TERMINATE CYCLE NEGATE DSACK
START NEXT CYCLE
FLOW
Figure 4-10 Write Cycle Flowchart 4.5.3 Fast Termination Cycles When external device fast access time, chip-select circuit fast-termination option provide two-cycle external transfer. Because chip-select circuits driven from system clock, cycle termination inherently synchronized with system clock. multiple chip selects used select same device that support fast termination, match conditions occur simultaneously, program DSACK field each associated chip-select option register fast termination. Alternately, program DSACK field fast termination remaining DSACK fields external termination. Fast termination cycles internal handshaking signals generated chip-select logic. initiate transfer, asserts address SIZ[1:0] signals.
MOTOROLA 4-26 SYSTEM INTEGRATION MODULE MC68332 USER'S MANUAL
When valid, peripheral device either places data (read cycle) latches data from (write cycle). appropriate time, chipselect logic asserts data size acknowledge signals. DSACK option fields chip-select option registers determine whether internally generated DSACK externally generated DSACK used. fast termination cycles, F-term encoding (%1110) must used. Refer 4.8.1 Chip-Select Registers information about fast-termination setup. fast-termination, external device must fast enough have data ready, within specified setup time, falling edge Refer APPENDIX ELECTRICAL CHARACTERISTICS tabular information about fast termination timing. When fast termination use, asserted during read cycles during write cycles. STRB field chip-select option register used must programmed with address strobe encoding assert chip select signal fast-termination write. 4.5.4 Space Cycles Function code signals FC[2:0] designate which eight external address spaces accessed during cycle. Address space designated space. space used control information normally associated with read write cycles. Function codes valid only while asserted. Refer 4.4.1.7 Function Codes more information codes encoding. During space access, ADDR[19:16] encoded reflect type access being made. Figure 4-11 shows three encodings used 68300 family microcontrollers. These encodings represent breakpoint acknowledge (Type cycles, power stop broadcast (Type cycles, interrupt acknowledge (Type cycles. Refer Interrupts information about interrupt acknowledge cycles.
SPACE CYCLES FUNCTION CODE BREAKPOINT ACKNOWLEDGE ADDRESS
BKPT#
POWER STOP BROADCAST INTERRUPT ACKNOWLEDGE
LEVEL SPACE TYPE FIELD
SPACE
Figure 4-11 Space Address Encoding
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MOTOROLA 4-27
4.5.4.1 Breakpoint Acknowledge Cycle Breakpoints stop program execution predefined point during system development. Breakpoints used alone conjunction with background debugging mode. following paragraphs discuss breakpoint processing when background debugging mode enabled. SECTION CENTRAL PROCESSING UNIT more information exception processing background debugging mode. M68300 microcontrollers, both hardware software initiate breakpoints. 4.5.4.1.1 Software Breakpoints CPU32 BKPT instruction allows user insert breakpoints through software. responds this instruction initiating breakpoint-acknowledge read cycle space. places breakpoint acknowledge (%0000) code ADDR[19:16], breakpoint number (bits [2:0] BKPT opcode) ADDR[4:2], (indicating software breakpoint) ADDR1. external breakpoint circuitry decodes function code address lines responds either asserting BERR placing instruction word data asserting DSACK. cycle terminated DSACK, CPU32 reads instruction data inserts instruction into pipeline. (For 8-bit ports, this instruction fetch require read cycles.) cycle terminated BERR, CPU32 then performs illegal-instruction exception processing: acquires number illegal-instruction exception vector, computes vector address from this number, loads content vector address into jumps exception handler routine that address. 4.5.4.1.2 Hardware Breakpoints Assertion BKPT input initiates hardware breakpoint. responds initiating breakpoint-acknowledge read cycle space. places $00001E address bus. (The breakpoint acknowledge code %0000 placed ADDR[19:16], breakpoint number value %111 placed ADDR[4:2], ADDR1 one, indicating hardware breakpoint.) external breakpoint circuitry decodes function code address lines, places instruction word data bus, asserts BERR. then performs hardware breakpoint exception processing: acquires number hardware breakpoint exception vector, computes vector address from this number, loads content vector address into jumps exception handler routine that address. external device asserts DSACK rather than BERR, ignores breakpoint continues processing. When BKPT assertion synchronized with instruction prefetch, processing breakpoint exception occurs that instruction. prefetched instruction "tagged" with breakpoint when enters instruction pipeline, breakpoint exception occurs after instruction executes. pipeline flushed before
MOTOROLA 4-28 SYSTEM INTEGRATION MODULE MC68332 USER'S MANUAL
tagged instruction executed, breakpoint occurs. When BKPT assertion synchronized with operand fetch, exception processing occurs instruction during which BKPT latched. Refer CPU32 Reference Manual (CPU32RM/AD) Reference Manual (SIMRM/AD) additional information.
MC68332 USER'S MANUAL
SYSTEM INTEGRATION MODULE
MOTOROLA 4-29
BREAKPOINT OPERATION FLOW CPU32 ACKNOWLEDGE BREAKPOINT BREAKPOINT INSTRUCTION EXECUTED: READ FUNCTION CODE SPACE PLACE SPACE TYPE ADDR[19:16] PLACE BREAKPOINT NUMBER ADDR[4:2] CLEAR T-BIT (ADDR1) ZERO SIZE WORD ASSERT BKPT ASSERTED: READ FUNCTION CODE SPACE PLACE SPACE TYPE ADDR[19:16] PLACE ONES ADDR[4:2] T-BIT (ADDR1) SIZE WORD ASSERT PERIPHERAL
BKPT INSTRUCTION EXECUTED: PLACE REPLACEMENT OPCODE DATA ASSERT DSACK ASSERT BERR INITIATE EXCEPTION PROCESSING BKPT ASSERTED: ASSERT DSACK ASSERT BERR INITIATE EXCEPTION PROCESSING
BREAKPOINT INSTRUCTION EXECUTED DSACK ASSERTED: LATCH DATA NEGATE BKPT ASSERTED DSACK ASSERTED: NEGATE BERR ASSERTED: NEGATE
BKPT INSTRUCTION EXECUTED: PLACE LATCHED DATA INSTRUCTION PIPELINE CONTINUE PROCESSING BKPT ASSERTED: CONTINUE PROCESSING
NEGATE DSACK BERR
BKPT INSTRUCTION EXECUTED: INITIATE ILLEGAL INSTRUCTION PROCESSING BKPT ASSERTED: INITIATE HARDWARE BREAKPOINT PROCESSING
1110A
Figure 4-12 Breakpoint Operation Flowchart
MOTOROLA 4-30
SYSTEM INTEGRATION MODULE
MC68332 USER'S MANUAL
4.5.4.2 LPSTOP Broadcast Cycle Low-power stop initiated CPU32. Individual modules stopped setting STOP bits each module configuration register, turn system clocks after execution LPSTOP instruction. When executes LPSTOP, LPSTOP broadcast cycle generated. brings low-power mode when either interrupt higher priority than stored mask reset occurs. Refer SECTION CENTRAL PROCESSING UNIT more information. During LPSTOP broadcast cycle, performs space write address $3FFFE. This write puts copy interrupt mask value clock control logic. mask encoded data shown Figure 4-13. LPSTOP space cycle shown externally available) indication external devices that going into low-power stop mode. provides internally generated DSACK response this cycle. timing this cycle same fast write cycle.
MASK
Figure 4-13 LPSTOP Interrupt Mask Level 4.5.5 Exception Control Cycles external device chip-select circuit must assert least DSACK[1:0] signals AVEC signal terminate cycle normally. error processing occurs when cycles terminated expected manner. internal monitor used generate BERR internally, causing error exception taken. cycles also terminated assertion external BERR HALT signal, assertion signals simultaneously. Acceptable cycle termination sequences summarized follows. case numbers refer Table 4-5, which indicates results each type cycle termination. Normal Termination DSACK asserted; BERR HALT remain negated (case Halt Termination HALT asserted same time before DSACK, BERR remains negated (case Error Termination BERR asserted lieu same time before DSACK, after DSACK, HALT remains negated; BERR negated same time after DSACK.
MC68332 USER'S MANUAL
SYSTEM INTEGRATION MODULE
MOTOROLA 4-31
Retry Termination HALT BERR asserted lieu same time before DSACK after DSACK; BERR negated same time after DSACK; HALT negated same time after BERR. Table 4-14 shows various combinations control signal sequences resulting cycle terminations. Table 4-14 DSACK, BERR, HALT Assertion Results
Case Number Control Signal Asserted Rising Edge State NA/A NA/A Result
DSACK BERR HALT DSACK BERR HALT DSACK BERR HALT DSACK BERR HALT DSACK BERR HALT DSACK BERR HALT
Normal termination.
Halt termination: normal cycle terminate halt. Continue when HALT negated. error termination: terminate take error exception, possibly deferred. error termination: terminate take error exception, possibly deferred. Retry termination: terminate retry when HALT negated. Retry termination: terminate retry when HALT negated.
NOTES:
number current even state (S2, etc.). Signal asserted this state. Signal asserted this state Don't care. Signal asserted previous state remains asserted this state.
properly control termination cycle retry error condition, DSACK, BERR, HALT must asserted negated with rising edge clock. This ensures that when signals asserted simultaneously, required setup time hold time both them same falling edge clock. (Refer APPENDIX ELECTRICAL CHARACTERISTICS timing requirements.) External circuitry that provides these signals must designed with these constraints mind, else internal monitor must used. DSACK, BERR, HALT negated after negated. WARNING DSACK BERR remain asserted into next cycle, that cycle terminated prematurely.
MOTOROLA 4-32
SYSTEM INTEGRATION MODULE
MC68332 USER'S MANUAL
4.5.5.1 Errors CPU32 treats errors type exception. error exception processing begins when detects assertion BERR signal internal monitor external source) while HALT signal remains negated. BERR assertions force immediate exception processing. signal synchronized with normal cycles latched into CPU32 cycle which asserted. Because cycles overlap instruction boundaries, error exception processing occur instruction which cycle begins. Timing BERR detection/acknowledge dependent upon several factors: Which cycle instruction terminated assertion BERR. number cycles instruction during which BERR asserted. number cycles instruction following instruction which BERR asserted. Whether BERR asserted during program space access data space access. Because these factors, impossible predict precisely long after occurrence error error exception processed. CAUTION external interface does latch data when external cycle terminated error. When this occurs during instruction prefetch, precharge state (bus pulled high, $FF) latched into CPU32 instruction register, with indeterminate results. 4.5.5.2 Double Faults Exception processing error exceptions follows standard exception processing sequence. Refer SECTION CENTRAL PROCESSING UNIT more information about exceptions. However, special case error, called double fault, abort exception processing. BERR assertion detected until instruction complete. BERR latch cleared first instruction BERR exception handler. Double fault occurs ways: When error exception processing begins second BERR detected before first instruction first exception handler executed. When more errors occur before first instruction after RESET exception executed. error occurs while CPU32 loading information from error stack frame during return from exception (RTE) instruction. Multiple errors within single instruction that generate multiple cycles cause single error exception after instruction been executed.
MC68332 USER'S MANUAL
SYSTEM INTEGRATION MODULE
MOTOROLA 4-33
Immediately after assertion second BERR, halts drives HALT line low. Only reset restart halted MCU. However, arbitration still occur (refer 4.5.6 External Arbitration). error address error that occurs after exception processing been completed (during execution exception handler routine, later) does cause double fault. continues retry same cycle long external hardware requests 4.5.5.3 Retry Operation When external device asserts BERR HALT during cycle, enters retry sequence. delayed retry also occur. terminates cycle, places signals their inactive state, does begin another cycle until BERR HALT signals negated external logic. After synchronization delay, retries previous cycle using same address, function codes, data (for write), control signals. BERR signal should negated before read cycle ensure correct operation retried cycle. BERR, HALT asserted same cycle, will enter rerun sequence first relinquishes external master. Once external master returns negates BERR HALT, runs previous cycle. This feature allows external device correct problem that caused error then cycle again. retries read write cycle indivisible read-modify-write operation separately; remains asserted during entire retry sequence. will relinquish while asserted. device that requires give retry cycle during read-modify-write cycle must assert BERR only (HALT must remain negated). error handler software should examine read-modify-write special status word take appropriate action resolve this type fault when occurs. 4.5.5.4 Halt Operation When HALT asserted while BERR asserted, halts external activity after negation DSACK. complete current word transfer progress. long-word byte transfer, this could after word byte transfer, activity ceases after Negating reasserting HALT according timing requirements provides single-step (bus cycle cycle) operation. HALT signal affects external cycles only, that program that does external continue executing. During dynamically-sized 8-bit transfers, external activity stop next cycle boundary. Occurrence error while HALT asserted causes CPU32 initiate retry sequence. When completes cycle while HALT signal asserted, data goes high-impedance state signals driven their inactive states. Address, function code, size, read/write signals remain same state.
MOTOROLA 4-34
SYSTEM INTEGRATION MODULE
MC68332 USER'S MANUAL
halt operation effect arbitration (refer 4.5.6 External Arbitration). However, when external arbitration occurs while halted, address control signals high-impedance state. HALT still asserted when regains control bus, address, function code, size, read/write signals revert previous driven states. cannot service interrupt requests while halted. 4.5.6 External Arbitration design provides single master time. Either external device master. arbitration protocols determine when external device become master. arbitration requests recognized during normal processing, HALT assertion, when halted double fault. controller manages arbitration signals that lowest priority. External devices that need obtain must assert arbitration signals sequences described following paragraphs. Systems that include several devices that become master require external circuitry assign priorities devices, that when more external devices attempt become master same time, having highest priority becomes master first. protocol sequence external device asserts request signal (BR); asserts grant signal (BG) indicate that available; external device asserts grant acknowledge (BGACK) signal indicate that assumed mastership. asserted during cycle between cycles. asserted response guarantee operand coherency, only asserted operand transfer. Additionally, asserted until indivisible read-modifywrite operation (when negated). more than external device master, required external arbitration must begin when requesting device receives external device must assert BGACK when assumes mastership, must maintain BGACK assertion long master. conditions must external device assume mastership. device must receive through arbitration process, BGACK must inactive, indicating that other master active. This technique allows processing requests during data transfer cycles. negated clock cycles after BGACK transition. However, requests still pending after negated, asserts again within clock cycles. This additional assertion allows external arbitration circuitry select next master before current master released bus. Refer Figure 4-14, which shows arbitration single device. flowchart shows negated same time BGACK asserted.
MC68332 USER'S MANUAL SYSTEM INTEGRATION MODULE MOTOROLA 4-35
REQUESTING DEVICE REQUEST
GRANT ARBITRATION ASSERT GRANT (BG)
ASSERT REQUEST (BR)
ACKNOWLEDGE MASTERSHIP EXTERNAL ARBITRATION DETERMINES NEXT MASTER NEXT MASTER WAITS BGACK NEGATED NEXT MASTER ASSERTS BGACK BECOME MASTER MASTER NEGATES
TERMINATE ARBITRATION NEGATE (AND WAIT BGACK NEGATED)
OPERATE MASTER PERFORM DATA TRANSFERS (READ WRITE CYCLES) ACCORDING SAME RULES PROCESSOR USES
RELEASE MASTERSHIP RE-ARBITRATE RESUME PROCESSOR OPERATION NEGATE BGACK
FLOW
Figure 4-14 Arbitration Flowchart Single Request State changes occur next rising edge CLKOUT after internal signal valid. signal transitions falling edge clock after state reached during which changes. control signals (controlled driven immediately following state change, when mastership returned MCU. State which both negated, state arbiter while master. Request acknowledge keep arbiter state long they both negated. 4.5.6.1 Slave (Factory Test) Mode Arbitration This mode used factory production testing internal modules. supported user operating mode. Slave mode enabled holding DATA11 during reset. slave mode, when asserted, slaved external master that full access internal registers. 4.5.6.2 Show Cycles normally performs internal data transfers without affecting external bus, possible show these transfers during debugging. asserted externally during show cycles.
MOTOROLA 4-36 SYSTEM INTEGRATION MODULE MC68332 USER'S MANUAL
Show cycles controlled SHEN field SIMCR (refer 4.2.3 Show Internal Cycles). This field cleared reset. When show cycles disabled, address bus, function codes, size, read/write signals reflect internal activity, asserted externally external data pins high-impedance state during internal accesses. When show cycles enabled, asserted externally during internal cycles, internal data driven external data bus. Because internal cycles normally continue when external granted, SHEN encoding halts internal activity while there external master. SIZ[1:0] signals reflect allocation during show cycles. Only appropriate portion data valid during cycle. During byte write internal address, portion that represents byte that written reflects internal conditions, indeterminate. During byte write external address, data multiplexer causes value byte that written driven both bytes data bus. Reset Reset occurs when active logic level RESET clocked into SIM. RESET input synchronized system clock. there clock when RESET asserted, reset does occur until clock starts. Resets clocked allow completion write cycles progress time RESET asserted. Reset procedures handle system initialization recovery from catastrophic failure. performs resets with combination hardware software. system integration module determines whether reset valid, asserts control signals, performs basic system configuration boot selection based hardware modeselect inputs, then passes control CPU32. 4.6.1 Reset Exception Processing CPU32 processes resets type asynchronous exception. exception event that preempts normal processing, caused internal external events. Exception processing makes transition from normal instruction execution execution routine that deals with exception. Each exception assigned vector that points associated handler routine. These vectors stored vector base register (VBR). contains base address 1024-byte exception vector table, which consists exception vectors. CPU32 uses vector numbers calculate displacement into table. Refer SECTION CENTRAL PROCESSING UNIT more information concerning exceptions. Reset highest-priority CPU32 exception. Unlike other exceptions, reset occurs cycle, instruction boundary. Handling resets this prevents write cycles progress time reset signal asserted from being corrupted. However, processing progress aborted reset exception, cannot restarted. Only essential reset tasks performed during exception processing. Other initialization tasks must accomplished exception handler routine. 4.6.8 Reset Processing Summary contains details exception processing.
MC68332 USER'S MANUAL SYSTEM INTEGRATION MODULE MOTOROLA 4-37
4.6.2 Reset Control Logic reset control logic determines cause reset, synchronizes reset assertion necessary completion current cycle, asserts appropriate reset lines. Reset control logic drive four different internal signals. EXTRST (external reset) drives external reset pin. CLKRST (clock reset) resets clock module. MSTRST (master reset) goes other internal circuits. SYSRST (system reset) indicates internal circuits that executed RESET instruction. resets gated CLKOUT. Resets classified synchronous asynchronous. asynchronous reset occur CLKOUT edge. Reset sources that cause asynchronous reset usually indicate catastrophic failure; thus reset control logic responds asserting reset system immediately. system reset, however, caused CPU32 RESET instruction, asynchronous does indicate type catastrophic failure). Synch
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