LC2MOS Complete 14-Bit AD7840 GENERAL DESCRIPTION PRODUCT HI

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LC2MOS Complete 14-Bit AD7840 GENERAL DESCRIPTION PRODUCT HI

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FEATURES Complete 14-Bit Voltage Output Parallel Serial Interface Capability Signal-to-Noise Ratio Interfaces High Speed Processors e.g., ADSP-2100, TMS32010, TMS32020 Pulse Width Power typ. Operates from Supplies
LC2MOS Complete 14-Bit AD7840
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
AD7840 fast, complete 14-bit voltage output converter. consists 14-bit DAC, buried Zener reference, output amplifier high speed control logic. part features double-buffered interface logic with 14-bit input latch 14-bit latch. Data loaded input latch either modes, parallel serial. This data then transferred latch under control asynchronous LDAC signal. fast data setup time allows direct parallel interfacing digital signal processors high speed 16-bit microprocessors. serial mode, maximum serial data clock rate high MHz. analog output from AD7840 provides bipolar output range AD7840 fully specified dynamic performance parameters such signal-to-noise ratio harmonic distortion well traditional specifications. Full power output signals created. AD7840 fabricated linear compatible CMOS (LC2MOS), advanced, mixed technology process that combines precision bipolar circuits with power CMOS logic. part available 24-pin plastic hermetic dual-in-line package (DIP) also packaged 28-terminal plastic leaded chip carrier (PLCC).
Complete 14-Bit Function AD7840 provides complete function creating signals voltages 14-bit accuracy. part features on-chip reference, output buffer amplifier 14-bit converter. Dynamic Specifications Users addition traditional specifications, AD7840 specified parameters including signal-to-noise ratio harmonic distortion. These parameters along with important timing parameters tested every device. Fast, Versatile Microprocessor Interface AD7840 capable 14-bit parallel serial interfacing. parallel mode, data setup times write pulse widths make AD7840 compatible with modern 16-bit microprocessors digital signal processors. serial mode, part features high data transfer rate MHz.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
DGND AD7840-SPECIFICATIONS ==100 All5%, TAGNDunless othewiseREF specifications noted.)
Parameter DYNAMIC PERFORMANCE2 Signal Noise Ratio3 (SNR)
Units
Test Conditions/Comments VOUT Sine Wave, fSAMPLE Typically +25°C VOUT kHz4 VOUT Sine Wave, fSAMPLE Typically +25°C VOUT kHz4 VOUT Sine Wave, fSAMPLE Typically +25°C VOUT kHz4
Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Bipolar Zero Error Positive Full Scale Error5 Negative Full Scale Error5 REFERENCE OUTPUT6 +25°C Reference Load Change (REF REFERENCE INPUT Reference Input Range Input Current LOGIC INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Current Input Only) Input Capacitance, CIN7 ANALOG OUTPUT Output Voltage Range Output Impedance Short-Circuit Current CHARACTERISTICS7 Voltage Output Settling Time Positive Full-Scale Change Negative Full-Scale Change Digital-to-Analog Glitch Impulse Digital Feedthrough POWER REQUIREMENTS Power Dissipation
2.99 3.01 2.85 3.15
2.99 3.01 2.85 3.15
2.99 3.01 2.85 3.15
Bits ppm/°C
Guaranteed Monotonic
Reference Load Current Change (0-500
=VSS
secs secs
Settling Time within Final Value Typically Typically
Specified Performance Specified Performance Output Unloaded, SCLK Typically Output Unloaded, SCLK Typically Typically
NOTES Temperature ranges follows: Versions, +70°C; Versions, -25°C +85°C; Version, -55°C +125°C. VOUT (pk-pk) calculation includes distortion noise components. Using external sample-and-hold (see Testing AD7840). Measured with respect includes bipolar offset error. capacitive loads greater than series resistor required (see Internal Reference section). Sample tested +25°C ensure compliance. Specifications subject change without notice.
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AD7840 TIMING CHARACTERISTICS1,
Parameter Limit TMIN, TMAX Versions)
(VDD
AGND DGND
Units Conditions/Comments Setup Time Hold Time Pulse Width Data Valid Setup Time Data Valid Hold Time LDAC Pulse Width SYNC SCLK Falling Edge SCLK Cycle Time Data Valid SCLK Setup Time Data Valid SCLK Hold Time SYNC SCLK Hold Time
Limit TMIN, TMAX Version)
NOTES Timing specifications bold print 100% production tested. other times sample tested ensure compliance. input signals specified with (10% timed from voltage level Figures SCLK mark/space ratio 40/60 60/40. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Temperature Range +70°C +70°C +70°C +70°C -25°C +85°C -25°C +85°C -25°C +85°C -55°C +125°C (dB) Integral Nonlinearity (LSB) Package Option2 N-24 N-24 P-28A P-28A Q-24 RS-24 Q-24 Q-24
AGND -0.3 AGND +0.3 AGND DGND -0.3 VOUT AGND AGND AGND -0.3 Digital Inputs DGND -0.3 Operating Temperature Range Commercial Versions) +70°C Industrial Versions) -25°C +85°C Extended Version) -55°C +125°C Storage Temperature Range -65°C +150°C Lead Temperature (Soldering, sec) +300°C Power Dissipation (Any Package) +75°C Derates above +75°C mW/°C
*Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Model1 AD7840JN AD7840KN AD7840JP AD7840KP AD7840AQ AD7840ARS AD7840BQ AD7840SQ3
NOTES order MIL-STD-883, Class processed parts, /883B part number. Contact your local sales office military data sheet availability. Plastic DIP; Plastic Leaded Chip Carrier; Cerdip. This grade will available /883B processing only.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7840 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
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AD7840
FUNCTION DESCRIPTION
Mnemonic CS/SERIAL
Function Chip Select/Serial Input. When driven with normal logic levels, active logic input which used conjunction with load parallel data input latch. applications where permanently low, required correct power-up (see LDAC input). this input tied VSS, defines AD7840 serial mode operation. Write/Frame Synchronization Input. parallel data mode, used conjunction with load parallel data. serial mode operation, this functions Frame Synchronization pulse with serial data expected after falling edge this signal. Data 13(MSB)/Serial Data. When parallel data selected, this input. serial mode, SDATA serial data input which used conjunction with SYNC SCLK transfer serial data AD7840 input latch. Data 12/Serial Clock. When parallel data selected, this input. serial mode, serial clock input. Serial data bits latched falling edge SCLK when SYNC low. Data 11/Data Format. When parallel data selected, this input. serial mode, Logic this input indicates that first valid serial data stream. Logic indicates that first valid (see Table Data 10/Data Justification. When parallel data selected, this input. serial mode, this input controls serial data justification (see Table Data Data Parallel data inputs. Digital Ground. Ground reference digital circuitry. Data Data Parallel data inputs. Data (LSB). Parallel data input. Positive Supply, Analog Ground. Ground reference DAC, reference output buffer amplifier. Analog Output Voltage. This buffer amplifier output voltage. Bipolar output range with Negative Supply Voltage, Voltage Reference Output. internal analog reference provided this pin. operate AD7840 with internal reference, should connected external load capability reference Voltage Reference Input. reference voltage applied this pin. internally buffered before being applied DAC. nominal reference voltage correct operation AD7840 Load DAC. Logic Input. word loaded into latch from input latch falling edge this signal (see Interface Logic Information section). AD7840 should powered-up with LDAC high. applications where LDAC permanently low, required correct power-up (see Figure 19).
Table Serial Data Modes
WR/SYNC
D13/SDATA
D12/SCLK D11/FORMAT
7-11 13-16
D10/JUSTIFY D9-D5 DGND D4-D1 AGND VOUT
LDAC
REV.
AD7840
CONFIGURATIONS DIP/SSOP PLCC
SECTION
AD7840 contains 14-bit voltage mode converter consisting highly stable thin film resistors high speed NMOS single-pole, double-throw switches. simplified circuit diagram section shown Figure three MSBs data word decoded drive seven switches A-G. LSBs switch 11-bit R-2R ladder structure. output voltage from this converter same polarity reference voltage, voltage internally buffered unity gain amplifier before being applied converter bipolar bias circuitry. converter configured sealed reference device tested with applied Operating AD7840 reference voltages outside tolerance range result degraded performance from part.
external use, should decoupled AGND with resistor series with parallel combination tantalum capacitor ceramic capacitor.
Figure Internal Reference
EXTERNAL REFERENCE
some applications, user require system reference some other external reference drive AD7840 reference input. Figure shows AD586 reference conditioned provide reference required AD7840 alternate source reference voltage AD7840 systems which both voltage ADCs such AD7870 AD7871. circuit showing this arrangement shown Figure
Figure Ladder Structure
INTERNAL REFERENCE
AD7840 on-chip temperature compensated buried Zener reference (see Figure which factory trimmed reference voltage provided pin. This reference used provide both reference voltage converter bipolar bias circuitry. This achieved connecting device. reference voltage also used reference other components capable providing external load. maximum recommended capacitance normal operation reference required REV.
Figure AD586 Driving AD7840
AD7840
SECTION Table Ideal Input/Output Code Table
output from voltage mode buffered noninverting amplifier. Internal scaling resistors AD7840 configure output voltage range input reference voltage arrangement these resistors around output shown Figure buffer amplifier capable developing across load ground produce peak-to-peak sine wave signals frequency kHz. output updated falling edge LDAC input. amplifier settles within final value typically less than small signal (200 p-p) bandwidth output buffer amplifier typically MHz. output noise from amplifier with figure nV/Hz frequency kHz. broadband noise from amplifier exhibits typical peakto-peak figure output bandwidth. Figure shows typical plot noise spectral density versus frequency output buffer amplifier on-chip reference.
Latch Contents 01111111111111 01111111111110 00000000000001 00000000000000 11111111111111 10000000000001 10000000000000
*Assuming
Analog Output, VOUT* +2.999634 +2.999268 +0.000366 -0.000366 -2.999634
output voltage expressed terms input code, using following expression:
REFIN 8192 +8191 16384
INTERFACE LOGIC INFORMATION
AD7840 contains 14-bit latches, input latch latch. Data loaded input latch basic interface formats. first parallel 14-bit wide data word; second serial interface where bits data serially clocked into input latch. parallel mode, control loading data. When serial data format selected, data loaded using SCLK, SYNC SDATA serial inputs. Data transferred from input latch latch under control LDAC signal. Only data latch determines analog output AD7840.
Parallel Data Format
Figure Noise Spectral Density Frequency
TRANSFER FUNCTION
basic circuit configuration AD7840 shown Figure Table shows ideal input code output voltage relationship this configuration. Input coding complement with FS/16,384 V/16,384
Table shows truth table AD7840 parallel mode operation. AD7840 normally operates with parallel input data format. this case, bits data (appearing data inputs (MSB) through (LSB)) loaded AD7840 input latch same time. control loading this data. These control signals level-triggered; therefore, input latch made transparent holding both signals logic level. Input data latched into input latch rising edge latch also level triggered. output normally updated falling edge LDAC signal. However, both latches cannot become transparent same time. Therefore, LDAC hardwired low, part operates follows; with LDAC high, latch transparent. When (with LDAC still low), input latch becomes transparent latch disabled. When return high, input latch locked latch becomes transparent again output updated. write cycle timing diagram parallel data shown Figure Figure shows simplified parallel input control logic AD7840.
Figure AD7840 Basic Connection Diagram
REV.
AD7840
Table III. Parallel Mode Truth Table Serial Data Format
LDAC
Function
}Both Latches Latched
Input Latch Transparent Input Latch Latched Latch Transparent Analog Output Updated Input Latch Transparent Latch Data Transfer Inhibited Input Latch Latched Latch Data Transfer Occurs
serial data format selected AD7840 connecting CS/SERIAL line this case, WR/SYNC, D13/SDATA, D12/SCLK, D11/FORMAT D10/JUSTIFY pins assume their serial functions. unused parallel inputs should left unconnected avoid noise pickup. Serial data loaded input latch under control SCLK, SYNC SDATA. AD7840 expects 16-bit stream serial data SDATA input. Serial data must valid falling edge SCLK. SYNC input provides frame synchronization signal which tells AD7840 that valid serial data will available next falling edges SCLK. Figure shows timing diagram serial data format.
Don't Care
Figure Parallel Mode Timing Diagram Figure Serial Mode Timing Diagram
Figure AD7840 Simplified Parallel Input Control Logic
Although bits data clocked into AD7840, only bits into input latch. Therefore, bits stream don't cares since their value does affect input latch data. order position which AD7840 accepts bits input data depends upon FORMAT JUSTIFY inputs. There four different input data modes which chosen (see Table Function Description section). first mode (M1) assumes that first bits input data stream don't cares, third last 16th bit) MSB. This mode chosen tying both FORMAT JUSTIFY pins logic second mode (M2; FORMAT JUSTIFY assumes that first data stream LSB, fourteenth last bits don't cares. third mode (M3; FORMAT= JUSTIFY assumes that first bits stream again don't cares, third sixteenth LSB. final mode (M4; FORMAT JUSTIFY= assumes that first MSB, fourteenth last bits stream don't cares.
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AD7840
parallel mode, LDAC signal controls loading data latch. Normally, data loaded latch falling edge LDAC. However, LDAC held low, then serial data loaded latch sixteenth falling edge SCLK. LDAC goes during transfer serial data input latch, latch update takes place falling edge LDAC. LDAC stays until serial transfer completed, then update takes place sixteenth falling edge SCLK. LDAC returns high before serial data transfer completed, latch update takes place. Figure shows simplified serial input control logic AD7840. this graph 81.8 should noted that harmonics taken into account when calculating SNR.
Figure AD7840 Plot
Effective Number Bits
formula given relates number bits. Rewriting formula, possible measure performance expressed effective number bits (N).
Figure AD7840 Simplified Serial Input Control Logic
AD7840 DYNAMIC SPECIFICATIONS
1.76 6.02
effective number bits device calculated directly from measured SNR.
Harmonic Distortion
AD7840 specified 100% tested dynamic performance specifications well traditional specifications such integral differential nonlinearity. These specifications required signal processing applications such speech synthesis, servo control high speed modems. These applications require information DAC's effect spectral content signal creating. Hence, parameters which AD7840 specified include signal-to-noise ratio, harmonic distortion peak harmonics. These terms discussed more detail following sections.
Signal-to-Noise Ratio (SNR)
Harmonic distortion ratio harmonics fundamental. AD7840, total harmonic distortion (THD) defined
measured signal-to-noise ratio output DAC. signal magnitude fundamental. Noise nonfundamental signals half sampling frequency (fs/2) excluding dependent upon number quantization levels used digitization process; more levels, smaller quantization noise. theoretical signal noise ratio sine wave output given
(6.02N 1.76)
where amplitude fundamental amplitudes second through sixth harmonic. also derived from 2048-point plot.
Peak Harmonic Spurious Noise
Peak harmonic spurious noise defined ratio value next largest component output spectrum fs/2 excluding value fundamental. Normally, value this specification will determined largest harmonic spectrum, parts where harmonics buried noise floor peak will noise peak.
Testing AD7840
where number bits. Thus ideal 14-bit converter, Figure shows typical 2048 point Fast Fourier Transform (FFT) plot AD7840KN with output frequency update rate kHz. obtained from
simplified diagram method used test dynamic performance specifications outlined Figure Data loaded AD7840 under control microcontroller associated logic update rate. output AD7840 applied ninth order, kHz, low-pass filter. output filter turn applied 16-bit accurate digitizer. This digitizes signal microcontroller generates plot from which dynamic performance AD7840 evaluated.
REV.
AD7840
Performance versus Frequency
Figure AD7840 Dynamic Performance Test Circuit
typical performance plots Figures show AD7840's performance over wide range input frequencies update rate kHz. plot Figure without sample-and-hold AD7840 output while plot Figure generated with sample-and-hold circuit Figure output.
digitizer sampling synchronized with AD7840 update rate ease calculations. digitizer samples AD7840 after output settled value. Therefore, digitizer sample output directly would effectively sampling value each time. result, dynamic performance AD7840 would measured correctly. Using digitizer directly AD7840 output would give better results than actual performance AD7840. Using filter between digitizer means that digitizer samples continuously moving signal true dynamic performance AD7840 measured. Some applications will require improved performance versus frequency from AD7840. these applications, simple sample-and-hold circuit such that outlined Figure will extend very good performance AD7840 kHz.
Figure Performance Frequency Sample-and-Hold)
Figure Sample-and-Hold Circuit
Other applications will already have inherent sample-andhold function following AD7840. example this type application driving switched-capacitor filter where updating synchronized with switched-capacitor filter. This inherent sample-and-hold function also extends frequency range performance AD7840.
Figure Performance Frequency (with Sample-and-Hold)
REV.
AD7840
MICROPROCESSOR INTERFACING
AD7840 logic architecture allows interfacing options interfacing part microprocessor systems. offers 14-bit wide parallel format serial format. Fast pulse widths data setup times allow AD7840 interface directly most microprocessors including processors. Suitable interfaces various microprocessors shown Figures
Parallel Interfacing
Figures show interfaces processors, ADSP-2100, TMS32010 TMS32020. external timer controls updating AD7840. Data loaded AD7840 input latch using following instructions: ADSP-2100: DM(DAC) TMS32010: DAC,D TMS32020: DAC,D ADSP-2100 Register Data Memory Address AD7840 Address
Figure AD7840-TMS32020 Parallel Interface
Some applications require that updating AD7840 latch controlled microprocessor rather than external timer. option (for double-buffered interfacing) decode AD7840 LDAC from address that write operation latch separate address than input latch) updates output. example this shown 8086 interface Figure Note that connecting LDAC input input will load latch correctly since both latches cannot transparent same time. AD7840-8086 Interface Figure shows interface between AD7840 8086 microprocessor. this interface, LDAC input derived from decoded address. least significant address line, decoded then input latch latch reside consecutive addresses. move instruction loads input latch while second move instruction updates latch AD7840 output. move instruction load data word WXYZ input latch follows:
Figure AD7840-ADSP-2100 Parallel Interface
DAC,#YZWX AD7840 Address
Figure AD7840-TMS32010 Parallel Interface
Figure AD7840-8086 Parallel Interface
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REV.
AD7840
AD7840-68000 Interface interface between AD7840 68000 microprocessor shown Figure this interface example, LDAC input hardwired low. result latch analog output updated rising edge single move instruction, therefore, loads input latch updates output. MOVE.W D0,$DAC 68000 Register AD7840 Address update latch analog output takes place sixteenth falling edge SCLK (with SYNC low). FORMAT AD7840 must tied JUSTIFY tied DGND this interface operate correctly.
Figure AD7840-MC68000 Parallel Interface
Serial Interfacing
Figure Complete DAC/ADC Serial Interface
Figures show AD7840 configured serial interfacing with input hardwired parallel activated during serial communication with AD7840. AD7840-ADSP-2101/ADSP-2102 Serial Interface Figure shows serial interface between AD7840 ADSP-2101/ADSP-2102 processor. Also included interface AD7870, 12-bit converter. interface such this suitable modem other applications which have serial communication with microprocessor. interface uses just serial ports ADSP-2101/ADSP-2102. Conversion initiated AD7870 fixed sample rate (e.g., kHz) which provided timer clock recovery circuitry. While communication takes place between ADSP-2101/ ADSP-2102, AD7870 SSTRB line low. This SSTRB line used provide frame synchronization pulse AD7840 SYNC ADSP-2101/ADSP-2102 lines. This means that communication between processor AD7840 only take place while AD7870 communicating with processor. This arrangement desirable systems such modems where communication should synchronous. AD7870 SCLK AD7840 SCLK ADSP-2101/ADSP-2102 SCLK means that only serial port processor used. serial clock AD7870 must continuous clock correct operation this interface. Data from ADSP-2101/ADSP-2102 valid falling edge SCLK. LDAC input AD7840 permanently
AD7840-DSP56000 Serial Interface serial interface between AD7840 DSP56000 shown Figure DSP56000 configured normal mode synchronous operation with gated clock. also 16-bit word with outputs control internally generated DSP56000 applied AD7840 SCLK input. Data from DSP56000 valid falling edge SCK. output provides framing pulse valid data. This line must inverted before being applied SYNC input AD7840. LDAC input AD7840 connected DGND update latch takes place sixteenth falling edge SCLK. with previous interface, FORMAT AD7840 must tied JUSTIFY tied DGND.
Figure AD7840-DSP56000 Serial Interface
REV.
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AD7840
AD7840-TMS32020 Serial Interface Figure shows serial interface between AD7840 TMS32020 processor. this interface, CLKX TMS32020 generated from clock/timer circuitry. same clock/timer circuitry generates LDAC signal AD7840 synchronize update output with serial transmission. TMS32020 must configured input. Data from TMS32020 valid falling edge CLKX. Once again, FORMAT AD7840 must tied while JUSTIFY must tied DGND.
APPLYING AD7840
Good printed circuit board layout important overall circuit design itself achieving high speed converter performance. AD7840 works size Therefore, designer must conscious minimizing noise both converter itself surrounding circuitry. Switching mode power supplies recommended switching spikes feed through on-chip amplifier. Other causes concern ground loops digital feedthrough from microprocessors. These factors which influence high performance converter, proper layout which minimizes these effects essential best performance.
LAYOUT HINTS
Ensure that layout printed circuit board digital analog lines separated much possible. Take care digital track alongside analog signal track. Establish single point analog ground (star ground) separate from logic system ground. Place this star ground close possible AD7840 shown Figure Connect analog grounds this star ground also connect AD7840 DGND this ground. connect other digital grounds this analog ground point.
Figure AD7840-TMS32020 Serial Interface
AD7840-NEC7720 Serial Interface
serial interface between AD7840 NEC7720 shown Figure serial clock must inverted before being applied AD7840 SCLK input because data from processor valid rising edge SCK. NEC7720 programmed first serial data stream. Therefore, AD7840 with FORMAT tied DGND JUSTIFY tied
Figure Power Supply Grounding Practice
impedance analog digital power supply common returns essential noise operation high performance converters. Therefore, foil width these tracks should kept wide possible. ground planes minimizes impedance paths also guards analog circuitry from digital noise. circuit layouts Figures have both analog digital ground planes which kept separated only joined star ground close AD7840.
NOISE
Keep signal leads VOUT signal signal return leads AGND short possible minimize noise coupling. applications where this possible, shielded cable between output destination. Reduce ground circuit impedance much possible since potential difference grounds between destination device appears error voltage series with output.
Figure AD7840-NEC7720 Serial Interface
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REV.
AD7840
DATA ACQUISITION BOARD POWER SUPPLY CONNECTIONS
Figure shows AD7840 data acquisition circuit. corresponding printed circuit board (PCB) layout silkscreen shown Figures board layout three interface ports: serial parallel. parallel ports directly compatible with ADSP-2100 evaluation board expansion connector. Some systems will require addition re-construction filter output AD7840 complete data acquisition system. There component grid provided near analog output which used such filter other output conditioning circuitry. facilitate this option, there shorting plug (labeled PCB) analog output track. this shorting plug used, analog output connects output AD7840; otherwise this shorting plug omitted wire link used connect analog output component grid. board also contains simple sample-and-hold circuit which used output AD7840 extend very good performance AD7840 over wider frequency range. second wire link (labelled PCB) connects VOUT (SKT1) either output this sample-and-hold circuit directly output AD7840.
INTERFACE CONNECTIONS
requires analog power supplies digital supply. Connections analog supplies made directly shown silkscreen Figure connections labelled range both these supplies Connection digital supply made through connectors (SKT4 SKT6). analog supply required AD7840 generated from voltage regulator power supply input (IC5 Figure 25).
SHORTING PLUG OPTIONS
There eight shorting plug options which must before using board. These outlined below: Connects analog output SKT1. analog output also connected component grid signal conditioning. Selects either AD7840 VOUT sample-andhold output. Selects either internal external reference. Selects decoded STRB inputs TMS32020 interfacing. Configures D11/FORMAT input. Configures D10/JUSTIFY input. Selects either inverted noninverted SYNC. Selects either parallel serial interfacing.
There parallel connectors, labeled SKT4 SKT6, serial connector, labeled SKT5. shorting plug option (LK8 Figure AD7840 CS/SERIAL input configures appropriate interface (see Function Description). SKT6 96-contact (3-row) Eurocard connector which directly compatible with ADSP-2100 Evaluation Board Prototype Expansion Connector. expansion connector ADSP-2100 eight decoded chip enable outputs labeled ECE1 ECE8. ECE6 used drive AD7840 input data acquisition board. avoid selecting on-board sockets same time, ADSP-2100 board must removed. AD7840 ADSP-2100 data lines aligned left justified data transfer. SKT4 26-way (2-row) connector. This connector contains same signal contacts SKT6 addition contains decoded STRB inputs which necessary TMS32020 interfacing. This decoded selected LK4. pinout this connector shown Figure SKT5 nine-way D-type connector which meant serial interfacing only. evaluation board facility invert SYNC line LK7. This necessary serial interfacing between AD7840 processors such DSP56000. SKT5 pinout shown Figure SKT1, SKT2 SKT3 three connectors which provide connections analog output, LDAC input external reference input. external reference optional; shorting plug (LK3) connects either this external reference AD7840's internal reference. Wire links connect inputs data lines parallel operation. serial mode, these links allow user select required format justification serial data (see Table REV.
COMPONENT LIST
C11, C13, C15, C12, C14, C16, RP1, LK1, LK2, LK3, LK4, LK5, LK6, LK7, SKT1, SKT2, SKT3 SKT4 SKT5 SKT6
AD7840 Digital-to-Analog Converter AD711 ADG201HS High Speed Switch 74HC221 Monostable 79L05 Voltage Regulator 74HC02 Capacitors Capacitors Capacitor Capacitor Resistors Resistor Resistor Packs
Shorting Plugs Sockets 26-Contact (2-Row) Connector 9-Contact D-Type Connector 96-Contact (3-Row) Eurocard Connector
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AD7840
Figure Data Acquisition Circuit Using AD7840
Figure Silkscreen Figure
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REV.
AD7840
Figure Component Side Layout Figure
Figure Solder Side Layout Figure
REV.
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AD7840
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
Plastic (N-24)
Ceramic (D-24A)
Figure SKT4, Connector Pinout
Figure SKT5, D-Type Connector Pinout
Cerdip (Q-24)
PLCC (P-28A)
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REV.
PRINTED U.S.A.
C1259-10-2/89

LC2MOS Complete 14-Bit AD7840 GENERAL DESCRIPTION PRODUCT HI

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