Quad, 12-Bit Voltage Output with Readback DAC8412/DAC8413 VLOGIC

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Quad, 12-Bit Voltage Output with Readback DAC8412/DAC8413 VLOGIC

Datasheet Thumbnail

Top Searches for this datasheet

FEATURES Operation Unipolar Bipolar Operation True Voltage Output Double-Buffered Inputs Reset (DAC8413) Center Scale (DAC8412) Fast Access Time Readback APPLICATIONS Automatic Test Equipment Digitally Controlled Calibration Servo Controls Process Control Equipment GENERAL DESCRIPTION
Quad, 12-Bit Voltage Output with Readback DAC8412/DAC8413
VLOGIC DATA PORT INPUT INPUT CONTROL LOGIC INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT VREFH VOUTA
DGND
VOUTB
VOUTC
VOUTD
RESET LDAC VREFL
DAC8412 DAC8413 quad, 12-bit voltage output DACs with readback capability. Built using complementary BiCMOS process, these monolithic DACs offer user very high package density. Output voltage swing reference inputs VREFH VREFL. setting VREFL input VREFH positive voltage, will provide unipolar positive output range. similar configuration with VREFH VREFL negative voltage will provide unipolar negative output range. Bipolar outputs configured connecting both VREFH VREFL nonzero voltages. This method setting output voltage range advantages over other bipolar offsetting methods because dependent internal external resistors with different temperature coefficients.
Digital controls allow user load read back data from DAC, load transfer data DACs time. active RESET loads output registers midscale DAC8412 zero scale DAC8413. DAC8412/DAC8413 available 28-lead plastic DIP, PLCC packages. They operated from wide variety supply reference voltages with supplies ranging from single references from +2.5 Power dissipation less than with supplies only with supply. MIL-STD-883 applications, contact your local sales office DAC8412/DAC8413/883 data sheet which specifies operation over -55°C +125°C temperature range. parts also available Standard Military Drawings 5962-91 76401MXA through 76404M3A.
0.500 0.375
LINEARITY ERROR
+125
0.250 0.125
-0.125 -0.250 -0.375 -0.500 +15V -15V VREFH +10V VREFL -10V +125 1024 1536 2046 2548 2560 DIGITAL INPUT CODE Decimal 3072 4096
Figure Code Over Temperature
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2000
ELECTRICAL CHARACTERISTICS unless otherwise noted. Note supply variations.)
DAC8412/DAC8413-SPECIFICATIONS +15.0 -15.0
LOGIC
+5.0 VREFH +10.0 VREFL -10.0
0.25 VREFH +2.75 +2.75 Units ppm/°C ppm/°C V/µs nV-s ppm/V
Parameter Integral Nonlinearity Error Differential Nonlinearity Error Min-Scale Error Full-Scale Error Min-Scale Tempco Full-Scale Tempco Linearity Matching REFERENCE Positive Reference Input Voltage Range Negative Reference Input Voltage Range Reference High Input Current Reference Input Current Large Signal Bandwidth AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate Analog Crosstalk LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Voltage Logic Output High Voltage Logic Output Voltage Logic Input Current Input Capacitance Digital Feedthrough3 LOGIC TIMING CHARACTERISTICS Chip Select Write Pulsewidth Write Setup Write Hold Address Setup Address Hold Load Setup Load Hold Write Data Setup Write Data Hold Load Data Pulsewidth Reset Pulsewidth Chip Select Read Pulsewidth Read Data Hold Read Data Setup Data Chip Select Data SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation
Symbol VZSE VFSE TCVZSE TCVFSE
Conditions Grade Grade Monotonic Over Temperature Adjacent Matching Note Note
IREFH IREFL IOUT
VREFL -2.75 +1.5 VREFH 0.01%, Step,
VINH VINL
+25°C +25°C +0.4 -1.6
VREFH +2.5 VREFL Note tWCS tWDS tWDH tLDW tRESET tRCS tRDH tRDS tCSD PDISS tWCS tWCS
tWCS tWCS
tRCS tRCS 14.25 15.75 VREFH +2.5
-6.5
NOTES supplies varied operation guaranteed. Device tested with nominal supplies. Operation guaranteed over this reference range, linearity neither tested guaranteed. parameters guaranteed design. input control signals specified with (10% timed from voltage level Specifications subject change without notice.
REV.
DAC8412/DAC8413 ELECTRICAL CHARACTERISTICS
Parameter Integral Nonlinearity Error
VLOGIC +5.0 VREFH +2.5 VREFL -5.0 VREFL -2.5 unless otherwise noted. Note supply variations.)
Conditions Grade Grade Grade2 Grade2 Monotonic Over Temperature -5.0 -5.0 VREFL -2.5 -1.0 -1.25 0.45 Note -5.0 +1.25 VREFH VREFH +1.0 Units ppm/°C ppm/°C V/µs ppm/V
Symbol VZSE VFSE VZSE VFSE TCVZSE TCVFSE
Differential Nonlinearity Error Min-Scale Error Full-Scale Error Min-Scale Error Full-Scale Error Min-Scale Tempco Full-Scale Tempco Linearity Matching REFERENCE Positive Reference Input Voltage Range Negative Reference Input Voltage Range Reference High Input Current Large Signal Bandwidth AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Voltage Logic Output High Voltage Logic Output Voltage Logic Input Current Input Capacitance LOGIC TIMING CHARACTERISTICS Chip Select Write Pulsewidth Write Setup Write Hold Address Setup Address Hold Load Setup Load Hold Write Data Setup Write Data Hold Load Data Pulsewidth Reset Pulsewidth Chip Select Read Pulsewidth Read Data Hold Read Data Setup Data Chip Select Data SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation
Adjacent Matching Note -5.0 Code 000H VREFH 0.01%, Step, +25°C +25°C +0.4 -1.6
IREFH IOUT VINH VINL tWCS tWDS tWDH tLDW tRESET tRCS tRDH tRDS tCSD PDISS
tWCS tWCS
tWCS tWCS
tRCS tRCS
NOTES supplies varied operation guaranteed. Device tested with +4.75 single supply operation only REFL internal offset errors, measured beginning code (002 Operation guaranteed over this reference range, linearity neither tested guaranteed. parameters guaranteed design. input control signals specified with (10% timed from voltage level Specifications subject change without notice.
REV.
DAC8412/DAC8413
80ns
A0/A1
DATA HI-Z DATA VALID
ADDRESS
ADDRESS
ADDRESS
ADDRESS THREE
ADDRESS FOUR
Figure Data Output (Read Timing)
LDAC tWDS DATA DATA1 VALID DATA2 VALID DATA3 VALID DATA4 VALID tLDW tWDH
Figure Double Buffer Mode
VREFH VREFL
A0/A1
LDAC
VREFH VOUTB VOUTA DGND RESET LDAC
VREFL VOUTC VOUTD VLOGIC DB11 DB10 ONCE PORT
DATA
RESET
RESET
Figure Data WRITE (Input Output Registers) Timing
80ns ADDRESS ADDRESS LDAC tWDS DATA DATA1 VALID DATA2 VALID DATA3 VALID DATA4 VALID tWDH ADDRESS ADDRESS THREE ADDRESS FOUR
DGND
+15V, -15V, VREFH +10V, VREFL 100k LCC, (ONCE PORT), 0.01 (EACH DEVICE) 1N4001 EQUIVALENT (ONCE PORT)
Figure Burn-In Diagram
Figure Single Buffer Mode
REV.
DAC8412/DAC8413
ABSOLUTE MAXIMUM RATINGS Thermal Resistance
+25°C unless otherwise noted) -0.3 +33.0 VLOGIC -0.3 +33.0 VLOGIC DGND -0.3 +7.0 VREFL -0.3 +VSS-2.0 VREFH +2.0 +33.0 VREFH VREFL +2.0 VSS-VDD Current into Digital Input Voltage DGND -0.3 VLOGIC +0.3 Digital Output Voltage DGND -0.3 +7.0 Operating Temperature Range -40°C +85°C -55°C +125°C Dice Junction Temperature +150°C Storage Temperature -65°C +150°C Power Dissipation Package 1000 Lead Temperature (Soldering, sec) +300°C
Package Type
Units
28-Lead Plastic 28-Lead Hermetic Leadless Chip Carrier (TC) 28-Lead Plastic Leaded Chip Carrier (PC)
°C/W °C/W °C/W
specified worst-case mounting conditions, specified device socket.
ORDERING INFORMATION
(LSB)
Military3 Temperature +125 DAC8412BTC/883
Extended Industrial3 Temperature DAC8412FPC DAC8412EP DAC8412FP DAC8413FPC
Package Description PLCC Plastic Plastic PLCC Plastic Plastic
Package Option P-28A E-28A N-28 N-28 P-28A E-28A N-28 N-28
DAC8413BTC/883 DAC8413EP DAC8413FP
NOTES Size 0.225 0.165 inches, 37,125 mils (5.715 4.191 23.95 mm). Substrate should connected Transistor Count 2595. Burn-in available extended industrial temperature range parts cerdip. complete /883 data sheet available. availability burn-in information, contact your local sales office.
CAUTION
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation above this specification implied. Exposure above maximum rating conditions extended periods affect device reliability. Digital inputs outputs protected, however, permanent damage occur unprotected units from high-energy electrostatic fields. Keep units conductive foam packaging times until ready use. proper antistatic handling procedures. Remove power before inserting removing units from their sockets. Analog outputs protected from short circuit ground either supply.
WARNING!
SENSITIVE DEVICE
REV.
DAC8412/DAC8413
FUNCTION DESCRIPTIONS CONFIGURATIONS Plastic
VREFH VOUTB VOUTA DGND RESET LDAC (LSB) VREFL VOUTC VOUTD
Name VREFH VOUTB VOUTA DGND RESET LDAC DB10 DB11
Description High-Side Reference Input Output Output Lower-Rail Power Supply Digital Ground Reset Input Output Registers Enabled Active Load Data DAC, Enabled Active Data Data Data Data Data Data Data Data Data Data Data Data Active Write Data DAC. Active High Readback Previous Data Data Pins with VLOGIC Connected Address Address Chip Select, Enabled Active Voltage Supply Readback Function. Open Circuit Used Upper-Rail Power Supply Output Output Low-Side Reference Input
DAC8412 DAC8413
VIEW (NOT SCALE)
VLOGIC DB11 (MSB) DB10
PLCC
VOUTA VOUTB VOUTC VOUTD VREFH VREFL
DGND RESET LDAC (LSB)
VLOGIC
VLOGIC VOUTD VOUTC VREFL
DAC8412PC DAC8413PC
VIEW (NOT SCALE)
DB11 (MSB)
DB10
VOUTD
VREFL
VOUTA VOUTB VOUTC VREFH
DGND RESET LDAC (LSB)
VLOGIC
DAC8412TC DAC8413TC
VIEW (NOT SCALE)
DB10
DB11 (MSB)
REV.
Typical Performance Characteristics- DAC8412/DAC8413
MAXIMUM LINEARITY ERROR
MAXIMUM LINEARITY ERROR
MAXIMUM LINEARITY ERROR
VREFL
+15V -15V VREFL
+15V -15V VREFL -10.0V VREFH Volts
VREFH Volts
VREFH Volts
Figure VREFH
Figure VREFH
Figure VREFH
+15V -15V VREFH +10V VREFL -10V
MAXIMUM LINEARITY ERROR
ZERO-SCALE ERROR
FULL-SCALE ERROR
-0.1 -0.3 +15V -15V VREFH +10V VREFL -10V 1000 HOURS OPERATION +125
-0.2 -0.4 -0.6
VREFL VREFH Volts
-0.5
-0.7 1000 HOURS OPERATION +125
Figure VREFH
Figure Full-Scale Error Time Accelerated Burn-In
Figure Zero-Scale Error Time Accelerated Burn-In
+15V -15V VREFH +10V VREFL -10V
FULL-SCALE ERROR
ZERO-SCALE ERROR
+15V -15V VREFH +10V VREFL -10V
-0.2
-0.1
-0.4
-0.3
-0.6
TEMPERATURE
-0.5
TEMPERATURE
Figure Full-Scale Error Temperature
Figure Zero-Scale Error Temperature
REV.
DAC8412/DAC8413
0.37500 0.26125
LINEARITY ERROR
LINEARITY ERROR
0.500 0.375 0.250 0.125 -0.125 -0.250 -0.375 -0.500 +15V -15V VREFH +10V VREFL -10V +125 1024 1536 2048 2560 3072 DIGITAL INPUT CODE Decimal 3584 4096
0.18750 0.08375 -0.09375 -0.18750 -0.23125 -0.37500 VREFH +10V VREFL 1024 1536 2048 2560 3072 DIGITAL INPUT CODE Decimal 3584 4096
Figure Channel-to-Channel Matching (VSUPPLY
1.00 0.75 +5.0V VREFH +2.5V
Figure Code
LINEARITY ERROR
0.50 0.25 -0.25 -0.50
+15V -15V VREFH +10V VREFL -10V
IVREFH
-0.75 -1.00 -0.5 1024 1536 2048 2560 3072 DIGITAL INPUT CODE Decimal 3584 4096 1023 1535 2047 2559 3071 DIGITAL INPUT CODE Decimal 3583 4095
Figure Channel-to-Channel Matching (VSUPPLY V/GND)
Figure IVREFH Code
+15V -15V VREFL -10V
VREFH Volts
Figure VREFH DACs High
REV.
DAC8412/DAC8413
32.5mV INPUT 15.5mV INPUT +15V -15V VREFH +10V VREFL -10V TRIG'D +15V -15V VREFH +10V VREFL -10V
5mV/DIV TRIG'D
ERROR BAND
2mV/DIV
+15V -15V VREFH +10V VREFL -10V s/DIV 18.04
TRIG'D
-17.5mV -1.96
-4.5mV -1.96
s/DIV
18.04
-580ns
s/DIV
9.42
Figure Settling Time (Positive)
Figure Settling Time (Negative)
Figure Positive Slew Rate
+15V -15V VREFH +10V VREFL -10V
+15V -15V VREFH +10V VREFL -10V
FULL SCALE VOLTAGE
TRIG'D
+15V -15V VREFH +10V VREFL -10V
-0.2 0.01
0.01
-580ns
s/DIV
9.42
0.10 1.00 10.0 LOAD RESISTANCE
0.10 1.00 10.0 LOAD RESISTANCE
Figure Negative Slew Rate
Figure 8412 Load Resistance
Figure 8412 Output Swing Load Resistance
POWER SUPPLY REJECTION +PSRR -PSRR +PSRR: +15V -15V -PSRR: +15V -15V VREFH DATA 100k FREQUENCY
POWER SUPPLY CURRENT
+15V -15V
GAIN
+15V -15V VREFH 100mV VREFL -10V DATA BITS 200mV
100k FREQUENCY
TEMPERATURE
Figure Small Signal Response
Figure Power Supply Current Temperature
Figure PSRR Frequency
REV.
DAC8412/DAC8413
10.0 +15V -15V VREFH +10V VREFL -10V
IOUT
-ISC +15V -15V VREFH +10V VREFL -10V DATA 000H +ISC
NOISE DENSITY
1.00
MEAN 66.19 +15V -15V VREFH +10V VREFL -10V
0.10
0.01
20uV/DIV
12.9mV
0.001 1000 NOISE FREQUENCY 10000
VOUT Volts
Figure DAC8412 Noise Frequency Noise Density
IOUT
Figure IOUT VOUT
Figure Broadband Noise
+15V VREFH +10V VREFL DATA 800H
+ISC
GLITCH OUTPUT
-ISC
DEGLITCHER OUTPUT 1.86V
VOUT Volts
Figure IOUT VOUT
Figure Glitch Deglitched Results
OPERATION Introduction
DAC8412 DAC8413 quad, voltage output, 12-bit parallel input DACs featuring 12-bit data with readback capability. only differences between DAC8412 DAC8413 reset functions. DAC8412 resets midscale (code 800H) DAC8413 resets minimum scale (code 000H). ability operate from single supply unique feature these DACs. Operation DAC8412 DAC8413 viewed dividing system into three separate functional groups: digital logic, digital analog converters output amplifiers.
DACs
precision instrumentation control, deglitcher circuit implemented with standard sample-and-hold circuit. (See Figure 34.) When enabled synchronizing hold period longer than glitch tradition, output voltage smoothed with minimum disturbance. quad sampleand-hold amplifier, SMP04, been used illustrate deglitching result. (See Figure 33.)
DACOUT DACOUT'
DACOUT
Each voltage switched, high impedance R-2R ladder configuration. Each resistor driven pair switches that connect resistor either VREFH VREFL.
Glitch
Worst-case glitch occurs transition between half-scale digital code 1000 0000 0000 half-scale minus LSB, 0111 1111 1111. measured about (See Figure 33.) demanding applications such waveform generation
DACOUT'
Figure Deglitcher Circuit
-10-
REV.
DAC8412/DAC8413
Reference Inputs
four DACs share common reference high (VREFH) reference (VREFL) inputs. voltages applied these reference inputs output high voltage limits four DACs. Each reference input voltage restrictions with respect other reference power supplies. VREFL voltage between VREFH VREFH value between +VDD VREFL Note that because these restrictions DAC8412 references cannot inverted (i.e., VREFL cannot greater than VREFH). important note that DAC8412's VREFH input both sinks sources current. Also input current both VREFH VREFL code dependent. Many references have limited current sinking capability must buffered with amplifier drive VREFH. VREFL such special requirements. recommended that reference inputs bypassed with capacitors when operating with references. This limits reference bandwidth.
Digital
input, when enabled controls writing reading from input register.
Coding
Both DAC8412 DAC8413 binary coding. output voltage calculated
VOUT VREFL (VREF VREFL 4096
where digital code decimal.
RESET
RESET function used either power-up time during DAC's operation. RESET function independent This active sets output registers either center code DAC8412, zero code DAC8413. reset center code most useful when configured bipolar references output zero volts after reset desired.
Supplies
Table digital control logic truth table. Digital consists 12-bit bidirectional data bus, registers select inputs, input, RESET input, Chip Select (CS), Load (LDAC) input. Control DACs direction determined these inputs shown Table Digital data bits labeled with defined data "11" data "0." digital pins TTL/ CMOS compatible. Figure simplified logic diagram. register select inputs select individual registers (binary code through (binary code 11). Decoding registers enabled input. When high decoding takes place, neither writing reading input registers enabled. loading second bank registers controlled asynchronous LDAC input. taking LDAC while enabled, output registers updated simultaneously. Note that tLDW required pulsewidth updating DACs minimum
Supplies required VSS, VLOGIC. supply between positive supply; operating range between VLOGIC digital output supply voltage readback function. normally connected This logic reference input only. does supply current device. using readback function, VLOGIC left opencircuit. While VLOGIC does supply current DAC8412, does supply currents digital outputs when readback used.
Amplifiers
Unlike many voltage output DACs, DAC8412 features buffered voltage outputs. Each output capable both sourcing sinking volts, eliminating need external amplifiers when driving smaller capacitive load most applications. These amplifiers short-circuit protected.
Table DAC8412/DAC8413 Logic Table
LDAC
INPUT
OUTPUT
MODE
WRITE WRITE Transparent WRITE WRITE Transparent WRITE WRITE Transparent WRITE WRITE Transparent WRITE HOLD WRITE INPUT WRITE HOLD WRITE INPUT WRITE HOLD WRITE INPUT WRITE HOLD WRITE INPUT READ HOLD READ INPUT READ HOLD READ INPUT READ HOLD READ INPUT READ HOLD READ INPUT HOLD Update output registers HOLD HOLD HOLD *All registers reset mid/zero-scale *All registers latched mid/zero-scale
*DAC8412 resets midscale, DAC8413 resets zero scale. Logic Low; Logic High; Don't Care. Input Output registers transparent when asserted.
REV.
-11-
DAC8412/DAC8413
VREFH RDDACA WRDB0 WRDB1 WRDACA WRDB2 WRDB3 WRDB4 WRDACB INPUT REGISTER WRDB6 RDDACC WRDB7 WRDACC WRDB8 WRDB9 RDDACD WRDB10 WRDB11 WRDACD DB11.DB0 VLOGIC VOUTD OUTPUT WRDB5 REGISTER VOUTB VOUTA
RDDACB
VOUTC
VREFL LDAC RESET READOUTBAR READBACKDATAIN_DB11 READBACK DATAOUT_DB11 READOUT READBACKDATAIN_DB10
DGND
Figure Simplified Logic Diagram
Careful attention grounding important accurate operation DAC8412. This because DAC8412 more sensitive than other 12-bit DACs, because with four outputs references there greater potential ground loops. Since DAC8412 analog ground, ground must specified with respect reference.
Reference Configurations
+15V +15V
BALANCE 100k
VREFH
Output voltage ranges configured either unipolar bipolar, within these choices wide variety options exists. unipolar configuration either positive negative voltage output, bipolar configuration either symmetrical nonsymmetrical.
+15V +15V INPUT OUTPUT OP-400 OP400 VREFH
GAIN 100k
AD688 AD588
DAC8412 DAC8413
VREFL
//10
-15V OPERATION
Figure Symmetrical Bipolar Operation
//10
REF10
TRIM VREFL +10V OPERATION
DAC8412 DAC8413
-15V
Figure Unipolar Operation
Figure (Symmetrical Bipolar Operation) shows DAC8412 configured operation. Note: AD688 data sheet full explanation reference operation. Adjustments required many applications since AD688 very high accuracy reference. However additional adjustments required, adjust DAC8412 full scale first. Begin loading digital full-scale code (FFFH), then adjust Gain Adjust potentiometer attain output voltage 9.9976 Then, adjust Balance Adjust center scale output voltage 0.000
-12-
REV.
DAC8412/DAC8413
bypass capacitors shown reference inputs Figure should used whenever references used. Applications with single references references require bypassing. resistor series with output reference amplifier keep amplifier from oscillating with capacitive load. have found that this large enough stabilize this circuit. Larger resistor values acceptable, provided that drop across resistor doesn't exceed VBE. Assuming minimum maximum current 2.75 then resistor should under loading single DAC8412. Using separate references recommended. Having references could cause different drifts with time temperature; whereas with single reference, most drifts will track. Unipolar positive full-scale operation usually with reference with correct output voltage. This preferable using reference dividing down required value. full-scale output, circuit configured shown Figure this configuration full-scale value first adjusting resistor full-scale output 9.9976
TRIM VREFH OUTPUT 0.01 ZERO -10V OPERATION -15V VREFL ZERO +2.5V OPERATION SINGLE SUPPLY //10
Figure shows DAC8412 configured operation. REF08 with output connected directly VREFL reference voltage.
Single Supply Operation
operation with supply, reference voltage should between +2.5 optimum linearity. Figure shows REF43 used supply +2.5 reference voltage. headroom reference both sufficient support supply with tolerance. VLOGIC should connected same supply. Separate bypassing each should also used.
INPUT OUTPUT VREFH VREFL 0.01
REF43
TRIM
DAC8412 DAC8413
//10
REF08
DAC8412 DAC8413
Figure Single Supply Operation
Figure Unipolar Operation
REV.
-13-
DAC8412/DAC8413
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
28-Position Leadless Chip Carrier Suffix)
0.075 (1.91) 0.095 (2.41) 0.075 (1.90) VIEW 0.458 (11.63) 0.011 (0.28) 0.007 (0.18) 0.075 (1.91) 0.088 (2.24) 0.054 (1.37)
0.458 (11.63) 0.442 (11.23)
0.100 (2.54) 0.064 (1.63)
0.300 (7.62) 0.150 (3.51)
0.015 (0.38) 0.028 (0.71) 0.022 (0.56) 0.050 (1.27)
BOTTOM VIEW
0.055 (1.40) 0.045 (1.14)
0.200 (5.08)
28-Lead PLCC (P-28A) Suffix)
0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)
IDENTIFIER
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07)
0.025 (0.63) 0.015 (0.38) 0.021 (0.53) 0.013 (0.33)
VIEW
(PINS DOWN)
0.050 (1.27)
0.032 (0.81) 0.026 (0.66)
0.430 (10.92) 0.390 (9.91)
0.020 (0.50)
0.456 (11.58) 0.450 (11.43) 0.495 (12.57) 0.485 (12.32)
0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
28-Lead Epoxy (N-28) Suffix)
1.565 (39.70) 1.380 (35.10)
0.580 (14.73) 0.485 (12.32)
0.060 (1.52) 0.015 (0.38)
0.625 (15.87) 0.600 (15.24) 0.195 (4.95) 0.125 (3.18)
0.250 (6.35) 0.200 (5.05) 0.022 (0.558) 0.125 (3.18) 0.014 (0.356)
0.150 (3.81) 0.100 (2.54) 0.070 SEATING (1.77) PLANE
0.015 (0.381) 0.008 (0.204)
-14-
REV.
PRINTED U.S.A.
C1544a-2-3/00 (rev.

Quad, 12-Bit Voltage Output with Readback DAC8412/DAC8413 VLOGIC

Top Searches for this datasheet

Other recent searches