Microcomputer ADSP-21161N Integrated Peripherals-Integrated Proce
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SUMMARY High Performance 32-Bit DSP-Applications Audio, Medical, Military, Wireless Communications, Graphics, Imaging, Motor-Control, Telephony Super Harvard Architecture-Four Independent Buses Dual Data Fetch, Instruction Fetch, Nonintrusive, Zero-Overhead Code Compatible with Other SHARC Family DSPs (SIMD) Computational Architecture-Two 32-Bit IEEE Floating-Point Computation Units, Each with Multiplier, ALU, Shifter, Register File Serial Ports Offer Support Programmable Simultaneous Receive Transmit Pins, which Support Transmit Receive Channels Audio
Microcomputer ADSP-21161N
Integrated Peripherals-Integrated Processor, On-Chip Dual-Ported SRAM, SDRAM Controller, Glueless Multiprocessing Features, Ports (Serial, Link, External Bus, SPI, JTAG) ADSP-21161N Supports 32-Bit Fixed, 32-Bit Float, 40-Bit Floating-Point Formats FEATURES Core Instruction Rate Single-Cycle Instruction Execution, Including SIMD Operations Both Computational Units MFLOPs Peak MFLOPs Sustained Performance 225-Ball MBGA Package
FUNCTIONAL BLOCK DIAGRAM
CORE PROCESSOR INSTRUCTION CACHE 48-BIT DUAL-PORTED SRAM
BLOCK
TIMER
PROCESSOR PORT ADDR ADDR DATA DATA DATA
PORT ADDR
BLOCK
INDEPENDENT DUAL-PORTED BLOCKS
JTAG TEST EMULATION GPIO FLAGS SDRAM CONTROLLER
DATA
ADDR
DAG1
DAG2
PROGRAM SEQUENCER
EXTERNAL PORT ADDR
ADDRESS ADDRESS CONNECT (PX) DATA DATA
MULTIPROCESSOR INTERFACE
DATA DATA REGISTER FILE (PEX) 40-BIT DATA REGISTER FILE (PEY) 40-BIT
HOST PORT
MULT
BARREL SHIFTER
BARREL SHIFTER
MULT
REGISTERS (MEMORY MAPPED) CONTROL, STATUS, DATA BUFFERS
CONTROLLER SERIAL PORTS
LINK PORTS PORTS
PROCESSOR
SHARC SHARC logo registered trademarks Analog Devices, Inc.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O.Box 9106, Norwood, 02062-9106, U.S.A. Tel:781/329-4700 www.analog.com Fax:781/326-8703 2003 Analog Devices, Inc. rights reserved.
ADSP-21161N
FEATURES (continued) On-Chip Dual-Ported SRAM (0.5 Block Block Independent Access Core Processor Million Fixed-Point MACs Sustained Performance Dual Data Address Generators (DAGs) with Modulo Bit-Reverse Addressing Zero-Overhead Looping with Single-Cycle Loop Setup, Providing Efficient Program Sequencing IEEE 1149.1 JTAG Standard Test Access Port On-Chip Emulation Single Instruction Multiple Data (SIMD) Architecture Provides: Computational Processing Elements Concurrent Execution-Each Processing Element Executes Same Instruction, Operates Different Data Code Compatibility-At Assembly Level, Uses Same Instruction Other SHARC DSPs Parallelism Buses Computational Units Enables: Single-Cycle Execution (with without SIMD) Multiply Operation, Operation, Dual Memory Read Write, Instruction Fetch Transfers Between Memory Core Four 32-Bit Floating- Fixed-Point Words Cycle, Sustained Gbytes/s Bandwidth Accelerated Butterfly Computation through Multiply with Subtract Controller Supports: Zero-Overhead Channels Transfers between ADSP-21161N Internal Memory External Memory, External Peripherals, Host Processor, Serial Ports, Link Ports, Serial Peripheral Interface (SPICompatible) 64-Bit Background Transfers Core Clock Speed, Parallel with Full-Speed Processor Execution Bytes/s Transfer Rate over Host Processor Interface 16-, 32-Bit Microprocessors; Host Directly Read/Write ADSP-21161N Registers 32-Bit 48-Bit) Wide Synchronous External Port Provides: Glueless Connection Asynchronous, SBSRAM SDRAM External Memories Memory Interface Supports Programmable Wait State Generation Wait Mode Off-Chip Memory Operation Non-SDRAM Accesses 1:2, 1:3, 1:4, 1:6, Clock into Core Clock Frequency Multiply Ratios 24-Bit Address, 32-Bit Data Bus. Additional Data Lines Multiplexed Link Port Data Pins Allow Complete 48-Bit Wide Data Single-Cycle External Instruction Execution Direct Reads Writes Registers from Host Other 21161N DSPs 62.7 Mega-Word Address Range Off-Chip SRAM SBSRAM Memories 32-48, 16-48, 8-48 Execution Packing Executing Instruction Directly from 32-Bit, 16-Bit, 8-Bit Wide External Memories 32-48, 16-48, 8-48, 32-32/64, 16-32/64, 8-32/64, Data Packing Transfers Directly from 32-Bit, 16-Bit, 8-Bit Wide External Memories from Internal 32-, 48-, 64-Bit Internal Memory Configured have 48-Bit Wide External Data Bus, Link Ports Used. Link Port Data Lines Multiplexed with Data Lines Enabled through Control Bits SYSCON SDRAM Controller Glueless Interface Cost External Memory Zero Wait State, Operation Most Accesses Extended External Memory Banks Words) SDRAM Accesses Page Sizes 2048 Words SDRAM Controller Supports SDRAM Memory Banks Support Interface Core Clock Half Core Clock Frequency Support Bits, Bits, Bits, Bits with SDRAM Data Configurations Mega-Word Address Range Off-Chip SDRAM Memory Multiprocessing Support Provides: Glueless Connection Scalable Multiprocessing Architecture Distributed On-Chip Arbitration Parallel Connect ADSP-21161Ns, Global Memory, Host 8-Bit Wide Link Ports Point-to-Point Connectivity Between ADSP-21161Ns Bytes/s Transfer Rate over Parallel Bytes/s Transfer Rate Over Link Ports Serial Ports Provide: Four Bit/s Synchronous Serial Ports with Companding Hardware Bidirectional Serial Data Pins, Configurable Either Transmitter Receiver Support, Programmable Direction Simultaneous Receive Transmit Channels, Either Transmit Channels Receive Channels Channel Support Interfaces Companding Selection Channel Basis Mode Serial Peripheral Interface (SPI) Slave Serial Boot through from Master Device Full-Duplex Operation Master-Slave Mode Multimaster Support Open-Drain Outputs Programmable Baud Rates, Clock Polarities Phases Programmable Pins Programmable Timer
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ADSP-21161N
TABLE CONTENTS
GENERAL DESCRIPTION ADSP-21161N Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Single-Cycle Fetch Instruction Four Operands Instruction Cache Data Address Generators With Hardware Circular Buffers Flexible Instruction ADSP-21161N Memory Interface Features Dual-Ported On-Chip Memory Off-Chip Memory Peripherals Interface SDRAM Interface Target Board JTAG Emulator Connector Controller Multiprocessing Link Ports Serial Ports Serial Peripheral (Compatible) Interface Host Processor Interface General-Purpose Ports Program Booting Phase-Locked Loop Crystal Double Enable Power Supplies Development Tools Designing Emulator-Compatible Board (Target) Additional Information FUNCTION DESCRIPTIONS BOOT MODES SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS SENSITIVITY TIMING SPECIFICATIONS Power Dissipation Power-up Sequencing Silicon Revision 0.3, 1.0, Clock Input Clock Signals Reset Interrupts Timer Flags Memory Read Master Memory Write Master Synchronous Read/Write Master Synchronous Read/Write Slave Host Request Asynchronous Read/Write Host ADSP-21161N Three-State Timing Master, Slave Handshake SDRAM Interface Master Link Ports Serial Ports REV.
Interface Specifications JTAG Test Access Port Emulation Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Environmental Conditions Thermal Characteristics 225-BALL METRIC MBGA CONFIGURATIONS OUTLINE DIMENSIONS ORDERING GUIDE Revision History
GENERAL DESCRIPTION
ADSP-21161N SHARC first cost derivative ADSP-21160 featuring Analog Devices Super Harvard Architecture. Easing portability, ADSP-21161N source code compatible with ADSP-21160 with first generation ADSP-2106x SHARCs SISD (Single Instruction, Single Data) mode. Like other SHARC DSPs, ADSP-21161N 32-bit processor that optimized high performance applications. ADSP-21161N includes core, dual-ported on-chip SRAM, integrated processor with multiprocessing support, multiple internal buses eliminate bottlenecks. first offered ADSP-21160, ADSP-21161N offers (SIMD) architecture. Using computational units (ADSP-2106x SHARCs have one), ADSP-21161N double cycle performance versus ADSP-2106x range algorithms. Fabricated state art, high speed, power CMOS process, ADSP-21161N instruction cycle time. With SIMD computational hardware running MHz, ADSP-21161N perform million math operations second. Table shows performance benchmarks ADSP-21161N.
Table Benchmarks MHz) Benchmark Algorithm Speed MHz)
1024 Point Complex (Radix with reversal) Filter (per tap)1 Filter (per biquad)1 Matrix Multiply (pipelined) Divide (y/x) Inverse Square Root Transfers
bytes/s
Specified SISD mode. Using SIMD, same benchmark applies sets computations. example, sets biquad operations performed same amount time SISD mode benchmark.
ADSP-21161N
ADSP-21161N continues SHARC's industry-leading standards integration DSPs, combining high performance 32-bit core with integrated, on-chip system features. These features include dual ported SRAM memory, host processor interface, processor that supports channels, four serial ports, link ports, SDRAM controller, interface, external parallel bus, glueless multiprocessing. block diagram ADSP-21161N Page illustrates following architectural features: processing elements, each made ALU, Multiplier, Shifter, Data Register File Data Address Generators (DAG1, DAG2) Program sequencer with instruction cache buses capable supporting four 32-bit data transfers between memory core every core processor cycle Interval timer On-Chip SRAM bit) SDRAM Controller glueless interface SDRAMs External port that supports: Interfacing off-chip memory peripherals Glueless multiprocessing support ADSP21161N SHARCs Host port read/write registers controller Four serial ports link ports compatible interface JTAG test access port General-Purpose Pins Figure shows typical single-processor system. multiprocessing system appears Figure Page
CONTROL
ADSP-21161N
CLOCK CLKIN XTAL CLK_CFG1-0 CLKDBL EBOOT LBOOT IRQ2-0 FLAG11-0 TIMEXP RPBA ID2-0
ADDRESS
DATA
ADDR
BRST
DATA ADDR
BOOT EPROM (OPTIONAL)
ADDR23-0
LINK DEVICES MAX) (OPTIONAL) SERIAL DEVICE (OPTIONAL)
DATA47-16 LXCLK LXACK MS3-0 LXDAT7-0 SCLK0 SCLK1 SCLK2 SCLK3 SDWE SDCLK1-0 SDCKE SDA10
MEMORY DATA PERIPHERALS (OPTIONAL) SDRAM (OPTIONAL) ADDR
SERIAL DEVICE (OPTIONAL)
SERIAL DEVICE (OPTIONAL)
DATA CLKOUT DMAR2-1 DMAG2-1
DEVICE (OPTIONAL) DATA
SERIAL DEVICE (OPTIONAL)
REDY BR6-1 ADDR DATA
COMPATIBLE DEVICE (HOST SLAVE) (OPTIONAL)
SPICLK SPIDS MOSI MISO
HOST PROCESSOR INTERFACE (OPTIONAL)
SBTS RESET RSTOUT JTAG
Figure System Diagram
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ADSP-21161N
ADSP-21161N Family Core Architecture
ADSP-21161N includes following architectural features ADSP-2116x family core. ADSP-21161N code compatible assembly level with ADSP-21160, ADSP21060, ADSP-21061, ADSP-21062, ADSP-21065L.
SIMD Computational Engine
processor simultaneously fetch four operands (two over each data bus) instruction (from cache), single cycle.
Instruction Cache
ADSP-21161N contains computational processing elements that operate Single Instruction Multiple Data (SIMD) engine. processing elements referred PEY, each contains ALU, multiplier, shifter, register file. always active, enabled setting PEYEN mode MODE1 register. When this mode enabled, same instruction executed both processing elements, each processing element operates different data. This architecture efficient executing math intensive algorithms. Entering SIMD mode also effect data transferred between memory processing elements. When SIMD mode, twice data bandwidth required sustain computational operation processing elements. Because this requirement, entering SIMD mode also doubles bandwidth between memory processing elements. When using DAGs transfer data SIMD mode, data values transferred with each access memory register file. SIMD supported only internal memory accesses supported off-chip accesses.
Independent, Parallel Computation Units
ADSP-21161N includes on-chip instruction cache that enables three-bus operation fetching instruction four data values. cache selective-only instructions whose fetches conflict with data accesses cached. This cache enables full-speed execution core, looped operations such digital filter multiply-accumulates, butterfly processing.
Data Address Generators With Hardware Circular Buffers
ADSP-21161N's data address generators (DAGs) used indirect addressing implementing circular data buffers hardware. Circular buffers allow efficient programming delay lines other data structures required digital signal processing, commonly used digital filters Fourier transforms. DAGs ADSP-21161N contain sufficient registers allow creation circular buffers primary register sets, secondary). DAGs automatically handle address pointer wrap-around, reduce overhead, increase performance, simplify implementation. Circular buffers start memory location.
Flexible Instruction
Within each processing element computational units. computational units consist arithmetic/logic unit (ALU), multiplier, shifter. These units perform single-cycle instructions. three units within each processing element arranged parallel, maximizing computational throughput. Single multifunction instructions execute parallel multiplier operations. SIMD mode, parallel multiplier operations occur both processing elements. These computation units support IEEE 32-bit single-precision floatingpoint, 40-bit extended precision floating-point, 32-bit fixed-point data formats.
Data Register File
48-bit instruction word accommodates variety parallel operations, concise programming. example, ADSP21161N conditionally execute multiply, add, subtract both processing elements, while branching, single instruction.
ADSP-21161N Memory Interface Features
ADSP-21161N adds following architectural features ADSP-2116x family core:
Dual-Ported On-Chip Memory
general-purpose data register file contained each processing element. register files transfer data between computation units data buses, store intermediate results. These 10-port, 32-register primary, secondary) register files, combined with ADSP-2116x enhanced Harvard architecture, allow unconstrained data flow between computation units internal memory. registers referred R0-R15 S0-S15.
Single-Cycle Fetch Instruction Four Operands
ADSP-21161N features enhanced Harvard architecture which data memory (DM) transfers data program memory (PM) transfers both instructions data (see Figure Page With ADSP-21161N's separate program data memory buses on-chip instruction cache,
ADSP-21161N contains megabit on-chip SRAM, organized blocks bits. Each block configured different combinations code data storage. Each memory block dual-ported single-cycle, independent accesses core processor processor. dualported memory combination with three separate on-chip buses allow data transfers from core from processor, single cycle. ADSP-21161N, memory configured maximum words 32-bit data, words 16-bit data, words 48-bit instructions 40-bit data), combinations different word sizes megabit. memory accessed 16-bit, 32-bit, 48-bit, 64-bit words. 16-bit floating-point storage format supported that effectively doubles amount data that stored on-chip. Conversion between 32-bit floating-point 16-bit floating-point formats done single instruction. While each memory block store combinations code data, accesses most efficient when block stores data using transfers, other block stores instructions data using transfers. Using
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ADSP-21161N
bus, with dedicated each memory block, assures single-cycle execution with data transfers. this case, instruction must available cache.
ADDRESS
ADDRESS
REGISTERS LONG WORD ADDRESSING INTERNAL MEMORY SPACE NORMAL WORD ADDRESSING
0x0000 0000 0x0001 FFFF 0x0002 0000 0x0002 1FFF (BLK 0x0002 8000 0x0002 9FFF (BLK 0x0004 0000 0x0004 3FFF (BLK 0x0005 0000 0x0005 3FFF (BLK 0x0008 0000 0x0008 7FFF (BLK 0x000A 0000 0x000A 7FFF (BLK
0x0020 0000
BANK 0x00FF FFFF (NON-SDRAM) 0x03FF FFFF (SDRAM)
SHORT WORD ADDRESSING
0x0400 0000 REGISTERS ADSP-21161N WITH REGISTERS ADSP-21161N WITH 0x0010 0000 0x0011 FFFF
0x0012 0000 0x0013 FFFF BANK
REGISTERS ADSP-21161N WITH
0x0014 0000 0x0015 FFFF
0x04FF FFFF (NON-SDRAM) 0x07FF FFFF (SDRAM)
MULTIPROCESSOR MEMORY SPACE
REGISTERS ADSP-21161N WITH
0x0016 0000 0x0017 FFFF
0x0800 0000
REGISTERS ADSP-21161N WITH
0x0018 0000 0x0019 FFFF BANK
REGISTERS ADSP-21161N WITH
0x001A 0000 0x001B FFFF
0x08FF FFFF (NON-SDRAM) 0x0BFF FFFF (SDRAM)
0x001C 0000 RESERVED 0x001F FFFF 0x0C00 0000
EXTERNAL MEMORY SPACE
BANK
0x0CFF FFFF (NON-SDRAM) 0x0FFF FFFF (SDRAM)
NOTE: BANK SIZES FIXED
Figure Memory Off-Chip Memory Peripherals Interface
ADSP-21161N's external port provides processor's interface off-chip memory peripherals. 62.7-M word off-chip address space (254.7-M word SDRAM) included ADSP-21161N's unified address space. separate onchip buses-for addresses, data, addresses, data, addresses, data-are multiplexed external port create external system with single 24-bit address single 32-bit data bus. Every access external memory based address that fetches 32-bit word. When fetching instruction from external memory, 32-bit data locations being accessed packed instructions. Unused link port lines also used additional data lines DATA15-DATA0, allowing single-cycle execution instructions from external memory, MHz. Figure Page shows alignment various accesses external memory.
external port supports asynchronous, synchronous, synchronous burst accesses. Synchronous burst SRAM interfaced gluelessly. ADSP-21161N also interface gluelessly SDRAM. Addressing external memory devices facilitated on-chip decoding high-order address lines generate memory bank select signals. ADSP-21161N provides programmable memory wait states external memory acknowledge controls allow interfacing memory peripherals with variable access, hold, disable time requirements.
SDRAM Interface
SDRAM interface enables ADSP-21161N transfer data from synchronous DRAM (SDRAM) core clock frequency one-half core clock frequency.
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synchronous approach, coupled with core clock frequency, supports data transfer high throughput-up bytes/s 32-bit transfers bytes/s 48-bit transfers. SDRAM interface provides glueless interface with standard SDRAMs-16 includes options support additional buffers between ADSP-21161N SDRAM. SDRAM interface extremely flexible provides capability connecting SDRAMs ADSP-21161N's four external memory banks, with four banks mapped SDRAM. Systems with several SDRAM devices connected parallel require buffering meet overall system timing requirements. ADSP-21161N supports pipelining address control signals enable such buffering between itself multiple SDRAM devices.
Target Board JTAG Emulator Connector
Other features include interrupt generation upon completion transfers, chaining automatic linked transfers.
DATA47-16
DATA15-0 L0DATA7-0 TA7-0
PROM BOOT
L1DATA7-0 A15-8
8-BIT PACKED 8-BIT PACKED INST RUCT EXECUTION 16-BIT PACKED DATA 16-BIT PACKED INSTRUCTION EXECUTION LOAT FIXED, D31-D0, 32-BIT CKED 32-BIT CKED INSTRUCT 48-BIT INSTRUCT FETCH PACKING) NOTE: EXTRA LINES DATA15-0 ONLY ACCESSIBLE LINK PORT DISABLED. ENAB THESE ADDITIONAL DATA INKS SELECTING IPACK1-0 SYSCON.
Analog Devices Tools product line JTAG emulators uses IEEE 1149.1 JTAG test access port ADSP-21161N processor monitor control target board processor during emulation. Analog Devices Tools product line JTAG emulators provides emulation full processor speed, allowing inspection modification memory, registers, processor stacks. processor's JTAG interface ensures that emulator will affect target system loading timing. complete information SHARC Analog Devices Tools product line JTAG emulator operation, appropriate Emulator Hardware User's Guide. detailed information interfacing Analog Devices JTAG emulators with Analog Devices products with JTAG emulation ports, please refer Engineer Engineer Note EE-68: Analog Devices JTAG Emulation Technical Reference. Both these documents found Analog Devices website:
Controller
Figure External Data Alignment Options Multiprocessing
ADSP-21161N offers powerful features tailored multiprocessing systems. external port link ports provide integrated glueless multiprocessing support. external port supports unified address space (see Figure Page that enables direct interprocessor accesses each ADSP-21161N's internal memory-mapped (I/O processor) registers. other internal memory indirectly accessed transfers initiated programming parameter control registers. Distributed arbitration logic included on-chip simple, glueless connection systems containing ADSP-21161Ns host processor. Master processor change over incurs only cycle overhead. arbitration selectable either fixed rotating priority. lock enables indivisible read-modify-write sequences semaphores. vector interrupt provided interprocessor commands. Maximum throughput interprocessor data transfer bytes/s over external port. link ports provide second method multiprocessing communications. Each link port support communications another ADSP-21161N. ADSP-21161N, running MHz, maximum throughput interprocessor communications over links bytes/s. link ports cluster multiprocessing used concurrently independently.
Link Ports
ADSP-21161N's on-chip controller enables zerooverhead data transfers without processor intervention. controller operates independently invisibly processor core, allowing operations occur while core simultaneously executing program instructions. transfers occur between ADSP-21161N's internal memory external memory, external peripherals, host processor. transfers also occur between ADSP21161N's internal memory serial ports, link ports, SPI-compatible (Serial Peripheral Interface) port. External packing unpacking 32-, 48-, 64-bit words internal memory performed during transfers from either 16-, 32-bit wide external memory. Fourteen channels available ADSP-21161N-two shared between interface link ports, eight serial ports, four processor's external port (for host processor, other ADSP-21161Ns, memory, transfers). Programs downloaded ADSP-21161N using transfers. Asynchronous off-chip peripherals control channels using Request/Grant lines (DMAR2-1, DMAG2-1).
ADSP-21161N features 8-bit link ports that provide additional capabilities. With capability running MHz, each link port support bytes/s. Link port especially useful point-to-point interprocessor communication multiprocessing systems. link ports operate independently simultaneously, with maximum data throughput bytes/s. Link port data packed into 32-bit words directly read core processor
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ADSP-21161N
CLOCK RESET
ADSP-21161N
CONTROL ADDRESS DATA
ADSP-21161N
CLKIN RESET ID2-0 CONTROL ADDR23-0 DATA47-16
ADSP-21161N
CLKIN RESET ID2-0 ADDR23-0 DATA47-16 CONTROL ADDR DATA BOOT EPROM (OPTIONAL)
ADSP-21161N
CLKIN RESET ID2-0
ADDR23-0 DATA47-16 MS3-0 SBTS
ADDR DATA GLOBAL MEMORY PERIPHERALS (OPTIONAL)
REDY ADDR BR6-2
CONTROL
CONTROL
HOST PROCESSOR INTERFACE (OPTIONAL)
DATA
ADDRESS DATA
SDWE SDCLK1-0 SDCKE
SDRAM (OPTIONAL)
SDA10
ADDR DATA
Figure Shared Memory Multiprocessing System
DMA-transferred on-chip memory. Each link port double-buffered input output registers. Clock/acknowledge handshaking controls link port transfers. Transfers programmable either transmit receive.
Serial Ports
ADSP-21161N features four synchronous serial ports that provide inexpensive interface wide variety digital mixed-signal peripheral devices. Each serial port made data lines, clock frame sync. data lines programmed either transmit receive.
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ADSP-21161N
serial ports operate half clock rate core, providing each with maximum data rate bit/s. serial data pins programmable either transmitter receiver, providing greater flexibility serial communications. Serial port data automatically transferred from on-chip memory dedicated DMA. Each serial ports features Time Division Multiplex (TDM) multichannel mode, where serial ports transmitters serial ports receivers (SPORT0 paired with SPORT2 SPORT1 paired with SPORT3 Tx). Each serial ports also support protocol industry standard interface commonly used audio codecs, ADCs DACs), with data pins, allowing four channels (using stereo devices) serial port, with maximum channels. serial ports permit little-endian big-endian transmission formats word lengths selectable from bits bits. mode, data-word lengths selectable between bits bits. Serial ports offer selectable synchronization transmit modes well optional µ-law A-law companding. Serial port clocks frame syncs internally externally generated.
Serial Peripheral (Compatible) Interface Program Booting
internal memory ADSP-21161N booted system power-up from either 8-bit EPROM, host processor, interface, through link ports. Selection boot source controlled Boot Memory Select (BMS), EBOOT (EPROM Boot), Link/Host Boot (LBOOT) pins. 16-, 32-bit host processors also used booting.
Phase-Locked Loop Crystal Double Enable
ADSP-21161N uses on-chip Phase-Locked Loop (PLL) generate internal clock core. CLK_CFG1-0 pins used select ratios 2:1, 3:1, 4:1. addition ratios, CLKDBL used more clock ratio options. CLKIN) rate CLKDBL determines rate input clock rate which external port operates. With combination CLK_CFG1-0 CLKDBL, ratios 2:1, 3:1, 4:1, 6:1, between core CLKIN supported. also Figure Page
Power Supplies
Serial Peripheral Interface (SPI) industry standard synchronous serial link, enabling ADSP-21161N SPI-compatible port communicate with other SPI-compatible devices. 4-wire interface consisting data pins, device select pin, clock pin. full-duplex synchronous serial interface, supporting both master slave modes. port operate multimaster environment interfacing with four other SPI-compatible devices, either acting master slave device. ADSP-21161N SPI-compatible peripheral implementation also features programmable baud rate clock phase/polarities. ADSP-21161N SPI-compatible port uses open drain drivers support multimaster configuration avoid data contention.
Host Processor Interface
ADSP-21161N separate power supply connections analog (AVDD/AGND), internal (VDDINT), external (VDDEXT) power supplies. internal analog supplies must meet requirement. external supply must meet requirement. external supply pins must connected same supply. Note that analog supply (AVDD) powers ADSP-21161N's clock generator PLL. produce stable clock, provide external circuit filter power input AVDD pin. Place filter close possible pin. example circuit, Figure prevent noise coupling, wide trace analog ground (AGND) signal install decoupling capacitor close possible pin.
VDDINT AGND 0.01 AVDD
ADSP-21161N host interface enables easy connection standard 8-bit, 16-bit, 32-bit microprocessor buses with little additional hardware required. host interface accessed through ADSP-21161N's external port. Four channels available host interface; code data transfers accomplished with software overhead. host processor requests ADSP-21161N's external with host request (HBR), host grant (HBG), chip select (CS) signals. host directly read write internal registers ADSP-21161N, access channel setup message registers. setup host would allow access internal memory address transfers. Vector interrupt support provides efficient execution host commands.
General-Purpose Ports
Figure Analog Power (AVDD) Filter Circuit Development Tools
ADSP-21161N supported with complete software hardware development tools, including Analog Devices emulators VisualDSP++1 development environment. same emulator hardware that supports other ADSP-21xxx DSPs, also fully emulates ADSP-21161N. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy-to-use assembler that based algebraic syntax; archiver (librarian/library builder), linker, loader,
ADSP-21161N also contains programmable, general purpose pins that function either input output. output, these pins signal peripheral devices; input, these pins provide test conditional branching.
VisualDSP++ registered trademark Analog Devices, Inc.
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cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ run-time library that includes mathematical functions. points these tools are: Compiled ADSP-21161N C/C++ code efficiency-The compiler been developed efficient translation C/C++ code ADSP-21161N assembly. architectural features that improve efficiency compiled C/C++ code. ADSP-2106x family code compatibility-The assembler legacy features ease conversion existing ADSP-2106x applications ADSP-21161N. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information) Insert break points conditional breakpoints registers, memory, stacks Trace instruction execution Perform linear statistical profiling program execution Fill, dump, graphically plot contents memory Source level debugging Create custom debugger windows VisualDSP++ lets programmers define manage software development. dialog boxes property pages programmers configure manage ADSP-21xxx development tools, including syntax highlighting VisualDSP++ editor. This capability permits: Controlling development tools process inputs generate outputs. Maintaining one-to-one correspondence with tool's command line switches. Analog Devices emulators IEEE 1149.1 JTAG test access port ADSP-21161N processor monitor control target board processor during emulation. emulator provides full-speed emulation, allowing inspection modification memory, registers, processor stacks. Nonintrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting ADSP-21xxx processor family. Hardware tools include ADSP-21xxx plug-in cards. Third Party software tools include libraries, real-time operating systems, block diagram design tools.
Designing Emulator-Compatible Board (Target)
uses access internal features DSP, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. must halted send data commands, once operation been completed emulator, system running full speed with impact system timing. these emulators, target's design must include interface between Analog Devices JTAG emulation header custom target board.
Target Board Header
emulator interface Analog Devices JTAG 14-pin header, shown Figure customer must supply this header target board order communicate with emulator. interface consists standard dual 0.025" square post header, 0.1" 0.1" spacing, with minimum post length 0.235". position used prevent from being inserted backwards. This must clipped target board. Also, clearance (length, width, height) around header must considered. Leave clearance least 0.15" 0.10" around length width header, reserve height clearance attach detach connector. seen Figure there sets signals header. There standard JTAG signals TMS, TCK, TDI, TDO, TRST, used emulation purposes (via emulator). There also secondary JTAG signals BTMS, BTCK, BTDI, BTRST that optionally used boardlevel (boundary scan) testing.
PIN) BTMS BTCK BTRST BTDI
TRST
VIEW
Figure JTAG Target Board Connector JTAG Equipped Analog Devices (Jumpers Place)
Analog Devices Tools family emulators tools that every developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) each JTAG DSP. emulator
When emulator connected this header, place jumpers across BTMS, BTCK, BTRST, BTDI shown Figure This holds JTAG signals correct state allow free. Remove jumpers when connecting emulator JTAG header.
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PIN) BTMS BTCK BTDI
0.88" 0.64"
BTRST
TRST
0.24"
Figure JTAG Connector Dimensions
VIEW
0.10"
Figure JTAG Target Board Connector with Local Boundary Scan JTAG Emulator Connector
0.15"
Figure JTAG Connector Keep-Out
Figure details dimensions JTAG connector 14-pin target end. Figure displays keep-out area target board header. keep-out area enables connector properly seat onto target board header. This board area should contain components (chips, resistors, capacitors, etc.). dimensions referenced center 0.025" square post pin.
Design-for-Emulation Circuit Information
EE-68: Analog Devices JTAG Emulation Technical Reference Analog Devices website (www.analog.com)-use site search "EE-68". This document updated regularly keep pace with improvements emulator support.
Additional Information
details target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic,
This data sheet provides general overview ADSP-21161N architecture functionality. detailed information ADSP-2116x Family core architecture instruction set, refer ADSP-21161 SHARC Hardware Reference ADSP-21160 SHARC Instruction Reference.
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ADSP-21161N
FUNCTION DESCRIPTIONS
ADSP-21161N definitions listed below. Inputs identified synchronous must meet timing requirements with respect CLKIN with respect TMS, TDI). Inputs identified asynchronous asserted asynchronously CLKIN TRST).Tie pull unused inputs VDDEXT GND, except following: ADDR23-0, DATA47-0, BRST, CLKOUT (Note: These pins have logic-level hold circuit enabled ADSP-21161N with ID2-0 00x.) ACK, DMARx, DMAGx, (ID2-0 00x) (Note: These pins have pull-up enabled ADSP21161N with ID2-0 00x.) LxCLK, LxACK, LxDAT7-0 (LxPDRDE (Note: Link Port Buffer Control Register definitions ADSP-21161N SHARC Hardware Reference.) DxA, DxB, SCLKx, SPICLK, MISO, MOSI, EMU, TMS,TRST, (Note: These pins have pull-up.)
Table Function Descriptions Type Function
following symbols appear Type column Table Asynchronous, Ground, Input, Output, Power Supply, Synchronous, (A/D) Active Drive, (O/D) Open Drain, Three-State (when SBTS asserted when ADSP-21161N slave). Unlike previous SHARC processors, ADSP-21161N contains internal series resistance equivalent input/output drivers except CLKIN XTAL pins. Therefore, traces longer than inches, external series resistors control, data, clock, frame sync pins required dampen reflections from transmission line effects point-to-point connections. However, more complex networks such star configuration, series termination still recommended.
ADDR23-0
I/O/T
DATA47-16
I/O/T
MS3-0
I/O/T
I/O/T
External Address. ADSP-21161N outputs addresses external memory peripherals these pins. multiprocessor system master outputs addresses read/writes registers other ADSP-21161Ns while other internal memory resources accessed indirectly control (that accessing parameter registers). ADSP-21161N inputs addresses when host processor multiprocessing master reading writing registers. keeper latch DSP's ADDR23-0 pins maintains input level last driven. This latch only enabled ADSP-21161N with ID2-0=00x. External Data. ADSP-21161N inputs outputs data instructions these pins. Pull-up resistors unused data pins necessary. keeper latch DSP's DATA47-16 pins maintains input level last driven. This latch only enabled ADSP-21161N with ID2-0=00x. Note: DATA15-8 pins (multiplexed with L1DAT7-0) also used extend data link ports disabled will used. addition, DATA7-0 pins (multiplexed with L0DAT7-0) also used extend data link ports used. This enables execution 48-bit instructions from external SBSRAM (system clock speed-external port), SRAM (system clock speed-external port) SDRAM (core clock one-half core clock speed). IPACKx Instruction Packing Mode Bits SYSCON should correctly (IPACK1-0=0x1) enable this full instruction Width/No-packing Mode operation. Memory Select Lines. These outputs asserted (low) chip selects corresponding banks external memory. Memory bank sizes fixed words nonSDRAM words SDRAM. MS3-0 outputs decoded memory address lines. asynchronous access mode, MS3-0 outputs transition with other address outputs. synchronous access modes, MS3-0 outputs assert with other address lines; however, they deassert after first CLKIN cycle which sampled asserted. multiprocessor system, signals tracked slave SHARCs. internal addresses zeros decoded into MS3-0. Memory Read Strobe. asserted whenever ADSP-21161N reads word from external memory from registers other ADSP-21161Ns. External devices, including other ADSP-21161Ns, must assert reading from word ADSP-21161N register memory. multiprocessing system, driven master. internal pull-up resistor that enabled DSPs with ID2-0=00x.
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ADSP-21161N
Table Function Descriptions (continued) Type Function
I/O/T
BRST
I/O/T
I/O/S
SBTS
SDWE SDCLK0 SDCLK1
I/O/T I/O/T I/O/T I/O/S/T O/S/T
SDCKE SDA10
I/O/T
IRQ2-0 FLAG11-0 TIMEXP
I/O/A
Memory Write Strobe. asserted when ADSP-21161N writes word external memory registers other ADSP-21161Ns. External devices must assert writing ADSP-21161N registers. multiprocessing system, master drives internal pull-up resistor that enabled DSPs with ID2-0=00x. Sequential Burst Access. BRST asserted ADSP-21161N indicate that data associated with consecutive addresses being read written. slave device samples initial address increments internal address counter after each transfer. incremented address pipelined bus. master ADSP-21161N multiprocessor environment read slave external port buffers (EPBx) using burst protocol. BRST asserted after initial access burst transfer. asserted every cycle after that, except last data request cycle (denoted asserted BRST negated). keeper latch DSP's BRST maintains input level last driven. This latch only enabled ADSP-21161N with ID2-0=00x. Memory Acknowledge. External devices de-assert (low) wait states external memory access. used devices, memory controllers, other peripherals hold completion external memory access. ADSP-21161N deasserts output wait states synchronous access registers. internal pull-up resistor that enabled during reset DSPs with ID2-0=00x. Suspend Three-State. External devices assert SBTS (low) place external address, data, selects, strobes high impedance state following cycle. ADSP-21161N attempts access external memory while SBTS asserted, processor will halt memory access will completed until SBTS deasserted. SBTS should only used recover from host processor/ADSP-21161N deadlock. SDRAM Column Access Strobe. conjunction with RAS, MSx, SDWE, SDCLKx, sometimes SDA10, defines operation SDRAM perform. SDRAM Access Strobe. conjunction with CAS, MSx, SDWE, SDCLKx, sometimes SDA10, defines operation SDRAM perform. SDRAM Write Enable. conjunction with CAS, RAS, MSx, SDCLKx, sometimes SDA10, defines operation SDRAM perform. SDRAM Data Mask. write mode, latency zero used during precharge command during SDRAM power-up initialization. SDRAM Clock Output Clock SDRAM devices. SDRAM Clock Output Additional clock SDRAM devices. systems with multiple SDRAM devices, handles increased clock load requirements, eliminating need offchip clock buffers. Either SDCLK1 both SDCLKx pins three-stated. SDRAM Clock Enable. Enables disables signal. details, data sheet supplied with SDRAM device. SDRAM Pin. Enables applications refresh SDRAM parallel with nonSDRAM accesses host accesses. This replaces DSP's only during SDRAM accesses. Interrupt Request Lines. These sampled rising edge CLKIN either edge-triggered level-sensitive. Flag Pins. Each configured control bits either input output. input, tested condition. output, used signal external peripherals. Timer Expired. Asserted four core clock cycles when timer enabled TCOUNT decrements zero. Host Request. Must asserted host processor request control ADSP21161N's external bus. When asserted multiprocessing system, ADSP21161N that master will relinquish assert HBG. relinquish bus, ADSP-21161N places address, data, select, strobe lines high impedance state. priority over ADSP-21161N requests (BR6-1) multiprocessing system.
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ADSP-21161N
Table Function Descriptions (continued) Type Function
REDY DMAR1
(O/D)
DMAR2
DMAG1
DMAG2
BR6-1
I/O/S
BMSTR
ID2-0
RPBA
I/O/T
SCLKx
Host Grant. Acknowledges request, indicating that host processor take control external bus. asserted (held low) ADSP-21161N until released. multiprocessing system, output ADSP-21161N master monitored others. After asserted, before given, will float CLKIN cycle). avoid erroneous grants, should pulled with external resistor. Chip Select. Asserted host processor select ADSP-21161N. Host Acknowledge. ADSP-21161N deasserts REDY (low) wait states host access registers when inputs asserted. Request (DMA Channel 11). Asserted external port devices request services. DMAR1 internal pull-up resistor that enabled DSPs with ID2-0=00x. Request (DMA Channel 12). Asserted external port devices request services. DMAR2 internal pull-up resistor that enabled DSPs with ID2-0=00x. Grant (DMA Channel 11). Asserted ADSP-21161N indicate that requested starts next cycle. Driven master only. DMAG1 internal pull-up resistor that enabled DSPs with ID2-0=00x. Grant (DMA Channel 12). Asserted ADSP-21161N indicate that requested starts next cycle. Driven master only. DMAG2 internal pull-up resistor that enabled DSPs with ID2-0=00x. Multiprocessing Requests. Used multiprocessing ADSP-21161Ns arbitrate mastership. ADSP-21161N only drives line (corresponding value ID2-0 inputs) monitors others. multiprocessor system with less than ADSP-21161Ns, unused pins should pulled high; processor's line must pulled high because output. Master Output. multiprocessor system, indicates whether ADSP-21161N current master shared external bus. ADSP-21161N drives BMSTR high only while master. single-processor system (ID=000), processor drives this high. This used debugging purposes. Multiprocessing Determines which multiprocessing request (BR6-BR1) used ADSP-21161N. corresponds BR1, ID=010 corresponds BR2, ID=000 ID=001 single-processor systems. These lines system configuration selection that should hardwired only changed reset. Rotating Priority Arbitration Select. When RPBA high, rotating priority multiprocessor arbitration selected. When RPBA low, fixed priority selected. This signal system configuration selection that must same value every ADSP21161N. value RPBA changed during system operation, must changed same CLKIN cycle every ADSP-21161N. Priority Access. Asserting enables ADSP-21161N slave interrupt background transfers gain access external bus. connected ADSP21161Ns system. access priority required system, should left unconnected. internal pull-up resistor that enabled DSPs with ID2-0=00x. Data Transmit Receive Channel (Serial Ports Each internal pull-up resistor. Bidirectional data pin. This signal configured output transmit serial data, input receive serial data. Data Transmit Receive Channel (Serial Ports Each internal pull-up resistor. Bidirectional data pin. This signal configured output transmit serial data, input receive serial data. Transmit/Receive Serial Clock (Serial Ports Each SCLK internal pull-up resistor. This signal either internally externally generated.
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ADSP-21161N
Table Function Descriptions (continued) Type Function
SPICLK
SPIDS
MOSI
(o/d)
MISO
(o/d)
LxDAT7-0 [DATA15-0]
[I/O/T]
LxCLK LxACK EBOOT LBOOT
Transmit Receive Frame Sync (Serial Ports frame sync pulse initiates shifting serial data. This signal either generated internally externally. active high early late frame sync, reference shifting serial data. Serial Peripheral Interface Clock Signal. Driven master, this signal controls rate which data transferred. master transmit data variety baud rates. SPICLK cycles once each transmitted. SPICLK gated clock that active during data transfers, only length transferred word. Slave devices ignore serial clock slave select input driven inactive (HIGH). SPICLK used shift shift data driven MISO MOSI lines. data always shifted clock edge clock sampled opposite edge clock. Clock polarity clock phase relative data programmable into SPICTL control register define transfer format. SPICLK internal pull-up resistor. Serial Peripheral Interface Slave Device Select. active signal used enable slave devices. This input signal behaves like chip select, provided master device slave devices. multimaster mode SPIDS signal asserted master device signal that error occurred, some other device also trying master device. asserted when device master mode, considered multimaster error. single-master, multiple-slave configuration where FLAG3-0 used, this must tied pulled high VDDEXT master device. ADSP-21161N ADSP21161N interaction, master ADSP-21161N's FLAG3-0 pins used drive SPIDS signal ADSP-21161N slave device. Master Slave. ADSP-21161N configured master, MOSI becomes data transmit (output) pin, transmitting output data. ADSP-21161N configured slave, MOSI becomes data receive (input) pin, receiving input data. ADSP-21161N interconnection, data shifted from MOSI output master shifted into MOSI input(s) slave(s). MOSI internal pullup resistor. Master Slave Out. ADSP-21161N configured master, MISO becomes data receive (input) pin, receiving input data. ADSP-21161N configured slave, MISO becomes data transmit (output) pin, transmitting output data. ADSP-21161N interconnection, data shifted from MISO output slave shifted into MISO input master. MISO internal pullup resistor. MISO configured setting SPICTL register. Note: Only slave allowed transmit data given time. Link Port Data (Link Ports 0-1). silicon revisions higher, each LxDAT keeper latch that enabled when used data pin; internal pull-down resistor that enabled disabled LxPDRDE LCTL register. silicon revisions 0.3, 1.0, each LxDAT internal pull-down resistor that enabled disabled LxPDRDE LCTL register. Note: L1DAT7-0 multiplexed with DATA15-8 pins L0DAT7-0 multiplexed with DATA7-0 pins. link ports disabled used, these pins used additional data lines executing instructions full clock rate from external memory. DATA47-16 more information. Link Port Clock (Link Ports 0-1). Each LxCLK internal pull-down resistor that enabled disabled LxPDRDE LCTL register. Link Port Acknowledge (Link Ports 0-1). Each LxACK internal pull-down resistor that enabled disabled LxPDRDE LCTL register. EPROM Boot Select. description this operates, table description. This signal system configuration selection that should hardwired. Link Boot. description this operates, table description. This signal system configuration selection that should hardwired.
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ADSP-21161N
Table Function Descriptions (continued) Type Function
I/O/T
CLKIN
XTAL CLK_CFG1-0
CLKDBL
CLKOUT
RESET
Boot Memory Select. Serves output input selected with EBOOT LBOOT pins (see Table This input system configuration selection that should hardwired. Host PROM boot, channel (EPB0) used. Link boot boot, channel used. Three-state only EPROM boot mode (when output). Local Clock Used conjunction with XTAL. CLKIN ADSP-21161N clock input. configures ADSP-21161N either internal clock generator external clock source. Connecting necessary components CLKIN XTAL enables internal clock generator. Connecting external clock CLKIN while leaving XTAL unconnected configures ADSP-21161N external clock source such external clock oscillator.The ADSP-21161N external port cycles frequency CLKIN. instruction cycle rate multiple CLKIN frequency; programmable powerup CLK_CFG1-0 pins. CLKIN halted, changed, operated below specified frequency. Crystal Oscillator Terminal Used conjunction with CLKIN enable ADSP21161N's internal clock oscillator disable external clock source. CLKIN. Core/CLKIN Ratio Control. ADSP-21161N core clock (instruction cycle) rate equal PLLICLK where user selectable using CLK_CFG1-0 inputs. These pins also used combination with CLKDBL generate additional core clock rates CLKIN CLKIN (see Clock Rate Ratios table CLKDBL description). Crystal Double Mode Enable. This used enable clock double circuitry, where CLKOUT configured either rate CLKIN. This CLKIN double circuit primarily intended used external crystal conjunction with internal clock generator XTAL pin. internal clock generator when used conjunction with XTAL external crystal designed support maximum external crystal frequency. CLKDBL used XTAL mode generate input into PLL. clock mode enabled (during RESET low) tying CLKDBL GND, otherwise connected VDDEXT clock mode. example, this enables crystal enable core clock rates CLKOUT operation when CLK_CFG0=0, CLK_CFG1=0 CLKDBL=0. This also used generate different clock rate ratios external clock oscillators well. possible clock rate ratio options MHz) either CLKIN (external clock oscillator) XTAL (crystal input) shown Table Page ratio enables 12.5 crystal generate core (instruction clock) rate CLKOUT (external port) clock rate. also Figure Page Note: When using external crystal, maximum crystal frequency cannot exceed MHz. other external clock sources, maximum CLKIN frequency MHz. Local Clock Out. CLKOUT driven either frequency CLKIN frequency current master. frequency determined CLKDBL pin. This output three-stated when ADSP-21161N master when host controls (HBG asserted). keeper latch DSP's CLKOUT maintains output level last driven. This latch only enabled ADSP-21161N with ID2-0=00x. CLKDBL enabled, CLKOUT=2 CLKIN CLKDBL disabled, CLKOUT=1 CLKIN Note: CLKOUT only controlled CLKDBL operates either CLKIN CLKIN. CLKOUT multiprocessing systems. CLKIN instead. Processor Reset. Resets ADSP-21161N known state begins execution program memory location specified hardware reset vector address. RESET input must asserted (low) power-up.
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Table Function Descriptions (continued) Type Function
RSTOUT1
TRST
(O/D)
VDDINT VDDEXT AVDD
AGND
Reset Out. When RSTOUT asserted (low), this indicates that core blocks reset. deasserted 4080 cycles after RESET deasserted indicating that stable locked. Test Clock (JTAG). Provides clock JTAG boundary scan. Test Mode Select (JTAG). Used control test state machine. internal pull-up resistor. Test Data Input (JTAG). Provides serial data boundary scan logic. internal pull-up resistor. Test Data Output (JTAG). Serial scan output boundary scan path. Test Reset (JTAG). Resets test state machine. TRST must asserted (pulsed low) after power-up held proper operation ADSP-21161N. TRST internal pull-up resistor. Emulation Status. Must connected ADSP-21161N Analog Devices Tools product line JTAG emulators target board connector only. internal pull-up resistor. Core Power Supply. Nominally +1.8 supplies DSP's core processor pins). Power Supply. Nominally +3.3 pins). Analog Power Supply. Nominally +1.8 supplies DSP's internal (clock generator). This same specifications VDDINT, except that added filtering circuitry required. Power Supplies Page Analog Power Supply Return. Power Supply Return. pins). Connect. Reserved pins that must left open unconnected. pins2).
RSTOUT exists only silicon revision 1.2. Four pins silicon revision 1.2, because RSTOUT been added.
Table Clock Rate Ratios CLKDBL CLK_CFG1 CLK_CFG0 Core:CLKIN CLKIN:CLKOUT
BOOT MODES
Table Boot Mode Selection EBOOT LBOOT Booting Mode
Output (Input) (Input) (Input) (Input) (Input)
EPROM (Connect EPROM chip select.) Host Processor Serial Boot Link Port Booting. Processor executes from external memory. Reserved
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ADSP-21161N
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter Test Conditions Grade Grade Unit
VDDINT AVDD VDDEXT TCASE
Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage1 VDDEXT Level Input Voltage1 VDDEXT Case Operating Temperature2
1.71 1.71 3.13 -0.5
1.89 1.89 3.47 VDDEXT +0.5 +0.8 +105
1.71 1.71 3.13 -0.5
1.89 1.89 3.47 VDDEXT +0.5 +0.8
Specifications subject change without notice. Applies input bidirectional pins: DATA47-16, ADDR23-0, MS3-0, ACK, SBTS, IRQ2-0, FLAG11-0, HBG, HBR, DMAR1, DMAR2, BR6-1, ID2-0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7-0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, CLKIN, RESET, TRST, TCK, TMS, TDI. Thermal Characteristics Page information thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions
Unit
IIHC IILC IIKH IIKL IIKH-OD IIKL-OD IILPU IOZH IOZL IOZLPU1 IOZLPU2 IOZHPD1 IOZHPD2 IDD-INPEAK IDD-INHIGH IDD-INLOW IDD-IDLE AIDD
High Level Output Voltage Level Output Voltage1 High Level Input Current3, Level Input Current3 CLKIN High Level Input Current5 CLKIN Level Input Current5 Keeper High Load Current6 Keeper Load Current6 Keeper High Overdrive Current6, Keeper Overdrive Current6, Level Input Current Pull-Up4 Three-State Leakage Current9, Three-State Leakage Current9, Three-State Leakage Current Pull-Up110 Three-State Leakage Current Pull-Up211 Three-State Leakage Current Pull-Down112 Three-State Leakage Current Pull-Down213 Supply Current (Internal)14, Supply Current (Internal)15, Supply Current (Internal)15, Supply Current (Idle)15, Supply Current (Analog)19 Input Capacitance20,
VDDEXT min, -2.0 VDDEXT min, VDDEXT max, VDDEXT VDDEXT max, VDDEXT max, VDDEXT VDDEXT max, VDDEXT max, VDDEXT max, VDDEXT VDDEXT VDDEXT max, VDDEXT= max, VDDEXT VDDEXT max, VDDEXT max, VDDEXT max, VDDEXT max, VDDEXT VDDEXT max, VDDEXT tCCLK 10.0 VDDINT tCCLK 10.0 VDDINT tCCLK 10.0 VDDINT tCCLK 10.0 VDDINT AVDD MHz, TCASE 25°C,
-100
-250 -300
Specifications subject change without notice. Applies output bidirectional pins: DATA47-16, ADDR23-0, MS3-0, ACK, DQM, FLAG11-0, HBG, REDY, DMAG1, DMAG2, BR6-1, BMSTR, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7-0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS, SDCLKx, SDCKE, EMU, XTAL, TDO, CLKOUT, TIMEXP, RSTOUT. Output Drive Currents Page typical drive current capabilities. Applies input pins: DATA47-16, ADDR23-0, MS3-0, SBTS, IRQ2-0, FLAG11-0, HBG, HBR, BR6-1, ID2-0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7-0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, TCK, RESET, CLKIN. Applies input pins with internal pull-ups: ACK, DMAR1, DMAR2, TRST, TMS, TDI. Applies CLKIN only. Applies pins with keeper latches: ADDR23-0, DATA47-0, MS3-0, BRST, CLKOUT. Current required switch from kept high from kept high. Characterized, tested.
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Applies three-statable pins: DATA47-16, ADDR23-0, MS3-0, CLKOUT, FLAG11-0, REDY, HBG, BMS, BR6-1, RAS, CAS, SDWE, DQM, SDCLKx, SDCKE, SDA10, BRST. Applies three-statable pins with pull-ups: DMAG1, DMAG2, Applies three-statable pins with internal pull-ups: DxA, DxB, SCLKx, SPICLK., EMU, MISO, MOSI Applies three-statable pins with internal pull-downs: LxDAT7-0 (below Revision1.2), LxCLK, LxACK. IOZHPD2 Rev. higher. Applies three-statable pins with internal pull-downs: LxDAT7-0 (Revision higher). test program used measure IDDINPEAK represents worst-case processor operation sustainable under normal application conditions. Actual internal power measurements made using typical applications less than specified. more information, "Power Dissipation" Page Current numbers VDDINT AVDD supplies combined. IDDINHIGH composite average based range high activity code. Power Dissipation Page IDDINLOW composite average based range activity code. Power Dissipation Page Idle denotes ADSP-21161N state during execution IDLE instruction. Power Dissipation Page Characterized, tested. Applies signal pins. Guaranteed, tested.
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage (VDDINT)1 -0.3 +2.2 Analog (PLL) Supply Voltage (AVDD)1 -0.3 +2.2 External (I/O) Supply Voltage (VDDEXT)1 -0.3 +4.6 Input Voltage1 -0.5 VDDEXT Output Voltage Swing1 -0.5 VDDEXT Load Capacitance1 .200 Storage Temperature Range1 .-65°C +150°C
Stresses greater than those listed above cause permanent damage device. These stress ratings only; functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
SENSITIVITY
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although ADSP-21161N features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
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ADSP-21161N TIMING SPECIFICATIONS
ADSP-21161N's internal clock switches higher frequencies than system input clock (CLKIN). generate internal clock, uses internal phase-locked loop (PLL). This PLL-based clocking minimizes skew between system clock (CLKIN) signal DSP's internal clock (the clock source external port logic pads). ADSP-21161N's internal clock multiple CLKIN) provides clock signal timing internal memory, processor core, link ports, serial ports, external port required read/write strobes asynchronous access mode). During reset, program ratio between DSP's internal clock frequency external (CLKIN) clock frequency with CLK_CFG1-0
Table CLKOUT CCLK Clock Generation Operation Timing Requirements Description1 Calculation
CLKDBL pins. Even though internal clock clock source external port, behaves described Clock Rate Ratio chart Table Page determine switching frequencies serial link ports, divide down internal clock, using programmable divider control each port (DIVx serial ports LxCLKD link ports). Note following definitions various clock periods that function CLKIN appropriate ratio control. Figure enables Core-to-CLKIN ratios 2:1, 3:1, 4:1, 6:1, with external oscillator crystal. also shows support CLKOUT-to-CLKIN ratios 2:1.
CLKIN CLKOUT PLLICLK CCLK tCCLK tLCLK tSCLK tSDK tSPICLK
Input Clock External Port System Clock Input Clock Core Clock CLKIN Clock Period (Processor) Core Clock Period Link Port Clock Period Serial Port Clock Period SDRAM Clock Period Clock Period
1/tCK 1/tCKOP 1/tPLLIN 1/tCCLK 1/CLKIN 1/CCLK (tCCLK) (tCCLK) (tCCLK) SDCKR (tCCLK) SPIR
where: link port-to-core clock ratio 1:4, determined LxCLKD) serial port-to-core clock ratio (wide range, determined CLKDIV) SDCKR SDRAM-to-Core Clock Ratio (1:1 1:2, determined SDCTL register) SPIR SPI-to-Core Clock Ratio (wide range, determined SPICTL register) LCLK Link Port Clock SCLK Serial Port Clock SDRAM Clock SPICLK Clock
SYNCHRONOUS MULTIPROCESSING SBSRAM
ASYNCHRONOUS HOST SRAM
PLLICLK (4.2-50MHz)
HARDWARE INTERRUPT FLAG TIMER
CCLK (33.3-100MHz)
CORE PROCESSOR
LINK PORTS 1/2, 1/3,
CLKIN (CRYSTAL OSCILLATOR 4.2-50MHz) CLOCK DOUBLER XTAL (QUARTZ CRYSTAL 25MHz MAX) CLKDBL
SDRAM
RATIOS
SERIAL PORTS
CLKOUT
CLK_CFG1-0
Figure Core Clock System Clock Relationship CLKIN
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exact timing information given. attempt derive parameters from addition subtraction others. While addition subtraction would yield meaningful results individual device, values given this data sheet reflect statistical variations worst cases. Consequently, meaningful parameters derive longer times. Figure Page under Test Conditions voltage reference levels. Switching characteristics specify processor changes signals. Circuitry external processor must designed compatibility with these signal characteristics. Switching characteristics describe what processor will given circumstance. switching characteristics ensure that timing requirement device connected processor (such memory) satisfied. Timing requirements apply signals that controlled circuitry external processor, such data input read operation. Timing requirements guarantee that processor operates correctly with other devices.
Table Operation Types Versus Input Current Operation Peak Activity1 (IDDINPEAK) High Activity1 (IDDINHIGH) Activity1 (IDDINLOW) Power Dissipation
Total power dissipation components: internal circuitry switching external output drivers. Internal power dissipation depends instruction execution sequence data operands involved. Using current specifications (IDDINPEAK, IDDINHIGH, IDDINLOW, IDDIDLE) from Electrical Characteristics Page current-versusoperation information Table programmer estimate ADSP-21161N's internal power supply (VDDINT) input current specific application, according following formula:
Peak DDINPEAK High DDINHIGH DDINLOW Idle DDIDLE DDINT
Instruction Type Instruction Fetch Core Memory Access2 Internal Memory External Memory Data pattern core memory access
Multifunction Cache cycle tCCLK cycles external port cycle Worst case
Multifunction Internal Memory cycle tCCLK cycles external port cycle Random
Single Function Internal Memory None
state PEYEN (SIMD versus SISD mode) does influence these calculations. These assume core clock ratio. more information ratios clocks (tCK tCCLK), timing ratio definitions Page
external component total power dissipation caused switching output pins. magnitude depends number output pins that switch during each cycle maximum frequency which they switch Their load capacitance Their voltage swing (VDD) calculated
External Data Memory writes occur every cycle rate 1/tCK with pins switching cycle time external SDRAM clock rate Ignoring SDRAM refresh cycles Addresses incremental same page PEXT equation calculated each class pins that drive, shown Table typical power consumption calculated these conditions adding typical internal power dissipation:
TOTAL
load capacitance should include processor package capacitance (CIN). switching frequency includes driving load high then back low. maximum rate 1/tCK, address data pins drive high low, while writing SDRAM memory. Example: Estimate PEXT with following assumptions: system with bank external memory bit) SDRAM chips used, each with load (ignoring trace capacitance)
Where: PEXT from Table PINT IDDINT using calculation IDDINT listed Power Dissipation Page PPLL AIDD using value AIDD listed Electrical Characteristics Page
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ADSP-21161N
Table External Power Calculations (3.3 Device) Type Number Pins Switching VDD2 PEXT
Address SDWE Data SDCLK0
24.7 24.7 24.7 14.7 24.7
10.9 10.9 10.9 10.9 10.9
0.030 0.000 0.000 0.128 0.027 PEXT 0.185
Note that conditions causing worst-case PEXT different from those causing worst-case PINT. Maximum PINT cannot occur while 100% output pins switching from ones zeros. Note also that common application have 100% even outputs switching simultaneously.
Power-Up Sequencing Silicon Revision 0.3, 1.0,
timing requirements startup silicon revision 0.3, 1.0, given Table
Table Power-Up Sequencing Revisions 0.3, 1.0, (DSP Startup) Parameter Unit
Timing Requirements tRSTVDD tVDDRAMP tIVDDEVDD tCLKVDD tVDDRST tCLKRST tPLLRST
RESET Before VDDINT/VDDEXT VDDINT/VDDEXT Voltage Ramp Rate1 VDDINT Before VDDEXT CLKIN Valid After VDDINT/VDDEXT Valid VDDINT/VDDEXT Valid Before RESET Deasserted2 CLKIN Valid Before RESET Deasserted3 Control Setup Before RESET Deasserted
0.0009
+200
V/µs
minimum V/ms based slowest allowable ramp-up time VDDINT ramp from volts volts (3.6 VDDEXT ramp from volts volts. minimum time assumes that VDDINT VDDEXT power supplies valid. VDDINT VDDEXT supplies must fully ramped their volt rails before RESET deasserted. minimum assumes stable CLKIN signal after meeting worst-case start-up timing crystal oscillator circuits. Refer crystal oscillator manufacturer's data sheet start-up time. maximum oscillator start-up time assumed using XTAL internal oscillator circuit conjunction with external crystal. minimum time required reliably lock valid (stable) CLKIN frequency.
RESET
tRSTVDD
VDDINT
tVDDRST
tVDDRAMP tVDDRAMP
VDDEXT
tIVDDEVDD tCLKVDD
CLKIN
tCLKRST
CLKDBL CLK_CFG1-0
tPLLRST
Figure Power-Up Sequencing Revisions 0.3, 1.0, (DSP Startup)
-22-
REV.
ADSP-21161N
Power-Up Sequencing Silicon Revision
timing requirements startup silicon with revision given Table
Table Power-Up Sequencing Revision (DSP Startup) Parameter Unit
Timing Requirements tRSTVDD RESET Before VDDINT/VDDEXT tIVDDEVDD VDDINT Before VDDEXT CLKIN Valid After VDDINT/VDDEXT Valid1 tCLKVDD tCLKRST CLKIN Valid Before RESET Deasserted2 tPLLRST Control Setup Before RESET Deasserted3 tWRST Subsequent RESET Pulsewidth4 Switching Requirements tCORERST core reset deasserted after RESET deasserted
4tCK 4080tCK3,
+200
Valid VDDINT/VDDEXT assumes that supplies fully ramped their volt rails. Voltage ramp rates vary from microseconds hundreds milliseconds depending design power supply subsystem. Assumes stable CLKIN signal, after meeting worst-case start-up timing crystal oscillators. Refer crystal oscillator manufacturer's data sheet start-up time. Assume maximum oscillator start-up time using XTAL internal oscillator circuit conjunction with external crystal. Based CLKIN cycles Applies after power-up sequence complete. Subsequent resets require minimum CLKIN cycles RESET held order properly initialize propagate default states pins. 4080 cycle count depends tSRST specification Table setup time met, additional CLKIN cycle added core reset time, resulting 4081 cycles maximum.
RSTOUT does currently exist ADSP-21161N revisions 0.3, 1.0, 1.1. This signal will placed current no-connect pins: ball B15.
RESET
tRSTVDD
VDDINT
tIVDDEVDD
VDDEXT
tCLKRST tCLKVDD
CLKIN
CLKDBL CLK_CFG1-0
tPLLRST
RSTOUT
tCORERST
Figure Power-Up Sequencing Revision (DSP Startup)
During power-up sequence DSP, differences ramp-up rates activation time between supplies cause current flow protection circuitry. prevent damage diode protection circuitry, Analog Devices recommends including bootstrap Schottky diode.
bootstrap Schottky diode connected between power supplies shown Figure protects ADSP-21161N from partially powering supply. Including Schottky diode will shorten delay between supply ramps thus prevent damage diode
REV.
-23-
ADSP-21161N
protection circuitry. With this technique, rail rises ahead rail, Schottky diode pulls rail along with rail.
Clock Input
INPUT SOURCE 3.3V VOLTAGE REGULATOR VDDEXT
ADSP-21161N
systems that multiprocessing SBSRAM, CLKDBL cannot enabled systems external crystal CLKIN source. CLKOUT clock source SBSRAM device. Using external crystal conjunction with CLKDBL generate CLKOUT frequency supported. Negative hold times result from potential skew between CLKIN CLKOUT.
Table Clock Input
1.8V CORE VOLTAGE REGULATOR
VDDINT
Figure Dual Voltage Schottky Diode
Parameter Unit
Timing Requirements CLKIN Period1 tCKL CLKIN Width Low1 tCKH CLKIN Width High1 CLKIN Rise/Fall (0.4 V-2.0 tCKRF tCCLK CCLK Period Switching Characteristics tDCKOO CLKOUT Delay After CLKIN tCKOP CLKOUT Period tCKWH CLKOUT Width High tCKWL CLKOUT Width
tCKOP tCKOP/2-2 tCKOP/2-2
tCKOP tCKOP/2+2 tCKOP/2+2
CLKIN dependent configuration CLKCFGx CLKDBL pins achieve desired tCCLK.
CLKIN
necessary components CLKIN XTAL. Figure shows component connections used crystal operating fundamental mode.
tCKH tDCKOO
tCKL tCKOP1
CLKIN XTAL
tCKWH1
CLKOUT
tCKWL1
27pF 27pF
tDCKOO2 tDCKOO2 tCKWH
CLKOUT NOTES: WHEN CLKDBL DISABLED, SPECIFICATION CLKIN APPLIES RISING EDGE, ONLY. WHEN CLKDBL ENABLED, SPECIFICATION CLKIN APPLIES RISING FALLING EDGE.
tCKOP2 tCKWL2
SUGGESTED COMPONENTS 100MHz OPERATION: ECLIPTEK EC2SM-25.000M (SURFACE MOUNT PACKAGE) ECLIPTEK EC-25.000M (THROUGH-HOLE PACKAGE) 27pF 27pF NOTE: SPECIFIC CRYSTAL SPECIFIED CONTACT CRYSTAL MANUFACTURER DETAILS. THIS 25MHz CRYSTAL GENERATES 100MHz CCLK 50MHz CLOCK WITH CLKDBL ENABLED MULTIPLY RATIO.
Figure Clock Input Clock Signals Figure Operation (Fundamental Mode Crystal)
ADSP-21161N external clock crystal. CLKIN description. programmer configure ADSP-21161N internal clock generator connecting
-24-
REV.
ADSP-21161N
Reset Table Reset Parameter Unit
Timing Requirements RESET Pulsewidth Low1 tWRST tSRST RESET Setup Before CLKIN High2
4tCK
Applies after power-up sequence complete. Only required multiple ADSP-21161Ns must come reset synchronous CLKIN with program counters (PC) equal. required multiple ADSP-21161Ns communicating over shared (through external port), because arbitration logic synchronizes itself automatically after reset.
CLKIN
tWRST
RESET
tSRST
Figure Reset Interrupts Table Interrupts Parameter Unit
Timing Requirements tSIR IRQ2-0 Setup Before CLKIN1 tHIR IRQ2-0 Hold After CLKIN1 tIPW IRQ2-0 Pulsewidth2
tCKOP
Only required IRQx recognition following cycle. Applies only tSIR tHIR requirements met.
CLKIN
tSIR
tHIR
IRQ2-0
tIPW
Figure Interrupts
REV.
-25-
ADSP-21161N
Timer Table Timer Parameter Unit
Switching Characteristic tDTEX CLKIN TIMEXP
CLKIN
tDTEX
TIMEXP
tDTEX
Figure Timer Flags Table Flags Parameter Unit
Timing Requirement FLAG11-0IN Setup Before CLKIN1 tSFI tHFI FLAG11-0IN Hold After CLKIN1 tDWRFI FLAG11-0IN Delay After RD/WR Low1 tHFIWR FLAG11-0IN Hold After RD/WR Deasserted1 Switching Characteristics tDFO FLAG11-0OUT Delay After CLKIN tHFO FLAG11-0OUT Hold After CLKIN CLKIN FLAG11-0OUT Enable tDFOE tDFOD CLKIN FLAG11-0OUT Disable
Flag inputs meeting these setup hold times instruction cycle will affect conditional instructions instruction cycle N+2.
CLKIN
tDFOE
tDFO tHFO
tDFO
tDFOD
FLAG11-0OUT FLAG OUTPUT
CLKIN
tSFI
FLAG11-0IN
tHFI
tDWRFI
FLAG INPUT
tHFIWR
Figure Flags
-26-
REV.
ADSP-21161N
Memory Read Master
these specifications asynchronous interfacing memories (and memory-mapped peripherals) without reference CLKIN. These specifications apply when ADSP-21161N master accessing external memory space asynchronous access mode.
Table Memory Read Master Parameter Unit
Timing Requirements tDAD Address, Selects Delay Data Valid1, tDRLD Data Valid1 tHDA Data Hold from Address, Selects3 tSDS Data Setup High tHDRH Data Hold from High3 tDAAK Delay from Address, Selects2, tDSAK Delay from Low4 tSAKC Setup CLKIN4 tHAKC Hold After CLKIN
0.5tCCLK+3
tCKOP -0.25tCCLK -11+W 0.75tCKOP -11+W tCKOP -0.5tCCLK -12+W tCKOP -0.75tCCLK -11+W
Switching Characteristics tDRHA Address Selects Hold After High 0.25tCCLK-1+H tDARL Address Selects Low2 0.25tCCLK Pulsewidth tCKOP-0.5tCCLK -1+W tRWR High DMAGx 0.5tCCLK -1+HI (number wait states specified WAIT register) tCKOP. tCKOP address hold cycle idle cycle occurs, specified WAIT register; otherwise tCKOP address hold cycle occurs specified WAIT register; otherwise
Data Delay/Setup: User must meet tDAD, tDRLD, tSDS. falling edge MSx, referenced. Data Hold: User must meet tHDA tHDRH asynchronous access mode. Example System Hold Time Calculation Page calculation hold times given capacitive loads. Delay/Setup: User must meet tDAAK, tDSAK, tSAKC deassertion (Low); three specifications must assertion (High).
tHDA
ADDRESS MSx,
tDARL
tDRHA
tDRLD tDAD
DATA
tSDS tHDRH
tDSAK tDAAK
tRWR
tSAKC
CLKIN
tHAKC
DMAG
Figure Memory Read Master
REV.
-27-
ADSP-21161N
Memory Write Master
these specifications asynchronous interfacing memories (and memory-mapped peripherals) without reference CLKIN. These specifications apply when ADSP-21161N master accessing external memory space asynchronous access mode.
Table Memory Write Master Parameter Unit
Timing Requirements Delay from Address, Selects1, tDAAK tDSAK Delay from Low1 Setup CLKIN1 tSAKC tHAKC Hold After CLKIN1
tCKOP-0.5tCCLK-12+W tCKOP-0.75tCCLK-11+W 0.5tCCLK
Switching Characteristics tDAWH Address, Selects Deasserted2 tCKOP 0.25tCCLK Address, Selects Low2 0.25tCCLK tDAWL Pulsewidth tCKOP 0.5tCCLK tDDWH Data Setup Before High tCKOP -0.25tCCLK 13.5+W tDWHA Address Hold After Deasserted 0.25tCCLK tDWHD Data Hold After Deasserted 0.25tCCLK tDATRWH Data Disable After Deasserted3 0.25tCCLK 0.25tCCLK+2.5+H High DMAGx 0.5tCCLK 1.25+HI tWWR tDDWR Data Disable Before 0.25tCCLK tWDE Data Enabled -0.25tCCLK (number wait states specified WAIT register) tCKOP. tCKOP address hold cycle occurs, specified WAIT register; otherwise tCKOP address hold cycle idle cycle occurs, specified WAIT register; otherwise tCKOP idle cycle occurs, specified WAIT register; otherwise
Delay/Setup: User must meet tDAAK tDSAK tSAKC deassertion (Low); three specifications must assertion (High). falling edge MSx, referenced. Example System Hold Time Calculation Page calculation hold times given capacitive loads.
ADDRESS MSx,
tDAWH tDAWL
tDWHA
tWWR tWDE tDDWH tDATRWH tDDWR
DATA
tDSAK tDAAK
tDWHD
tSAKC
CLKIN
tHAKC
DMAG
Figure Memory Write Master
-28-
REV.
ADSP-21161N
Synchronous Read/Write Master
these specifications interfacing external memory systems that require CLKIN, relative timing accessing slave ADSP-21161N multiprocessor memory space). When accessing slave ADSP-21161N, these switching characteristics
Table Synchronous Read/Write Master Parameter
must meet slave's timing requirements synchronous read/writes (see Synchronous Read/Write Slave Page 30). slave ADSP-21161N must also meet these (bus master) timing requirements data acknowledge setup hold times.
Unit
Timing Requirements Data Setup Before CLKIN tSSDATI tHSDATI Data Hold After CLKIN tSACKC Setup Before CLKIN tHACKC Hold After CLKIN Switching Characteristics tDADDO Address, MSx, BMS, BRST, Delay After CLKIN tHADDO Address, MSx, BMS, BRST, Hold After CLKIN High Delay After CLKIN tDRDO tDWRO High Delay After CLKIN tDRWL RD/WR Delay After CLKIN tDDATO Data Delay After CLKIN tHDATO Data Hold After CLKIN
0.5tCCLK+3 0.25tCCLK-1 0.25tCCLK-1 0.25tCCLK-1 0.25tCCLK+9 0.25tCCLK+9 0.25tCCLK+9 12.5
CLKIN
tDADDO
ADDRESS MSx, BRST
tHADDO
tSACKC
(IN)
tHACKC
READ CYCLE
tDRWL
tDRDO
tSSDATI
DATA (IN)
tHSDATI
WRITE CYCLE
tDRWL
tDWRO
tDDATO
DATA (OUT)
tHDATO
Figure Synchronous Read/Write Master
REV.
-29-
ADSP-21161N
Synchronous Read/Write Slave
these specifications ADSP-21161N master accesses slave's registers multiprocessor memory space. master must meet these (bus slave) timing requirements.
Table Synchronous Read/Write Slave Parameter Unit
Timing Requirements tSADDI Address, BRST Setup Before CLKIN Address, BRST Hold After CLKIN tHADDI tSRWI RD/WR Setup Before CLKIN tHRWI RD/WR Hold After CLKIN Data Setup Before CLKIN tSSDATI Data Hold After CLKIN tHSDATI Switching Characteristics tDDATO Data Delay After CLKIN tHDATO Data Hold After CLKIN tDACKC Delay After CLKIN Hold After CLKIN tHACKO
12.5
CLKIN
tSADDI
ADDRESS
tHADDI
tDACKC
tHACKO
READ ACCESS
tSRWI
tHRWI
tDDATO
DATA (OUT) WRITE ACCESS
tHDATO
tSRWI
tHRWI
tSSDATI
DATA (IN)
tHSDATI
Figure Synchronous Read/Write Slave
-30-
REV.
ADSP-21161N
Host Request
these specifications asynchronous host requests ADSP-21161N (HBR, HBG).
Table Host Request Parameter Unit
Timing Requirements tHBGRCSV RD/WR/CS Valid tSHBRI Setup Before CLKIN1 Hold After CLKIN1 tHHBRI tSHBGI Setup Before CLKIN tHHBGI Hold After CLKIN
Switching Characteristics tDHBGO Delay After CLKIN tHHBGO Hold After CLKIN tDRDYCS REDY (O/D) (A/D) from Low2 REDY (O/D) Disable REDY (A/D) High from HBG2 tCKOP+14 tTRDYHG tARDYTR REDY (A/D) Disable from High2
Only required recognition current cycle. (O/D) open drain, (A/D) active drive.
CLKIN
(OUT)
(IN)
REDY (O/D)
REDY (A/D)
(OUT) OPEN DRAIN, ACTIVE DRIVE
Figure Host Request
REV.
-31-
ADSP-21161N
Multiprocessor Request
these specifications passing mastership between multiprocessing ADSP-21161Ns (BRx).
Table Multiprocessor Request Parameter Unit
Timing Requirements BRx, Setup Before CLKIN High tSBRI tHBRI BRx, Hold After CLKIN High tSPAI Setup Before CLKIN High Hold After CLKIN High tHPAI tSRPBAI RPBA Setup Before CLKIN High tHRPBAI RPBA Hold After CLKIN High Switching Characteristics Delay After CLKIN High tDBRO Hold After CLKIN High tHBRO tDPASO Delay After CLKIN High, Slave tTRPAS Disable After CLKIN High, Slave tDPAMO Delay After CLKIN High, Master Disable Before CLKIN High, Master tPATR
0.25tCCLK+9 0.25tCCLK-5
CLKIN
(OUT)
(OUT) (SLAVE)
(OUT) (MASTER)
(IN)
(IN) (O/D)
RPBA
OPEN DRAIN
Figure Multiprocessor Request
-32-
REV.
ADSP-21161N
Asynchronous Read/Write Host ADSP-21161N
these specifications asynchronous host processor accesses ADSP-21161N, after host asserted (low). After returned ADSP-21161N, host drive pins access ADSP-21161N's registers. assumed this timing.
Table Read Cycle Parameter
Although will recognize asserted before reset, will returned until after reset deasserted completes synchronization. Note: Host internal memory access supported.
Unit
Timing Requirements tSADRDL Address Setup Before tHADRDH Address Hold Hold After RD/WR High Width tWRWH tDRDHRDY High Delay After REDY (O/D) Disable tDRDHRDY High Delay After REDY (A/D) Disable Switching Characteristics tSDATRDY Data Valid Before REDY Disable from tDRDYRDL REDY (O/D) (A/D) Delay After tRDYPRD REDY (O/D) (A/D) Pulsewidth Read Data Disable After High tHDARWH
Table Write Cycle Parameter
1.5tCCLK
Unit
Timing Requirements tSCSWRL Setup Before tHCSWRH Hold After High tSADWRH Address Setup Before High Address Hold After High tHADWRH tWWRL Width tWRWH RD/WR High Width tDWRHRDY High Delay After REDY (O/D) (A/D) Disable tSDATWH Data Setup Before High tHDATWH Data Hold After High Switching Characteristics REDY (O/D) (A/D) Delay After WR/CS Low1 tDRDYWRL REDY (O/D) (A/D) Pulsewidth Write1 tRDYPWR
tCCLK+1
Only when slave write FIFO full.
REV.
-33-
ADSP-21161N
READ CYCLE
ADDRESS/CS
tSADRDL
tHADRDH tWRWH
tHDARW
DATA (OUT)
tDRDY
REDY (O/D)
tDRDHRDY tRDYPRD
REDY (A/D)
WRITE CYCLE
ADDRESS
tSCS
tHADW tHCSWRH
WWRL
tSDATWH
DATA (IN)
tHDATWH
tDRDY
REDY (O/D)
tRDYPW
tDWRHRDY
REDY (A/D)
OPEN DRAIN, ACTIVE DRIVE
Figure Asynchronous Read/Write Host ADSP-21161N
-34-
REV.
ADSP-21161N
Three-State Timing Master, Slave
These specifications show memory interface disabled (stops driving) enabled (resumes driving) relative CLKIN SBTS pin. This timing applicable master transition cycles (BTC) host transition cycles (HTC) well SBTS pin.
Table Three-State Timing Master, Slave Parameter
During reset, will respond SBTS, HBR, accesses. Although will recognize asserted before reset, will returned until after reset deasserted completes synchronization.
Unit
Timing Requirements tSTSCK SBTS Setup Before CLKIN tHTSCK SBTS Hold After CLKIN Switching Characteristics Address/Select Enable After CLKIN High tMIENA tMIENS Strobes Enable After CLKIN High1 tMIENHG Enable After CLKIN tMITRA Address/Select Disable After CLKIN High tMITRS Strobes Disable After CLKIN High tMITRHG Disable After CLKIN2 Data Enable After CLKIN3 tDATEN tDATTR Data Disable After CLKIN3 tACKEN Enable After CLKIN High tACKTR Disable After CLKIN High tCDCEN CLKOUT Enable After CLKIN2 tCDCTR CLKOUT Disable After CLKIN Address/Select Disable Before Low4 tATRHBG tSTRHBG RD/WR/DMAGx Disable Before Low4 tBTRHBG Disable Before Low4 tMENHBG Memory Interface Enable After High4
-1.5 -0.5tCKOP-20 tCKOP- 0.25tCCLK-17 tCKOP-5 1.5tCKOP-6 tCKOP+ 0.25tCCLK-4 0.5tCKOP-4 tCKOP-5 -0.5tCKOP-15 tCKOP- 0.25tCCLK-12.5 tCKOP 1.5tCKOP+2 tCKOP+ 0.25tCCLK+3 0.5tCKOP+2 tCKOP+5
Strobes DMAGx. Where 0.5, 1.0, 1:2, 1:3, 1:4, respectively. addition master transition cycles, these specs also apply master slave synchronous read/write. Memory Interface Address, MSx, DMAGx, EPROM boot mode). only output EPROM boot mode.
REV.
-35-
ADSP-21161N
CLKIN
tSTSCK tHTSCK
SBTS
tMIENA, tMIENS, tMIENHG
MEMORY INTERFACE
tMITRA, tMITRS, tMITRHG
tDATEN
DATA
tDATTR
tACKEN
tACKTR
CLKIN
tCDCEN
CLKOUT
tCDCTR
tMENHBG
MEMORY INTERFACE MEMORY INTERFACE ADDRESS, MSx, DMAGx, EPROM MODE)
tATRHBG, tSTRHBG, tBTRHBG
Figure Three-State Timing Master, Slave
-36-
REV.
ADSP-21161N
Handshake
These specifications describe three handshake modes. three modes DMAR used initiate transfers. handshake mode, DMAG controls latching enabling data externally. external handshake mode, data transfer controlled ADDR23-0, MS3-0, ACK,
Table Handshake Parameter
DMAG signals. Paced Master mode, data transfer controlled ADDR23-0, MS3-0, (not DMAG). Paced Master mode, Memory Read-Bus Master, Memory Write-Bus Master, Synchronous Read/Write-Bus Master timing specifications ADDR23-0, MS3-0, DATA47-16, also apply.
Unit
Timing Requirements tSDRC DMARx Setup Before CLKIN1 tWDR DMARx Width (Nonsynchronous)2 tSDATDGL Data Setup After DMAGx Low3 tHDATIDG Data Hold After DMAGx High Data Valid After DMARx High3 tDATDRH tDMARLL DMARx Edge Edge4 tDMARH DMARx Width High2
tCCLK +4.5 tCKOP 0.5tCCLK tCKOP tCKOP tCCLK +4.5 0.25tCCLK
Switching Characteristics tDDGL DMAGx Delay After CLKIN 0.25tCCLK tWDGH DMAGx High Width 0.5tCCLK 1+HI tWDGL DMAGx Width tCKOP 0.5tCCLK DMAGx High Delay After CLKIN tCKOP 0.25tCCLK +1.0 tHDGC tVDATDGH Data Valid Before DMAGx High5 tCKOP 0.25tCCLK tDATRDGH Data Disable After DMAGx High6 0.25tCCLK tDGWRL Before DMAGx -1.5 tDGWRH DMAGx Before High tCKOP 0.5tCCLK tDGWRR High Before DMAGx High7 -1.5 Before DMAGx -1.5 tDGRDL tDRDGH Before DMAGx High tCKOP 0.5tCCLK -2+W tDGRDR High Before DMAGx High7 -1.5 tDGWR DMAGx High WRx, 0.5tCCLK 2+HI tDADGH Address/Select Valid DMAGx High tDDGHA Address/Select Hold After DMAGx High (number wait states specified WAIT register) tCKOP. tCKOP data idle cycle occurs, specified WAIT register; otherwise
tCKOP 0.25tCCLK tCKOP 0.25tCCLK 0.25tCCLK
Only required recognition current cycle. Maximum throughput using DMARx/DMAGx handshaking equals tWDR tDMARH (tCCLK +4.5) (tCCLK +4.5)=29 (34.5 MHz). This throughput limit applies non-synchronous access mode only. tSDATDGL data setup requirement DMARx being used hold completion write. Otherwise, DMARx holds completion write, data driven tDATDRH after DMARx brought high. tDMARLL DMARx transitions synchronous with CLKIN. Otherwise, tWDR tDMARH. tVDATDGH valid DMARx being used hold completion read. DMARx used prolong read, then tVDATDGH tCKOP 0.25tCCLK tCKOP) where equals number extra cycles that access prolonged. Example System Hold Time Calculation Page calculation hold times given capacitive loads. This parameter applies synchronous access mode only.
REV.
-37-
ADSP-21161N
CLKIN
tDMARLL tSDRC tWDR
DMARx
tSDRC tDMARH
tHDGC tDDGL
DMAGx
tWDGL
tWDGH
TRANSFERS BETWEEN ADSP-21161N INTERNAL MEMORY EXTERNAL DEVICE
tVDATDGH
tDATRDGH
DATA (FROM ADSP-2116x EXTERNAL DRIVE)
tDATDRH tSDATDGL
DATA (FROM EXTERNAL DRIVE ADSP-21161N)
tHDATIDG
TRANSFERS BETWEEN EXTERNAL DEVICE EXTERNAL MEMORY1 (EXTERNAL HANDSHAKE MODE)
tDGWRL
(EXTERNAL DEVICE EXTERNAL MEMORY)
tDGWRH
tDGWRR
tDGWR
tDGRDL
(EXTERNAL MEMORY EXTERNAL DEVICE)
tDGRDR
tDRDGH tDADGH
ADDRESS
1MEMORY
tDDGHA
READ MASTER, MEMORY WRITE MASTER, SYNCHRONOUS READ/WRITE MASTER TIMING SPECIFICATIONS ADDR23-0, MS3-0 ALSO APPLY HERE.
Figure Handshake
-38-
REV.
ADSP-21161N
SDRAM Interface Master
these specifications ADSP-21161N master accesses SDRAM:
Table SDRAM Interface Master Parameter Unit
Timing Requirements Data Setup Before SDCLK tSDSDK tHDSDK Data Hold After SDCLK Switching Characteristics tDSDK1 First SDCLK Rise Delay After CLKIN1, tSDK SDCLK Period tSDKH SDCLK Width High SDCLK Width tSDKL tDCADSDK Command, Address, Data, Delay After SDCLK3 tHCADSDK Command, Address, Data, Hold After SDCLK3 Data Three-State After SDCLK4 tSDTRSDK tSDENSDK Data Enable After SDCLK5 tSDCTR Command Three-State After CLKIN tSDCEN Command Enable After CLKIN tSDSDKTR SDCLK Three-State After CLKIN tSDSDKEN SDCLK Enable After CLKIN Address Three-State After CLKIN tSDATR tSDAEN Address Enable After CLKIN
0.75tCCLK tCCLK 0.75tCCLK tCCLK
0.5tCCLK
0.25tCCLK +2.5
0.75tCCLK 0.5tCCLK -1.5 -0.25 tCCLK-5 -0.4
0.5tCCLK -0.25tCCLK +7.2
second, third, fourth rising edges SDCLK delay from CLKIN, appropriate number SDCLK period tDSDK1 tSSDKC1 values, depending upon SDCKR value core clock CLKIN ratio. Subtract tCCLK from result value greater than equal tCCLK. Command SDCKE, MSx, DQM, RAS, CAS, SDA10, SDWE SDRAM Controller adds SDRAM three-stated cycle delay read, followed write. Valid when transitions SDRAM master from SDRAM slave.
SDRAM Interface Slave
These timing requirements allow slave sample master's SDRAM command detect when refresh occurs:
Table SDRAM Interface Slave Parameter Unit
Timing Requirements First SDCLK Rise tSSDKC1 after CLKOUT1, Command Setup tSCSDK before SDCLK4 Command Hold tHCSDK after SDCLK4
SDCK
tCCLK -0.5tCCLK-
SDCKR
tCCLK -0.25tCCLK
second, third, fourth rising edges SDCLK delay from CLKOUT, appropriate number SDCLK period tDSDK1 tSSDKC1 values, depending upon SDCKR value Core clock CLKOUT ratio. SDCKR SDCLK equal core clock frequency SDCKR SDCLK equal half core clock frequency. Subtract tCCLK from result value greater than equal tCCLK. Command SDCKE, RAS, CAS, SDWE.
REV.
-39-
ADSP-21161N
CLKIN
tDSDK1
tSDK
tSDKH
SDCLK
tSDSDK tHDSDK
DATA(IN)
tSDKL
tDCADSDK tSDENSDK
DATA(OUT)
tSDTRSDK tHCADSDK
CMND1ADDR (OUT)
tDCADSDK
tSDCEN
CMND1(OUT)
tHCADSDK
tSDCTR
ADDR (OUT)
tSDAEN
tSDATR
CLKIN
tSDSDKEN
SDCLK
tSDSDKTR
CLKOUT
tSSDKC1
SDCLK (IN)
tSCSDK
CMND2 (IN)
tHCSDK
1COMMAND 2COMMAND
SDCKE, MSx, RAS, CAS, SDWE, DQM, SDA10. SDCKE, RAS, CAS, SDWE.
Figure SDRAM Interface
-40-
REV.
ADSP-21161N
Link Ports
Calculation link receiver data setup hold relative link clock required determine maximum allowable skew that introduced transmission path between LDATA LCLK. Setup skew maximum delay that introduced LDATA relative LCLK, (setup skew tLCLKTWH min- tDLDCH tSLDCL). Hold skew maximum delay that introduced LCLK relative LDATA, (hold skew tLCLKTWL tHLDCH tHLDCL). Calculations made directly from speed specifications
Table Link Ports Receive Parameter
will result unrealistically small skew times because they include multiple tester guardbands. setup hold skew times shown below calculated include only tester guardband. ADSP-21161N Setup Skew ADSP-21161N Hold Skew Note that there two-cycle effect latency between link port enable instruction enabling link port.
Unit
Timing Requirements tSLDCL Data Setup Before LCLK tHLDCL Data Hold After LCLK LCLK Period tLCLKIW tLCLKRWL LCLK Width tLCLKRWH LCLK Width High Switching Characteristics tDLALC LACK Delay After LCLK High1
tLCLK
LACK goes with tDLALC relative rise LCLK after first nibble, does receiver's link buffer about fill.
RECEIVE
tLCLKIW tLCLKRWH
LCLK
tLCLKRWL
tSLDCL
LDAT7-0
tHLDCL
tDLALC
LACK (OUT)
Figure Link Ports-Receive
REV.
-41-
ADSP-21161N
Table Link Ports Transmit Parameter Unit
Timing Requirements tSLACH LACK Setup Before LCLK High tHLACH LACK Hold After LCLK High Switching Characteristics Data Delay After LCLK High tDLDCH tHLDCH Data Hold After LCLK High tLCLKTWL LCLK Width tLCLKTWH LCLK Width High tDLACLK LCLK Delay After LACK High
0.5tLCLK-1.0 0.5tLCLK-1.0 0.5tLCLK+3 0.5tLCLK+1.0 0.5tLCLK+1.0 3tLCLK+11
TRANSMIT
tLCLKTWH
LCLK
tLCLKTWL
LAST NIBBLE/BYTE TRANSMITTED
FIRST NIBBLE/BYTE TRANSMITTED
LCLK INACTIVE (HIGH)
tDLDCH tHLDCH
LDAT7-0
tSLACH
LACK (IN)
tHLACH
tDLACLK
tSLACH REQUIREMENT APPLIES RISING EDGE LCLK ONLY FIRST NIBBLE TRANSMITTED.
Figure Link Ports-Transmit
-42-
REV.
ADSP-21161N
Serial Ports
determine whether communication possible between devices clock speed following specifications must confirmed: frame sync delay frame sync setup hold, data delay data setup hold, SCLK width.
Table Serial Ports External Clock Parameter Unit
Timing Requirements tSFSE Transmit/Receive Setup Before Transmit/Receive SCLK1 Transmit/Receive Hold After Transmit/Receive tHFSE SCLK1 Receive Data Setup Before Receive SCLK1 tSDRE Receive Data Hold After Receive SCLK1 tHDRE tSCLKW SCLKx Width tSCLK SCLKx Period
2tCCLK
Referenced sample edge.
Table Serial Ports Internal Clock Parameter Unit
Timing Requirements tSFSI Setup Time Before SCLK (Transmit/Receive Mode)1 Hold After SCLK (Transmit/Receive Mode)1 tHFSI tSDRI Receive Data Setup Before SCLK1 tHDRI Receive Data Hold After SCLK1
0.5tCCLK+1
Referenced sample edge.
Table Serial Ports External Clock Parameter Unit
Switching Characteristics tDFSE Delay After SCLK (Internally Generated Hold After SCLK (Internally Generated FS)1, tHOFSE tDDTE Transmit Data Delay After SCLK Transmit Data Hold After SCLK tHDTE
Referenced drive edge. SCLK/FS Configured transmit clock/frame sync with DDIR SPCTLx register. SCLK/FS Configured receive clock/frame sync with DDIR SPCTLx register.
Table Serial Ports Internal Clock Parameter Unit
Switching Characteristics tDFSI Delay After SCLK (Internally Generated FS)1, tHOFSI Hold After SCLK (Internally Generated FS)1, Transmit Data Delay After SCLK1, tDDTI tHDTI Transmit Data Hold After SCLK1, SCLK Width2 tSCLKIW
-1.5 0.5tSCLK-2.5 0.5tSCLK+2
Referenced drive edge. SCLK/FS Configured transmit clock/frame sync with DDIR SPCTLx register. SCLK/FS Configured receive clock/frame sync with DDIR SPCTLx register.
REV.
-43-
ADSP-21161N
Table Serial Ports Enable Three-State Parameter Unit
Switching Characteristics Data Enable from External Transmit SCLK1, tDDTEN tDDTTE Data Disable from External Transmit SCLK1 tDDTIN Data Enable from Internal Transmit SCLK1 tDDTTI Data Disable from Internal Transmit SCLK1
Referenced drive edge. SCLK/FS Configured transmit clock/frame sync with DDIR SPCTLx register.
Table Serial Ports External Late Frame Sync Parameter Unit
Switching Characteristics tDDTLFSE Data Delay from Late External Transmit External Receive with Data Enable from Late tDDTENFS
Transmit enable Transmit valid follow tDDTLFSE tDDTENFS.
-44-
REV.
ADSP-21161N
DATA RECEIVE- INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA RECEIVE- EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
SCLK SCLK
tSCLKW
tDFSI tHOFSI
tDFSE tSFSI tHFSI
tHOFSE
tSFSE
tHFSE
tSDRI
DXA/DXB
tHDRI
DXA/DXB
tSDRE
tHDRE
NOTE: EITHER RISING EDGE FALLING EDGE SCLK (EXTERNAL), SCLK (INTERNAL) USED ACTIVE SAMPLING EDGE.
DATA TRANSMIT INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
SCLK SCLK
tSCLKW
tDFSI tHOFSI
tDFSE tSFSI tHFSI
tHOFSE
tSFSE
tHFSE
tHDTI
DXA/DXB
tDDTI
DXA/DXB
tHDTE
tDDTE
NOTE: EITHER RISING EDGE FALLING EDGE SCLK (EXTERNAL), SCLK (INTERNAL) USED ACTIVE SAMPLING EDGE.
DRIVE EDGE SCLK (EXT) SCLK
DRIVE EDGE
tDDTEN
DXA/DXB DRIVE EDGE SCLK (INT) SCLK
tDDTTE
DRIVE EDGE
tDDTIN
DXA/DXB
tDDTTI
Figure Serial Ports
REV.
-45-
ADSP-21161N
EXTERNAL RECEIVE WITH DRIVE SCLK SAMPLE DRIVE
tSFSE/I
tHOFSE/I
tDDTE/I tDDTENFS
DXA/DXB
tHDTE/I
tDDTLFSE
LATE EXTERNAL TRANSMIT
DRIVE SCLK
SAMPLE
DRIVE
tSFSE/I
tHOFSE/I
tDDTE/I tDDTENFS
DXA/DXB
tHDTE/I
tDDTLFSE
Figure Serial Ports External Late Frame Sync
-46-
REV.
ADSP-21161N
Interface Specifications Table Interface Protocol Master Switching Timing Parameter Unit
Timing Requirements Data Input Valid SPICLK Edge (Data Input Set-up tSSPIDM Time) SPICLK Last Sampling Edge Data Input Valid tHSPIDM tSPITDM Sequential Transfer Delay Switching Characteristics Serial Clock Cycle tSPICLKM Serial Clock High Period tSPICHM tSPICLM Serial Clock Period tDDSPIDM SPICLK Edge Data Valid (Data Delay Time) tHDSPIDM SPICLK Edge Data Valid (Data Hold Time) tSDSCIM_0 FLAG3-0 (SPI Device Select) First SPICLK Edge CPHASE FLAG3-0 (SPI Device Select) First SPICLK Edge tSDSCIM_1 CPHASE Last SPICLK Edge FLAG3-0 High tHDSM
Table Interface Protocol Slave Switching Timing Parameter
0.5tCCLK+10 0.5tCCLK+1 2tCCLK tCCLK 4tCCLK-4 4tCCLK-4 5tCCLK 3tCCLK tCCLK-3
Unit
Timing Requirements tSPICLKS Serial Clock Cycle tSPICHS Serial Clock High Period tSPICLS Serial Clock Period tSDSCO SPIDS Assertion First SPICLK Edge CPHASE CPHASE tHDS Last SPICLK Edge SPIDS Asserted CPHASE Data Input Valid SPICLK Edge (Data Input Set-up Time) tSSPIDS SPICLK Last Sampling Edge Data Input Valid tHSPIDS SPIDS Deassertion Pulsewidth (CPHASE tSDPPW Switching Characteristics tDSOE SPIDS Assertion Data Active tDSDHI SPIDS Deassertion Data High Impedance SPICLK Edge Data Valid (Data Delay Time) tDDSPIDS tHDSPIDS1 SPICLK Edge Data Valid (Data Hold Time) tHDLSBS1 SPICLK Edge Last Valid (Data Hold Time) SPIDS Assertion Data Valid (CPHASE tDSOV2
8tCCLK 4tCCLK-4 4tCCLK-4 3.5tCCLK+8 1.5tCCLK+8 tCCLK+1 tCCLK 0.25tCCLK+3 0.5tSPICLK+4.5tCCLK 1.5tCCLK+7 0.5tCCLK+5.5 0.5tCCLK+5.5 0.75tCCLK+3
When CPHASE baud rate greater than tHDLSBS affects length last transmitted. Applies first deassertion SPIDS only.
REV.
-47-
ADSP-21161N
AG3- UTPUT
tSDSCIM
SPICLK UTPUT
tSPICHM
tSPICLM
tSPICLKM
tHDSM
tSPITDM
tSPICLM
SPIC UTPUT
tSPICHM
tHDSPIDM
MOSI (OUTPUT) CPHASE (INPUT)
VALID
tHSSPIDM
tHSPIDM
MOSI (OUTPUT) CPHASE (INPUT)
tSSPIDM
tHSPIDM
VALID
Figure Interface Protocol Master Switching Timing
-48-
REV.
ADSP-21161N
SPIDS (INPUT)
tSPICHS
SPICLK (INPUT)
tSPICLS
tHDS
tSDPPW
tSDSCO
SPICLK (INPUT)
tDDSPIDS tDSO
MISO (OUTPUT MOSI PUT)
tHDSPIDS
tDSDHI
tSSPIDS
tHSPIDS
tSSPIDS
tDSO tDSO
MISO (OUTPUT MOSI PUT)
tHDLSBS
tDSDHI
VALI
Figure Interface Protocol Slave Switching Timing
REV.
-49-
ADSP-21161N
JTAG Test Access Port Emulation Table JTAG Test Access Port Emulation Parameter Unit
Timing Requirements tTCK Period TDI, Setup Before High tSTAP tHTAP TDI, Hold After High tSSYS System Inputs Setup Before Low1 System Inputs Hold After Low1 tHSYS tTRSTW TRST Pulsewidth Switching Characteristics tDTDO Delay from tDSYS System Outputs Delay After Low2
4tCK
System Inputs DATA47-16, ADDR23-0, ACK, RPBA, SPIDS, EBOOT, LBOOT, DMAR2-1, CLK_CFG1-0, CLKDBL, HBR, SBTS, ID2-0, IRQ2-0, RESET, BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7-0, LxCLK, LxACK, SDWE, HBG, RAS, CAS, SDCLK0, SDCKE, BRST, BR6-1, MS3-0, FLAG11-0. System Outputs BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7-0, LxCLK, LxACK, DATA47-16, SDWE, ACK, HBG, RAS, CAS, SDCLK1-0, SDCKE, BRST, BR6-1, MS3-0, ADDR23-0, FLAG11-0, DMAG2-1, DQM, REDY, CLKOUT, SDA10, TIMEXP, EMU, BMSTR, RSTOUT.
tTCK
tSTAP
tHTAP
tDTDO
tSSYS
SYSTEM INPUTS
tHSYS
tDSYS
SYSTEM OUTPUTS
Figure JTAG Test Access Port Emulation
-50-
REV.
ADSP-21161N
Output Drive Currents
Figure shows typical characteristics output drivers ADSP-21161N. curves represent current drive capability output drivers function output voltage.
REFERENCE SIGNAL
tMEASURED tDIS
VDDEXT 3.47V, -40°C
LOAD (VDDEXT) CURRENT
tENA
(MEASURED) (MEASURED) 2.0V (MEASURED) 1.0V (MEASURED)
(MEASURED) (MEASURED)
VDDEXT 3.3V, +25°C
tDECAY
VDDEXT 3.13V, +105°C
SWEEP (VDDEXT) VOLTAGE VDDEXT 3.47V, -40°C VDDEXT 3.3V, +25°C VDDEXT 3.13V, +105°C
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE APPROXIMATELY 1.5V.
Figure Output Enable/Disable
input threshold device requiring hold time. typical will total capacitance (per data line), total leakage three-state current (per data line). hold time will tDECAY plus minimum disable time (i.e., tDATRWH write cycle).
Figure Typical Drive Currents Test Conditions
tested output enable, disable, hold time.
Output Enable Time
OUTPUT
1.5V
Output pins considered enabled when they have made transition from high impedance state point when they start driving. output enable time tENA interval from point when reference signal reaches high voltage level point when output reached specified high trip point, shown Output Enable/Disable diagram (Figure 38). multiple pins (such data bus) enabled, measurement value that first start driving.
Output Disable Time
30pF
Figure 31Equivalent Device Loading Measurements (Includes Fixtures)
Output pins considered disabled when they stop driving, into high impedance state, start decay from their output high voltage. time voltage decay dependent capacitive load, load current, This decay time approximated following equation:
DECAY
INPUT OUTPUT
1.5V
1.5V
Figure Voltage Reference Levels Measurements (Except Output Enable/Disable)
output disable time tDIS difference between tMEASURED tDECAY shown Figure time tMEASURED interval from when reference signal switches when output voltage decays from measured output high output voltage. tDECAY calculated with test loads with equal
Example System Hold Time Calculation
determine data output hold time particular system, first calculate tDECAY using equation given above. Choose difference between ADSP-21161N's output voltage REV. -51-
ADSP-21161N
Capacitive Loading
OUTPUT DELAY HOLD
0.0835X 2.42
Output delays holds based standard capacitive loads: pins (see Figure Page 51). Figure shows graphically output delays holds vary with load capacitance. (Note that this graph derating does apply output disable delays; Output Disable Time Page 51.) graphs Figure Figure Figure linear outside ranges shown Typical Output Delay Load Capacitance Typical Output Rise Time (20% 80%, Min) Load Capacitance.
Environmental Conditions
NOMINAL
LOAD CAPACITANCE
thermal characteristics which operating influence performance.
Thermal Characteristics
Figure Typical Output Delay Hold Load Capacitance Case Temperature)
16.0 14.0
RISE FALL TIMES (0.694V 2.77V, 80%)
12.0 10.0
0.0743X 1.5613 RISE TIME
ADSP-21161N packaged 225-ball Mini Ball Grid Array (MBGA). ADSP-21161N specified case temperature (TCASE). ensure that TCASE data sheet specification exceeded, heatsink and/or flow source used. center block ground pins (MBGA balls: F6-10, G6-10, H6-10, J6-10, K6-10) provide thermal pathways printed circuit board's ground plane. heatsink should attached ground plane close possible thermal pathways) with thermal adhesive.
CASE
FALL TIME 0.0414X 2.0128
where: TCASE Case temperature (measured surface package)
LOAD CAPACITANCE
Power dissipation (this value depends upon specific application; method calculating shown under Power Dissipation). Value from Table 8.0°C/W
Table Airflow Over Package Versus
Figure Typical Output Rise/Fall Time (20% 80%, VDDEXT Max)
16.0 14.0 12.0 10.0 FALL TIME 0.0417X 1.8674 0.0773X 1.4399 RISE TIME
Airflow (Linear Ft./Min.) (°C/W)1 6.8°C/W.
17.9
15.2
13.7
RISE FALL TIMES (0.694V 2.77V, 80%)
LOAD CAPACITANCE
Figure Typical Output Rise/Fall Time (20% 80%, VDDEXT Min)
-52-
REV.
ADSP-21161N
225-BALL METRIC MBGA CONFIGURATIONS Table 225-Ball Metric MBGA Assignments Name PBGA Number Name PBGA Number Name PBGA Number Name PBGA Number
BMSTR SPIDS EBOOT LBOOT SCLK2 L0DAT4 L0ACK L0DAT2 L1DAT6 L1CLK L1DAT2 FLAG10 RESET FLAG8 VDDEXT VDDINT VDDEXT VDDINT VDDEXT VDDINT VDDEXT L0DAT0 DATA39 DATA43 DATA41 IRQ2 VDDEXT VDDEXT DATA26 DATA24 DATA25 DATA27
TRST RPBA MOSI SCLK1 L0DAT7 L0CLK L0DAT1 L1DAT4 L1ACK L1DAT0 RSTOUT1 FLAG5 FLAG7 FLAG9 FLAG6 VDDINT VDDINT DATA37 DATA40 DATA38 DATA36 TIMEXP ADDR22 ADDR20 ADDR23 VDDINT VDDINT DATA22 DATA19 DATA21 DATA23
SPICLK L0DAT6 L1DAT7 L1DAT3 L1DAT1 DATA45 DATA47 FLAG1 FLAG2 FLAG4 FLAG3 VDDEXT VDDEXT DATA34 DATA35 DATA33 DATA32 ADDR19 ADDR17 ADDR21 ADDR2 VDDEXT VDDINT VDDEXT VDDINT VDDEXT VDDINT VDDEXT DATA20 DATA16 DATA18
FLAG11 MISO SCLK0 VDDINT SCLK3 L0DAT5 L0DAT3 L1DAT5 DATA42 DATA46 DATA44 FLAG0 IRQ0 VDDINT IRQ1 VDDINT VDDINT DATA29 DATA28 DATA30 DATA31 ADDR16 ADDR12 ADDR18 ADDR6 ADDR0 VDDEXT SDA10 DATA17 DMAG2 DMAG1
REV.
-53-
ADSP-21161N
Table 225-Ball Metric MBGA Assignments (continued) Name PBGA Number Name PBGA Number Name PBGA Number Name PBGA Number
ADDR14 ADDR15 ADDR10 ADDR5 ADDR1 BRST SDCKE CLK_CFG1 CLK_CFG0 AVDD DMAR1
ADDR13 ADDR9 ADDR8 ADDR4 SBTS SDCLK1 SDCLK0 REDY CLKIN AGND DMAR2
ADDR11 ADDR7 ADDR3 CLKOUT CLKDBL XTAL SDWE
RSTOUT exists only silicon revisions greater. Leave this unconnected silicon revisions 0.3, 1.0, 1.1.
KEY: VDDINT VDDEXT GND* AGND AVDD SIGNAL
*USE CENTER BLOCK GROUND PINS PROVIDE THERMAL
PATHWAYS YOUR PRINTED CIRCUIT BOARD GROUND PLANE
Figure 225-Ball Metric MBGA Assignments (Bottom View, Summary)
-54-
REV.
ADSP-21161N
OUTLINE DIMENSIONS
ADSP-21161N comes 225-ball MBGA package with rows balls.
225-Ball Mini-BGA (CA-225)
17.00
BALL INDICATOR 17.00 14.00
1.00
VIEW DETAIL
1.00 (BALL PITCH) BOTTOM VIEW
1.85 (SEE NOTE 1.31 (SEE NOTE SEATING PLANE 0.30 0.70 0.20 0.60 0.50 (BALL DIAMETER)
DETAIL NOTES: DIMENSIONS MILLIMETERS COMPLY WITH JEDEC STANDARD MO-192-AAF2, EXCEPT HEIGHT THICKNESS DIMENSIONS NOTED. ACTUAL POSITION BALL GRID WITHIN 0.25 IDEAL POSITION RELATIVE PACKAGE EDGES. ACTUAL POSITION EACH BALL WITHIN 0.10 IDEAL POSITION RELATIVE BALL GRID.
ORDERING GUIDE Case Temperature Range On-Chip SRAM
Part Number1
Instruction Rate
Operating Voltage
ADSP-21161NKCA-100 ADSP-21161NCCA-100
+85°C -40°C +105°C
int/3.3 int/3.3
These parts packaged 225-ball Mini-Ball Grid Array (MBGA).
REV.
-55-
ADSP-21161N Revision History
Location Page
5/03-Changed from Rev. Rev. Changes FEATURES Table SIMD Computational Engine Figure Off-Chip Memory Peripherals Interface Controller Host Processor Interface Phase-Locked Loop Crystal Double Enable Design-for-Emulation Circuit Information Table Table ELECTRICAL CHARACTERISTICS TIMING SPECIFICATIONS Table Figure Power Dissipation Table Figure Table Figure Clock Input Table Figure Table Figure Table Figure Table Figure Memory Read Master Table Figure Memory Write Master Table Figure Synchronous Read/Write Master Table Figure Host BusRequest Table Figure Table Figure Asynchronous Read/Write Host ADSP-21161N Table Table Three-State Timing Master, Slave Figure Table Table Figure -56- REV.
ADSP-21161N
Location Page
Changes Table Table Figure Table Table Table Table Table Figure Figure Figure Table OUTLINE DIMENSIONS Changes formatting Global
REV.
-57-
-58-
-59-
-60-
C02935-0-5/03(A)
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