Cost Microprocessor System Hardware Monitor ADM9240 ADM9240 compl
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FEATURES Direct Voltage Measurement Inputs (Including Processor Core Voltages) with On-Chip Attenuators On-Chip Temperature Sensor Five Digital Inputs Bits Fully Supports Intel's LANDesk Client Manager (LDCM) Register-Compatible with LM7x Products Speed Monitoring Inputs Compatible System Management (SMBus) Chassis Intrusion Detect Interrupt Output Programmable RESET Shutdown Mode Minimize Power Consumption Limit Comparison Monitored Values APPLICATIONS Network Servers Personal Computers Microprocessor-Based Office Equipment Test Equipment Measuring Instruments
Cost Microprocessor System Hardware Monitor ADM9240
ADM9240 complete system hardware monitor microprocessor-based systems, providing measurement limit comparison four power supplies processor core voltages, plus temperature, speeds chassis intrusion. Measured values read I2C-compatible serial System Management Bus, values limit comparisons programmed over same serial bus. high speed successive approximation allows frequent sampling analog channels ensure fast interrupt response out-of-limit measurement. ADM9240's 2.85 5.75 supply voltage range, supply current compatible interface, make ideal wide range applications. These include hardware monitoring protection applications personal computers, electronic test equipment office electronics.
FUNCTIONAL BLOCK DIAGRAM
VID0 VID1 VID2 VID3 VID4 DEVICE REGISTER VID0 DIVISOR REGISTERS
SERIAL ADDRESS REGISTER SERIAL INTERFACE
NTEST_OUT/A0 VALUE LIMIT REGISTERS LIMIT COMPARATORS INTERRUPT STATUS REGISTERS MASK REGISTERS CONFIGURATION REGISTER
VID4
FAN1 FAN2
SPEED COUNTER ADDRESS POINTER REGISTER TEMPERATURE CONFIGURATION REGISTER
+VCCP1 +2.5VIN +3.3VIN +5VIN +12VIN +VCCP2 BANDGAP TEMPERATURE SENSOR INPUT ATTENUATORS ANALOG MULTIPLEXER
9-BIT ANALOG OUTPUT REGISTER 8-BIT NTEST_IN/AOUT RESET
ADM9240
CHASSIS INTRUSION CLEAR REGISTER
GNDA
GNDD
registered trademark Philips Corporation.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1998
ADM9240-SPECIFICATIONS1,
TMAX VMIN VMAX, unless otherwise noted)
5.75 Units Test Conditions/Comments
Parameter POWER SUPPLY Supply Voltage, Supply Current,
2.85
Interface Inactive, Active Inactive, Active Shutdown Mode -40°C +125°C +25°C
TEMPERATURE-TO-DIGITAL CONVERTER Accuracy Resolution ANALOG-TO-DIGITAL CONVERTER (INCLUDING ATTENUATORS) Total Unadjusted Error, Differential Nonlinearity, Power Supply Sensitivity Total Monitoring Cycle Time Input Resistance ANALOG OUTPUT Output Voltage Range Total Unadjusted Error, Full-Scale Error Zero Error Differential Nonlinearity, Integral Nonlinearity Output Source Current Output Sink Current RPM-TO-DIGITAL CONVERTER Accuracy Full-Scale Count FAN1 FAN2 Nominal Input
1.25
Note +25°C +125°C (Note -40°C +125°C (Note
Load Monotonic Design
8800 4400 2200 1100
+25°C +125°C -40oC +125°C Divisor Count (Note Divisor Count (Note Divisor Count (Note Divisor Count (Note +25°C +125°C -40oC +125°C IOUT 4.25 V-5.75 IOUT 2.85 V-3.45 IOUT -5.0 4.25 V-5.75 IOUT -3.0 2.85 V-3.45
Internal Clock Frequency DIGITAL OUTPUT NTEST_OUT Output High Voltage,
21.1 19.8
22.5 22.5
23.9 25.2
Output Voltage,
OPEN-DRAIN DIGITAL OUTPUTS (INT, RESET, Output Voltage, High Level Output Current, RESET Pulsewidth
IOUT -5.0 5.75 IOUT -3.0 3.45 VOUT
REV.
ADM9240
Parameter OPEN-DRAIN SERIAL DATA OUTPUT (SDA) Output Voltage, Units Test Conditions/Comments
High Level Output Current, SERIAL DIGITAL INPUTS (SCL, SDA) Input High Voltage, Input Voltage, Hysteresis DIGITAL INPUT LOGIC LEVELS (A0, RESET, VID0 VID4, FAN1, FAN2) Input High Voltage, Input Voltage, Input High Voltage, Input Voltage, NTEST_IN Input High Voltage, Input High Voltage, DIGITAL INPUT CURRENT Input High Current, Input High Current, Input Current, Input Capacitance, SERIAL TIMING7 Clock Frequency, fSCLK Glitch Immunity, Free Time, tBUF Start Setup Time, tSU;STA Start Hold Time, tHD;STA Time, tLOW High Time, tHIGH SCL, Rise Time, SCL, Fall Time, Data Setup Time, tSU;DAT Data Hold Time, tHD;DAT
IOUT -3.0 4.25 V-5.75 IOUT -3.0 2.85 V-3.45 VOUT
-200
4.25 V-5.75 4.25 V-5.75 2.85 V-3.45 2.85 V-3.45 4.25 V-5.75 2.85 V-3.45 (Note
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
NOTES voltages measured with respect GND, unless otherwise noted. Typicals +25°C represent most likely parametric norm. Shutdown current measured with (Total Unadjusted Error) includes Offset, Gain Linearity errors ADC, multiplexer on-chip input attenuators, including external series input protection resistor value between zero Total monitoring cycle time time taken measure analog inputs plus temperature sensor. total count based pulses revolution tachometer output. have internal pull-down. Timing specifications tested logic levels falling edge rising edge. Specifications subject change without notice.
REV.
ADM9240
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (VCC) Voltage Input Output -0.3 (VCC (Except Analog Inputs) Other Analog Inputs +7.5 Ground Difference (GNDD-GNDA) Input Current Package Input Current Maximum Junction Temperature max) 150°C Storage Temperature Range -65°C +150°C Lead Temperature, Soldering Vapor Phase (sec) +215°C Infrared (sec) +200°C Rating Pins Except 2000 Rating
Start Condition (A7)
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
THERMAL CHARACTERISTICS
24-Lead Small Outline Package: 50°C/Watt, 10°C/Watt
ORDERING GUIDE Temperature Range -40°C +125°C Package Description Package Option
Model ADM9240ARU
24-Lead TSSOP RU-24
CONFIGURATION
(A6) NTEST_OUT/A0
PROTOCOL
tSU;STA
tLOW
tHIGH
1/fSCL
VID0 VID1 VID2 VID3 VID4
tBUF
FAN1 FAN2
ADM9240
tHD;STA
(R/W)
tSU;DAT
Stop Condition
tHD;DAT
GNDD
+VCCP1 VIEW (Not Scale) +2.5VIN
+3.3VIN +5VIN +12VIN +VCCP2 GNDA
PROTOCOL
Acknowledge
NTEST_IN/AOUT
RESET
tVD;DAT
tSU;STO
Figure Diagram Serial Timing
REV.
ADM9240
FUNCTION DESCRIPTIONS
Number
Mnemonic NTEST_OUT/A0 FAN1 FAN2
Description Digital I/O. Dual Function Pin. lowest order programmable Serial Address. This functions output when doing NAND Tree test. Digital Input. highest order programmable Serial Address. Digital I/O. Serial Bidirectional Data. Open-drain output. Digital Input. Serial Clock. Digital Input. amplitude tachometer input. Digital Input. amplitude tachometer input. Digital I/O. active high input from external circuit that latches Chassis Intrusion event. This line high without clamping action regardless powered state ADM9240. ADM9240 provides internal open drain this line, controlled Register Register 46h, provide minimum pulse this line, reset external Chassis Intrusion Latch. Digital Ground. Internally connected digital circuitry. Power (+2.85 +5.75 Typically powered from +3.3 power rail. Bypass with parallel combination (electrolytic tantalum) (ceramic) bypass capacitors. Digital Output. Interrupt Request (open drain). output enabled when Configuration Register default state disabled. Digital Input/Analog Output. active-high input that enables NAND Tree mode boardlevel connectivity testing. Refer section NAND Tree testing. Also functions programmable analog output when NAND Tree selected Digital I/O. Master Reset, driver (open drain), active output with minimum pulsewidth. Available when enabled Register 44h, using Register 40h. Also acts reset input when pulled (e.g., power-on reset). Analog Ground. Internally connected analog circuitry. ground reference analog inputs. Analog Input. Monitors processor core voltage +VCCP2 V-3.6 also used monitor supply adding external resistors. Analog Input. Monitors supply. Analog Input. Monitors supply. Analog Input. Monitors +3.3 supply. Analog Input. Monitors +2.5 supply. Analog Input. Monitors processor core voltage +VCCP1 V-3.6 Digital Input. Core Voltage readouts from processor. This value read into VID4 Status Register. Digital Input. Core Voltage readouts from processor. This value read into VID0-VID3 Status Register. Digital Input. Core Voltage readouts from processor. This value read into VID0-VID3 Status Register. Digital Input. Core Voltage readouts from processor. This value read into VID0-VID3 Status Register. Digital Input. Core Voltage readouts from processor. This value read into VID0-VID3 Status Register.
GNDD NTEST_IN/AOUT
RESET
GNDA +VCCP2 +3.3 +2.5 +VCCP1 VID4 VID3 VID2 VID1 VID0
REV.
ADM9240
GENERAL DESCRIPTION INTERNAL REGISTERS ADM9240
ADM9240 complete system hardware monitor microprocessor-based systems. device communicates with system serial System Management Bus. serial controller hardwired address lines device selection (Pin serial data line reading writing addresses data (Pin input line serial clock (Pin control programming functions ADM9240 performed over serial bus. on-chip analog-to-digital converter with multiplexed analog inputs measures power supply voltages (+12 +3.3 +2.5 V-Pins processor core voltages (+VCCP1 +VCCP2-Pins 14). also accepts input from on-chip bandgap temperature sensor that monitors system ambient temperature. count inputs (Pins provided monitoring speed fans with tachometer outputs. accommodate fans with different speeds different tacho outputs, divisor programmed into counter. Five digital inputs (VID4 VID0-Pins read processor Voltage code, while chassis intrusion input (Pin provided detect unauthorized tampering with equipment. When ADM9240 monitoring sequence started, cycles sequentially through measurement analog inputs temperature sensor, while same time speed inputs independently monitored. Measured values from these inputs stored value registers. These read over serial bus, compared with programmed limits stored limit registers. results out-of-limit comparisons stored interrupt status registers will generate interrupt line (Pin 10). Interrupt Status Bits masked appropriate programming Interrupt Mask Register. RESET input/output (Pin provided. Pulling this will reset ADM9240 internal registers default values. ADM9240 also programmed give low-going reset pulse this pin. ADM9240 contains on-chip, 8-bit digital-to-analog converter with output range zero 1.25 (Pin 11). This typically used implement temperature-controlled controlling speed dependent upon temperature measured on-chip temperature sensor. Testing board level connectivity simplified providing NAND tree test function. AOUT (Pin also doubles NAND test input, while doubles NAND tree output.
brief description ADM9240's principal internal registers given below. More detailed information function each register given Tables XVII. Configuration Register: Provides control configuration. Serial Address Register: Stores serial address ADM9240. Address Pointer Register: Contains address that selects other internal registers. When writing ADM9240, first byte data always register address, which written Address Pointer Register. Interrupt (INT) Status Registers: registers provide status each Interrupt event. Interrupt (INT) Mask Registers: Allow masking individual Interrupt sources. Temperature Configuration Register: configuration temperature interrupt controlled lower three bits this register. VID/Fan Divisor Registers: status VID0 VID4 pins processor written read from these registers. Divisor values fan-speed measurement also stored these registers. Value Limit Registers: results analog voltage inputs, temperature speed measurements stored these registers, along with their limit values. Analog Output Register: code controlling analog output stored this register. Chassis Intrusion Clear Register: signal latched chassis intrusion cleared writing this register.
REV.
ADM9240
SERIAL INTERFACE
Control ADM9240 carried serial bus. ADM9240 connected this slave device, under control master device, e.g., PIIX4. ADM9240 7-bit serial address. When device powered will with default serial address. five MSBs address 01011, LSBs determined logical states 1(NTEST_OUT/A0) (A1) power-up. These pins have internal pull-down resistors, they left open-circuit default address will 0101100. facility make hardwired changes allows user avoid conflicts with other devices sharing same serial bus, example more than ADM9240 used system. Once ADM9240 been powered five MSBs serial address changed writing 7-bit word serial Address Pointer Register (the hardwired values cannot overwritten). Thereafter, serial address must used select ADM9240, until changed again, device powered off. serial protocol operates follows: master initiates data transfer establishing START condition, defined high-to-low transition serial data line while serial clock line remains high. This indicates that address/data stream will follow. slave peripherals connected serial respond START condition, shift next eight bits, consisting 7-bit address (MSB first) plus bit, which determines direction data transfer, i.e., whether data will written read from slave device. peripheral whose address corresponds transmitted address responds pulling data line during period before ninth clock pulse, known acknowledge bit. other devices remain idle while selected device waits data read from written master will write slave device. master will read from slave device. Data sent over serial sequences nine clock pulses, eight bits data followed acknowledge
from slave device. Transitions data line must occur during period clock signal remain stable during high period, low-to-high transition when clock high interpreted STOP signal. number data bytes that transmitted over serial single READ WRITE operation limited only what master slave devices handle. When data bytes have been read written, stop conditions established. WRITE mode, master will pull data line high during tenth clock pulse assert STOP condition. READ mode, master device will override acknowledge pulling data line high during period before ninth clock pulse. This known Acknowledge. master will then take data line during period before tenth clock pulse, then high during tenth clock pulse assert STOP condition. number bytes data transferred over serial operation, possible read write operation, because type operation determined beginning cannot subsequently changed without starting operation. case ADM9240, write operations contain either bytes, read operations contain byte perform following functions: write data device data registers read data from Address Pointer Register must that correct data register addressed, then data written into that register read from first byte write operation always contains address that stored Address Pointer Register. data written device, then write operation contains second data byte that written register selected Address Pointer Register. This illustrated Figure device address sent over followed This followed data bytes. first data byte address internal data register written which stored Address Pointer Register. second data byte data written internal data register.
START MASTER
ACK. ADM9240
ACK. ADM9240
FRAME SERIAL ADDRESS BYTE (CONTINUED)
FRAME ADDRESS POINTER REGISTER BYTE
(CONTINUED)
ACK. STOP ADM9240 MASTER
FRAME DATA BYTE
Figure Writing Register Address Address Pointer Register, then Writing Data Selected Register
REV.
ADM9240
When reading data from register there possibilities: ADM9240's Address Pointer Register value unknown desired value, first necessary correct value before data read from desired data register. This done performing write ADM9240 before, only data byte containing register address sent, data written register. This shown Figure read operation then performed consisting serial address, followed data byte read from data register. This shown Figure Address Pointer Register known already desired address, data read from corresponding data register without first writing Address Pointer Register, Figure omitted. Notes: Although possible read data byte from data register without first writing Address Pointer Register, Address Pointer Register already correct value, possible write data register without writing Address Pointer Register, because first data byte write always written Address Pointer Register. Figures serial address shown default value 01011(A1)(A0), where hardwired either Logic Logic
ANALOG INPUTS
ADM9240 analog inputs. Four these dedicated monitoring following power supply voltages: +3.3 +2.5 These inputs multiplexed into on-chip, successive approximation, analog-to-digital converter. This resolution bits, only eight bits used voltage measurement limit comparison. basic input range power supply inputs scaled onchip attenuators such that produces output full scale decimal, when input voltage nominal value. on-chip scaling guarantees accuracy removes need precision external resistors.
START MASTER
ACK. ADM9240
ACK. ADM9240 STOP MASTER
FRAME SERIAL ADDRESS BYTE
FRAME ADDRESS POINTER REGISTER BYTE
Figure Writing Address Pointer Register only
START MASTER
ACK. ADM9240
ACK. STOP MASTER MASTER
FRAME SERIAL ADDRESS BYTE
FRAME DATA BYTE FROM ADM9240
Figure Reading Data from Previously Selected Register
REV.
ADM9240
input ranges analog inputs shown more detail Table +VCCP1 +VCCP2 inputs used measure processor core voltages, have input range from only single processor core voltage being monitored, VCCP2 input used monitor supply. This achieved using resistive divider network referenced known positive voltage. This illustrated Figure
INPUT CIRCUITS
42.7k +VCCP2 97.3k 122.2k +12V 22.7k 91.6k 55.2k 61.1k +3.3V 80.9k 36.7k +2.5V 111.2k 42.7k 97.3k 50pF 25pF 25pF 25pF 35pF 50pF
internal structure analog inputs shown Figure Each input circuit consists input protection diode, attenuator, plus capacitor form first order low-pass filter which gives input immunity high frequency noise.
+VCCP1
Figure Internal Structure Analog Inputs
Table Output Code
<0.062 0.062-0.125 0.125-0.187 0.188-0.250 0.250-0.313 0.313-0.375 0.375-0.438 0.438-0.500 0.500-0.563
<0.026 0.026-0.052 0.052-0.078 0.078-0.104 0.104-0.130 0.130-0.156 0.156-0.182 0.182-0.208 0.208-0.234
Input Voltage +3.3 +2.5 <0.0172 0.017-0.034 0.034-0.052 0.052-0.069 0.069-0.086 0.086-0.103 0.103-0.120 0.120-0.138 0.138-0.155 <0.013 0.013-0.026 0.026-0.039 0.039-0.052 0.052-0.065 0.065-0.078 0.078-0.091 0.091-0.104 0.104-0.117 0.833-0.846 1.667-1.680 2.500-2.513 3.190-3.203 3.203-3.216 3.216-3.229 3.229-3.242 3.242-3.255 3.255-3.268 3.268-3.281 3.281-3.294 3.294-3.307 3.307-3.320 >3.320
+VCCP1 <0.014 0.014-0.028 0.028-0.042 0.042-0.056 0.056-0.070 0.070-0.084 0.084-0.098 0.098-0.112 0.112-0.126
+VCCP2 <0.014 0.014-0.028 0.028-0.042 0.042-0.056 0.056-0.070 0.070-0.084 0.084-0.098 0.098-0.112 0.112-0.126
Output Decimal Binary 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000
4.000-4.063
1.666-1.692
1.100-1.117
0.900-0.914
0.900-0.914
(1/4 Scale)
01000000
8.000-8.063
3.330-3.560
2.200-2.217
1.800-1.814
1.800-1.814
(1/2 Scale) 10000000
12.000-12.063
5.000-5.026
3.300-3.317
2.700-2.714
2.700-2.714
(3/4 Scale) 11000000
15.313-15.375 15.375-15.438 15.438-15.500 15.500-15.563 15.563-15.625 15.625-15.688 15.688-15.750 15.750-15.813 15.813-15.875 15.875-15.938 >15.938 REV.
6.380-6.406 6.406-6.432 6.432-6.458 6.458-6.484 6.484-6.510 6.510-6.536 6.536-6.562 6.562-6.588 6.588-6.615 6.615-6.640 >6.640
4.210-4.230 4.230-4.245 4.245-4.263 4.263-4.280 4.280-4.300 4.300-4.314 4.314-4.331 4.331-4.348 4.348-4.366 4.366-4.383 >4.383
3.445-3.459 3.459-3.473 3.473-3.487 3.487-3.501 3.501-3.515 3.515-3.529 3.529-3.543 3.543-3.558 3.558-3.572 3.572-3.586 >3.586
3.445-3.459 3.459-3.473 3.473-3.487 3.487-3.501 3.501-3.515 3.515-3.529 3.529-3.543 3.543-3.558 3.558-3.572 3.572-3.586 >3.586
11110101 11110110 11110111 11111000 11111001 11111010 11111011 11111100 11111101 11111110 11111111
ADM9240
SETTING OTHER INPUT RANGES
inputs unused, there requirement monitoring another power supply such input range unused input easily scaled offset accommodate this. example, only processor core voltage monitored, unused VCCP input used monitor another supply voltage. voltage monitored positive, simply matter using input with lower full scale than voltage measured adding external input attenuator, bear mind that input resistance (140 on-chip attenuator will load external attenuator. This accounted calculation, values on-chip attenuator resistors precise vary with temperature. Therefore, external attenuator should have much lower output resistance minimize loading. this acceptable, buffer amplifier used. input voltage range negative, must first converted positive voltage. simplest this simply attenuate offset voltage, shown Figure which shows +VCCP2 input scaled measure input. Using values shown, input range zero -13.5 which will accommodate +12.5% tolerance nominal value.
supply increases input (R2+RP), while decrease supply correspondingly decreases input ADC. on-chip input attenuators will load external attenuator, mentioned earlier. This technique applied other unused input. suitable choice input resistors, variety negative and/or bipolar input ranges obtained.
TEMPERATURE MEASUREMENT SYSTEM
ADM9240 contains on-chip bandgap temperature sensor. on-chip performs 9-bit conversions output this sensor outputs temperature data 9-bit twos complement format, only eight most significant bits used temperature limit comparison. full 9-bit temperature data obtained reading MSBs from Temperature Value Register (Address 27h) from Temperature Configuration Register (Address 4Bh). format temperature data shown Table Theoretically, temperature sensor measure temperatures from -128°C +127°C with resolution 0.5°C, although temperatures below -40°C above +125°C outside operating temperature range device.
Table Temperature Data Format
2.7k -13.2V 3.6V
+VCCP2 140k
Temperature -128°C -125°C -100°C -75°C -50°C -25°C -0.5°C +0.5°C +10°C +25°C +50°C +75°C +100°C +125°C +127°C
LIMIT VALUES
Digital Output 0000 0000 0000 0110 0011 1000 0110 1010 1001 1100 1100 1110 1111 1111 0000 0000 0000 0001 0001 0100 0011 0010 0110 0100 1001 0110 1100 1000 1111 1010 1111 1111
Figure Scaling VCCP2 (+10%)
resistor ratios calculated follows: R1/R2 |V-|(max)/V+ give zero volts input most negative value effect under this condition voltage across zero) and: VFS)/VFS R2/RP Parallel) give voltage input when zero, where normal full-scale voltage input used). This simple cheap solution, following points should noted. Since input signal inverted, increase magnitude supply (going more negative), will cause input voltage fall give lower output code from ADC. Conversely, decrease magnitude supply will cause code increase. This means that upper lower limits will transposed. Since offset voltage derived from supply, variations this supply will affect code. therefore good idea read value supply adjust limits supply accordingly. supply attenuated factor RP/(R2+R where parallel combination increase -10-
Limit values analog measurements stored appropriate limit registers. case voltage measurements, high limits stored that interrupt request will generated measured value goes above below acceptable values. case temperature, Temperature Limit programmed, Temperature Hysteresis Limit, which will usually some degrees lower. This useful allows system shut down when limit exceeded, automatically restarted when cooled down safe temperature.
REV.
ADM9240
MONITORING CYCLE TIME
monitoring cycle begins when written Start (Bit zero INT_Clear (Bit Configuration Register. INT_Enable (Bit should enable output. measures each analog input turn, starting with VCCP2 finishing with on-chip temperature sensor. each measurement completed result automatically stored appropriate value register. This "round-robin" monitoring cycle continues until disabled writing Configuration Register. counter controlling multiplexer driven on-chip clock nominally 22.5 kHz, entire measurement sequence takes (nominally): 44.4 310.8 This rapid sampling analog inputs ensures quick response event input going limits, unlike other monitoring chips that employ slower ADCs. When monitoring cycle started, monitoring speed inputs begins same time monitoring analog inputs. However, monitoring cycles synchronized way, monitoring cycle time inputs dependent speed much slower than analog inputs. more details Speed Measurement section.
INPUT SAFETY
powered from precautions such clamp diode ground needed prevent baseemitter junction transistor being reverse-biased unlikely event that output should swing negative reason. positive output swing should close possible that maximum voltage obtained from transistor. Even swings rail, maximum voltage from emitter transistor will about 11.4 typical values this condition would Gain 11.4/1.25 9.12 R1/R2 (nearest preferred value) giving actual gain 9.2. transistor should have reasonably high avoid base current pulling down output amp, must have ICMAX greater than maximum current capable dissipating power voltage dropped across when operating full speed. Depending parameters, some suitable devices would 2N2219A, 2N3019 ZTX450.
+12V NTEST_IN/AOUT
Scaling analog inputs performed on-chip, external attenuators normally required. However, since power supply voltages will appear directly pins, advisable small external resistors series with supply traces chip prevent damaging traces power supplies should accidental short such probe connect power supplies together. resistors will form part input attenuators, they will affect accuracy analog measurement their value high. analog input channels calibrated assuming external series resistor accuracy will remain within specification value from zero standard resistor suitable. worst such accident would connecting total difference, with series resistors this would draw maximum current approximately
ANALOG OUTPUT
Figure Analog Output Driving
LAYOUT GROUNDING
Analog inputs will provide best accuracy when referred GNDA pin. separate, impedance ground plane analog ground, which provides ground point voltage dividers analog components, will provide best performance mandatory. power supply bypass, parallel combination (electrolytic tantalum) (ceramic) bypass capacitors connected between ground, should also located close possible ADM9240.
ADM9240 single analog output from unsigned 8-bit which produces V-1.25 analog output register defaults during power-on reset, which produces maximum speed. analog output amplified buffered with external circuitry such transistor provide speed control. suitable drive circuit given Figure Care must taken when choosing ensure that input common-mode range output voltage swing suitable. powered from rail alone from powered from then input commonmode range should include ground accommodate minimum output voltage DAC, output voltage should swing below ensure that transistor turned fully off. REV. -11-
ADM9240
INPUTS
+12V
inputs provide monitoring condition cooling fans. Signal conditioning ADM9240 accommodates slow rise fall times typical tachometer outputs. maximum input signal range VCC. event that these inputs supplied from outputs that exceed VCC, either resistive attenuation signal diode clamping must included keep inputs within acceptable range. Figures show circuits most common tacho outputs. tacho output resistive pull-up connected directly input, shown Figure
+12V
TACHO OUTPUT
FAN1 FAN2
SPEED COUNTER
*SEE TEXT
Figure with Strong Tachometer Pull-Up >VCC Totem-Pole Output, Attenuated with R1/R2
INPUT CURRENT LIMITING
PULL-UP 4.7k TYP. TACHO OUTPUT
FAN1 FAN2
SPEED COUNTER
Figure with Tachometer Pull-Up +VCC
fans powered while ADM9240 unpowered, inputs ADM9240 will clamp output voltage. this case input current must limited less than maximum value Absolute Maximum Ratings table. pull-up resistor tacho output provide this current limiting but, value low, necessary additional resistance series with input pins.
SPEED MEASUREMENT
output resistive pull-up other voltage greater than VCC), output clamped with Zener diode, shown Figure Zener voltage should chosen that greater than less than VCC, allowing voltage tolerance Zener. value about suitable.
+12V *CHOOSE VOLTAGE APPROX.
PULL-UP 4.7k TYP.
TACHO OUTPUT ZD1* ZENER
FAN1 FAN2
SPEED COUNTER
counter does count tacho output pulses directly, because speed less than 1000 would take several seconds accumulate reasonably large accurate count. Instead, period revolution measured gating on-chip 22.5 oscillator into input 8-bit counter periods tacho output, shown Figure accumulated count actually proportional tacho period inversely proportional speed. monitoring cycle begins when written start (Bit zero INT_Clear (Bit Configuration Register INT_Enable (Bit should enable output. measurement begins rising edge tacho pulse, ends next-but-one rising edge. Once speeds have been measured, they will stored Speed Value Registers read time. measurements will updated long monitoring cycle continues.
22.5kHz CLOCK
Figure with Tachometer Pull-Up Voltage (e.g., Clamped with Zener Diode
strong pull-up (less than totem-pole output, series resistor added limit zener current, shown Figure Alternatively, resistive attenuator used, shown Figure should chosen such that: VPULL-UP R2/(RPULL-UP value pull-up resistor known, value should made fairly large, large that input leakage current will cause large voltage drop across them. With pull-up voltage pull-up resistor less than suitable values would This will give high input voltage 3.83
+12V *CHOOSE VOLTAGE APPROX.
CONFIG REG.
FAN1 INPUT
FAN2 INPUT FAN1 MEASUREMENT PERIOD START MONITORING CYCLE FAN2 MEASUREMENT PERIOD
TACHO OUTPUT PULL-UP TYP. TOTEM-POLE
FAN1 FAN2 ZD1* ZENER
SPEED COUNTER
Figure Speed Measurement
Figure with Strong Tachometer Pull-Up >VCC Totem-Pole Output, Clamped with Zener Resistor
-12-
REV.
ADM9240
accommodate fans different speed and/or different numbers output pulses revolution, prescaler (divisor) added before counter. default value which gives count running 4400 producing output pulses revolution. count calculated equation: Count (22.5 /(rpm Divisor) constant speed fans, failure normally considered have occurred when speed drops below nominal, which would correspond count 219. Full scale (255) would reached speed fell nominal value. temperature controlled variable speed fans situation will different. Table shows relationship between speed time revolution 60%, 100% nominal speeds 1100 rpm, 2200 rpm, 4400 8800 rpm, divisor that would used each these fans, based tacho pulses revolution.
Table III. Speeds Divisors
Time (ms) 6.82 13.64 27.27 54.54 6160 3080 1540 Time (ms) 9.74 19.48 38.96 77.92 5280 2640 1320 Time (ms) 11.36 22.73 45.45 90.9
MANUFACTURERS
Manufacturers cooling fans with tachometer outputs listed below: Tech 9730 Independence Ave. Chatsworth, California 91311 818-341-3355 818-341-8207 Model 2408NL 2410ML 3108NL 3110KL Frame Size 2.36 0.79 2.36 0.98 3.15 0.79 3.15 0.98 Airflow 9-16 14-25 25-42 25-40
Mechatronis Inc. P.O. Preston, 98050 800-453-4569 Models-Various sizes available with tach output option. Sanyo Denki/Keymarc Electronics Amapola Ave. Torrance, 90501 310-783-5400 Models-109P Series
CHASSIS INTRUSION INPUT
Divisor
Nominal 8800 4400 2200 1100
Note that Divisors programmed into Bits VID0-VID3/Fan Divisor Register.
LIMIT VALUES
Fans general will overspeed from correct voltage, failure condition interest underspeed electrical mechanical failure. this reason only speed limits programmed into limit registers fans. should noted that, since period rather than speed being measured, failure interrupt will occur when measurement exceeds limit value.
MONITORING CYCLE TIME
Chassis Intrusion (CI) input active high input/opendrain output intended detection signalling unauthorized tampering with system. external circuit powered from system's CMOS backup battery used detect latch chassis intrusion event, whether system powered not. Once chassis intrusion been detected latched, input will generate interrupt when system powered actual detection chassis intrusion performed external circuit that will, example, detect when cover been removed. wide variety techniques used detection: Microswitch that opens closes when cover removed. Reed switch operated magnet fixed cover. Hall-effect switch operated magnet fixed cover. Phototransistor that detects light when cover removed.
monitoring cycle time depends speed number tacho output pulses revolution. complete periods tacho output (three rising edges) required each measurement. Therefore, start measurement just misses rising edge, measurement take almost three tacho periods. order read valid result from value registers, total monitoring time allowed after starting monitoring cycle should therefore three tacho periods FAN1 plus three tacho periods FAN2 lowest normal speed. Although monitoring cycle analog input monitoring cycle started together, they synchronized other way.
chassis intrusion interrupt will remain asserted until external detection circuit reset. This achieved setting Configuration Register, Chassis Intrusion Clear Register one, which will cause pulled least These register bits self-clearing.
REV.
-13-
ADM9240
chassis intrusion circuit should designed that reset pulling output low. suitable chassis intrusion circuit using phototransistor shown Figure Light falling phototransistor when cover removed will cause turn pull input thus setting latch N3/N4. After cover replaced, reset output will pull down input resetting latch.
1N914 CMOS BACKUP BATTERY MRD901 1N914
AD22105
RSET TEMP. SENSOR
Figure Using Input with Temperature Sensor
74HC132
100k 470k
Note: chassis intrusion input does have protective clamp diode VCC, this could pull down chassis intrusion latch reset when ADM9240 powered down.
ADM9240 INTERRUPT STRUCTURE
Figure Chassis Intrusion Detector Latch
Interrupt Structure ADM9240 shown Figure each measurement value obtained stored appropriate value register, value limits from corresponding limit registers high limit comparators. result each comparison limit, limit) routed corresponding input Interrupt Status Registers data demultiplexer used that high appropriate. Interrupt Mask Registers have bits corresponding each Interrupt Status Register Bits. Setting Interrupt Mask high forces corresponding Status output low, while setting Interrupt Mask allows corresponding Status asserted. After masking, status bits ORed together produce output, which will pull unmasked status goes high, i.e., when measured value goes limit. output enabled when Configuration Register (INT_Enable) high, (INT_Clear) low.
Chassis Intrusion input also used other types alarm input. Figure shows temperature alarm circuit using AD22105 temperature switch sensor. This produces lowgoing output when preset temperature exceeded, output inverted make compatible with input. almost small-signal transistor, CMOS inverter gate used available. AD22105 data sheet information selecting RSET.
+VCCP2 HIGH LIMIT FROM VALUE LIMIT REGISTERS LIMIT VALUE HIGH LIMIT COMPARATORS DATA DEMULTIPLEXER +12V +3.3V +2.5V +VCCP1 TEMP FAN1 FAN2 MASK GATING STATUS MASK INTERRUPT STATUS REGISTERS
LIMIT
(CHASSIS INTRUSION)
MASKING DATA FROM
INTERRUPT MASK REGISTERS
INT_ENABLE
INT_CLEAR
CONFIGURATION REGISTER
Figure Interrupt Register Structure
-14-
REV.
ADM9240
INTERRUPT CLEARING
Reading Interrupt Status Register will output contents Register, then clear will remain cleared until monitoring cycle updates next read operation should performed register until this happened, result will invalid. time taken complete monitoring cycle mainly dependent time taken measure speeds, described earlier. output cleared with INT_Clear bit, which Configuration Register, without affecting contents Interrupt (INT) Status Registers. When this high, ADM9240 monitoring loop will stop. will resume when low.
TEMPERATURE INTERRUPT MODES
goes below THOTHYST. Operation one-time interrupt mode illustrated Figure Again, interval between read operations shown being longer than monitoring cycle time.
THOT
TEMP THOTHYST
READ
READ
READ
READ
READ
READ
READ
mentioned earlier, limit values programmed temperature measurement, Temperature Limit (THOT), Temperature Hysteresis Limit (THOTHYST which normally some degrees lower. interrupt function temperature sensor differs from interrupt operation other inputs that there three interrupt modes, called "One-Time Interrupt" mode, "Default Interrupt" mode "Comparator" mode.
DEFAULT INTERRUPT MODE
Figure Output One-Time Interrupt Mode
COMPARATOR MODE
Exceeding THOT causes output Low. will remain until temperature goes below THOT. Once temperature goes below THOT, will High. THOTHYST ignored. other words, Comparator Mode operates like thermostat with hysteresis. Operation comparator mode illustrated Figure
THOT
Exceeding THOT causes Interrupt that will remain active indefinitely until reset reading Interrupt Status Register cleared INT_Clear Configuration register. Once Interrupt event occurred crossing THOT then reset, Interrupt will occur again once next temperature conversion completed. interrupts will continue occur this manner until temperature goes below THOTHYST. Operation default interrupt mode illustrated Figure clarity, this illustration interval between read operations shown considerably longer than monitoring cycle time, that interrupt always reasserted after being reset, before next read operation occurs.
THOT
TEMP
Figure Output Comparator Mode
RESET INPUT/OUTPUT
TEMP THOTHYST
RESET (Pin that function opendrain output, providing going output pulse when Configuration Register provided reset function first been enabled setting Interrupt Mask Register automatically cleared when reset pulse output. also function RESET input pulling this reset internal registers ADM9240 default values. Only those registers that have power default values listed Table affected this function. register, Value Limit Registers affected.
NAND TREE TESTS
READ
READ
READ
READ
READ
READ
READ
Figure Temperature Output Default Interrupt Mode
ONE-TIME INTERRUPT MODE
Exceeding THOT causes Interrupt that will remain active indefinitely until reset reading Interrupt Status Register cleared INT_Clear Configuration Register. Once Interrupt event occurred crossing THOT then reset, Interrupt will occur again until temperature
NAND tree provided ADM9240 Automated Test Equipment (ATE) board level connectivity testing. device placed into NAND Test Mode powering with held high. This sampled automatically after power-up connected high, then NAND test mode invoked. NAND test mode, digital inputs tested illustrated below. A0/NTEST_OUT will become NAND tree output pin. perform NAND tree test, pins included NAND tree should driven high.
REV.
-15-
ADM9240
structure NAND tree shown Figure Beginning with working clockwise around chip, each toggled resulting toggle observed NTEST_OUT/A0. Allow typical propagation delay
FAN1 FAN2 VID0 VID1 VID2 VID3 VID4
Configuration Register controls monitoring loop ADM9240. Setting stops monitoring loop puts ADM9240 into power mode thereby reducing power consumption. Serial communication still possible with register ADM9240 while power mode. Setting high starts monitoring loop. Configuration Register enables disables Interrupt output. Setting high enables output, setting disables output. Configuration Register used clear interrupt output when high. ADM9240 monitoring function will stop until low. Interrupt Status Register contents will affected. Configuration Register used initiate minimum RESET signal RESET output function enabled Register Configuration Register used reset Chassis Intrusion (CI) output when high. Configuration Register used start Configuration Register Initialization when taken high.
STARTING CONVERSION
NTEST_OUT
Figure NAND Tree
Note: inputs shown Figure unused, they should connected directly ground, resistor such This will allow (Automatic Test Equipment) drive every input high that NAND tree test properly carried out.
USING ADM9240
POWER-ON RESET
When power first applied, ADM9240 performs "poweron reset" several registers. Registers whose power-on values shown have power-on conditions that indeterminate (this includes Value Limit Registers). inactive. most applications, usually first action after power-on would write limits into Limit Registers. Power-on reset clears initializes following registers (the initialized values shown Table Configuration Register Serial Address Register Interrupt (INT) Status Registers Interrupt (INT) Mask Registers /Fan Divisor Register VID4 Register Chassis Intrusion Clear Register Temperature Configuration Register Test Register Compatibility Register Analog Output Register
monitoring function (analog inputs, temperature speeds) ADM9240 started writing Configuration Register setting Start (Bit high, INT_Enable (Bit high INT_Clear (Bit low. Apart from initially starting together, analog measurements speed measurements proceed independently synchronized way. analog measurements will completed more than time taken complete speed measurements depends speed number tacho output pulses revolution. Once measurements have been completed, results read from Value Registers time. Table shows measurement sequence analog inputs.
Table Measurement Sequence
Measurement
Parameter Analog +VCCP2 Analog Analog Analog +3.3 Analog +2.5 Analog +VCCP1 Temperature Reading
INITIALIZATION
Configuration Register INITIALIZATION performs similar, identical, function power-on reset. Test Register Analog Output Register initialized. Configuration Register INITIALIZATION accomplished setting Configuration Register high. This automatically clears after being set.
Using Configuration Register
POWER SHUTDOWN MODE
Control ADM9240 provided through Configuration Register. stopped upon power-up, INT_Clear signal asserted, clearing output. Configuration Register used start stop ADM9240; enable disable interrupt outputs modes, provide initialization function described above.
ADM9240 placed power mode setting Configuration register This disables internal ADC. Full shutdown mode then achieved setting Test Register This turns analog output stops monitoring cycle, running, does affect condition registers. device will return previous state when this reset zero.
-16-
REV.
ADM9240
APPLICATION CIRCUIT
Figure shows generic application circuit using AD9240. analog monitoring inputs connected power supplies including processor core voltage inputs. inputs connected processor voltage pins. There tacho inputs from fans, analog output used control speed third fan. chassis intrusion latch with opto-sensor connected input. course, actual application, every input output used, which case unused analog digital inputs should tied analog digital ground appropriate.
+12V +3.3V NTEST_OUT/A0 VID0
+3.3V SERIAL 1N914 CMOS BACKUP BATTERY MRD901 1N914 +3.3V
VID1
VID2
FROM PINS PROCESSOR
VID3
FAN1
VID4
74HC132
100k 470k
FAN2
+VCCP1
ADM9240
+2.5VIN
GNDD +3.3V
+3.3VIN
+5VIN
+12VIN
+12V NTEST_IN/AOUT 2N2219A OP295 GNDA RESET +VCCP2
Figure Application Circuit
REV.
-17-
ADM9240
Table Address Pointer Register
Name Address Pointer
Write
Description Address ADM9240 Registers. tables below detail.
Table List Registers
Address
Description Test Register
Power Value 0000 0000
Notes A7-A0 (Binary 7-0) Setting this register selects shutdown mode. Caution: write other bits this register. Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
Programmed Value Analog Output +2.5 Measured Value +VCCP1 Measured Value +3.3 Measured Value Measured Value Measured Value VCCP2 Measured Value Reserved Temperature Reading FAN1 Reading FAN2 Reading Reserved +2.5 High Limit +2.5 Limit +VCCP1 High Limit +VCCP1 Limit +3.3 High Limit +3.3 Limit High Limit Limit High Limit +12V Limit VCCP2 High Limit VCCP2 Limit Reserved Reserved Temperature Limit (High) Temperature Hysteresis Limit (Low) FAN1 Count Limit FAN2 Count Limit Reserved Company Number Revision Number Configuration Register Interrupt Status Register Interrupt Status Register Mask Register Mask Register Compatibility Register Chassis Intrusion Clear Register VID0-3/Fan Divisor Register Serial Address Register VID4 Register Temperature Configuration Register
1111 1111 Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate 0010 0011 Revision 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0101 (VID3-VID0) 0010 11(A1)(A0) 1000 000(VID4) 0000 0001
This location will contain company identification number (Read Only). This location will contain revision number part. (Read Only). Table Table VIII Table Table Table Table Table XIII Table Table Table Table XVII
-18-
REV.
ADM9240
Table VII. Register 40h, Configuration Register (Power-On Default 08h)
Name START
Description Logic enables startup ADM9240, Logic places standby mode. Caution: outputs Interrupt pins will cleared user writes zero this location after interrupt occurred (see "INT_Clear" bit). startup, limit checking functions scanning begins. Note, high limits should into ADM9240 prior turning this bit. (Power-Up Default Logic enables output. Enabled Disabled (Power-Up Default Default During Interrupt Service Routine (ISR) this asserted Logic clear output without affecting contents Interrupt Status Register. device will stop monitoring. will resume upon clearing this bit. (Power-Up Default Creates RESET (Active Low) signal minimum (Power-Up Default This cleared once pulse goes active. Default outputs minimum active pulse Chassis Intrusion pin. (Power-Up Default (Note: This performs same function Register 46h). Logic restores power-up default values Configuration register, Interrupt status registers, Interrupt Mask Registers, Divisor Register Temperature Configuration Register. This automatically clears itself since power-on default zero.
INT_Enable Reserved INT_Clear
RESET Reserved CI_Reset Initialization
Table VIII. Register 41h, Interrupt Status Register (Power-On Default 00h)
Name +2.5 V_Error VCCP_Error +3.3 V_Error V_Error Temp_Error Reserved FAN1_Error FAN2_Error
Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
Description indicates high limit been exceeded. indicates high limit been exceeded. indicates high limit been exceeded. indicates high limit been exceeded. indicates that temperature interrupt been set. Undefined. indicates that count limit been exceeded. indicates that count limit been exceeded.
Table Register 42h, Interupt Status Register (Power-On Default 00h)
Name V_Error VCCP2_Error Reserved Reserved Chassis_Error Reserved Reserved Reserved
Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
Description indicates high limit been exceeded. indicates high limit been exceeded. Undefined. Undefined. indicates chassis intrusion gone high. Undefined. Undefined. Undefined.
Note: time STATUS Register read out, conditions (i.e., Register) that read automatically reset. case channel priority indication, more channels were limits, another indication would automatically generated were handled during ISR. Mask Register, errant voltage interrupt disabled until operator time clear errant condition limit higher/lower.
REV.
-19-
ADM9240
Table Register 43h, Interrupt Mask Register (Power-On Default 00h)
Name +2.5 +VCCP1 +3.3 Temp Reserved FAN1 FAN2
Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
Description disables corresponding interrupt status disables corresponding interrupt status disables corresponding interrupt status disables corresponding interrupt status disables corresponding interrupt status Power-On Default disables corresponding interrupt status disables corresponding interrupt status interrupt. interrupt. interrupt. interrupt. interrupt. interrupt. interrupt.
Table Register 44h, Mask Register (Power-On Default 00h)
Name VCCP2 Reserved Reserved Reserved Reserved RESET Enable
Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
Description disables corresponding interrupt status interrupt. disables corresponding interrupt status interrupt. Power-up default Low. Power-up default Low. disables corresponding interrupt status interrupt. Undefined. Undefined. enables RESET function configuration register.
Table XII. Register 45h, Reserved Compatibility (Power-On Default 00h)
Name Reserved
Read/Write
Description Reserved Compatibility.
Table XIII. Register 46h, Chassis Intrusion Clear (Power-On Default 00h)
Name Reserved Chassis Int. Clear
Read/Write Read/Write
Description Undefined (Power Default 00h) outputs minimum active pulse chassis intrusion pin. register clears itself after pulse been output.
Table XIV. Register 47h, VID0-3/Fan Divisor Register (Power-On Default 0101(VID3-VID0))
Name FAN1 Divisor
Read Read/Write
Description VID[3:0] inputs from processor core power supplies indicate operating voltage (e.g., Sets Counter Prescaler FAN1 Speed Measurement <5:4> Divide <5:4> Divide <5:4> Divide <5:4> Divide Sets Counter Prescaler FAN2 Speed Measurement <7:6> Divide <7:6> Divide <7:6> Divide <7:6> Divide
FAN2 Divisor
Read/Write
-20-
REV.
ADM9240
Table Register 48h, Serial Address Register (Power-On Default 0010 11(A1)(A0))
Name Serial Address
Read/Write
Description Serial Address (Bits Read Only)
Table XVI. Register 49h, 4/Device Register (Power-On Default 1000000(VID4))
Name VID4 Reserved
Read Read/Write
Description VID4 Input from Pentium®
Table XVII. Register 4Bh, Temperature Configuration Register (Power-On Default 01h)
Name Temperature Interrupt Mode Select Bits
Read/Write
Description this register both zero one, this selects default interrupt mode, which gives user interrupt temperature goes above limit. interrupt will cleared once status register read, will again generated when next conversion completed. will continue until temperature goes below hysteresis limit. selects one-time interrupt mode, which gives user interrupt when temperature goes above limit. interrupt will cleared once status register read. Another interrupt will generated until temperature first goes below hysteresis limit. more interrupts will generated until temperature again goes above limit. corresponding will cleared status register every time read, again when next conversion done. Note that this power-up default mode. selects comparator mode. This gives when temperature exceeds limit. This remains active until temperature goes below limit hysteresis), when will become inactive. Default 00000 Temperature Reading 0.5°C
Reserved Temp
Read/Write Read only
Pentium registered trademark Intel Corp.
REV.
-21-
ADM9240
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
24-Lead TSSOP (RU-24)
0.311 (7.90) 0.303 (7.70)
0.177 (4.50) 0.169 (4.30)
0.006 (0.15) 0.002 (0.05)
0.0433 (1.10) 0.0256 (0.65) 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
0.256 (6.50) 0.246 (6.25)
SEATING PLANE
0.028 (0.70) 0.020 (0.50)
-22-
REV.
PRINTED U.S.A.
C3295-8-3/98
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