SHARC® Microcomputer ADSP-21160M FEATURES (12.5 Core Instruction
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SUMMARY High-Performance 32-Bit DSP-Applications Audio, Medical, Military, Graphics, Imaging, Communication Super Harvard Architecture-Four Independent Buses Dual Data Fetch, Instruction Fetch, Nonintrusive, Zero-Overhead Backwards-Compatible-Assembly Source Level Compatible with Code ADSP-2106x DSPs (SIMD) Computational Architecture-Two 32-Bit IEEE Floating-Point Computation Units, Each with Multiplier, ALU, Shifter, Register File Integrated Peripherals-Integrated Processor, On-Chip Dual-Ported SRAM, Glueless Multiprocessing Features, Ports (Serial, Link, External Bus, JTAG)
SHARC® Microcomputer ADSP-21160M
FEATURES (12.5 Core Instruction Rate Single-Cycle Instruction Execution, Including SIMD Operations Both Computational Units MFLOPS Peak MFLOPS Sustained Performance (Based FIR) Dual Data Address Generators (DAGs) with Modulo Bit-Reverse Addressing Zero-Overhead Looping Single-Cycle Loop Setup, Providing Efficient Program Sequencing IEEE 1149.1 JTAG Standard Test Access Port On-Chip Emulation 400-Ball Metric PBGA Package
FUNCTIONAL BLOCK DIAGRAM
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SHARC registered trademark Analog Devices, Inc.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O.Box 9106, Norwood, 02062-9106, U.S.A. Tel:781/329-4700 World Wide Site: http://www.analog.com Fax:781/326-8703 Analog Devices, Inc., 2001
ADSP-21160M
FEATURES (CONTINUED) Single Instruction Multiple Data (SIMD) Architecture Provides: Computational Processing Elements Concurrent Execution-Each Processing Element Executes Same Instruction, Operates Different Data Code Compatibility-at Assembly Level, Uses Same Instruction ADSP-2106x SHARC DSPs Parallelism Buses Computational Units Allows: Single-cycle Execution (with without SIMD) Multiply Operation, Operation, Dual Memory Read Write, Instruction Fetch Transfers Between Memory Core Four 32-Bit Floating- Fixed-Point Words Cycle Accelerated Butterfly Computation Through Multiply with Subtract On-Chip Dual-Ported SRAM Independent Access Core Processor, Host, Controller supports: Zero-Overhead Channels Transfers Between ADSP-21160M Internal Memory External Memory, External Peripherals, Host Processor, Serial Ports, Link Ports 64-Bit Background Transfers Core Clock Speed, Parallel with Full-Speed Processor Execution 560M Bytes/s Transfer Rate Over Host Processor Interface 32-Bit Microprocessors Word Address Range Off-Chip Memory Memory Interface Supports Programmable Wait State Generation Page-Mode Off-Chip Memory Multiprocessing Support Provides: Glueless Connection Scalable Multiprocessing Architecture Distributed On-Chip Arbitration Parallel Connect ADSP-21160Ms plus Host Link Ports Point-To-Point Connectivity Array Multiprocessing Serial Ports Provide: Bit/s Synchronous Serial Ports with Companding Hardware Independent Transmit Receive Functions Support Interfaces 64-Bit Wide Synchronous External Port Provides: Glueless Connection Asynchronous SBSRAM External Memories Operation GENERAL DESCRIPTION
ADSP-21160M SHARC first processor family featuring Analog Devices' Super Harvard Architecture. Easing portability, ADSP-21160M application source code compatible with first generation ADSP-2106x SHARC DSPs SISD (Single Instruction, Single Data) mode. take advantage processor's SIMD (Single Instruction, Multiple Data) capability, some code changes needed. Like other SHARCs, ADSP-21160M 32-bit processor that optimized high performance applications. ADSP-21160M includes core, dual-ported on-chip SRAM, integrated processor with multiprocessing support, multiple internal buses eliminate bottlenecks. ADSP-21160M introduces Single-Instruction, Multiple-Data (SIMD) processing. Using computational units (ADSP-2106x SHARC DSPs have one), ADSP-21160M double performance versus ADSP-2106x range algorithms. Fabricated state art, high speed, power CMOS process, ADSP-21160M 12.5 instruction cycle time. With SIMD computational hardware running MHz, ADSP-21160M perform million math operations second. Table shows performance benchmarks ADSP-21160M.
Table ADSP-21160M Benchmarks Benchmark Algorithm Speed
1024 Point Complex (Radix with reversal) Filter (per tap) Filter (per biquad) Matrix Multiply (pipelined) Matrix Multiply (pipelined) Divide (y/x) Inverse Square Root Transfer Rate
6.25 56.25 37.5 56.25 560M Bytes/s
These benchmarks provide single-channel extrapolations measured dual-channel processing performance. more information benchmarking optimizing code single- dual-channel processing, Analog Devices's website. ADSP-21160M continues SHARC's industry-leading standards integration DSPs, combining high-performance 32-bit core with integrated, on-chip system features. These features include dual ported SRAM memory, host processor interface, processor that supports channels, serial ports, link ports, external parallel bus, glueless multiprocessing. REV.
ADSP-21160M
functional block diagram page shows block diagram ADSP-21160M, illustrating following architectural features: processing elements, each made ALU, Multiplier, Shifter, Data Register File Data Address Generators (DAG1, DAG2) Program sequencer with instruction cache buses capable supporting four 32-bit data transfers between memory core every core processor cycle Interval timer On-Chip SRAM Mbit) External port that supports: Interfacing off-chip memory peripherals Glueless multiprocessing support ADSP-21160M SHARCs Host port controller Serial ports link ports JTAG test access port Figure shows typical single-processor system. multiprocessing system appears Figure
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ADSP-21160M Family Core Architecture
ADSP-21160M includes following architectural features ADSP-2116x family core. ADSP-21160M code compatible assembly level with ADSP-21060, ADSP-21061, ADSP-21062.
SIMD Computational Engine
ADSP-21160M contains computational processing elements that operate Single Instruction Multiple Data (SIMD) engine. processing elements referred PEY, each contains ALU, multiplier, shifter, register file. always active, enabled setting PEYEN mode MODE1 register. When this mode enabled, same instruction executed both processing elements, each processing element operates different data. This architecture efficient executing math-intensive algorithms. Entering SIMD mode also effect data transferred between memory processing elements. When SIMD mode, twice data bandwidth required sustain computational operation processing elements. Because this requirement, entering SIMD mode also doubles bandwidth between memory processing elements. When using DAGs transfer data SIMD mode, data values transferred with each access memory register file.
Independent, Parallel Computation Units
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Within each processing element computational units. computational units consist arithmetic/logic unit (ALU), multiplier, shifter. These units perform single-cycle instructions. three units within each processing element arranged parallel, maximizing computational throughput. Single multifunction instructions execute parallel multiplier operations. SIMD mode, parallel multiplier operations occur both processing elements. These computation units support IEEE 32-bit single-precision floating-point, 40-bit extended precision floating-point, 32-bit fixed-point data formats.
Data Register File
general-purpose data register file contained each processing element. register files transfer data between computation units data buses, store intermediate results. These 10-port, 32-register primary, secondary) register files, combined with ADSP-2116x enhanced Harvard architecture, allow unconstrained data flow between computation units internal memory. registers referred R0-R15 S0-S15.
Single-Cycle Fetch Instruction Four Operands
Figure Single-Processor System
ADSP-21160M features enhanced Harvard architecture which data memory (DM) transfers data, program memory (PM) transfers both instructions data (see functional block diagram page REV.
ADSP-21160M
With ADSP-21160M's separate program data memory buses on-chip instruction cache, processor simultaneously fetch four operands instruction (from cache), single cycle.
Instruction Cache
ADSP-21160M includes on-chip instruction cache that enables three-bus operation fetching instruction four data values. cache selective-only instructions whose fetches conflict with data accesses cached. This cache allows full-speed execution core, providing looped operations such digital filter multiply- accumulates butterfly processing.
Data Address Generators with Hardware Circular Buffers
between 32-bit floating-point 16-bit floating-point formats done single instruction. While each memory block store combinations code data, accesses most efficient when block stores data, using transfers, other block stores instructions data, using transfers. Using this way, with dedicated each memory block, assures single-cycle execution with data transfers. this case, instruction must available cache.
Off-Chip Memory Peripherals Interface
ADSP-21160M's data address generators (DAGs) used indirect addressing provide implementing circular data buffers hardware. Circular buffers allow efficient programming delay lines other data structures required digital signal processing, commonly used digital filters Fourier transforms. DAGs ADSP-21160M contain sufficient registers allow creation circular buffers primary register sets, secondary). DAGs automatically handle address pointer wraparound, reducing overhead, increasing performance, simplifying implementation. Circular buffers start memory location.
Flexible Instruction
ADSP-21160M's external port provides processor's interface off-chip memory peripherals. word off-chip address space included ADSP-21160M's unified address space. separate on-chip buses-for addresses, data, addresses, data, addresses, data-are multiplexed external port create external system with single 32-bit address single 64-bit data bus. lower bits external data connect even addresses upper bits connect addresses. Every access external memory based address that fetches 32-bit word, with 64-bit bus, address locations accessed once. When fetching instruction from external memory, 32-bit data locations being accessed bits unused). Figure shows alignment various accesses external memory. external port supports asynchronous, synchronous, synchronous burst accesses. synchronous burst SRAM interfaced gluelessly. Addressing external memory devices facilitated on-chip decoding high-order address lines generate memory bank select signals. Separate control lines also generated simplified addressing page-mode DRAM. ADSP-21160M provides programmable memory wait states external memory acknowledge controls allow interfacing DRAM peripherals with variable access, hold, disable time requirements.
Controller
48-bit instruction word accommodates variety parallel operations, concise programming. example, ADSP-21160M conditionally execute multiply, add, subtract, both processing elements, while branching, single instruction.
ADSP-21160M Memory Interface Features
Augmenting ADSP-2116x family core, ADSP-21160M adds following architectural features:
Dual-Ported On-Chip Memory
ADSP-21160M contains four megabits on-chip SRAM, organized blocks Mbits each, which configured different combinations code data storage. Each memory block dual-ported single-cycle, independent accesses core processor processor. dual-ported memory combination with three separate on-chip buses allows data transfers from core from processor, single cycle. ADSP-21160M, memory configured maximum 128K words 32-bit data, 256K words 16-bit data, words 48-bit instructions 40-bit data), combinations different word sizes four megabits. memory accessed 16-bit, 32-bit, 48-bit, 64-bit words. 16-bit floating-point storage format supported that effectively doubles amount data that stored on-chip. Conversion
ADSP-21160M's on-chip controller allows zero-overhead data transfers without processor intervention. controller operates independently invisibly processor core, allowing operations occur while core simultaneously executing program instructions. transfers occur between ADSP-21160M's internal memory external memory, external peripherals, host processor. transfers also occur between ADSP-21160M's internal memory serial ports link ports. External packing 16-, 32-, 48-, 64-bit words performed during transfers. Fourteen channels available ADSP-21160M-six link ports, four serial ports, four processor's external port (for either REV.
ADSP-21160M
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Figure ADSP-21160M External Data Alignment Options
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rotating priority. lock allows indivisible read-modify-write sequences semaphores. vector interrupt provided interprocessor commands. Maximum throughput interprocessor data transfer 320M bytes/s over external port. Broadcast writes allow simultaneous transmission data ADSP-21160Ms used implement reflective semaphores. link ports provide second method multiprocessing communications. Each link port support communications another ADSP-21160M. Using links, large multiprocessor system constructed fashion. Systems link ports cluster multiprocessing concurrently independently.
Link Ports
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Figure ADSP-21160M Memory
host processor, other ADSP-21160Ms, memory transfers). Programs downloaded ADSP-21160M using transfers. Asynchronous off-chip peripherals control channels using Request/Grant lines (DMAR1-2, DMAG1-2). Other features include interrupt generation upon completion transfers, two-dimensional DMA, chaining automatic linked transfers.
Multiprocessing
ADSP-21160M offers powerful features tailored multiprocessing systems shown Figure external port link ports provide integrated glueless multiprocessing support. external port supports unified address space (see Figure that allows direct interprocessor accesses each ADSP-21160M's internal memory. Distributed arbitration logic included on-chip simple, glueless connection systems containing ADSP-21160Ms host processor. Master processor changeover incurs only cycle overhead. arbitration selectable either fixed REV.
ADSP-21160M features 8-bit link ports that provide additional capabilities. With capability running rates, each link port support bytes/s. Link port especially useful point-to-point interprocessor communication multiprocessing systems. link ports operate independently simultaneously. Link port data packed into 32-bit words, directly read core processor DMA-transferred on-chip memory. Each link port double-buffered input output registers. Clock/acknowledge handshaking controls link port transfers. Transfers programmable either transmit receive. data throughput information, link port timing details Table page
Serial Ports
ADSP-21160M features synchronous serial ports that provide inexpensive interface wide variety digital mixed-signal peripheral devices. serial ports operate half clock rate core, providing each with maximum data rate bit/s. Independent
ADSP-21160M
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tle-endian big-endian transmission formats, with word lengths selectable from bits bits. They offer selectable synchronization transmit modes well optional µ-law A-law companding. Serial port clocks frame syncs internally externally generated.
Host Processor Interface
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ADSP-21160M host interface allows easy connection standard microprocessor buses, both 16-bit 32-bit, with little additional hardware required. host interface accessed through ADSP-21160M's external port memory-mapped into unified address space. Four channels available host interface; code data transfers accomplished with software overhead. host processor communicates with ADSP-21160M's external with host request (HBR), host grant (HBG), ready (REDY), acknowledge (ACK), chip select (CS) signals. host directly read write internal memory ADSP-21160M, access channel setup mailbox registers. Vector interrupt support provides efficient execution host commands.
Program Booting
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internal memory ADSP-21160M booted system power-up from 8-bit EPROM, host processor, through link ports. Selection boot source controlled (Boot Memory Select), EBOOT (EPROM Boot), LBOOT (Link/Host Boot) pins. 32-bit 16-bit host processors used booting.
Phased Locked Loop
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ADSP-21160M uses on-chip generate internal clock core. Ratios 2:1, 3:1, between core CLKIN supported. CLK_CFG pins used select ratio. CLKIN rate rate which synchronous external port operates.
Power Supplies
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ADSP-21160M separate power supply connections internal (VDDINT), external (VDDEXT), analog (AVDD/AGND) power supplies. internal analog supplies must meet requirement. external supply must meet requirement. external supply pins must connected same supply. Note that analog supply (AVDD) powers ADSP-21160M's clock generator PLL. produce stable clock, system must provide external circuit filter power input AVDD pin. Place filter close possible pin. example circuit, Figure prevent noise coupling, wide trace analog ground (AGND) signal install decoupling capacitor close possible pin.
Figure Shared Memory Multiprocessing System
transmit receive functions provide greater flexibility serial communications. Serial port data automatically transferred from on-chip memory dedicated DMA. Each serial ports offers multichannel mode. serial ports operate with lit-
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ADSP-21160M
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ADSP-2116x development tools, including syntax highlighting VisualDSP++ editor. This capability permits: Control development tools process inputs generate outputs. Maintain one-to-one correspondence with tool's command line switches. Analog Devices' emulators IEEE 1149.1 JTAG test access port ADSP-21160M processor monitor control target board processor during emulation. emulator provides full-speed emulation, allowing inspection modification memory, registers, processor stacks. Nonintrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting ADSP-2116x processor family. Hardware tools include ADSP-2116x plug-in cards. Third Party software tools include libraries, real-time operating systems, block diagram design tools.
Designing Emulator-Compatible Board (Target)
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ADSP-21160M supported with complete software hardware development tools, including Analog Devices' emulators VisualDSP++1 development environment. same emulator hardware that supports other ADSP-2116x DSPs, also fully emulates ADSP-21160M. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy-to-use assembler that based algebraic syntax; archiver (librarian/library builder), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ run-time library that includes mathematical functions. points these tools are: Compiled ADSP-2116x C/C++ code efficiency-the compiler been developed efficient translation C/C++ code ADSP-2116x assembly. architectural features that improve efficiency compiled C/C++ code. ADSP-2106x family code compatibility-The assembler legacy features ease conversion existing ADSP-2106x applications ADSP-2116x. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information) Insert break points conditional breakpoints registers, memory, stacks Trace instruction execution Perform linear statistical profiling program execution Fill, dump, graphically plot contents memory Source level debugging Create custom debugger windows VisualDSP++ lets programmers define manage software development. dialog boxes property pages programmers configure manage
White Mountain (Product Line Analog Devices, Inc.) family emulators tools that every developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) each JTAG DSP. emulator uses access internal features DSP, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. must halted send data commands, once operation been completed emulator, system running full speed with impact system timing. these emulators, target's design must include interface between Analog Devices' JTAG emulation header custom target board.
Target Board Header
emulator interface Analog Devices' JTAG 14-pin header, shown Figure customer must supply this header target board order communicate with emulator. interface consists standard dual 0.025" square post header, 0.1" 0.1" spacing, with minimum post length 0.235". position used prevent from being inserted backwards. This must clipped target board.
VisualDSP++ registered trademark Analog Devices, Inc.
REV.
ADSP-21160M
Also, clearance (length, width, height) around header must considered. Leave clearance least 0.15" 0.10" around length width header, reserve height clearance attach detach connector.
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Figure JTAG Target Board Connector with Local Boundary Scan
Figure JTAG Target Board Connector JTAG Equipped Analog Devices (Jumpers Place)
seen Figure there sets signals header. There standard JTAG signals TMS, TCK, TDI, TDO, TRST, used emulation purposes (via emulator). There also secondary JTAG signals BTMS, BTCK, BTDI, BTRST that optionally used board-level (boundary scan) testing. When emulator connected this header, place jumpers across BTMS, BTCK, BTRST, BTDI shown Figure This holds JTAG signals correct state allow free. Remove jumpers when connecting emulator JTAG header.
JTAG Emulator Connector
Figure JTAG Connector Dimensions Design-for-Emulation Circuit Information
Figure details dimensions JTAG connector 14-pin target end. Figure displays keep-out area target board header. keep-out area allows connector properly seat onto target board header. This board area should contain components (chips, resistors, capacitors, etc.). dimensions referenced center 0.25" square post pin.
details target board design issues including: single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, EE-68: Analog Devices JTAG Emulation Technical Reference Analog Devices website-use site search "EE-68" (www.analog.com). This document updated regularly keep pace with improvements emulator support.
Additional Information
This data sheet provides general overview ADSP-21160M architecture functionality. detailed information ADSP-2116x Family core architecture instruction set, refer ADSP-2116x SHARC Hardware Reference.
FUNCTION DESCRIPTIONS
Figure JTAG Connector Keep-Out
ADSP-21160M definitions listed below. Inputs identified synchronous must meet timing requirements with respect CLKIN with respect TMS, TDI). Inputs identified asynchronous asserted asynchronously CLKIN TRST). REV.
ADSP-21160M
Unused inputs should tied pulled GND, except ADDR31-0, DATA63-0, FLAG3-0, inputs that have internal pull-up pull-down resistors (PA, ACK, BRST, PAGE, CLKOUT, MS3-0, RDx, WRx, DMARx, DMAGx, DTx, DRx, TCLKx, RCLKx, LxDAT7-0, LxCLK, LxACK, TMS, TRST TDI)-these pins left floating. These pins have logic-level hold circuit (only enabled ADSP-21160M with ID2-0 00x) that prevents input from floating internally.
Table Function Descriptions Type Function
following symbols appear Type column Table Asynchronous, Ground, Input, Output, Power Supply, Synchronous, (A/D) Active Drive, (O/D) Open Drain, Three-State (when SBTS asserted, when ADSP-21160M slave).
ADDR31-0
I/O/T
DATA63-0
I/O/T
MS3-0
I/O/T
I/O/T
I/O/T
I/O/T
PAGE
External Address. ADSP-21160M outputs addresses external memory peripherals these pins. multiprocessor system, master outputs addresses read/writes internal memory registers other ADSP-21160Ms. ADSP-21160M inputs addresses when host processor multiprocessing master reading writing internal memory registers. keeper latch DSP's ADDR31-0 pins maintains input level last driven (only enabled ADSP-21160M with ID2-0 00x). External Data. ADSP-21160M inputs outputs data instructions these pins. Pull-up resistors unused DATA pins necessary. keeper latch DSP's DATA63-0 pins maintains input level last driven (only enabled ADSP-21160M with ID2-0 00x). Memory Select Lines. These outputs asserted (low) chip selects corresponding banks external memory. Memory bank size must defined SYSCON control register. MS3-0 outputs decoded memory address lines. asyn- chronous access mode, MS3-0 outputs transition with other address outputs. synchronous access modes, MS3-0 outputs assert with other address lines; however, they de-assert after first CLKIN cycle which sampled asserted. Memory Read Strobe. asserted whenever ADSP-21160M reads from word external memory from internal memory other ADSP-21160Ms. External devices, including other ADSP-21160Ms, must assert reading from word ADSP-21160M internal memory. multiprocessing system, driven master. Memory Read High Strobe. asserted whenever ADSP-21160M reads from high word external memory from internal memory other ADSP-21160Ms. External devices, including other ADSP-21160Ms, must assert reading from high word ADSP-21160M internal memory. multiprocessing system, driven master. Memory Write Strobe. asserted when ADSP-21160M writes word external memory internal memory other ADSP-21160Ms. External devices must assert writing ADSP-21160M's word internal memory. multiprocessing system, driven master. Memory Write High Strobe. asserted when ADSP-21160M writes high word external memory internal memory other ADSP-21160Ms. External devices must assert writing ADSP-21160M's high word internal memory. multiprocessing system, driven master. DRAM Page Boundary. ADSP-21160M asserts this signal that external DRAM page boundary been crossed. DRAM page size must defined ADSP-21160M's memory control register (WAIT). DRAM only implemented external memory Bank PAGE signal only activated Bank accesses. multiprocessing system PAGE output master. keeper latch DSP's PAGE maintains output level last driven (only enabled ADSP-21160M with ID2-0 00x).
REV.
ADSP-21160M
Table Function Descriptions (Continued) Type Function
BRST
I/O/T
I/O/S
SBTS
IRQ2-0 FLAG3-0 TIMEXP
I/O/A
REDY DMAR1 DMAR2 ID2-0
(O/D)
DMAG1
Sequential Burst Access. BRST asserted ADSP-21160M host indicate that data associated with consecutive addresses being read written. slave device samples initial address increments internal address counter after each transfer. incremented address pipelined bus. burst access read from host ADSP-21160M, ADSP-21160M automatically increments address long BRST asserted. BRST asserted after initial access burst transfer. asserted every cycle after that, except last data request cycle (denoted asserted BRST negated). keeper latch DSP's BRST maintains input level last driven (only enabled ADSP-21160M with ID2-0 00x). Memory Acknowledge. External devices de-assert (low) wait states external memory access. used devices, memory controllers, other peripherals hold completion external memory access. ADSP-21160M deasserts output wait states synchronous access internal memory. keeper latch DSP's maintains input level last driven (only enabled ADSP-21160M with ID2-0 00x). Suspend Three-State. External devices assert SBTS (low) place external address, data, selects, strobes high impedance state following cycle. ADSP-21160M attempts access external memory while SBTS asserted, processor will halt memory access will completed until SBTS deasserted. SBTS should only used recover from host processor and/or ADSP-21160M deadlock used with DRAM controller. Interrupt Request Lines. These sampled rising edge CLKIN either edge-triggered level-sensitive. Flag Pins. Each configured control bits either input output. input, tested condition. output, used signal external peripherals. Timer Expired. Asserted four CLKIN cycles when timer enabled TCOUNT decrements zero. Host Request. Must asserted host processor request control ADSP-21160M's external bus. When asserted multiprocessing system, ADSP-21160M that master will relinquish assert HBG. relinquish bus, ADSP-21160M places address, data, select, strobe lines high impedance state. priority over ADSP-21160M requests (BR6-1) multiprocessing system. Host Grant. Acknowledges request, indicating that host processor take control external bus. asserted (held low) ADSP-21160M until released. multiprocessing system, output ADSP-21160M master monitored others. Chip Select. Asserted host processor select ADSP-21160M. Host Acknowledge. ADSP-21160M deasserts REDY (low) waitstates host access when inputs asserted. Request (DMA Channel 11). Asserted external port devices request services. Request (DMA Channel 12). Asserted external port devices request services. Multiprocessing Determines which multiprocessing request (BR1-BR6) used ADSP-21160M. corresponds BR1, corresponds BR2, single-processor systems. These lines system configuration selection which should hardwired only changed reset. Grant (DMA Channel 11). Asserted ADSP-21160M indicate that requested starts next cycle. Driven master only.
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ADSP-21160M
Table Function Descriptions (Continued) Type Function
DMAG2 BR6-1
I/O/S
RPBA
I/O/T
TCLKx RCLKx TFSx RFSx LxDAT7-0 LxCLK LxACK EBOOT LBOOT
I/O/T
CLKIN
CLK_CFG3-0
CLKOUT
RESET
Grant (DMA Channel 12). Asserted ADSP-21160M indicate that requested starts next cycle. Driven master only. Multiprocessing Requests. Used multiprocessing ADSP-21160Ms arbitrate mastership. ADSP-21160M only drives line (corresponding value ID2-0 inputs) monitors others. multiprocessor system with less than ADSP-21160Ms, unused pins should pulled high; processor's line must pulled high because output. Rotating Priority Arbitration Select. When RPBA high, rotating priority multiprocessor arbitration selected. When RPBA low, fixed priority selected. This signal system configuration selection which must same value every ADSP-21160M. value RPBA changed during system operation, must changed same CLKIN cycle every ADSP-21160M. Priority Access. Asserting allows ADSP-21160M slave interrupt background transfers gain access external bus. connected ADSP-21160Ms system. access priority required system, should left unconnected. Data Transmit (Serial Ports Each internal pull-up resistor. Data Receive (Serial Ports Each internal pull-up resistor. Transmit Clock (Serial Ports Each TCLK internal pull-up resistor. Receive Clock (Serial Ports Each RCLK internal pull-up resistor. Transmit Frame Sync (Serial Ports Receive Frame Sync (Serial Ports Link Port Data (Link Ports 0-5). Each LxDAT internal pull-down resistor that enabled disabled LPDRD LCTL0-1 register. Link Port Clock (Link Ports 0-5). Each LxCLK internal pull-down resistor that enabled disabled LPDRD LCTL0-1 register. Link Port Acknowledge (Link Ports 0-5). Each LxACK internal pull-down resistor that enabled disabled LPDRD LCOM register. EPROM Boot Select. description this operates, Table This signal system configuration selection that should hardwired. Link Boot. description this operates, Table This signal system configuration selection that should hardwired. Boot Memory Select. Serves output input selected with EBOOT LBOOT pins; Table This input system configuration selection that should hardwired. Local Clock CLKIN ADSP-21160M clock input. ADSP-21160M external port cycles frequency CLKIN. instruction cycle rate multiple CLKIN frequency; programmable power-up. CLKIN halted, changed, operated below specified frequency. Core/CLKIN Ratio Control. ADSP-21160M core clock (instruction cycle) rate equal CLKIN where user-selectable using CLK_CFG3-0 inputs. clock configuration definitions, RESET CLKIN section System Design chapter ADSP-21160 SHARC Hardware Reference manual. Local Clock Out. CLKOUT driven CLKIN frequency current master. This output three-stated when ADSP-21160M master, when host controls (HBG asserted). keeper latch DSP's CLKOUT maintains output level last driven (only enabled ADSP-21160M with ID2-0 00x). Processor Reset. Resets ADSP-21160M known state begins execution program memory location specified hardware reset vector address. RESET input must asserted (low) power-up. -11-
REV.
ADSP-21160M
Table Function Descriptions (Continued) Type Function
TRST
VDDINT VDDEXT AVDD
(O/D)
AGND
Test Clock (JTAG). Provides clock JTAG boundary scan. Test Mode Select (JTAG). Used control test state machine. internal pull-up resistor. Test Data Input (JTAG). Provides serial data boundary scan logic. internal pull-up resistor. Test Data Output (JTAG). Serial scan output boundary scan path. Test Reset (JTAG). Resets test state machine. TRST must asserted (pulsed low) after power-up held proper operation ADSP-21160M. TRST internal pull-up resistor. Emulation Status. Must connected ADSP-21160M emulator target board connector only. internal pull-up resistor. Core Instruction Fetch. Signal active when external instruction fetch performed. Driven master only. Three-state when host master. Core Power Supply. Nominally supplies DSP's core processor pins). Power Supply. Nominally pins). Analog Power Supply. Nominally supplies DSP's internal (clock generator). This same specifications VDDINT, except that added filtering circuitry required. more information, Power Supplies page Analog Power Supply Return. Power Supply Return. pins) Connect. Reserved pins that must left open unconnected pins).
Table Boot Mode Selection EBOOT LBOOT Booting Mode
Output (Input) (Input) (Input) (Input) (Input)
EPROM (Connect EPROM chip select.) Host Processor Link Port Booting. Processor executes from external memory. Reserved Reserved
-12-
REV.
ADSP-21160M ADSP-21160M SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
Signal Grade Parameter1 Unit
VDDINT AVDD VDDEXT VIH1 VIH2 TCASE
Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage2, VDDEXT =Max High Level Input Voltage3, VDDEXT =Max Level Input Voltage2,3, VDDEXT =Min Case Operating Temperature4
2.37 2.37 3.13 -0.5
2.63 2.63 3.47 VDDEXT +0.5 VDDEXT +0.5
Specifications subject change without notice. Applies input bidirectional pins: DATA63-0, ADDR31-0, RDx, WRx, ACK, SBTS, IRQ2-0, FLAG3-0, HBG, DMAR1, DMAR2, BR6-1, ID2-0, RPBA, BRST, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1. Applies input pins: CLKIN, RESET, TRST. Environmental Conditions page information thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter1 Test Conditions
Unit
IILPU1 IILPU2 IOZH IOZL IOZHPD IOZLPU1 IOZLPU2 IOZHA IOZLA IDD-INPEAK IDD-INHIGH IDD-INLOW IDD-IDLE AIDD
High Level Output Voltage Level Output Voltage2 High Level Input Current4,5,6 Level Input Current4 Level Input Current Pull-Up15 Level Input Current Pull-Up26 Three-State Leakage Current7,8,9,10 Three-State Leakage Current7 Three-State Leakage Current Pull-Down10 Three-State Leakage Current Pull-Up18 Three-State Leakage Current Pull-Up29 Three-State Leakage Current11 Three-State Leakage Current11 Supply Current (Internal)12 Supply Current (Internal)13 Supply Current (Internal)14 Supply Current (Idle)15 Supply Current (Analog)16 Input Capacitance17,18
VDDEXT =Min, =-2.0 VDDEXT =Min, =4.0 VDDEXT =Max, =VDD VDDEXT =Max, VDDEXT =Max, VDDEXT =Max, VDDEXT =Max, =VDD VDDEXT =Max, VDDEXT =Max, =VDD VDDEXT =Max, VDDEXT =Max,
1400
VDDEXT =Max, =VDD VDDEXT =Max, tCCLK =12.5 VDDINT =Max tCCLK =12.5 VDDINT =Max tCCLK =12.5 VDDINT =Max tCCLK =12.5 VDDINT =Max @AVDD =Max MHz, TCASE =25°C, =2.5
Specifications subject change without notice. Applies output bidirectional pins: DATA63-0, ADDR31-0, MS3-0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1, DMAG2, BR6-1, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, BMS, TDO, EMU. Output Drive Currents page typical drive current capabilities. Applies input pins: ACK, SBTS, IRQ2-0, HBR, ID2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, CLK_CFG3-0.
REV.
-13-
ADSP-21160M
Applies input pins with internal pull-ups: DR0, DR1. Applies input pins with internal pull-ups: DMARx, TMS, TDI, TRST. Applies three-statable pins: DATA63-0, ADDR31-0, PAGE, CLKOUT, ACK, FLAG3-0, REDY, HBG, BMS, BR6-1, TFSx, RFSx, TDO. Applies three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, EMU. Applies three-statable pins with internal pull-ups: MS3-0, RDx, WRx, DMAGx, CIF. Applies three-statable pins with internal pull-downs: LxDAT7-0, LxCLK, LxACK. Applies pulled internally with during reset ID2-0 00x.
test program used measure IDD-INPEAK represents worst case processor operation sustainable under normal application conditions. Actual internal power measurements made using typical applications less than specified. more information, Power Dissipation page IDDINHIGH composite average based range high activity code. more information, Power Dissipation page IDDINLOW composite average based range activity code. more information, Power Dissipation page Idle denotes ADSP-21160M state during execution IDLE instruction. more information, Power Dissipation page Characterized, tested. Applies signal pins. Guaranteed, tested.
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage (VDDINT)1 .-0.3 +3.0 Analog (PLL) Supply Voltage (AVDD) .-0.3 +3.0 External (I/O) Supply Voltage (VDDEXT) .-0.3 +4.6 Input Voltage. -0.5 VDDEXT +0.5 Output Voltage Swing -0.5 VDDEXT +0.5 Load Capacitance Storage Temperature Range Lead Temperature seconds)
Stresses greater than those listed above cause permanent damage device. These stress ratings only. Functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
SENSITIVITY
CAUTION: (electrostatic discharge) sensitive device. Electrostatic charges high 4000V readily accumulate human body test equipment discharge without detection. Although ADSP-21160M features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
-14-
REV.
ADSP-21160M
Timing Specifications
ADSP-21160M's internal clock switches higher frequencies than system input clock (CLKIN). generate internal clock, uses internal phase-locked loop (PLL). This PLL-based clocking minimizes skew between system clock (CLKIN) signal DSP's internal clock (the clock source external port logic pads). ADSP-21160M's internal clock multiple CLKIN) provides clock signal timing internal memory, processor core, link ports, serial ports, external port required read/write strobes asynchronous access mode). During reset, program ratio between DSP's internal clock frequency external (CLKIN) clock frequency with CLK_CFG3-0 pins. Even though internal clock clock source external port, external port clock always switches CLKIN frequency. determine switching frequencies serial link ports, divide down internal clock, using programmable divider control each port (TDIVx/RDIVx serial ports LxCLKD1-0 link ports). Note following definitions various clock periods that function CLKIN appropriate ratio control: tCCLK (tCK) tLCLK (tCCLK) tSCLK (tCCLK) Where: LCLK Link Port Clock SCLK Serial Port Clock CLKIN Clock Period tCCLK (Processor) Core Clock Period tLCLK Link Port Clock Period tSCLK Serial Port Clock Period Core/CLKIN Ratio 4:1, determined CLK_CFG3-0 reset) Link Port/Core Clock Ratio 4:1, determined LxCLKD) Serial Port/Core Clock Ratio (wide range, determined CLKDIV) exact timing information given. attempt derive parameters from addition subtraction others. While addition subtraction would yield meaningful results individual device, values given this data sheet reflect statistical variations worst cases. Consequently, meaningful parameters derive longer times. Figure under Test Conditions voltage reference levels.
Switching Characteristics specify processor changes signals. Circuitry external processor must designed compatibility with these signal characteristics. Switching characteristics describe what processor will given circumstance. switching characteristics ensure that timing requirement device connected processor (such memory) satisfied. Timing Requirements apply signals that controlled circuitry external processor, such data input read operation. Timing requirements guarantee that processor operates correctly with other devices.
REV.
-15-
ADSP-21160M
Clock Input Table Clock Input Parameter Unit
Timing Requirements: CLKIN Period tCKL CLKIN Width tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4V-2.0V)
&/.,1
10.5 10.5
Figure Clock Input Reset Table Reset Parameter Unit
Timing Requirements: RESET Pulsewidth Low1 tWRST tSRST RESET Setup Before CLKIN High2
4tCK
Applies after power-up sequence complete. power-up, processor's internal phase-locked loop requires more than while RESET low, assuming stable CLKIN (not including start-up time external clock oscillator). Only required multiple ADSP-21160Ms must come reset synchronous CLKIN with program counters (PC) equal. required multiple ADSP-21160Ms communicating over shared (through external port), because arbitration logic automatically synchronizes itself after reset.
&/.,1
Figure Reset
-16-
REV.
ADSP-21160M
Interrupts Table Interrupts Parameter Unit
Timing Requirements: IRQ2-0 Setup Before CLKIN High1 tSIR tHIR IRQ2-0 Hold After CLKIN High1 tIPW IRQ2-0 Pulsewidth2
2+tCK
Only required IRQx recognition following cycle. Applies only tSIR tHIR requirements met.
&/.,1
Figure Interrupts Timer Table Timer Parameter Unit
Switching Characteristic: CLKIN High TIMEXP tDTEX
&/.,1
Figure Timer
REV.
-17-
ADSP-21160M
Flags Table Flags Parameter Unit
Timing Requirements: FLAG3-0 Setup Before CLKIN High1 tSFI tHFI FLAG3-0 Hold After CLKIN High1 tDWRFI FLAG3-0 Delay After RDx/WRx Low1 tHFIWR FLAG3-0 Hold After RDx/WRx Deasserted1 Switching Characteristics: FLAG3-0 Delay After CLKIN High tDFO FLAG3-0 Hold After CLKIN High tHFO tDFOE CLKIN High FLAG3-0 Enable tDFOD CLKIN High FLAG3-0 Disable
Flag inputs meeting these setup hold times instruction cycle will affect conditional instructions instruction cycle N+2.
&/.,1
&/.,1
Figure Flags
-18-
REV.
ADSP-21160M
Memory Read-Bus Master
these specifications asynchronous interfacing memories (and memory-mapped peripherals) without reference CLKIN. These specifications apply when ADSP-21160M master accessing external
Table Memory Read-Bus Master Parameter
memory space asynchronous access mode. Note that timing ACK, DATA, RDx, WRx, DMAG strobe timing parameters only applies asynchronous access mode.
Unit
Timing Requirements: Address, CIF, Selects Delay Data 0.25tCCLK 11+W tDAD Valid1,2 Data Valid1,3 0.75tCK 11+W tDRLD tHDA Data Hold from Address, Selects4 tSDS Data Setup High1 tHDRH Data Hold from High3,4 tDAAK Delay from Address, Selects2,5 0.5tCCLK 12+W Delay from Low3,5 0.75tCCLK 11+W tDSAK tSAKC Setup CLKIN3,5 0.5tCCLK tHAKC Hold After CLKIN3 Switching Characteristics: Address, CIF, Selects Hold After 0.25tCCLK tDRHA High3 tDARL Address, CIF, Selects Low2 0.25tCCLK Pulse width3 0.5tCCLK High WRx, RDx, DMAGx Low3 0.5tCCLK 1+HI tRWR (number wait states specified WAIT register) tCK. address hold cycle idle cycle occurs, specified WAIT register; otherwise address hold cycle occurs specified WAIT register; otherwise
Data Delay/Setup: User must meet tDAD, tDRLD, tSDS. falling edge MSx, referenced. Note that timing ACK, DATA, RDx, WRx, DMAG strobe timing parameters only applies asynchronous access mode. Data Hold: User must meet tHDA tHDRH asynchronous access mode. Example System Hold Time Calculation page calculation hold times given capacitive loads. Delay/Setup: User must meet tDAAK, tDSAK, tSAKC deassertion (Low), three specifications must assertion (High).
&/.,1
Figure Memory Read-Bus Master
REV.
-19-
ADSP-21160M
Memory Write-Bus Master
these specifications asynchronous interfacing memories (and memory-mapped peripherals) without reference CLKIN. These specifications apply when ADSP-21160M master accessing external
Table Memory Write-Bus Master Parameter
memory space asynchronous access mode. Note that timing ACK, DATA, RDx, WRx, DMAG strobe timing parameters only applies asynchronous access mode.
Unit
Timing Requirements: Delay from Address, Selects1,2 0.5tCCLK-12+W tDAAK tDSAK Delay from Low1,3 0.75tCCLK 11+W Setup CLKIN1,3 0.5tCCLK tSAKC tHAKC Hold After CLKIN1,3 Switching Characteristics: Address, CIF, Selects 0.25tCCLK tDAWH Deasserted2,3 tDAWL Address, CIF, Selects Low2 0.25tCCLK Pulse width3 0.5tCCLK Data Setup before High3 0.25tCCLK 12.5+W tDDWH tDWHA Address Hold after Deasserted3 0.25tCCLK tDWHD Data Hold after Deasserted3 0.25tCCLK tDATRWH Data Disable after Deasserted3,4 0.25tCCLK 0.25tCCLK+2+H tWWR High WRx, RDx, DMAGx 0.5tCCLK 1+HI Low3 tDDWR Data Disable before 0.25tCCLK tWDE Data Enabled -0.25tCCLK (number wait states specified WAIT register) tCK. address hold cycle occurs, specified WAIT register; otherwise address hold cycle idle cycle occurs, specified WAIT register; otherwise idle cycle occurs, specified WAIT register; otherwise
Delay/Setup: User must meet tDAAK tDSAK tSAKC deassertion (Low), three specifications must assertion (High). falling edge MSx, referenced. Note that timing ACK, DATA, RDx, WRx, DMAG strobe timing parameters only applies asynchronous access mode. Example System Hold Time Calculation page calculation hold times given capacitive loads.
-20-
REV.
ADSP-21160M
&/.,1
Figure Memory Write-Bus Master
REV.
-21-
ADSP-21160M
Synchronous Read/Write-Bus Master
these specifications interfacing external memory systems that require CLKIN-relative timing accessing slave ADSP-21160M multiprocessor memory space). These synchronous switching characteristics also valid during asynchronous memory reads writes except where noted (see Memory Read-Bus Master page Memory Write-Bus Master page 20).
Table Synchronous Read/Write-Bus Master Parameter
When accessing slave ADSP-21160M, these switching characteristics must meet slave's timing requirements synchronous read/writes (see Synchronous Read/Write-Bus Slave page 24). slave ADSP-21160M must also meet these (bus master) timing requirements data acknowledge setup hold times.
Unit
Timing Requirements: Data Setup Before CLKIN1 tSSDATI tHSDATI Data Hold After CLKIN1 tSACKC Setup Before CLKIN1 tHACKC Hold After CLKIN1 Switching Characteristics: tDADDO Address, MSx, BMS, BRST, Delay After CLKIN tHADDO Address, MSx, BMS, BRST, Hold After CLKIN tDPGO PAGE Delay After CLKIN tDRDO High Delay After CLKIN1 tDWRO High Delay After CLKIN1 tDRWL RDx/WRx Delay After CLKIN tDDATO Data Delay After CLKIN tHDATO Data Hold After CLKIN tDACKMO Delay After CLKIN2 tACKMTR Disable Before CLKIN2 tDCKOO CLKOUT Delay After CLKIN tCKOP CLKOUT Period CLKOUT Width High tCKWH tCKWL CLKOUT Width
0.5tCCLK 0.25tCCLK 0.25tCCLK 0.25tCCLK 0.25tCCLK 0.25tCCLK tCK/2 tCK/2 0.25tCCLK+9 0.25tCCLK 0.25tCCLK 12.5 0.25tCCLK tCK3 tCK/2+23 tCK/2+23
Note that timing ACK, DATA, RDx, WRx, DMAG strobe timing parameters only applies synchronous access mode. Applies broadcast write, master precharge ACK. Applies only when drives operation; CLKOUT held inactive three-state otherwise, more information, System Design chapter ADSP-2116x SHARC Hardware Reference.
-22-
REV.
ADSP-21160M
&/.,1
&/.28
Figure Synchronous Read/Write-Bus Master
REV.
-23-
ADSP-21160M
Synchronous Read/Write-Bus Slave
these specifications ADSP-21160M master accesses slave's registers internal memory multiprocessor memory space). master must meet these (bus slave) timing requirements.
Table Synchronous Read/Write-Bus Slave Parameter Unit
Timing Requirements: Address, BRST Setup Before CLKIN tSADDI tHADDI Address, BRST Hold After CLKIN RDx/WRx Setup Before CLKIN tSRWI tHRWI RDx/WRx Hold After CLKIN tSSDATI Data Setup Before CLKIN tHSDATI Data Hold After CLKIN Switching Characteristics: Data Delay After CLKIN tDDATO tHDATO Data Hold After CLKIN tDACKC Delay After CLKIN Hold After CLKIN tHACKO
12.5
-24-
REV.
ADSP-21160M
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5($' &&(6
Figure Synchronous Read/Write-Bus Slave
REV.
-25-
ADSP-21160M
Multiprocessor Request Host Request
these specifications passing mastership between multiprocessing ADSP-21160Ms (BRx) host processor (HBR, HBG).
Table Multiprocessor Request Host Request Parameter Unit
Timing Requirements: RDx/WRx/CS Valid tHBGRCSV Setup Before CLKIN1 tSHBRI tHHBRI Hold After CLKIN1 tSHBGI Setup Before CLK/=']IN tHHBGI Hold After CLKIN High tSBRI BRx, Setup Before CLKIN tHBRI BRx, Hold After CLKIN High tSPAI Setup Before CLKIN tHPAI Hold After CLKIN High tSRPBAI RPBA Setup Before CLKIN tHRPBAI RPBA Hold After CLKIN Switching Characteristics: tDHBGO Delay After CLKIN tHHBGO Hold After CLKIN tDBRO Delay After CLKIN tHBRO Hold After CLKIN tDPASO Delay After CLKIN, Slave tTRPAS Disable After CLKIN, Slave tDPAMO Delay After CLKIN, Master tPATR Disable Before CLKIN, Master tDRDYCS REDY (O/D) (A/D) from Low2 REDY (O/D) Disable REDY (A/D) High from HBG2 tTRDYHG tARDYTR REDY (A/D) Disable from High2
0.25tCCLK 0.25tCCLK 0.5tCK
Only required recognition current cycle. (O/D) open drain, (A/D) active drive.
-26-
REV.
ADSP-21160M
&/.,1
3%$,
Figure Multiprocessor Request Host Request
REV.
-27-
ADSP-21160M
Asynchronous Read/Write-Host ADSP-21160M
these specifications (Table Table asynchronous host processor accesses ADSP-21160M, after host asserted (low). After
Table Read Cycle Parameter
returned ADSP-21160M, host drive pins access ADSP-21160M's internal memory registers. assumed this timing
Unit
Timing Requirements: Address Setup/CS Before tSADRDL tHADRDH Address Hold/CS Hold After tWRWH RDx/WRx High Width tDRDHRDY High Delay After REDY (O/D) Disable High Delay After REDY (A/D) Disable tDRDHRDY Switching Characteristics: Data Valid Before REDY Disable from tSDATRDY tDRDYRDL REDY (O/D) (A/D) Delay After tRDYPRD REDY (O/D) (A/D) Pulsewidth Read tHDARWH Data Disable After High
Figure Read Cycle (Asynchronous Read-Host ADSP-21160M)
-28-
REV.
ADSP-21160M
Table Write Cycle Parameter Unit
Timing Requirements: Setup Before tSCSWRL tHCSWRH Hold After High tSADWRH Address Setup Before High tHADWRH Address Hold After High Width tWWRL tWRWH RDx/WRx High Width tDWRHRDY High Delay After REDY (O/D) (A/D) Disable tSDATWH Data Setup Before High tHDATWH Data Hold After High Switching Characteristics: REDY (O/D) (A/D) Delay After WRx/CS tDRDYWRL tRDYPWR REDY (O/D) (A/D) Pulsewidth Write
5$,1
Figure Write Cycle (Asynchronous Write-Host ADSP-21160M)
REV.
-29-
ADSP-21160M
Three-State Timing-Bus Master Slave
These specifications show memory interface disabled (stops driving) enabled (resumes driving) relative CLKIN SBTS pin. This timing applicable master transition cycles (BTC) host transition cycles (HTC) well SBTS pin.
Table Three-State Timing-Bus Slave, HBR, SBTS Parameter Unit
Timing Requirements: tSTSCK SBTS Setup Before CLKIN tHTSCK SBTS Hold After CLKIN Switching Characteristics: Address/Select Enable After CLKIN tMIENA tMIENS Strobes Enable After CLKIN1 tMIENHG Enable After CLKIN tMITRA Address/Select Disable After CLKIN tMITRS Strobes Disable After CLKIN1 Disable After CLKIN tMITRHG tDATEN Data Enable After CLKIN2 tDATTR Data Disable After CLKIN2 tACKEN Enable After CLKIN2 tACKTR Disable After CLKIN2 tCDCEN CLKOUT Enable After CLKIN tCDCTR CLKOUT Disable After CLKIN tMTRHBG Memory Interface Disable Before Low3 tMENHBG Memory Interface Enable After High3
0.25tCCLK 0.25tCCLK tCCLK 0.25tCCLK 0.25tCCLK tCCLK
Strobes RDx, WRx, DMAGx. addition master transition cycles, these specs also apply master slave synchronous read/write. Memory Interface Address, RDx, WRx, MSx, PAGE, DMAGx, EPROM boot mode).
-30-
REV.
ADSP-21160M
&/.,1
&/.28
Figure Three-State Timing-Bus Slave, HBR, SBTS
REV.
-31-
ADSP-21160M
Handshake
These specifications describe three handshake modes. three modes DMAR used initiate transfers. handshake mode, DMAG controls latching enabling data externally. external handshake mode, data transfer controlled ADDR31-0, RDx, WRx, PAGE, MS3-0, ACK, DMAG signals. Paced
Table Handshake Parameter
Master mode, data transfer controlled ADDR31-0, RDx, WRx, MS3-0, (not DMAG). Paced Master mode, Memory Read-Bus Master, Memory Write-Bus Master, Synchronous Read/Write-Bus Master timing specifications ADDR31-0, RDx, WRx, MS3-0, PAGE, DATA63-0, also apply.
Unit
Timing Requirements: DMARx Setup Before CLKIN1 tSDRC tWDR DMARx Width (Nonsynchronous)2 tCCLK +4.5 tSDATDGL Data Setup After DMAGx Low3 0.75tCK tHDATIDG Data Hold After DMAGx High tDATDRH Data Valid After DMARx High3 tDMARLL DMARx Edge Edge4 tDMARH DMARx Width High2 tCCLK +4.5 Switching Characteristics: tDDGL DMAGx Delay After CLKIN 0.25tCCLK 0.25tCCLK tWDGH DMAGx High Width 0.5tCCLK 1+HI tWDGL DMAGx Width 0.5tCCLK tHDGC DMAGx High Delay After CLKIN 0.25tCCLK +1.5 0.25tCCLK tVDATDGH Data Valid Before DMAGx High5 0.25tCCLK 0.25tCCLK tDATRDGH Data Disable After DMAGx High6 0.25tCCLK 0.25tCCLK +1.5 tDGWRL Before DMAGx -1.5 tDGWRH DMAGx Before High 0.5tCCLK tDGWRR High Before DMAGx High7 -1.5 tDGRDL Before DMAGx -1.5 tDRDGH Before DMAGx High 0.5tCCLK -2+W High Before DMAGx High7 -1.5 tDGRDR tDGWR DMAGx High WRx, RDx, DMAGx 0.5tCCLK 2+HI Address/Select Valid DMAGx High tDADGH tDDGHA Address/Select Hold after DMAGx High (number wait states specified WAIT register) tCK. data idle cycle occurs, specified WAIT register; otherwise
Only required recognition current cycle. Maximum throughput using DMARx/DMAGx handshaking equals tWDR tDMARH (tCCLK +4.5) (tCCLK +4.5)=34ns (29.4 MHz). This throughput limit applies non-synchronous access mode only. tSDATDGL data setup requirement DMARx being used hold completion write. Otherwise, DMARx holds completion write, data driven tDATDRH after DMARx brought high. tDMARLL DMARx transitions synchronous with CLKIN. Otherwise, tWDR tDMARH. tVDATDGH valid DMARx being used hold completion read. DMARx used prolong read, then tVDATDGH .25tCCLK tCK) where equals number extra cycles that access prolonged. Example System Hold Time Calculation page calculation hold times given capacitive loads. This parameter applies synchronous access mode only.
-32-
REV.
ADSP-21160M
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7,'*
(;7(51$
1&+5 &,),&$7
Figure Handshake Timing
REV.
-33-
ADSP-21160M
Link Ports
Calculation link receiver data setup hold relative link clock required determine maximum allowable skew that introduced transmission path between LDATA LCLK. Setup skew maximum delay that introduced LDATA relative LCLK (setup skew tLCLKTWH tDLDCH tSLDCL). Hold skew maximum delay that introduced LCLK relative LDATA (hold skew tLCLKTWL tHLDCH tHLDCL). Calculations made directly from speed specifications will result unrealistically small skew times because they include multiple tester guardbands. Note that there two-cycle effect latency between link port enable instruction enabling link port. Maximum throughput varies across link port transmit/receive pairs. Table shows maximum throughput transmit/receive pairs based setup skew (setup skew=tLCLKTWH min-tDLDCH -tSLDCL =0.5 ns). Hold skew results indicate operation across link ports. hold time skews equal greater link port transmit/receive pairs MHz. Based upon these values, link port transmit/receive pairs operated maximum throughput LxCLK:CCLK ratios 2:1, 3:1, CCLK. operate link port transmit/receive pairs LxCLK:CCLK ratio 1:1, core clock frequency must greater than 62.5 MHz. Maximum data throughput values based upon reset value Link Port Assignment Register (Link Buffer assigned Link Port Link Buffer assigned Link Port etc.). Throughputs guaranteed settings other than reset value. additional details LAR, refer ADSP-21160 Hardware Reference manual.
Table Link Port-Maximum Data Throughput Transmit/Receive Pairs Transmit Link Port Receive Link Port Maximum Operating Frequency (MHz)
Table Link Port-Maximum Data Throughput Transmit/Receive Pairs (Continued) Transmit Link Port Receive Link Port Maximum Operating Frequency (MHz)
68.97 71.43 71.43 76.92 74.07 64.52 66.67 66.67 71.43 71.43 71.43 64.52 66.67 66.67 74.07 74.07 71.43 62.5 66.67 64.52 71.43 71.43 71.43
71.43 74.07 71.43 76.92 68.97 71.43 68.97 76.92 74.07
-34-
REV.
ADSP-21160M
Table Link Ports-Receive Parameter Unit
Timing Requirements: Data Setup Before LCLK tSLDCL tHLDCL Data Hold After LCLK tLCLKIW LCLK Period tLCLKRWL LCLK Width LCLK Width High tLCLKRWH Switching Characteristics: LACK Delay After LCLK High1 tDLALC
tLCLK
LACK goes with tDLALC relative rise LCLK after first nibble, doesn't receiver's link buffer about fill.
/&/.
/&/.
/&/.,:
/$/&
/$&.
Figure Link Ports-Receive
REV.
-35-
ADSP-21160M
Table Link Ports-Transmit Parameter Unit
Timing Requirements: LACK Setup Before LCLK High tSLACH tHLACH LACK Hold After LCLK High Switching Characteristics: Data Delay After LCLK High tDLDCH tHLDCH Data Hold After LCLK High tLCLKTWL LCLK Width LCLK Width High tLCLKTWH tDLACLK LCLK Delay After LACK High
/&/. /&/.
1,%%/(
0.5tLCLK 0.5tLCLK 0.5tLCLK 0.5tLCLK +1.5 0.5tLCLK +1.5 3tLCLK
1,%%/(
/&/.
/&/.
/$&.
/$&+ 8,5( /&/. ),56 1,%%/(
Figure Link Ports-Transmit
-36-
REV.
ADSP-21160M
Serial Ports
determine whether communication possible between devices clock speed following specifications must confirmed: frame sync delay frame sync setup hold, data delay data setup hold, SCLK width.
Table Serial Ports-External Clock Parameter Unit
Timing Requirements: TFS/RFS Setup Before TCLK/RCLK1 tSFSE tHFSE TFS/RFS Hold After TCLK/RCLK1,2 tSDRE Receive Data Setup Before RCLK1 tHDRE Receive Data Hold After RCLK1 tSCLKW TCLK/RCLK Width tSCLK TCLK/RCLK Period
2tCCLK
Referenced sample edge. hold after when minimum from drive edge. hold after late external minimum from drive edge.
Table Serial Ports-Internal Clock Parameter Unit
Timing Requirements: Setup Before TCLK1; Setup Before RCLK1 tSFSI TFS/RFS Hold After TCLK/RCLK1,2 tHFSI tSDRI Receive Data Setup Before RCLK1 tHDRI Receive Data Hold After RCLK1
Referenced sample edge. hold after when minimum from drive edge. hold after late external minimum from drive edge.
Table Serial Ports-External Internal Clock Parameter Unit
Switching Characteristics: Delay After RCLK (Internally Generated RFS)1 tDFSE tHOFSE Hold After RCLK (Internally Generated RFS)1
Referenced drive edge.
Table Serial Ports-External Clock Parameter Unit
Switching Characteristics: Delay After TCLK (Internally Generated TFS)1 tDFSE tHOFSE Hold After TCLK (Internally Generated TFS)1 tDDTE Transmit Data Delay After TCLK1 tHDTE Transmit Data Hold After TCLK1
Referenced drive edge.
Table Serial Ports-Internal Clock Parameter Unit
Switching Characteristics: tDFSI Delay After TCLK (Internally Generated TFS)1 tHOFSI Hold After TCLK (Internally Generated TFS)1 REV. -37-
-1.5
ADSP-21160M
Table Serial Ports-Internal Clock (Continued) Parameter Unit
tDDTI tHDTI tSCLKIW
Transmit Data Delay After TCLK Transmit Data Hold After TCLK1 TCLK/RCLK Width
0.5tSCLK 0.5tSCLK
Referenced drive edge.
Table Serial Ports-Enable Three-State Parameter Unit
Switching Characteristics: Data Enable from External TCLK1 tDDTEN tDDTTE Data Disable from External TCLK1 tDDTIN Data Enable from Internal TCLK1 tDDTTI Data Disable from Internal TCLK1
Referenced drive edge.
-38-
REV.
ADSP-21160M
&/.:
$//,1* 7&/. /,1*
$//,1* 7&/. /,1* 5&/.
5&/.
Figure Serial Ports
REV.
-39-
ADSP-21160M
Table Serial Ports-External Late Frame Sync Parameter Unit
Switching Characteristics: Data Delay from Late External External with tDDTLFSE tDDTENFS Data Enable from late
enable valid follow tDDTLFSE tDDTENFS.
+'7(
Figure External Late Frame Sync
-40-
REV.
ADSP-21160M
JTAG Test Access Port Emulation Table JTAG Test Access Port Emulation Parameter Unit
Timing Requirements: Period tTCK tSTAP TDI, Setup Before High tHTAP TDI, Hold After High tSSYS System Inputs Setup Before Low1 System Inputs Hold After Low1 tHSYS tTRSTW TRST Pulsewidth Switching Characteristics: Delay from tDTDO tDSYS System Outputs Delay After Low2
4tCK
System Inputs DATA63-0, ADDR31-0, RDx, WRx, ACK, SBTS, HBR, HBG, DMAR1, DMAR2, BR6-1, ID2-0, RPBA, IRQ2-0, FLAG3-0, BRST, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET. System Outputs DATA63-0, ADDR31-0, MS3-0, RDx, WRx, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6-1, BRST, CIF, FLAG3-0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7-0, LxCLK, LxACK, BMS.
Figure IEEE 11499.1 JTAG Test Access Port
REV.
-41-
ADSP-21160M
Output Drive Currents
Figure shows typical characteristics output drivers ADSP-21160M. curves represent current drive capability output drivers function output voltage.
6285&( &855(17
Figure ADSP-21160M Typical Drive Currents Power Dissipation
Total power dissipation components, internal circuitry switching external output drivers. Internal power dissipation dependent instruction execution sequence data operands involved. Using current specifications (IDDINPEAK, IDDINHIGH, IDDINLOW, IDDIDLE) from Electrical Characteristics page current-versus-operation information Table engineers estimate ADSP-21160M's internal power supply (VDDINT) input current specific application, according following formula:
Peak IDDINPEAK High DDINHIGH DDINLOW Idle DDIDLE DDINT
external component total power dissipation caused switching output pins. magnitude depends number output pins that switch during each cycle maximum frequency which they switch their load capacitance their voltage swing (VDD) PEXT VDD2
calculated
-42-
REV.
ADSP-21160M
load capacitance should include processor's package capacitance (CIN). switching frequency includes driving load high then back low. Address data pins drive high maximum rate
Table ADSP-21160M Operation Types Input Current Operation Peak Activity1 High Activity1 Activity1
1/(2tCK). write strobe switch every cycle frequency 1/tCK. Select pins switch 1/(2tCK), selects switch each cycle.
Instruction Type Instruction Fetch Core Memory Access2 Internal Memory External Memory Data pattern core memory access
Multifunction Cache cycle tCCLK cycles external port cycle Worst case
Multifunction Internal Memory cycle tCCLK cycles external port cycle Random
Single Function Internal Memory None None None
Peak Activity=IDDINPEAK, High Activity=IDDINHIGH, Activity=IDDINLOW. state PEYEN (SIMD versus SISD mode) does influence these calculations. These assume core clock ratio. more information ratios clocks (tCK tCCLK), timing ratio definitions page
REV.
-43-
ADSP-21160M
Example: Estimate PEXT with following assumptions: system with bank external data memory-asynchronous (64-bit) Four chips used, each with load
Table External Power Calculations (3.3 Device) Type Pins Switching VDD2 PEXT
External data memory writes occur every other cycle, rate 1/(4 tCK), with pins switching cycle time (tCK ns). PEXT equation calculated each class pins that drive:
Address Data CLKOUT
44.7 44.7 44.7 14.7
12.5 12.5 12.5
10.9 10.9 10.9 10.9 10.9
0.046 0.000 0.024 0.064 0.001 PEXT 0.135
typical power consumption calculated these conditions adding typical internal power dissipation: PTOTAL PEXT PINT PPLL Where: PEXT from Table PINT IDDINT 2.5V, using calculation IDDINT listed Power Dissipation page PPLL AIDD 2.5V, using value AIDD listed ABSOLUTE MAXIMUM RATINGS page Note that conditions causing worst-case PEXT different from those causing worst-case PINT. Maximum PINT cannot occur while 100% output pins switching from ones zeros. Note also that common application have 100% even outputs switching simultaneously.
Test Conditions
Output Enable Time
Output pins considered enabled when they have made transition from high impedance state when they start driving. output enable time tENA interval from when reference signal reaches high voltage level when output reached specified high trip point, shown Output Enable/Disable diagram (Figure 30). multiple pins (such data bus) enabled, measurement value that first start driving.
Example System Hold Time Calculation
test conditions timing parameters appearing ADSP-21160M specifications page include output disable time, output enable time, capacitive loading.
Output Disable Time
determine data output hold time particular system, first calculate tDECAY using equation given above. Choose difference between ADSP-21160M's output voltage input threshold device requiring hold time. typical will total capacitance (per data line), total leakage three-state current (per data line). hold time will tDECAY plus minimum disable time (i.e., tDATRWH write cycle).
Output pins considered disabled when they stop driving, into high impedance state, start decay from their output high voltage. time voltage decay dependent capacitive load, load current, This decay time approximated following equation: tDECAY (CLV)/IL output disable time tDIS difference between tMEASURED tDECAY shown Figure time tMEASURED interval from when reference signal switches when output voltage decays from measured output high output voltage. tDECAY calculated with test loads with equal
MEASURED
(MEASURED) (MEASURED) (MEASURED) (MEASURED) 2.0V 1.0V
DECAY
ITIO 1.5V
Figure Output Enable/Disable
-44-
REV.
ADSP-21160M
5,6( )$// 7,0(6
Figure Equivalent Device Loading Measurements (Includes Fixtures)
/2$' &$3$&,7$1&(
Figure Typical Output Rise Time (10%-90%, VDDEXT Min) Load Capacitance
Figure Voltage Reference Levels Measurements (Except Output Enable/Disable) Capacitive Loading
287387 '(/$< +2/'
Output delays holds based standard capacitive loads: pins (see Figure 31). delay hold specifications given should derated factor ns/50 loads other than nominal value Figure Figure show output rise time varies with capacitance. Figure graphically shows output delays holds vary with load capacitance. (Note that this graph derating does apply output disable delays; Output Disable Time page 44.) graphs Figure Figure Figure linear outside ranges shown.
/2$' &$3$&,7$1&(
Figure Typical Output Delay Hold Load Capacitance Case Temperature)
Environmental Conditions
5,6( )$// 7,0(6
5,6( 7,0(
ADSP-21160M tested performance over commercial temperature range, 85°C.
Thermal Characteristics
)$// 7,0(
/2$' &$3$&,7$1&(
ADSP-21160M packaged 400-ball Plastic Ball Grid Array (PBGA). ADSP-21160M specified case temperature (TCASE). ensure that TCASE data sheet specification exceeded, heatsink and/or flow source used. center block ground pins (PBGA balls: H8-13, J8-13, K8-13, L8-13, M8-13, N8-13) provide thermal pathways printed circuit board's ground plane. heatsink should attached ground plane close possible thermal pathways) with thermal adhesive.
Figure Typical Output Rise Time (10%-90%, VDDEXT Max) Load Capacitance
REV.
-45-
ADSP-21160M
CASE
TCASE Case temperature (measured surface package) Power dissipation (this value depends upon specific application; method calculating shown under Power Dissipation). Value from Table 6.46°C/W
Table Airflow Over Package Versus
Airflow (Linear Ft./Min.) (°C/W)1 °C/W.
12.13
9.86
400-BALL METRIC PBGA CONFIGURATIONS
Table lists assignments PBGA package, configurations diagram page shows assignment summary.
-46-
REV.
ADSP-21160M
Table 400-ball Metric PBGA Assignments Name PBGA Pin# Name PBGA Pin# Name PBGA Pin# Name PBGA Pin#
DATA[14] DATA[13] DATA[10] DATA[8] DATA[4] DATA[2] TRST RESET RPBA IRQ0 FLAG1 TIMEXP VDDEXT TFS1 RFS1 RCLK0 L0DAT[4] DATA[30] DATA[29] DATA[23] DATA[21] VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDEXT L1DAT[6] L1DAT[5] L1ACK L1DAT[1]
DATA[22] DATA[16] DATA[15] DATA[9] DATA[6] DATA[3] DATA[0] IRQ2 FLAG3 FLAG0 VDDEXT RCLK1 RFS0 TCLK0 L0DAT[5] L0DAT[2] DATA[34] DATA[33] DATA[27] DATA[26] VDDEXT VDDINT VDDINT VDDEXT L1DAT[4] L1DAT[3] L1DAT[0] L2DAT[7]
DATA[24] DATA[18] DATA[17] DATA[11] DATA[7] DATA[5] DATA[1] IRQ1 FLAG2 VDDEXT TCLK1 L0DAT[7] L0DAT[6] L0ACK L0DAT[0] DATA[38] DATA[35] DATA[32] DATA[31] VDDEXT VDDINT VDDINT VDDEXT L1DAT[2] L2DAT[6] L2DAT[4] L2CLK
DATA[28] DATA[25] DATA[20] DATA[19] DATA[12] VDDEXT VDDINT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDEXT TFS0 L1DAT[7] L0CLK L0DAT[3] L0DAT[1] L1CLK DATA[40] DATA[39] DATA[37] DATA[36] VDDEXT VDDINT VDDINT VDDEXT L2DAT[5] L2ACK L2DAT[3] L2DAT[1]
REV.
-47-
ADSP-21160M
Table 400-ball Metric PBGA Assignments (Continued) Name PBGA Pin# Name PBGA Pin# Name PBGA Pin# Name PBGA Pin#
DATA[44] DATA[43] DATA[42] DATA[41] VDDEXT VDDINT VDDINT VDDEXT L2DAT[2] L2DAT[0] DATA[48] DATA[51] VDDEXT VDDINT VDDINT VDDEXT L3DAT[5] L3DAT[6] L3DAT[4] L3CLK
CLK_CFG_0 DATA[46] DATA[45] DATA[47] VDDEXT VDDINT VDDINT VDDEXT DATA[49] DATA[50] DATA[52] DATA[55] VDDEXT VDDINT VDDINT VDDEXT L3DAT[2] L3DAT[1] L3DAT[3] L3ACK
CLKIN CLK_CFG_1 AGND CLK_CFG_2 VDDEXT VDDINT VDDINT VDDEXT REDY DATA[53] DATA[54] DATA[57] DATA[60] VDDEXT VDDINT VDDEXT L4DAT[5] L4DAT[6] L4DAT[7] L3DAT[0]
AVDD CLK_CFG_3 CLKOUT VDDEXT VDDINT VDDINT VDDEXT PAGE SBTS L3DAT[7] DATA[56] DATA[58] DATA[59] DATA[63] VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDEXT L4DAT[3] L4ACK L4CLK L4DAT[4]
-48-
REV.
ADSP-21160M
Table 400-ball Metric PBGA Assignments (Continued) Name PBGA Pin# Name PBGA Pin# Name PBGA Pin# Name PBGA Pin#
DATA[61] DATA[62] ADDR[3] ADDR[2] VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT L5DAT[7] L4DAT[0] L4DAT[1] L4DAT[2]
ADDR[4] ADDR[6] ADDR[7] ADDR[10] ADDR[14] ADDR[18] ADDR[22] ADDR[25] ADDR[28] ADDR[1] DMAR2 L5DAT[0] L5DAT[2] L5ACK L5DAT[4] L5DAT[6]
ADDR[5] ADDR[9] ADDR[12] ADDR[15] ADDR[17] ADDR[20] ADDR[23] ADDR[26] ADDR[29] ADDR[0] DMAG2 LBOOT L5DAT[1] L5DAT[3] L5DAT[5]
ADDR[8] ADDR[11] ADDR[13] ADDR[16] ADDR[19] ADDR[21] ADDR[24] ADDR[27] ADDR[30] ADDR[31] BRST DMAG1 DMAR1 EBOOT L5CLK
REV.
-49-
ADSP-21160M
400-BALL METRIC PBGA CONFIGURATIONS (BOTTOM VIEW, SUMMARY)
9''(;7
-50-
REV.
ADSP-21160M
OUTLINE DIMENSIONS
ADSP-21160M comes 27mm
27mm, 400-ball Metric PBGA package with rows balls.
400-BALL METRIC PBGA (B-400)
127(6 ,7,2
3/$1(
REV.
-51-
ADSP-21160M
ORDERING GUIDE Part Number1, Case Temperature Range On-Chip SRAM
Instruction Rate
Operating Voltage
ADSP-21160MKB-80
85°C
Mbit
INT/3.3
Plastic Ball Grid Array (PBGA) package. ADSP-21160N data sheet ordering information higher-performance derivative.
-52-
REV.
PRINTED U.S.A.
C02426-2.5-4/01(0)
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