Programmable Controller April 1999, ver. 1.01 Features
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a8237
Programmable Controller
April 1999, ver. 1.01
Features
a8237 MegaCore function implementing programmable direct memory access (DMA) controller Optimized FLEX® architecture Provides four independent channels Offers static read/write handshaking modes Includes direct set/reset capability Uses approximately 1,201 FLEX logic elements (LEs) Functionally based Intel 8237A Harris 82C37A devices, except noted "Variations Clarifications" page
General Description
a8237 MegaCore function implements programmable controller, which controls memory-to-peripheral memory-tomemory data transfers provides block memory initialization capability. Four independently programmable channels available a8237, requests made hardware software. Figure shows symbol a8237.
Figure a8237 Symbol
A8237
hlda neopin niorin niowin ready reset ain[3.0] dbin[7.0] dreq[3.0] adstb dben dmaenable neopout niorout niowout nmemr nmemw aout[7.0] dack[3.0] dbout[7.0]
Altera Corporation
A-DS-A8237-01.01
a8237 Programmable Controller
Table describes input output ports a8237 MegaCore function.
Table a8237 Ports (Part
Name
hlda neopin niorin niowin ready
Type
Input Input Input Input Input Input Input
Polarity
High High
Description
Clock. Used generate synchronize a8237 operations. Hold acknowledge. This signal from microprocessor indicates release system a8237. Chip select. When active, a8237 selected, read write transactions internal registers enabled. process. Permits external termination current service. read control. When niorin a8237 selected, read transactions from internal registers enabled. write control. When niowin a8237 selected, data asynchronously written into a8237. Ready. Extends read write pulses associated with slow memory peripherals. When ready low, wait states inserted until ready returns high. Reset. Clears command, status, request, temporary registers. Also clears byte pointer, mode register counter, controller state machine. Sets mask register requests ignored after initialization. Register address bus. Selects internal a8237 registers. Table page Data input. microprocessor writes data internal registers dbin[7.0] bus. request bus. Programmable polarity. Asynchronous signals from peripherals requesting service. Address strobe. Latches address from dbout[7.0] into external address latch. Address enable. Enables external address latch containing most significant address byte transfer. Data enable. Active when data registers read. Also active during transfers, allowing most significant (MSB) address latch output temporary register data during memory-to-memory writes. enable. Asserted during active cycle. create bidirectional signals from niorin, niorout, niowin, niowout signals, lower four bits address bus. Hold request. Requests control system bus. process. Indicates normal termination transfer. read output. Read strobe devices writes memory.
reset
Input
High
ain[3.0] dbin[7.0] dreq[3.0] adstb dben
Input Input Input Output Output Output
High High High
dmaenable
Output
High
neopout niorout
Output Output Output
High
Altera Corporation
a8237 Programmable Controller
Table a8237 Ports (Part
Name
niowout nmemr nmemw aout[7.0] dack[3.0] dbout[7.0]
Type
Output Output Output Output Output Output
Polarity
Description
write output. Write strobe devices reads from memory. Memory read. Read strobe memory elements during reads memory-to-memory transfers. Memory write. Write strobe memory elements during writes memory-to-memory transfers. Address output. During service, aout[7.0] comprises least significant byte address. acknowledge bus. Programmable polarity. Indicates cycle been granted peripheral. Data output. microprocessor reads data from internal registers dbout[7.0] bus. Also used output most significant byte address temporary data held during memory-to-memory transfers.
Altera Corporation
a8237 Programmable Controller
Functional Description
Figure shows block diagram a8237 MegaCore function.
Figure a8237 Block Diagram
hlda neopin niorin niowin ready reset ain[3.0] dbin[7.0] Control Logic (State Machine Decoder) Internal Control Signals hrq, aen, adstb niorout, niowout nmemr, nmemw dben, dmaenable, neopout Address Registers Channel Base Channel Base Mode Registers Channel Channel Channel Channel Command Register Temporary Register Channel Base Channel Base Channel Current Channel Current Channel Current Channel Current aout[7.0] Temporary Register aout[15.8] dbout[7.0]
Word Count Registers Channel Base Channel Base Channel Base Channel Base Channel Current Channel Current Channel Current Channel Current Temporary Register Control Logic
Status Register aout[15.8] dbout[7.0] Data Output Multiplexer Request Register Mask Register Request Priority Encoder dack[3.0]
Other Registers
dreq[3.0]
Programming
Several registers a8237 must programmed before cycles executed. However, avoid unpredictable behavior, disable cycles during programming setting command register.
Altera Corporation
a8237 Programmable Controller
microprocessor program a8237 when input ain[3.0] asserted. When niowin ain[3.0] asserted, microprocessor writes data internal registers dbin[7.0] bus. When niorin ain[3.0] asserted, microprocessor reads data from internal registers dbout[7.0] bus. "Host Processor Write Timing" "Host Processor Read Timing" Figure byte pointer must toggled correct value before operating address register word count register. byte pointer clear mode register counter commands change contents registers, effectively acting write commands.
Register Address
Table shows register address a8237.
Table Register Address
ain3 ain2 ain1 ain0
Channel
Write (1),
Base current address register Base current word count register Base current address register Base current word count register Base current address register Base current word count register Base current address register Base current word count register Command register Single request command Single mask command Mode register Clear byte pointer command Master clear command Clear mask register command Mask register
Read (1),
Current address register Current word count register Current address register Current word count register Current address register Current word count register Current address register Current word count register Status register Request register Command register Mode register byte pointer command Temporary register Clear mode register counter Mask register
Notes:
byte pointer byte pointer flag selects least significant byte. byte pointer byte pointer flag selects most significant byte. byte pointer flag single-bit internal register that selects either least significant most significant byte 16-bit registers a8237, allowing microprocessor write read 8-bit data bus. "Clear Byte Pointer Command" "Set Byte Pointer Command" page more information. indicates "don't care."
Altera Corporation
a8237 Programmable Controller
Registers
a8237 MegaCore function contains following registers:
Base address Current address Base word count Current word count Command Mode Request Mask Status Temporary
Base Address Register
Each four channels base address register, which 16-bit register that contains starting address transfers. auto-initialization enabled, a8237 loads base address value into current address register conclusion cycle. microprocessor writes base address register parts dbin[7.0], simultaneously loads current address register. byte pointer flag chooses either least significant most significant byte. microprocessor cannot read base address register.
Current Address Register
Each four channels current address register, which 16-bit register containing working address value transfers. microprocessor loads current address register simultaneously with base address register dbin[7.0]. auto-initialization enabled, a8237 reloads base address value conclusion cycle. microprocessor reads writes current address register parts 8-bit data bus. byte pointer flag chooses least significant most significant byte. After each transfer, current address value updated with incremented decremented value from temporary address register (except channel memory-to-memory mode when address held constant).
Altera Corporation
a8237 Programmable Controller
Base Word Count Register
Each four channels base word count register, which 16-bit register containing beginning word count transfers. auto-initialization enabled, a8237 loads base word count value into current word count register conclusion cycle. microprocessor writes base word count register parts dbin[7.0], simultaneously loads current word count register. byte pointer flag chooses least significant most significant byte. microprocessor cannot read base word count register.
Current Word Count Register
Each four channels current word count register, which 16-bit register containing working word count value transfers. microprocessor loads current word count value simultaneously with base word count register dbin[7.0]. auto-initialization enabled, a8237 reloads base word count value conclusion cycle. microprocessor reads writes current word count register parts 8-bit data bus. byte pointer flag chooses least significant most significant byte. After each transfer, current word count value updated with decremented value from temporary word count register. terminal count flag generated when count rolls over from zero hexadecimal FFFF. number transfers more than value written current word count register. example, 16-word transfer desired, word count should hexadecimal 000F.
Command Register
command register configures operation a8237, such dreq dack polarity, request priority, function enables/disables, transfer timing. microprocessor reads from writes command register 8-bit data bus. reset input master clear command clears command register. Table
Altera Corporation
a8237 Programmable Controller
Table Command Register Format
Description
Memory-to-memory disable Memory-to-memory enable Channel address hold disable Channel address hold enable Note Controller enable Controller disable Normal timing Compressed timing Note Fixed priority Rotating priority Late write Extended write compressed timing, Note dreq active high dreq active dack active dack active high
Note:
indicates "don't care."
Mode Register
6-bit mode registers contain configuration each four channels. When writing from dbin[7.0], first bits mode register format selects channel mode register. Before reading each mode registers, clear mode register counter command must executed. next read from mode register address returns value from channel mode register. Subsequent mode register reads step through other mode registers order. Table
Altera Corporation
a8237 Programmable Controller
Table Mode Register Format
Description
Channel select Channel select Channel select Channel select during Read Verify transfer Write transfer Read transfer Illegal Auto-initialization disable Auto-initialization enable Address increment Address decrement Demand mode select Single mode select Block mode select Unused (Cascade mode supported.)
Request Register
4-bit request register allows software requests. Hardware requests (from dreq inputs) masked mask register values; software requests generated from request register unmaskable. request register request bits only programmed single request command. reset input master clear command clears request register. Table
Table Request Register Format
Description
Channel request Channel request Channel request Channel request 1111
Altera Corporation
a8237 Programmable Controller
Mask Register
4-bit mask register disable incoming request, contains mask flags dreq inputs each channel. microprocessor read write mask register 8-bit data bus. Also, microprocessor write individual bits mask register with single mask command. reset input master clear command sets bits mask register. Table
Table Mask Register Format
Description
Channel unmasked Channel masked Channel unmasked Channel masked Channel unmasked Channel masked Channel unmasked Channel masked XXXX during write, Note 1111 during read
Note:
indicates "don't care."
Status Register
8-bit status register contains status flags four channels. Each channel terminal count flag request flag. terminal count flag indicates that cycle complete been terminated neopin signal since last read status register. request flag indicates dreq input channel asserted regardless state associated mask bit. status register reset reset input master clear command. terminal count flags reset each read status register. Table
Altera Corporation
a8237 Programmable Controller
Table Status Register Format
Description
Channel terminal count Channel terminal count Channel terminal count Channel terminal count Channel request Channel request Channel request Channel request
Temporary Register
8-bit temporary register holds data value memory-to-memory transfers. Reading this register from microprocessor dbout[7.0] yields last data value transferred during most recent memory-to-memory cycle. temporary register cannot written directly microprocessor dbin[7.0], cleared reset input master clear command.
Commands
a8237 MegaCore function perform following commands:
Single request command Single mask command Clear byte pointer command byte pointer command Master clear command Clear mask register command Clear mode register counter command
These commands issued performing either read write operation with specific address ain[3.0]. Table page shows issue these commands.
Altera Corporation
a8237 Programmable Controller
Single Request Command
single request command alters single 4-bit request register. Table
Table Single Request Command Format
Description
Channel select Channel select Channel select Channel select Reset request request XXXXX during write, Note
Note:
indicates "don't care."
Single Mask Command
single mask command alters single 4-bit mask register. Table
Table Single Mask Command Format
Description
Channel mask select Channel mask select Channel mask select Channel mask select Reset mask mask XXXXX during write, Note
Note:
indicates "don't care."
Altera Corporation
a8237 Programmable Controller
Clear Byte Pointer Command
byte pointer single-bit internal register that selects either least significant most significant byte 16-bit registers a8237. byte pointer allows microprocessor write read operations 8-bit data bus. clear byte pointer command write command that resets byte pointer, allowing subsequent access least significant byte 16-bit register. data value clear byte pointer command ignored. reset input master clear command resets byte pointer.
Byte Pointer Command
byte pointer command read command that sets byte pointer, allowing subsequent access most significant byte 16-bit register. data value byte pointer command unknown. byte pointer reset reset input master clear command.
Master Clear Command
master clear command performs same function reset input. This command resets command, status, request, temporary byte pointer registers, mode register counter, state machine, also sets mask register.
Clear Mask Register Command
clear mask register command write command that resets 4-bit mask register, enabling requests from dreq inputs. data value clear mask register command ignored.
Clear Mode Register Counter Command
clear mode register counter command read command that resets 2-bit mode register counter. This counter incremented after each subsequent read mode register, allowing user cycle through four mode registers. data value clear mode register counter command unknown.
Operation
This section describes following a8237 MegaCore function operations:
State machine Transfer modes Other operations
Altera Corporation
a8237 Programmable Controller
State Machine
a8237 state machine synchronously controls various functions execute types transfers. memory to/from transfer executes simultaneous read write operation, which requires total four states. memory-to-memory transfer must perform read write operation separately, which requires total eight states (i.e., four states read memory location store data value temporary register, another four write data value memory location). state machine loops through these states until word count decrements zero until transfer externally aborted. Upon reset, state machine enters state. state, internal registers programmed appropriate configuration. After programming, a8237 continuously samples unmasked request (dreq) inputs. valid dreq detected, state machine transitions into acquire state. Figure page state, output asserted, state machine waits microprocessor assert hlda. When hlda input asserted, a8237 controls microprocessor 8-bit data bus, allowing transfers begin.
state first state transfer, where adstb signals asserted. most significant byte address appears dbout[7.0] bus, least significant byte address appears aout[7.0] bus. state second state, where adstb deasserted, latching most significant byte address from dbout[7.0] into external latch. state third state, where niorout nmemr asserted, depending direction transfer. state fourth state, where niowout nmemw asserted. cycle been reached, state machine loops state next transfer. most significant byte address does change subsequent cycles transfer, then state transitions directly state (i.e., state skipped), which effectively suppresses adstb generation speeds block transfers.
Altera Corporation
a8237 Programmable Controller
memory-to-memory transfers, eight states executed: four states read memory location store data value temporary register, another four write data value memory location. equivalent state always executed both memory accesses. compensate slower memory peripherals, additional wait states inserted before write state holding ready low. Returning ready high halts insertion wait states, allowing normal operation continue beginning with next cycle.
Transfer Modes
a8237 MegaCore function three transfer modes: single transfer, block transfer, demand transfer modes.
single transfer mode, only transfer executed, state machine enters state allow prioritized access other channels. block transfer mode, transfers continue uninterrupted until transfer completed neopin asserted. demand transfer mode, transfers interrupted deasserting dreq input. When dreq reasserted, transfers restart from point which they were stopped.
Other Operations
addition state machine transfer modes, a8237 also provides following operations controlling transfers:
Auto-initialization Verify transfer Memory-to-memory transfer Priority encoding Compressed timing Extended timing
Altera Corporation
a8237 Programmable Controller
Auto-initialization
Auto-initialization allows each channel reinitialize after completion cycle without microprocessor intervention. This feature enabled setting each channel's mode register. current address current word count registers loaded with values contained base address base word count registers following normal aborted neopin signal) conclusion cycle.
Verify Transfer
verify transfer type operates normal read write operation, except that memory control signals remain deasserted. (The verify transfer type originated means refresh DRAM early personal computers.)
Memory-to-Memory Transfer
memory-to-memory transfers enabled command register, must performed using channels transfer initiated software hardware request channel conclusion cycle, terminal count channel status register, while counterpart channel remains unchanged. Also, channel configured hold address constant, allowing memory fills with single data value.
Priority Encoding
requests priority encoded arbitrate between simultaneous requests multiple pending requests. modes priority encoding available command register:
fixed priority mode, highest priority pending request selected, with channel highest priority channel lowest priority. rotating priority mode, last channel serviced becomes lowest priority when selecting next channel, with other channels rotating accordingly.
Altera Corporation
a8237 Programmable Controller
Compressed Timing
Compressed timing operation speeds transfer state machine loop skipping state, thereby forcing read write pulses equal duration (i.e., clock cycle). This operation enabled setting command register. Compressed timing operation cannot used memory-to-memory transfers.
Extended Timing
Extended timing operation asserts write pulse during state, thereby forcing read write pulses equal duration (i.e., clock cycles). This operation enabled setting command register. Extended timing operation cannot used memory-tomemory transfers.
Altera Corporation
a8237 Programmable Controller
Timing Waveforms
Figure shows timing waveforms a8237 MegaCore function.
Figure a8237 Timing Waveforms (Part
Two-Word Cycle
dreq
hlda
adstb
dbin
Valid Data
Valid Data
dbout
A8-A15
dben
aout
Valid Address
Valid Address
dack
niorout
nmemw
neopout
Altera Corporation
a8237 Programmable Controller
Figure a8237 Timing Waveforms (Part
Memory-to-Memory Transfer
dreq
hlda
adstb
dbin[7.0]
dbout[7.0]
A8-A15
Read Data
A8-A15
Write Data
dben
aout[7.0]
Read Address
Write Address
dack
nmemr
nmemw
neopout
Altera Corporation
a8237 Programmable Controller
Figure a8237 Timing Waveforms (Part
Host Processor Write Timing
niowin
ain[3.0]
Address Valid
dbin[7.0]
Address Valid
Host Processor Read Timing
niorin
ain[3.0]
Address Valid
dbout[7.0]
Data Valid
Variations Clarifications
following list provides clarifications Altera's implementation a8237 functionality Intel 8237A Harris 82C27A devices. Altera believes that a8237 provides consistent functionality that Intel Harris devices. These interpretations have been implemented Altera a8237 MegaCore function believed consistent with implementation Intel Harris devices.
neopin asserted least clock cycle terminates cycle current transfer. neopin output asserted normal conclusion cycle, asserted when cycle aborted neopin. reset input master clear command clears temporary data register used memory-to-memory transfers, including temporary address word count registers. a8237 does implement wait-state support memory-tomemory transfers.
following list provides more information differences between Altera's implementation a8237 functionality Intel 8237A Harris 82C27A devices.
a8237 function, tri-state outputs bidirectional ports split into separate inputs, outputs, enables necessary.
Altera Corporation
a8237 Programmable Controller Data Sheet
a8237 does support cascade mode because would efficient device resources. implement this capability, designer should hand-coded module stripped down a8237 function. rising edge CLK, Harris 82C37A deasserts nMEMR states deasserts nIOROUT state However, this approach reliable from timing perspective CPLD. Altera a8237 deasserts nMEMR falling edge states nIOROUT state This action effectively extends assertion these signals clock cycle.
Revision History
information contained a8237 Programmable Controller Data Sheet version 1.01 supersedes information published previous versions. Version 1.01 includes following changes:
"State Machine" page updated. waveforms Figures were updated. "Variations Clarifications" page updated. Minor style text changes were made throughout document.
Altera Corporation
Copyright 1995, 1996, 1997, 1998, 1999 Altera Corporation, Innovation Drive, Jose, 95134, USA, rights reserved. accessing this information, agree bound terms Altera's Legal Notice.
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