MB86660A Package 48-pin plastic FPT-48P-M15 Description

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MB86660A Package 48-pin plastic FPT-48P-M15 Description

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Single-Chip Demodulator Digital Satellite Broadcasting
MB86660A
Package
48-pin plastic FPT-48P-M15
Description
MB86660A single-chip demodulator digital satellite broadcasting receivers compliant with DVB-S DSS. features converters I-input Q-input, QPSK demodulator forward-error correction (FEC) block, which comprised Viterbi decoder, deinterleaver, Reed-Solomon decoder descrambler.
Features
DVB-S DSS-compliant single-chip demodulator Operation rate Mbps Integrated dual converters I-input Q-input Analog Msymbol/s input QPSK demodulator Gray-coded QPSK demodulation with absolute mapping On-chip multi-rate operation) Automatic carrier capture range Half-Nyquist filters roll-off factor 0.35 Automatic gain control output Viterbi decoder Constraint length Viterbi rate 1/2, 2/3, 3/4, 5/6, Reed-Solomon decoder: 204, Deinterleaver: depth Energy-dispersal removal: PRBS polynomial monitoring output interface interface Power supply voltage: +3.3V Package: QFP-48 Process: 0.35µm CMOS
Single-Chip Demodulator Digital Satellite Broadcasting
Fujitsu Microelectronics, Inc.
MB86660A
Table Contents
Assignment Descriptions Block Diagram Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics Characteristics Register Table Register Functional Description Mode-1 Mode-2 Status Converter Nyquist Filter Carrier Recovery Clock Recovery Reset Viterbi Decoder Monitor Frame Synchronization Timing Deinterleaver Reed-Solomon Decoder Timing Energy Dispersal Removal Output Signal Timing Power-On Reset Application Example Peripheral Circuit Example Package Dimensions
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
Assignment
VIEW
FSYNC
RESET
TCLK
VRHI AVSS AVDD VRLI VRLQ AVDD AVSS VRHQ AVSS
CLKI
TESTI
AVDD
CLKO
EXTCLK
BCLK
ADR2
ADR1
ADR0
FPT-48P-M15
Fujitsu Microelectronics, Inc.
MB86660A
Descriptions
Symbol VRHI VRLI VRHQ VRLQ Name QPSK analog I-input QPSK analog Q-input high reference reference high reference reference output Function QPSK analog in-phase input: Analog input. maximum input rate Msymbol/s. QPSK analog quadrature-phase input: Analog input. maximum input rate Msymbol/s. high-reference input IIN: High-reference voltage input. typical voltage 1.4V. low-reference input IIN: Low-reference voltage input. typical voltage high-reference input QIN: High-reference voltage input. typical voltage 1.4V. low-reference input QIN: Low-reference voltage input. typical voltage output: (Pulse Width Modulation) `H/L' level output. This output external analog filter that controls amplifier tuner. Crystal oscillator input: Connect 27.0 crystal oscillator between these pins. used frequency internal multi-rate VCO. This crystal oscillator required when EXTCLK inputs 27.0 clock. When crystal oscillator used, CLKI CLKO must `OPEN', respectively. When crystal oscillator used, EXTCLK must `L'. External clock input: This inputs 27.0 clock frequency internal multi-rate VCO. crystal oscillator required when this used. When this EXTCLK used, must `L'. Transport data output: These pins transport stream packet data. user select output mode, either from 8-bit parallel data serial data output. When parallel output selected, user select position TS0. When serial output selected, user select output position, TS7. selections done setting internal register. Transport clock output: This transport stream packet clock TS0. user select output mode that parallel serial clock, select clock polarity. selections done setting appropriate internal register. Transport enable output: This outputs when valid packet data present, outputs during other times, such parity bytes. Error indicator output: This outputs period packet that Reed-Solomon decoder could correct, outputs period packet that could correct. Frame synchronous output: This outputs when frame synchronized. Serial clock input Serial data Address input bus: These lower 3-bit address. upper 4-bit fixed with "0001".
CLKI CLKO
Crystal oscillator input
EXTCLK
External clock input
Transport packet data output
TCLK
Transport packet clock output
Transport packet enable
Error indicator Frame synchronous output clock data address
FSYNC ADR2 ADR1 ADR0
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
Descriptions (continued)
Symbol RESET Name Reset input Function Reset input: MB86660A reset when this `L'. must reset when power turned Refer "Power-on Reset" section timing details. clock output: This output clock signal twice symbol rate, clock signal symbol rate, packet start signal. selections done setting internal register. This outputs initial stage. Test pin: This input test must connected normal operation. Analog VDD: Analog internal A/Ds Analog VSS: Analog internal A/Ds Digital Digital
BCLK
clock output
TESTI AVDD AVSS
Test Analog Analog Digital Digital
Block Diagram
QPSK Block RESET VRHI VRLI Complex multiplier HalfNyquist filter Viterbi decoder Block Sync-byte decoder deinterleaver Energy-dispersal removal Reed-Solomon decoder TCLK FSYNC Carrier recovery
VRLQ VRHQ
HalfNyquist filter
recovery BCLK
CLKI CLKO EXTCLK
Fujitsu Microelectronics, Inc.
MB86660A
Absolute Maximum Ratings (See WARNING)
Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VDD, AVDD Rating Min. -0.5 -0.5 -0.5 Max. +4.0 +125 Unit
WARNING:
Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings.
Recommended Operating Conditions (See WARNING)
Parameter Power supply voltage High-level input voltage Low-level input voltage Operating temperature Symbol VDD, AVDD Value Min. 0.65 -0.3 Typ. Max. 0.25 Unit
WARNING:
Recommended operating conditions normal operating ranges semiconductor device. device's electrical characteristics warranted when operated within these ranges. Always semiconductor devices within recommended operating conditions. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their Fujitsu representative beforehand.
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
Electrical Characteristics
Characteristics
(VDD +3.3 +70°C unless otherwise specified)
Parameter Logic input Input high voltage Input voltage input (SDA SCL) Input high voltage Input voltage input (VRHI, VRHQ, VRLI, VRLQ, QIN) Input reference high voltage (for VRHI VRHQ) Input reference voltage (for VRLI VRLQ) Differential reference voltage Reference input resistance Analog input voltage (for QIN) Analog input capacitance (for QIN) Logic output Output high voltage Output voltage output (SDA) Output voltage Power supply current (VDD AVDD) Average power supply current Typical values assume that +3.3 +25°C. IIN, Mbaud/s T.B.D. -0.5 0.65 -0.3 0.25 Symbol Conditions Value Min. Typ.*1 Max. Unit
Fujitsu Microelectronics, Inc.
MB86660A
Register Table
Register
<I2C address:
Register Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 (10) 00001011 (11) 00001100 (12) 00010000 (16) 00010001 (17) 00010010 (18) 00010011 (19) Note:
Access
ADR2
ADR1
(MSB)
ADR0
Function Reserved Reserved AGCP VCO6 SYT2 CA_2 CL_2 AFC6 CAS_2 AGC_2 MOD5 Reserved AGCM VCO5 SYT1 CA_1 CL_1 AFC5 CAS_1 AGC_1 MOD4 BCLK1 AGC4 VCO4 VIR4 SYT0 CA_0 CL_0 STA4 AFC4 CAS_0 AGC_0 MOD3 BCLK0 AGC3 VCO3 VIR3 SYA3 MOD2 ER_EN AGC2 VCO2 VIR2 SYA2 CA_2 CL_2 STA2 AFC2 CAS_2 AGC_2 MOD1 RS_EN AGC1 VCO1 VIR1 SYA1 CA_1 CL_1 QP_RST STA1 AFC1 CAS_1 AGC_1 MOD0 DI_EN AGC0 VCO0 VIR0 SYA0 CA_0 CL_0 LSI_RST STA0 AFC0 CAS_0 AGC_0
Register Name
MOD7 Reserved Reserved VCO7 LVCO SYT3 CA_SW AFC7
MODE-1
MODE-2
Viterbi expansion Frame synchronization Carrier recovery loop filter coefficient Clock recovery loop filter coefficient RESET Status Reserved Reserved Start carrier coefficient Unused coefficient
STA3 AFC3
Don't care (1): Default value
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
Functional Description
MODE-1
user select output polarity TCLK, output mode TS0, setting register. Register value: address 0001ADR [2:0]. Register address 00000000(2).
Name MOD0 Function TCLK polarity Value (default) (default) MOD2 Output mode Output order FSYNC output mode Frame sync-mode Reserved Data reverse switch (default) (default) (default) (default) (default) Operation latched falling edge TCLK. latched rising edge TCLK. error indicator flag transport stream packet when Reed-Solomon decoder cannot correct error. error indicator flag transport stream packet changed. Parallel output Serial output. Unused bits output `L'. when parallel. outputs when serial mode. when parallel. outputs when serial mode. FSYNC outputs frame synchronous signal. FSYNC outputs Viterbi synchronous signal. `B8(h)' frame sync-byte value changed `47(h)'. `B8(h)' frame sync-byte value changed. Don't change Normal operation Received data reversed LSI.
MOD1
Error indicator
MOD3
MOD4
MOD5 bit6 MOD7
[MOD0 function]
MOD0 MOD0
TCLK
TCLK
Fujitsu Microelectronics, Inc.
MB86660A
MODE-1 (continued)
[MOD1 function] structure transport packet
byte Packet header bits bytes) Sync.byte Transport error indicator
Transport packet
Data
MOD1 This when Reed-Solomon decoder cannot correct error. MOD1 This changed.
[MOD5 function] MOD5
packet packet Frame sync. byte Packet sync. byte Packet sync. byte Frame sync. byte Packet sync. byte Frame sync. byte Packet sync. byte Frame sync. byte packet packet
byte
byte
byte
byte
byte
byte
byte
Complemented
Frame sync. byte Packet sync. byte Packet sync. byte
Complemented
Frame sync. byte Packet sync. byte
Complemented
Frame sync. byte Packet sync. byte
Complemented
Frame sync. byte
byte
byte
byte
byte
byte
byte
byte
MOD5
packet packet Frame sync. byte Packet sync. byte Packet sync. byte Frame sync. byte Packet sync. byte Frame sync. byte Packet sync. byte Frame sync. byte packet packet
byte
byte
byte
byte
byte
byte
byte
Complemented
Complemented
Complemented
Frame sync. byte
byte
Packet sync. byte
byte
Packet sync. byte
byte
Frame sync. byte
byte
Packet sync. byte
byte
Frame sync. byte
byte
Packet sync. byte
byte
Frame sync. byte
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
MODE-2
Deinterleaver, Reed-Solomon Energy dispersal removal functions bypassed setting this register. Register value: address 0001ADR [2:0]. Register address 00000001(2) 1(10).
Name DI_EN Function Deinterleaver enable Value (default) (default) (default) Operation Deinterleaver bypassed. Normal operation. Deinterleaving performed. Read-Solomon decoder bypassed. Normal operation. Reed-Solomon decoding performed. Energy dispersal removal performed. Normal operation. Energy dispersal removal performed.
RS_EN
Reed-Solomon enable Energy dispersal removal enable
ER_EN
BCLK output changed setting register. Register value: address 0001ADR [2:0]. Register address 00000001(2) 1(10).
Name Function Value (default) BCLK [1:0] BCLK output select level output Packet start signal output Clock signal with frequency twice symbol rate Clock signal with frequency symbol rate Operation
should changed. Register value: address 0001ADR [2:0]. Register address 00000001(2) 1(10)
Name Reserved Function Value (default) (default) (default) Don't change. Don't change. Don't change. Operation
Fujitsu Microelectronics, Inc.
MB86660A
Status
user monitor internal status reading status register. Register value: address 0001ADR [2:0]. Register address 00001001(2) 9(10), Read only.
Name STA0 Function Frame synchronization Viterbi decode synchronization Value [4:2] Viterbi rate detection Operation Shows Frame synchronization. Shows Frame synchronization. Shows Viterbi decoder synchronization. Shows Viterbi decoder synchronization. Shows Viterbi decoder synchronization. Shows Viterbi rate 1/2. Shows Viterbi rate 2/3. Shows Viterbi rate 3/4. Shows Viterbi rate 5/6. Shows Viterbi rate 7/8.
STA1
Converter
analog input data automatically sampled internal clock.
Nyquist Filter
Digital half-Nyquist filtering performed input signal. roll-off factor 0.35.
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
amplitude input data compared with reference value [4:0] user. compared result output (Pulse Width Modulation) form `H/L' level. adjusts amplifier gain tuner external analog filter. pulse width output changed 1/(2Fs) (µs) step (n=0 255, symbol rate (Msymbol/s)). frequency Fs/128 (MHz). pulse width `H/L' level output changed minimum 4/Fs (µs) step (Fs: symbol rate (Msymbol/s)). frequency maximum Fs/8 (MHz). response faster than PWM, useful quick response required. reference value [4:0] output polarity programmable. Register value: address 0001ADR [2:0]. Register address 00000010(2) 2(10).
Name Function Value 00000 [4:0] Reference value 10000 (default) 11111 AGCM output mode (default) Maximum reference value output `H/L' level output When [4:0] Amplitude input data: AGCM (PWM output), repeatedly outputs pulses with period longer than period. AGCM (`H/L' level output), outputs `H'. (default) When [4:0] Amplitude input data: AGCM (PWM output), repeatedly outputs pulses with period longer than period. AGCM (`H/L' level output), outputs `L'. When [4:0] Amplitude input data: AGCM (PWM output), repeatedly outputs pulses with period longer than period. AGCM (`H/L' level output), outputs `L'. When [4:0] Amplitude input data: AGCM (PWM output), repeatedly outputs pulses with period longer than period. AGCM (`H/L' level output), outputs `H'. Reserved (default) this bit. amplifier gain tuner adjusted equal reference value. Minimum reference value Operation
AGCP
output polarity
Fujitsu Microelectronics, Inc.
MB86660A
(continued)
Some external AGC-loop configuration user systems need adjust filter value using following register. Register value: address 0001ADR [2:0]. Register address 00010011(2) 19(10).
Name Function Value AGC_ [2:0] -Coefficiency loop-filter (default) (default) AGC_ [2:0] -Coefficiency loop-filter Operation 128)
Block Diagram AGC:
AGC_ [2:0]
Detector
AGC_ [2:0]
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
(continued)
output waveform: pulse width changed 1/(2Fs) (µs) step 255, symbol rate (Msymbol/s). frequency Fs/128 (MHz).
AGCP 1/(2Fs) (µs) [4:0] When difference between amplitude [4:0] maximum 1/(2Fs) (µs) 1/(2Fs) (µs) AGCP 1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
[4:0] 1/(2Fs) (µs) 1/(2Fs) (µs) 1/(2Fs) (µs) 1/(2Fs) (µs)
When amplitude [4:0].
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
[4:0]
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
1/(2Fs) (µs)
[4:0] When difference between [4:0] amplitude maximum
level (fixed)
level (fixed)
symbol rate (Msymbol/s)
Fujitsu Microelectronics, Inc.
MB86660A
(continued)
`H/L' level output waveform: pulse changed minimum 4/Fs (µs) step (Fs: symbol rate). frequency Fs/8 (MHz).
AGCP 4/Fs (µs) AGCP 4/Fs (µs)
[4:0] amplitude
level (fixed)
level (fixed)
4/Fs (µs) [4:0] amplitude level (fixed)
4/Fs (µs)
level (fixed)
symbol rate (Msymbol/s)
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
Carrier Recovery
difference between actual expected carrier frequency automatically recovered LSI. loop filter coefficient carrier recovery operates with CAS_ [2:0] CAS_ [2:0] first then automatically switches [2:0] [2:0] after lock-up. However, when CA_SW "0", filter coefficient always operates with [2:0] [2:0]. loop filter variable. Register value: address 0001ADR [2:0]. <Register address 00010001(2) 17(10)>.
Name Function Value CAS_ [2:0] -factor loop filter first (default) CAS_ [2:0] -factor loop filter first (default) Operation (=2) (=4) (=8) (=16) (=32) (=64) (=256) (=512) (=1024) (=2048) (=4096) (=8192) CA_SW Loop filter [2:0] [2:0] -factor loop filter after lock-up
<Register address 00000110(2) 6(10)>.
Name Function Value (default) (default) -factor loop filter after lock-up 1(default) Operation (=2) (=4) (=8) (=16) (=32) (=64) (=256) (=512) (=1024) (=2048) (=4096) (=8192) Auto Auto
Carrier Recovery Block Diagram:
CAS_ [2:0] [2:0] Phase Detector Sin/Cos table
CAS_ [2:0] [2:0]
Fujitsu Microelectronics, Inc.
MB86660A
user monitor difference between actual recovered carrier frequency nominal local oscillator frequency tuner. different frequency tuner calculated reading register: (kHz) (128 [7:0]) 82.474 (n/42.192) Receiving rate (Mbps)) Ex.1: When [7:0] 01111100 Receiving rate (Mbps), (DEC) 312.8 (kHz) shows local oscillator frequency tuner 312.8 higher. Ex.2: When [7:0] 10000101 Receiving rate (Mbps), (DEC) -586.4 (kHz) shows local oscillator frequency tuner 586.4 lower. Register value: address 0001ADR [2:0], Register address 00001010 (2), Read only
Name Function Value 00000000 00000001 01111111 [7:0] difference carrier frequency 10000000 10000001 11111110 11111111 Shows local oscillator frequency tuner very low. Shows local oscillator frequency tuner almost correct. Operation Shows local oscillator frequency tuner very high.
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
Clock Recovery
clock synchronized baseband data automatically recovered LSI. internal must required frequency advance. Refer Section setting internal frequency. Loop filter variable. Register value: address 0001ADR [2:0]. Register address 00000111(2) 7(10).
Name Function Value [2:0] -factor clock recovery loop filter (default) 110, [2:0] -factor clock recovery loop filter (default) 110, Operation (=512) (=1024) (=2048) (=4096) (=8192) (=16384) Prohibited (=131072) (=262144) (=524288) (=1048576) (=2097152) (=4194304) Prohibited
Clock Recovery Block Diagram:
[2:0] Phase Detector
[2:0]
Fujitsu Microelectronics, Inc.
MB86660A
internal frequency must times received data symbol rate. Because frequency resolution MHz, should nearest step. Exp.: When received data symbol rate 21.096 Msym/s, 42.2 21.096 Msym/s 42.192 MHz. Register value: adress 0001ADR [2:0]. Register address 00000011(2) 3(10) 00000100(2) 4(10).
Name Function Value 00000000 00000001 00000110 00010110 01000100 01110100 [7:0] frequency (0.1 step) 10010110 10100010 11001000 11011000 11100000 11111110 11111111 Operation LVCO Register Internal 40.0 MHz. Internal 40.1 MHz. Internal 40.6 MHz. Internal 42.2 MHz. (Initial value) Internal 46.8 MHz. Internal 51.6 MHz. Internal 55.0 MHz. Internal 56.2 MHz. Internal 60.0 MHz. Internal 61.6 MHz. Internal 62.4 MHz. Internal 65.4 MHz. Internal 65.5 MHz. 36.0 36.8 39.8 39.9 LVCO Register
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
Reset
whole block QPSK-block only reset when LSI_RST QP_RST `1'. Register value: address 0001ADR [2:0]. Register address 00001000(2) 8(10).
Name LSI_RST QP_RST Function software reset QPSK block software reset Value Operation whole (including QPSK block, block interface) reset when LSI_RST `1'. QPSK block only reset when QP_RST `1'.
Viterbi Decoder
Constraint length Optionally, some Viterbi rates selected from 1/2, 2/3, 3/4, 7/8. receiving Viterbi rate automatically detected from selected Viterbi rates. time takes detect actual rate proportional number selected rates, recommended select rate rate known beforehand. detected Viterbi rate written [4:2] register (refer section Status, page 13). Register value: address 0001ADR [2:0], Register address 00000100(2) 4(10).
Name VIR0 Function setting Value (default) (default) (default) (default) (default) Operation Viterbi rate detection performed 1/2. Viterbi rate detection performed 1/2. Viterbi rate detection performed 2/3. Viterbi rate detection performed 2/3. Viterbi rate detection performed 3/4. Viterbi rate detection performed 3/4. Viterbi rate detection performed 5/6. Viterbi rate detection performed 5/6. Viterbi rate detection performed 7/8. Viterbi rate detection performed 7/8.
VIR1
setting
VIR2
setting
VIR3
setting
VIR4
setting
Fujitsu Microelectronics, Inc.
MB86660A
Monitor
approximate value input signal monitored. monitored value depends evaluation environment, mounting conditions, user application system. Therefore, value must carefully checked. typical characteristic curve shown below. Register value: address 0001ADR [2:0]. Register address 00001011(2) 11(10), Read only.
Name Function Value 00000000 [7:0] monitor 11111111 Shows that error receiving data small. Operation Shows that error receiving data large.
Monitor Characteristics
[7:0] Read Value
(dB)
Note: [7:0] Read Value translated decimal value.
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
Frame Synchronization
frame synchronization signal (B8h) start packets detected. number states acquisition tracking programmable. considered lock synchronization signal continuously detected number acquisition states, then FSYNC changed to`H' when ((MOD4 (Register address: 00000000) =`0')). After lock, considered lock synchronization signal would continuously detected number tracking states, then FSYNC changing `L'. Register value: address 0001ADR [2:0]. Register address 00000101(2) 5(10).
Name Function Value 0000,0001, 0010 (default) 1111 0000 0010 [3:0] Number tracking states 1111 (default) considered lock synchronization signal would continuously detected fifteen times. considered lock synchronization signal continuously detected fifteen times. considered lock synchronization signal would continuously detected times. Operation considered lock synchronization signal continuously detected times.
[3:0]
Number acquisition states
Timing
packets packet Sync. -byte byte Sync. -byte byte Sync. -byte byte Sync. -byte byte packet Sync. -byte byte Sync. -byte byte packets Sync. -byte byte Sync. -byte byte
byte
byte
byte
byte
byte
byte
byte
Frame sync. (B8h)
(47h)
(47h)
Frame sync. (B8h)
(47h)
Frame sync. (B8h)
(47h)
Frame sync. (B8h)
FSYNC
frame-sync continuously detected number acquisition states.
frame-sync continuously detected number tracking states.
Deinterleaver
deinterleaving depth byte-stream. When DI_EN (Register address =00000001) `0', deinterleaving performed. When DI_EN `1', deinterleaving performed.
Fujitsu Microelectronics, Inc.
MB86660A
Reed-Solomon Decoder
204, 188, Code Generator Polynomial: Field Generator Polynomial: total errors less than bytes 204-byte block, errors corrected. total errors more than bytes, errors corrected. outputs packet that errors were corrected. outputs packet that errors were corrected. distinguish parity bytes Reed-Solomon, outputs period valid data, then outputs period parity bytes. When RS_EN (Register address: 00000001) `0', Reed-Solomon decoding performed errors corrected. operates normally, outputs `L'. When RS_EN `1', Reed-Solomon decoding performed.
Timing
Corrected Packet Sync. -byte byte Data byte Parity byte Uncorrected packet Sync. -byte byte Data byte Parity byte Corrected Packet Sync. -byte byte Data byte Parity byte Sync. -byte byte
TCLK (when RSEN `1') (when RSEN `0')
level
Energy Dispersal Removal
When ER_EN (Register address: 00000001) `0', Energy dispersal removal performed. When ER_EN `1', Energy dispersal removal performed. Pseudo-Random Binary Sequence (PRBS) Polynomial: polynomial initialized into sequence `100101010000000'every eight packets.
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
Write protocol
address (LSI) Register address-1 Data-1 (LSI) (LSI) Register address-2 Data-2 -ACK (LSI) (LSI) (LSI)
Write register address-1.
Write register address-2.
Read protocol
address (LSI) Register address-1 (LSI) address (LSI) (LSI)
Data-1
register address-1 before reading.
Read register address-1.
address
(LSI)
Register
(LSI)
address
(LSI)
(LSI)
address-2
Data-2
register address-2 before reading.
Read register address-2.
Notes: Start condition address (7bit): 0001 (ADR2) (ADR1) (ADR0) [2:0]: User setting (1bit): write, read Data-n (8bit): Data register address-n ACK: Acknowledge Stop condition Output from master (LSI): Output from MB86660A
Fujitsu Microelectronics, Inc.
MB86660A
Output Signal Timing
Corrected Packet Sync. -byte byte Data byte Parity byte Uncorrected packet Sync. -byte byte Data byte Parity byte Corrected Packet Sync. -byte byte Data byte Parity byte Sync. -byte byte
TCLK BCLK (when BCLK [1:0] `01')
FSYNC
level fixed
Note: TCLK polarity changed setting register.
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
Power-On Reset
MB86660A must reset RESET when power turned Apply reset signal power-on, then remove reset after AVDD have reached 3.3V have input reset pulse width after they reached 3.3V. Note that 27.0 clock crystal oscillator external clock EXTCLK must stable before reset removed. (See diagram below.)
VDD, AVDD VDD, AVDD
more
(inactive) RESET (active) Stable clock clock Select either RESET (inactive) (active) more Stable clock clock (inactive)
Fujitsu Microelectronics, Inc.
MB86660A
Application Example
When crystal oscillator used
Tuner
Demultiplexer MPEG2 decoder
MB86660A
TCLK
deg. shifter
L.O.
CLKI
CLKO
X'tal
When external clock used.
Tuner
Demultiplexer MPEG2 decoder
MB86660A
TCLK
deg. shifter
L.O.
EXTCLK
clock
Fujitsu Microelectronics, Inc.
Single-Chip Demodulator Digital Satellite Broadcasting
Peripheral Circuit Example
Line
FSYNC RESET
VRHI AVSS AVDD VRLI
AVSS AVDD CLKI CLKO EXTCLK TESTO ADR2 ADR1 ADR0 TESTI
TCLK
VIEW
VRLQ AVDD AVSS VRHQ
Analog
X'tal
Digital
Notes: analog digital power supplies should separated each pattern should sufficiently wide. Connect bypass capacitors with good high-frequency characteristics AVDD AVSS. Connect analog digital power supply pattern point such illustration above. Connect bypass capacitors with good high-frequency characteristics between analog `AVSS' VRHI, VRLI, VRHQ VRLQ which reference voltages A/Ds. very important stabilize reference voltages A/D. Furthermore, recommended connect large value about AVSS. board with layers more.
Fujitsu Microelectronics, Inc.
MB86660A
Package Dimensions
48-pin plastic (FPT-48P-M15)
15.30±0.40 (.602±.016) +0.30 12.00 -0.10 +.012 .472 -.004 2.70(.106)MAX 0.05(.002)MIN (STAND OFF)
Details part 0.15(.006) 8.80 (.346)
13.60±0.40 (.535±.016)
0.20(.008) 0.15(.006)MAX 0.50(.020)MAX
INDEX
Details part LEAD
0.80(.0315)TYP
0.30±0.06 (.012±.002)
0.16(.006)
0.15 -0.01 +.002 .006 -.0004 0.85±0.30 (.033±.012)
+0.05
0~10°
0.10(.004)
1994 FUJITSU LIMITED F48025S-1C-1
Dimensions (inches)
Fujitsu Microelectronics, Inc.
FUJITSU MICROELECTRONICS, INC.
Corporate Headquarters 3545 North First Street, Jose, California 95134-1804 Tel: (800) 866-8608 Fax: (408) 922-9179 E-mail: fmicrc@fmi.fujitsu.com Internet: http://www.fujitsumicro.com
1998 Fujitsu Microelectronics, Inc. company product names trademarks registered trademarks their respective owners. Printed U.S.A. ASIC-DS-20736-7/98

MB86660A Package 48-pin plastic FPT-48P-M15 Description

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