CMOS SRAM 1M-bit (128K CMOS SRAM organized 131,072 8bits Single +

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CMOS SRAM 1M-bit (128K CMOS SRAM organized 131,072 8bits Single +

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GLT710008
CMOS SRAM 1M-bit (128K
CMOS SRAM organized 131,072 8bits Single +5.0V(± 10%) Power Supply High Speed Access time: power operation
Active: (max.) Standby: (max.)
Package Options
32-Pin Plastic (300 mil) 32-Pin Plastic (400 mil) 32-Pin Plastic TSOP (Type
Corner Power Ground
GENERAL DESCRIPTION
GLT710008 high performance CMOS static organized 131,072 8bits. Writing this device accomplished when write enable (WE) chip select (CE1) inputs both high. Reading accomplished when High output enable (OE) both Low. GLT710008 operates from single +5.0V power supply inputs outputs fully compatible.
March 1998 (Rev.
GLT710008
FUNCTIONAL BLOCK DIAGRAM
Address Decoder Memory Matrix
Data Input Data Control Column
Description
Symbol A[16:0] I/O[7:0] Address input Data input/output Chip Enable input Chip Enable input Output Enable input Write Enable input Power Supply (+5V) Ground Name
Mode Selection Table
High
don't care.
High High
High
High High High
High Impedance High Impedance Data Data High Impedance
MODE Standby Standby Read Write Output disable
G-LINK Technology
March 1998 (Rev.
GLT710008
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Symbol VTERM TSTG IOUT Terminal Voltage with Respect Operating Temperature Storage Temperature Power Dissipation Output Current Parameter Rating -0.5
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Recommended Operating Conditions (0°C 70°C, 5.0V 10%)
Symbol Supply Voltage Supply Voltage Input High Voltage Input Voltage Parameter -0.5 Unit
VIL(min) -3.0V pulse width less than 20ns.
Capacitance +25°C, MHz)
Symbol COUT Input Capacitance Output Capacitance Parameter VOUT Condition Max. Unit
Operating Conditions Maximum Limits
Symbol ISB1 Parameter Dynamic Operating Current VIH, max, fmax, IOUT 0mA, Standby Power Supply Current (TTL level) and/or VIL, max, fmax, Full Standby Power Supply Current (CMOS level) and/or VLC, max, Unit
Characteristics (VCC 5.0V 10%)
Symbol Parameter Input Leakage Current Output Leakage Current Output voltage Test Condition max, max, and/or VIL, VOUT Output high voltage Min. Max. Unit
G-LINK Technology
March 1998 (Rev.
GLT710008
Characteristics (VCC 5.0V 10%, +70°C)
Parameter Read Cycle Symbol tACE tLZCE tHZCE tAOE tLZOE tHZOE Write Cycle tLZWE tHZWE Read Cycle time Address access time Chip enable access time Output hold from address change Chip enable output low-Z Chip disable output high-Z Chip enable power time Chip enable power down time Output enable access time Output enable output low-Z Output disable output high-Z Write Cycle time Chip enable write Address valid write Address set-up time Address hold from write Write pulse width VIH) Data set-up time Data hold time Write disable output low-Z Write enable output high-Z Description Units
tLZCE, tLZWE, tHZCE, tLZOE, tHZOE, simulated values.
Test Conditions
Parameter Input pulse levels Input rise fall times Input timing reference levels Output reference levels Output load Rating 3.0V 1.5V 1.5V Figure
tLZCE, tHZCE, tLZWE, tHZWE, tLZOE, tHZOE 30pF
Figure Output Load Equivalent
G-LINK Technology
March 1998 (Rev.
GLT710008
ADDR DOUT Previous Data Valid Note: High READ cycle Data Valid Undefined
Figure Read Cycle Timing
tACE tAOE tLZOE tLZCE DOUT Hi-Z High READ cycle. given temperature voltage condition, tHZCE less than tLZCE. tHZCE Data Valid Undefined tHZCE
Figure Read Cycle Timing
ADDR
tWP2
tLZWE Data Valid
tHZWE DOUT Note: Hi-Z Undefined Don't Care
Figure Write Cycle Timing (Write Enabled Controlled, Low)
G-LINK Technology
March 1998 (Rev.
GLT710008
ADDR
tWP1
Data Valid
DOUT Note: High
Hi-Z Don't Care
Figure Write Cycle Timing (Chip Enabled Controlled)
ADDR
tWP1
Data Valid
DOUT Note: High
Hi-Z Undefined Don't Care
Figure Write Cycle Timing (Chip Enabled Controlled)
G-LINK Technology
March 1998 (Rev.
GLT710008
PACKAGE INFORMATION
VIew
Figure 32-Pin Plastic SOJ/TSOP Logical Pinout
G-LINK Technology
March 1998 (Rev.
GLT710008
0.875 ±0.005
0.335 ±0.005 0.30 ±0.005
0.132 0.100 ±0.005
0.082 0.010
0.265 ±0.01 0.048 0.050 0.028 ±0.003 0.018 0.026
Dimensions inches
Figure 32-Pin Plastic (300 mil) Package Dimensions
G-LINK Technology
March 1998 (Rev.
GLT710008
0.875 ±0.005
0.435 ±0.005 0.40 ±0.005
0.140 0.110 ±0.005
0.082 0.010
0.370 ±0.01 0.045 0.050 0.028 ±0.003 0.018 0.027
Dimensions inches
Figure 32-Pin Plastic (400 mil) Package Dimensions
G-LINK Technology
March 1998 (Rev.
GLT710008
14.0 ±0.2
12.4 ±0.1
1.20 (MAX)
±0.1 1.05
0.15 ±0.05 +0.1/-0.05 0.10 0.25 0.05 ±0.05
0~10° ±0.1
Figure 32-Pin Plastic TSOP (Type Package Dimensions
G-LINK Technology
March 1998 (Rev.
GLT710008
ORDERING INFO
Part Number GLT710008-12J3 GLT710008-15J3 GLT710008-12J4 GLT710008-15J4 GLT710008-12TS GLT710008-15TS Organization 128Kx8 128Kx8 128Kx8 128Kx8 128Kx8 128Kx8 Power Ground Corner Corner Corner Corner Corner Corner Operating Current (mA) 155mA 160mA 155mA 160mA 155mA Access Time 12ns 15ns 12ns 15ns 12ns 15ns Package Type (300 mil) (300 mil) (400 mil) (400 mil) TSOP (Type TSOP (Type
G-LINK Technology
March 1998 (Rev.
GLT710008
www.glinktech.com
G-LINK Technology 1753 South Main Street Milpitas, California, 95035, TEL: 408-240-1380 FAX: 408-240-1385 G-LINK Technology Corporation, Taiwan 24-2, Industry Science-Based Industrial Park Hsin Chu, Taiwan, R.O.C. TEL: 03-578-2833 FAX: 03-578-5820
2001 G-LINK Technology rights reserved. part this document copied reproduced form means transferred third party without prior written consent G-LINK Technology. Circuit diagrams utilizing G-LINK products included means illustrating typical semiconductor applications. Complete information sufficient design purposes necessarily given. G-LINK Technology reserves right change products specifications without notice. information contained this document does convey license under copyrights, patent rights trademarks claimed owned G-LINK subsidiaries. G-LINK assumes liability G-LINK applications assistance, customer's product design, infringement patents arising from semiconductor devices such systems' designs. does G-LINK warrant represent that patent right, copyright, other intellectual property right G-LINK covering relating combination, machine, process which such semiconductor devices might used. G-LINK Technology's products authorized life support devices systems. Life support devices systems device systems which are: intended surgical implant into human body designed support sustain life; when properly used according label instructions, reasonably expected cause significant injury user event failure. information contained this document believed entirely accurate. However, G-LINK Technology assumes responsibility inaccuracies. Printed

CMOS SRAM 1M-bit (128K CMOS SRAM organized 131,072 8bits Single +

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