Data Sheet January 2002 FEATURES 100ns volt supply) maximum addre

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Data Sheet January 2002 FEATURES 100ns volt supply) maximum addre

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QCOTSUT7Q512 512K SRAM
Data Sheet January 2002
FEATURES 100ns volt supply) maximum address access time Asynchronous operation compatibility with industrystandard 512K SRAMs compatible inputs output levels, three-state bidirectional data Typical radiation performance Total dose: 30krad(Si) 30krad(Si) 300krad(Si), depending orbit, using Aeroflex UTMC patented shielded package Immune >100 MeV-cm2/mg TH(0.25) MeV-cm2 Saturated Cross Section (cm2) bit, 7.32E-8 1.5E-7 errors/bit-day, Adams geosynchronous heavy Packaging options: 32-lead ceramic flatpack (weight 2.5-2.6 grams) 36-lead flatpack shielded (weight 10.77 grams) Standard Microcircuit Drawing 5962-99606 compliant INTRODUCTION QCOTSUT7Q512 Quantified Commercial Off-theShelf product high-performance CMOS static organized 524,288 words bits. Easy memory expansion provided active Chip Enable (E), active Output Enable (G), three-state drivers. This device power-down feature that reduces power consumption more than when deselected. Writing device accomplished taking Chip Enable input Write Enable input LOW. Data eight pins (DQ0 through DQ7) then written into location specified address pins through A18). Reading from device accomplished taking Chip Enable Output Enable while forcing Write Enable HIGH. Under these conditions, contents memory location specified address pins will appear eight pins. eight input/output pins (DQ0 through placed high impedance state when device deselected HIGH), outputs disabled HIGH), during write operation LOW).
Clk. Gen.
Pre-Charge Circuit
Select
Memory Array 1024 Rows 512x8 Columns
Circuit Column Select Data Control Gen.
Figure UT7Q512 SRAM Block Diagram
NAMES A(18:0) DQ(7:0) Address Data Input/Output Chip Enable Write Enable Output Enable Power Ground
DEVICE OPERATION UT7Q512 three control inputs called Enable Write Enable Output Enable (G); address inputs, A(18:0); eight bidirectional data lines, DQ(7:0). Device Enable controls device selection, active, standby modes. Asserting enables device, causes rise active value, decodes address inputs select 524,288 words memory. controls read write operations. During read cycle, must asserted enable outputs. Table Device Operation Truth Table Mode 3-state Data 3-state Data Mode Standby Write Read2 Read
Notes: defined "don't care" condition. Device active; outputs disabled.
READ CYCLE combination greater than (min), less than (max) defines read cycle. Read access time measured from latter Device Enable, Output Enable, valid address valid data output. SRAM read Cycle Address Access figure initiated change address inputs while chip enabled with asserted deasserted. Valid data appears data outputs DQ(7:0) after specified AVQV satisfied. Outputs remain active throughout entire cycle. long Device Enable Output Enable active, address inputs change rate equal minimum read cycle time (tAVAV SRAM read Cycle Chip Enable-Controlled Access figure initiated going active while remains asserted, remains deasserted, addresses remain stable entire cycle. After specified ETQV satisfied, eight-bit word addressed A(18:0) accessed appears data outputs DQ(7:0). SRAM read Cycle Output Enable-Controlled Access figure initiated going active while asserted, deasserted, addresses stable. Read access time tGLQV unless AVQV tETQV have been satisfied.
Figure UT7Q512 100ns SRAM Shielded Package Pinout (36)
Figure UT7Q512 100ns SRAM Package Pinout (32)
WRITE CYCLE combination less than (max) less than VIL(max) defines write cycle. state "don't care" write cycle. outputs placed high-impedance state when either greater than (min), when less than (max). Write Cycle Write Enable-Controlled ccess figure defined write terminated going high, with still active. write pulse width defined tWLWH when write initiated ETWH when write initiated Unless outputs have been previously placed highimpedance state byG, user must wait WLQZ before applying data nine bidirectional pins DQ(7:0) avoid contention. Write Cycle Chip Enable-Controlled Access figure defined write terminated latter going inactive. write pulse width defined tWLEF when write initiated ETEF when write initiated going active. initiated write, unless outputs have been previously placed high-impedance state
user must wait WLQZ before applying data eight bidirectional pins DQ(7:0) avoid contention. TYPICAL RADIATION HARDNESS Table Typical Radiation Hardness Design Specifications Total Dose Heavy Error Rate2 1.5E-7 krad(Si) nominal Errors/Bit-Day
Notes: SRAM will latchup during radiation exposure under recommended operating conditions. worst case particle environment, Geosynchronous orbit, Aluminum.
ABSOLUTE MAXIMUM RATINGS1 (Referenced SYMBOL TSTG PARAMETER supply voltage Voltage Storage temperature Maximum power dissipation Maximum junction temperature Thermal resistance, junction-to-case3 input current LIMITS -0.5 7.0V -0.5 7.0V +150°C 1.0W +150°C 10°C/W
Notes: Stresses outside listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond limits indicated operational sections this specification recommended. Exposure absolute maximum rating conditions extended periods affect device reliability performance. Maximum junction temperature increased +175°C during burn-in steady-static life. Test MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Positive supply voltage Case temperature range input voltage LIMITS 5.5V +125°C
ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (VDD 5.0V±10%) (-55°C +125°C) SYMBOL PARAMETER High-level input voltage Low-level input voltage Low-level output voltage High-level output voltage Input capacitance Bidirectional capacitance Input leakage current Three-state output leakage current 2.1mA,V =4.5V -1mA,VDD =4.5V 1MHz 1MHz (max) (max) (max) DD(OP) Short-circuit output current Supply current operating 1MHz Inputs: 0.8V, 2.2V IOUT (max) (OP) Supply current operating @10MHz Inputs: 0.8V, 2.2V IOUT (max) IDD2(SB) Nominal standby supply current @0MHz Inputs: IOUT (max) 0.5V
Notes: Post-radiation performance guaranteed 25°C MIL-STD-883 Method 1019 Measured only initial qualification after process design changes that could affect input/output capacitance. Supplied design limit guaranteed tested. more than output shorted time maximum duration second.
CONDITION
UNIT
-55°C 25°C +125°C
CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)* (VDD 5.0V±10%) (-55°C +125°C) SYMBOL tAVAV1 tAVQV tAXQX2 tGLQX tGLQV tGHQZ tETQX tETQV tEFQZ1,2,4 Read cycle time Read access time Output hold time G-controlled Output Enable time G-controlled Output Enable time (Read Cycle G-controlled output three-state time E-controlled Output Enable time E-controlled access time E-controlled output three-state time PARAMETER UNIT
Notes: Post-radiation performance guaranteed MIL-STD-883 Method 1019. Functional test. Three-state defined 500mV change from steady-state output voltage (see Figure (enable true) notation refers falling edge immunity does affect read parameters. (enable false) notation refers rising edge immunity does affect read parameters.
High Active Levels
Active High Levels
VLOAD 500mV VLOAD VLOAD 500mV
500mV
500mV
Figure 5-Volt SRAM Loading
tAVAV A(18:0)
DQ(7:0)
Previous Valid Data
Valid Data tAVQV
Assumptions: (max) (min)
tAXQX Figure SRAM Read Cycle Address Access
A(18:0)
tETQV tEFQZ ETQX
DATA VALID
DQ(7:0)
Assumptions: (max) (min)
Figure SRAM Read Cycle Chip Enable Controlled Access
AVQV A(18:0) tGLQX DQ(7:0)
Assumptions: (max) (min)
tGHQZ
DATA VALID
tGLQV
Figure SRAM Read Cycle Output Enable Controlled Access
CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)* (VDD 5.0V±10%) (-55°C +125°C) SYMBOL tAVAV tETWH tAVET tAVWL tWLWH tWHAX tEFAX tWLQZ tWHQX tETEF tDVWH tWHDX tWLEF tDVEF tEFDX tAVWH tWHWL1 Write cycle time Device Enable write Address setup time write controlled) Address setup time write controlled) Write pulse width Address hold time write controlled) Address hold time Device Enable controlled) controlled three-state time controlled Output Enable time Device Enable pulse width controlled) Data setup time Data hold time Device Enable controlled write pulse width Data setup time Data hold time Address valid write Write disable time PARAMETER UNIT
Notes: Post-radiation performance guaranteed 25°C MIL-STD-883 Method Functional test performed with outputs disabled high). Three-state defined 500mV change from steady-state output voltage (see Figure
A(18:0) AVAV2 tAVWH ETWH tAVWL Q(7:0) tWLQZ D(7:0)
Assumptions: (max). (min) then 7:0) will three-state entire cycle. high AVAV cycle. APPLIED DATA
WHWL tWHAX
WLWH
tWHQX
tDVWH
tWHDX
Figure SRAM Write Cycle Write Enable Controlled Access
tAVAV A(18:0) AVET tETEF tEFAX
AVET tETEF tWLEF
APPLIED DATA
tEFAX
D(7:0)
WLQZ Q(7:0)
DVEF
EFDX
Assumptions Notes: (max). (min) then Q(7:0) will three-state entire cycle. Either scenario above occur. high AVAV cycle.
Figure SRAM Write Cycle Chip Enable Controlled Access
CMOS DD-0.05V ohms LOAD 1.75V 0.5V 50pF Input Pulses
Notes: 50pF including scope probe test socke capacitance. Measurement data output occurs high high transition mid-point (i.e., CMOS input DD/2).
Figure Test Loads Input Waveforms
DATA RETENTION MODE
4.5V
Figure Data Retention Waveform (100ns)
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) 25°C, Data Retention Test) SYMBOL tEFR tR1,2 PARAMETER data retention Data retention current Chip deselect data retention time Operation recovery time MINIMUM tAVAV MAXIMUM UNIT
Notes: other inputs guaranteed tested.
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) 25°C, Second Data Retention Test) SYMBOL tEFR2, tR2, PARAMETER data retention Chip select data retention time Operation recovery time MINIMUM tAVAV MAXIMUM UNIT
Notes: Performed (min) (max). other inputs guaranteed tested.
PACKAGING
exposed metalized areas gold plated over electroplated nickel MIL-PRF-38535. electrically connected Lead finishes accordance MIL-PRF-38535. Lead position coplanarity measured. mark vendor option. With solder increase maximum 0.003". Weight 2.5-2.6 grams. Figure 32-pin Ceramic FLATPACK package
package finishes MIL-PRF-38535. Letter designations cross-reference MIL-STD-1835. leads increase max. limit 0.003 measured center flat, when lead finish (solder) applied. Total weight approx. 10.77 Figure 36-lead flatpack shielded package
ORDERING INFORMATION 512K SRAM:
UT7Q512K
Lead Finish: solder dipped Gold Factory option (gold solder)
Screening: Military Temperature Range flow Prototype flow Extended Industrial Temperature Range Flow (-40oC +125oC)
Package Type: 36-lead flatpack ielded package (bottom brazed) 32-lead ceramic flatpack package (bottom brazed) 100ns access time, operation
Aeroflex UTMC Core Part Number
Notes: Lead finish (A,C, must specified. specified when ordering, then part marking will match lead finish will either (solder) (gold). Prototype flow UTMC Manufacturing Flows Document. Tested 25°C only. Lead finish GOLD ONLY. Radiation neither tested guaranteed. Military Temperature Range flow UTMC Manufacturing Flows Document. Devices tested room temp, +125° Radiation neither tested guaranteed. 36LBBFP Shielded Package reduced high orders only. Extended Industrial Temperature Range flow UTMC Manufacturing Flows Document. Devices tested -40°C +125°C. Radiation neither tested guaranteed. Gold Lead Finish Only.
512K SRAM:
5962 99606
Lead Finish: solder dipped Gold Factory Option (gold solder) Case Outline: 36-lead flatpack shielded package (bottom-brazed) 32-lead ceramic flatpack package (bottom-brazed) Class Designator: Class Class
Device Type 100ns access time, volt operation Mil-Temp 100ns access time, volt operation, Extended Industrial Temp (-40 +125 Drawing Number: 99606 Total Dose none krad(Si)) (30krad(Si)), Contact Factory Federal Stock Class Designator: Options
Notes: 1.Lead finish (A,C, must specified. 2.If specified when ordering, part marking will match lead finish will either (solder) (gold). 3.Total dose radiation must specified when ordering. available without radiation hardening.

Data Sheet January 2002 FEATURES 100ns volt supply) maximum addre

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