MONOLITHIC MANCHESTER ENCODER/DECODER (SERIES 3D7503) All-silicon

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MONOLITHIC MANCHESTER ENCODER/DECODER (SERIES 3D7503) All-silicon

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3D7503
MONOLITHIC MANCHESTER ENCODER/DECODER (SERIES 3D7503)
All-silicon, low-power CMOS technology Encoder decoder function independently Encoder buffered clock output TTL/CMOS compatible inputs outputs Vapor phase, wave solderable Auto-insertable (DIP pkg.) ground bounce noise Maximum data rate: MBaud Data rate range: ±15% Lock-in time:
COUT RESB
data delay devices, inc.
PACKAGES
CBUF LOOP TXENB DOUTB
3D7503-xxx (.300) 3D7503G-xxx Gull Wing (.300) 3D7503D-xxx SOIC (.150)
FUNCTIONAL DESCRIPTION
3D7503 monolithic CMOS Manchester Encoder/Decoder combo chip. device uses bi-phase-level encoding embed clock signal into data stream transmission across communications link. this encoding mode, logic represented high-to-low transition center cell, while logic zero represented low-to-high transition. Manchester encoder combines clock (CIN) data (DIN) into single bi-phase-level signal (TX). inverted version this signal (TXB) also available. data baud rate MBaud) equal input clock frequency MHz). replica clock input also available (CBUF).
DESCRIPTIONS
Encoder: Clock Input Data Input RESB Reset Clock buffer enable TXENB Transmit enable CBUF Buffered clock TX,TXB Transmitted signal Decoder: Received Signal COUT Recovered Clock DOUTB Recovered Data
encoder reset setting RESB input low; otherwise, Common: should left high. signals disabled (high-Z) LOOP Loop enable setting TXENB high. Similarly, CBUF disabled setting Volts low. Under most operating conditions, encoder never reset, Ground always enabled, CBUF used. With this mind, 3D7503 provides internal pull-up resistor RESB internal pulldown resistors TXENB, that most users leave these inputs uncommitted. Manchester decoder accepts embedded-clock signal input. recovered clock data signals presented COUT DOUTB, respectively, with data signal inverted. operating baud rate MBaud) specified dash number device. input baud rate vary much ±15% from nominal device baud rate without compromising integrity information received. Because decoder PLL-based, does require long preamble order lock onto received signal. Rather, device requires most cell before data presented output valid. This extremely useful cases where information arrives bursts input otherwise turned off. Normally, encoder decoder function independently. However, LOOP input high, encoded signal back internally into decoder input ignored. This feature useful diagnostics. LOOP input internal pull-down resistor left uncommitted this feature needed. ©1998 Data Delay Devices
#98009
12/11/98
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7503 TABLE PART NUMBER SPECIFICATIONS
PART NUMBER
3D7503-5 3D7503-10 3D7503-20 3D7503-25 3D7503-30 3D7503-40 3D7503-50 NOTE:
DECODER BAUD RATE (MBaud) Nominal Minimum Maximum
5.00 10.00 20.00 25.00 30.00 40.00 50.00 4.25 8.50 17.00 21.25 25.50 34.00 42.50 5.75 11.50 23.00 28.75 34.50 46.00 57.50
baud rate between MBaud shown also available extra cost.
APPLICATION NOTES
ENCODER
Manchester encoder subsystem samples data input rising edge input clock. sampled data used conjunction with clock rising falling edges generate byphase level Manchester code. encoder employs timing clock rising falling edges (duty cycle) implement required coding scheme, shown Figure reduce difference between output data high time time, essential that deviation input clock duty cycle from 50/50 minimized. encoder presents outputs true complimented encoded data. High-toLow time skew selected data output should budgeted user, relates application, satisfactorily estimate distortion transmitted data stream. Such estimate very useful determining functionality margins data link, Manchester decoder used decode received data.
RESET (RESB)
(Left high normal operation)
1/fC
CLOCK (CIN)
DATA (DIN)
TRANSMIT (TXB)
TRANSMIT (TX)
Figure Timing Diagram (Encoder)
#98009
12/11/98
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7503
APPLICATION NOTES (CONT'D)
DECODER
Manchester decoder subsystem samples input precise pre-selected intervals retrieve data recover clock from received data stream. architecture comprises finely tuned delay elements proprietary circuitry which, conjunction with other circuits, implement data decoding clock recovery function. Typically, encoded data transmitted from source arrives decoder corrupted. Such corruption received data manifests itself jitter and/or pulse width distortion decoder input. instantaneous deviations from nominal Baud Rate and/or Pulse Width (high low) adversely impact data extraction clock recovery function their published limits exceeded. Table Allowed Baud Rate/Duty Cycle. decoder, being self-timed device, tolerant frequency modulation (jitter) present input data stream, provided that input data pulse width variations remain within allowable ranges. decoder presents outputs decoded data (inverted) recovered clock. decoded data valid rising edge clock. clock recovery function operates modes dictated input data stream sequence. When data succeeded inverse, clock recovery circuit engaged forces clock output time equal over twice baud rate. Otherwise, input presented clock output unchanged, shifted time. Therefore, clock duty cycle strongly dependent baud rate, this will affect clock-high duration. clock output falling edge operated clock recovery circuitry. therefore, preserves more accurately clock frequency information embedded transmitted data. therefore used, desired, retrieve clock frequency information.
INPUT SIGNAL CHARACTERISTICS
3D7503 inputs compatible. user should assure him/herself that volt threshold used when referring timing, especially input clock duty cycle (encoder) received data (decoder).
POWER SUPPLY TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry strongly dependent power supply temperature. monolithic 3D7503 Manchester encoder/decoder utilizes novel innovative compensation circuitry minimize timing variations induced fluctuations power supply and/or temperature. Nevertheless, optimum performance achieved providing stable power supply clean ground plane, placing bypass capacitor (0.1uf typically) close device possible.
ENCODED RECEIVED (RX)
CLOCK (CLK) DATA (DATB) DECODED
tCWL
Figure Timing Diagram (Decoder)
#98009
12/11/98
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7503
DEVICE SPECIFICATIONS
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Input Current Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
70C, 4.75V 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current High Level Output Current Level Output Current Output Rise Fall Time SYMBOL -4.0 UNITS NOTES
4.75V 2.4V 4.75V 0.4V
*IDD(Dynamic) where: Average capacitance load/pin (pf) Input frequency (GHz)
Input Capacitance typical Output Load Capacitance (CLD)
TABLE ELECTRICAL CHARACTERISTICS
70C, 4.75V 5.25V, except noted) PARAMETER
Input Baud Rate (Encoder) Clock Frequency Data set-up clock rising Data hold from clock rising High-Low time skew High-Low time skew High/Low time skew Nominal Input Baud Rate (Decoder) Allowed Input Baud Rate Deviation Allowed Input Baud Rate Deviation Allowed Input Baud Rate Deviation Allowed Input Duty Cycle Cell Time Input Data Edge Clock Falling Edge Clock Width Clock Falling Edge Data Transition SYMBOL
-3.5 -2.0 -3.0 -0.15 -0.05 -0.03 42.5 50.0 1000/fB 0.75 500/fBN
0.15 0.05 0.03 57.5
UNITS MBaud MBaud MBaud MBaud MBaud
NOTES
25C, 5.00V -40C 4.75V 5.25V -55C 125C 4.75V 5.25V
tCWL
±2ns
Notes: Assumes duty cycle clock input
#98009
12/11/98
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7503
AUTOMATED TESTING MONOLITHIC PRODUCTS
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High 3.0V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.4V Pulse Width: PWIN 1/(2*BAUD) Period: PERIN 1/BAUD OUTPUT: Rload: Cload: Threshold: 1.5V (Rising Falling)
Device Under Test
Digital Scope
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
WAVEFORM GENERATOR
TRIG
DEVICE UNDER TEST (DUT)
TRIG
DIGITAL SCOPE
Figure Test Setup
PERIN PWIN tRISE INPUT SIGNAL
2.4V 1.5V 0.6V
tFALL
2.4V 1.5V 0.6V
tPHL
tPLH OUTPUT SIGNAL
1.5V
1.5V
Figure Timing Diagram
#98009
12/11/98
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013

MONOLITHIC MANCHESTER ENCODER/DECODER (SERIES 3D7503) All-silicon

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