µPD98402A LOCAL ASONET FRAMER µPD98402A ATM-LAN LSIs incorpo
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INTEGRATED CIRCUIT
µPD98402A
LOCAL ASONET FRAMER
µPD98402A ATM-LAN LSIs incorporates sublayer function SONET/SDHbased physical layer Aprotocol. main functions µPD98402A include transmit function mapping Acells received from Alayer onto payload block SONET STS-3c/SDH STM-1 frame sending them (Physical Media Dependent) physical layer, receive function separating overhead block Acells from data string received from sublayer sending Acells Alayer. Futhermore, µPD98402A compliant with AForum Recommendations.
FEATURES
Provision sublayer function Aprotocol physical layer Support SONET STS-3c frame/SDH STM-1 frame format Provision stop mode cell scramble/descramble frame scramble/descramble Disposal/transitory selection unassigned cells possible. Compliant with UTOPIA interface Incorporation internal loopback function Alayer turns interface 155.52 Mbps serial interface 19.44 parallel interface Provided with registers writing/reading overhead information (section overhead): (1st 3rd) bytes, byte (line overhead): byte (pass overhead): byte, byte CMOS process single power supply
information this document subject change without notice.
Document S10835EJ1V0DS00 (1st edition) Date Published December 1995 Printed Japan
1995
µPD98402A
Incorporation (Operation Maintenance) function Transmitting side Transmission various alarms Transmission generation sources Line (FERF), Path (FERF) Line FEBE, Path FEBE Transmission command instruction Line AIS, Path Line FEBE, Path FEBE Receiving side Detection alarms error signals (Loss Signal) (Out Frame) (Loss Frame) (Loss Pointer) (Loss Cell delineation) Line (FERF), Path (FERF) Line AIS, Path Detection display quality deterioration sources error, error, error, Line FEBE, Path FEBE Incorporation counter counting number performance monitoring errors byte error counter byte error counter byte error counter Line FEBE error counter Path FEBE error counter
µPD98402A
ORDERING INFORMATION
Part Number Package
µPD98402AGM-KED160-pin plastic (FINE PITCH)
APPLICATION EXAMPLES
followings examples terminal equipment AHub application using µPD98402A. APPLICATION
DATA (UTOPIA)
CLOCK RECOVERY CHIP
CONTROL MEMORY
PD98401A CHIP
PD98402A CHIP
155.52MHz HOST SYNTHESIZER
HOST
APPLICATION (NIC SIDE)
DATA SWITCH SYSTEM (UTOPIA) PD98402A CHIP
CLOCK RECOVERY CHIP
155.52MHz SYNTHESIZER
CONTROLLER
CONTROLLER
BLOCK DIAGRAM
RxFP
PSEL
TDOC, TDOT
TCOC, TCOT
TFKC, TFKT
Serialfi Parallel
Cell Descrambler
Descrambler Idle Cell Drop
Timing Generator Cell Delineation Verification Correction
Loop Back
FIFO Cell
RDIC, RDIT
SONET Framing
RCIC, RCIT
RDO0-RDO7 RENBL EMPTY RSOC RCLK TDI0-TDI7 TENBL FULL TSOC TCLK
Loop Back
TPD0-TPD7
Interface
ALayer Interface
RPD0-RPD7
Parallel fiSerial
Scrambler
Cell Scrambler
Generator
FIFO Cell Idle Cell Insert
Overhead Registers C1(#1~#3) Overhead Controller Overhead Controller
D0-D7 A0-A5
Generator (Tx)
Generator (Rx) Timing Generator Sequencer
Overhead Registers C1(#1~#3) Mode Register Performance Registers Cause Registers
PHINT
Management Interface
TRST
Test Block
RESET
µPD98402A
TxFP
TFSS
µPD98402A
FUNCTIONAL GROUPS
Control
RESET
TFSS
RxFP
TxFP
RDIC RDIT RCIC RCIT TDOC TDOT Interface TCOC TCOT TFKC TFKT
RDO0-RDO7 RCLK RSOC RENBL EMPTY TDI0-TDI7 TCLK TSOC TENBL FULL
ALayer Interface
TPD0-TPD7
D0-D7 A0-A5
Management Interface
RPD0-RPD7 PSEL
PHINT
Interface
JTAG boundary scanNote
Note This function supported customer's request.
TRST
µPD98402A
CONFIGURATION
160-pin plastic (FINE PITCH) (Top View)
TRST TFSS RxFP TxFP TPD0 TPD1 TPD2 TPD3 TPD4 RESET
Remarks Internally Connected. Leave open. Connect GND.
TPD5 TPD6 TPD7 TFKT TFKC TCOT TCOC TDOT TDOC RCIT RCIC RDIT RDIC RPD7 RPD6 RPD5 RPD4 RPD3 RPD2 RPD1 RPD0 PSEL
RDO7 RDO6 RDO5 RDO4 RDO3 RDO2 RDO1 RDO0 RCLK RENBL RSOC EMPTY FULL TSOC TEMBL TCLK TDI7 TDI6 TDI5 TDI4 TDI3 TDI2 TDI1 TDI0 PHINT
PD98402AGM-KED
µPD98402A
A0-A5 D0-D7 EMPTY FULL PHINT PSEL RCIC RCIT RCLK RDIC RDIT Address Read/write Cycle Receive Acknowledge Chip Enable Data Output Buffer Empty Buffer Full Ground Loss Signal Output Enable Frame Physical Interrupt Select Receive Alarm Receive Clock Input Complement Receive Clock Input True Internal Receive System Clock Receive Data Transferring Clock from ALayer Device Receive Data Input Complement Receive Data Input True
RDO0-RDO7 Receive Data Output RENBL Receive Data Enable RESET System Reset Receive Parallel Data Clock
RPD0-RPD7 Receive Parallel Data RSOC Receive Start Address ACell RxFP TCLK TCOC TCOT TDI0-TDI7 TDOC TDOT TENBL TFKC TFKT TFSS Read/write Control Receive Frame Pulse Transmit Alarm Test Clock Internal Transmit System Clock Transmit Data Transferring Clock from ALayer Device Transmit Clock Output Complement Transmit Clock Output True Transmit Data Input from ALayer Test Data Output Transmit Data Output Complement Transmit Data Output True Transmit Data Enable Transmit Reference Clock Transmit Reference Clock Complement Transmit Reference Clock True Transmit Frame Signal Test JTAG Data Input
Transmit Parallel Data Clock TPD0-TPD7 Transmit Parallel Data TRST TSOC TxFP Test Mode Select Test Reset Transmit Start Address ACell Transmit Frame Pulse Supply Voltage
µPD98402A
FUNCTIONS
Interface
Symbol RDIC RDIT RCIC RCIT TDOC TDOT TCOC Level Pseudo Complement Pseudo True Pseudo Complement Pseudo True Pseudo Complement Pseudo True Pseudo Complement Pseudo True Pseudo Complement Pseudo True Function These pins used input receive serial data when serial interface mode used (PSEL input level). Ground them when Parallel interface mode used.
These pins used input receive system clock when serial interface mode used (PSEL input level). Clocks input synchronization with receive data. Ground them when parallel interface mode used. These pins used output transmit serial data when serial interface mode used (PSEL input level). They open-drain pins. Terminate them with resistor. undefined after reset. These pins used output transmit clocks when serial interface mode used (PSEL input level). Transmit clocks input TFKC/TFKT pins output passing through internal gates. They open-drain pins. Terminate them with resistor. undefined after reset. These pins used input transmit system clocks when serial interface mode used (PSEL input level). Transmit data output from TDOC/TDOT pins output synchronization with clocks that input these pins. Ground them when parallel interface mode used.
TCOT
TFKC
TFKT
RPD0-RPD7
77-73, 71-69
These pins used input receive parallel data when parallel interface mode used (PSEL input high level). Leave them open when serial interface mode used. This used input receive system clock when parallel interface mode used (PSEL input high level). Input clocks synchronous with receive data. Leave open when serial interface mode used. These pins used output transmit parallel data when parallel interface mode used (PSEL input high level). Leave them open when serial interface mode used. This used output transmit clocks when parallel interface mode used (PSEL input high level). Transmit clocks input output passing through internal gates. Leave open when serial interface mode used. This pins used input transmit system clocks when parallel interface mode used (PSEL input high level). Transmit data output from pins TPD0 TPD7 output synchronization with clocks input this pin. Leave open when serial interface mode used. This used select mode interface serial/ parallel interface. level: Serial interface mode High level: Parallel interface mode
TPD0-TPD7
35-39, 43-45
CMOS
CMOS
PSEL
CMOS
µPD98402A
Power supply
Symbol 100, 120, 137, 101, 107, 113, 121, 122, 128, 138, 140, 147, 149, 159, Supply voltage, Function
Ground
ALayer Interface
Symbol RDO0-RDO7 151-158 Level CMOS Function Connected 8-bit data output receive data ALayer device. Output synchronized with RCLK rising undefined after reset. Input receive data transferring clock from ALayer device. Receive cell start address signal. ALayer device, this signal indicates start address byte receive Acell. undefined after reset. Receive enable signal. Input signal indicating that Alayer device receive data. Output buffer empty signal. This signal indicates that there data transferred receive FIFO µPD98402A. inactive after reset. 8-bit data input transmit data from ALayer device. Reading data synchronized with TCLK rising-up. Input transmit data transferring clock from Alayer device. Transmit cell start address signal. Input signal indicating start byte transmit Acell input from ALayer device µPD98402A. Transmit enable signal. This signal indicates that ALayer device transmitting valid data TDI0-TDI7. Input buffer full signal. When bytes remain acceptable bytes transmit FIFO last, this signal changes active. inactive after reset.
RCLK RSOC
CMOS
RENBL EMPTY
CMOS
TDI0-TDI7
129-136
TCLK TSOC
TENBL FULL
CMOS
µPD98402A
Management Interface
Symbol D0-D7 A0-A5 104-106 108-112 114-119 Level CMOS Function 8-bit data data transfer between control processor internal register µPD98402A. Address bus. Used setting internal register address µPD98402A. Read/write control signal. level: Write cycle High level: Read cycle Chip enable signal. level, internal register access enable. Read/write cycle receive acknowledge ready signal. After reset, this signal indicates inactive level. Signal which indicates interrupt cause occurrence processor. After reset, this signal indicates inactive level. Output enable. When this signal level, µPD98402A outputs data control bus. Even signal inactive, when this signal level, µPD98402A drives control bus.
PHINT
CMOS CMOS
Interface
Symbol Level CMOS Function Loss signal detection. Output high level when receive serial data input continuously optical input stop signal (RAL) input. When consecutive frames valid synchronous pattern detected, when input optical input stop signal released, level output. inactive after reset. frame detection. When consecutive frames wrong synchronous pattern detected, high level output. When consecutive frames normal synchronous pattern detected, level output. inactive after reset. Receive alarm. Inputs receiver-side optical input stop signal optical module. level: Normal High level: Optical input stopped. Transmit alarm. Inputs transmit-side optical output stop signal output optical module. level: Normal High level: Optical output stopped.
CMOS
µPD98402A
Control
Symbol TFSS Level Function This transmit frame setting signal input pin. allows synchronization timing transmit frame output set. µPD98402A samples this input signal internal transmit system clock (TCL). Initial output transmit frame restarted clocks into clock cycle after high level latched rise. This system reset signal input pin. initializes µPD98402A. necessary input reset signal with pulse width cycles more clock that longest cycle among following clocks input µPD98402A. Alayer TCLK, RCLK clock cycles layer cycle TFKT/TFKC, RCIC/RCIT clocks, TFC, clock cycles Immediately after reset, read/write possible registers during clocks clock (19.44 MHz). This used output internal transmit system clock. µPD98402A outputs internal transmit system clock, TFKT/TFKC input clock (155.52 MHz) scaled serial interface mode, input clock (19.44 MHz) parallel interface mode. This used output internal receive system clock. µPD98402A outputs internal receive system clock, RCIC/RCIT input clock (155.52 MHz) scaled serial interface mode, input clock (19.44 MHz) parallel interface mode. This frame pulse signal transmitting side. outputs pulses synchronous with transmit frame start. inactive after reset. This frame pulse signal receiving side. outputs pulses synchronous with receive frame start. inactive after reset.
RESET
CMOS
CMOS
TxFP
CMOS
RxFP
CMOS
JTAG boundary scan pins (This function supported customer's request.)
Symbol TRST Level CMOS Function This JTAG boundary scan. Pull ground normal operation. This JTAG boundary scan. Leave open normal operation. This JTAG boundary scan. Pull ground normal operation. This JTAG boundary scan. Pull ground normal operation. This JTAG boundary scan. Ground normal operation.
µPD98402A
Recommended Connection Unused Pins
TDOC, TDOT, TCOC, TCOT, ACK, LOS, OOF, TCL, TxFP, RxFP RAL, TAL, TFSS Recommended connection leave open connect
µPD98402A
ELECTRICAL SPECIFICATION
Absolute maximum ratings
Parameters Supply voltage Input/output voltage Operating ambient temperature Storage temperature Symbol VI/VO Tstg Conditions Ratings -0.5 +6.5 -0.5 +0.5 +150 Unit
Caution
Exposure absolute maximum ratings extended periods affect device reliability; exceeding ratings could cause permanent damage. parameters apply independently. device should operated within limits specified under characteristics.
Capacitance
Parameters Input capacitance Output capacitance Input/output capacitance Symbol Conditions MIN. TYP. MAX. Unit
Recommended operating conditions
Parameters Supply voltage Operating ambient temperature Symbol VIL1 level input voltage VIL2 VIL3 VIH1 High level input voltage VIH2 VIH3 Note1 Note2 Note3 Note1 Note2 Note3 Conditions MIN. 4.75 DD-2 DD-1.1 TYP. MAX. 5.25 +0.8 DD-1.5 Unit
Notes
input Pseudo input CMOS input
µPD98402A
Characteristics (VDD ±0.25
Parameters Off-state output current Input leak current ILI2 VOH1 High level output voltage VOH2 level output voltage Supply current Note Normal operation DD-2.0 DD-1.7 Note Note4 DD-0.9 DD-0.4 Note -0.5 Note4 Symbol ILI1 Conditions Note1 Note2 MIN. TYP. MAX. Unit
Notes
3-state data input Pseudo input CMOS output Pseudo output
µPD98402A
Characteristics Management Interface Internal Register Read/Write
Parameters A0-A5 setup time setup time A0-A5 hold time hold time CEACK delay time (read) Symbol tSCC1 tSCC2 tHCC1 tHCC2 tDCNAR Load capacitor parallel data input Load capacitor serial data input CEACK delay time (write) tDCNAW Load capacitor parallel data input Load capacitor serial data input CEACK delay time tDCPA Load capacitor parallel data input Load capacitor serial data input data output delay time tDCD Load capacitor parallel data input Load capacitor serial data input data output delay time data floating output delay time D0-D7 setup time D0-D7 hold time low-level width tDOD tFOD tSDC tHCD tCEBW parallel data input serial data input low-level width tOEBW parallel data input serial data input Load capacitor Load capacitor Conditions MIN. tCYPPR (tCYPSR tCYPPR (tCYPSR tCYPPR (tCYPSR tCYPPR (tCYPSR tCYPPR (tCYPSR tCYPPR (tCYPSR tCYPPR (tCYPSR tCYPPR (tCYPSR tCYPPR (tCYPSR tCYPPR (tCYPSR TYP. MAX. Unit
Remarks
tCYPPR, refer parallel interface timing. tCYPSR, refer serial interface timing.
µPD98402A
Management Interface Internal Register Read Case When host uses signal
tSCC1 A0-A5
tHCC1
tSCC2
tHCC2 tCEBW
tOEBW tDCNAR tDOD Valid tDCD
tDCPA
D0-D7
tFOD
Case
When host does signal
tSCC1 A0-A5
tHCC1
tSCC2
tHCC2 tCEBW
tOEBW Valid tDOD tFOD
D0-D7
µPD98402A
Internal Register Write
tSCC1 A0-A5
tHCC1
tHCC2 tSCC2 tDCNAW Valid tSDC tHCD tDCPA
D0-D7
Interface
Parameters TCLLOS delay time RCLOOF delay time Symbol tDCLS tDCOF Conditions load capacitor load capacitor MIN. TYP. MAX. Unit
Interface
tDCLS tDCOF
µPD98402A
Control Signal Interface
Parameters TCLTPC delay time TFSS setup time TCL) TFSS hold time TCL) TCLTxFP delay time RCLRxFP delay time Symbol tDTCP tSFSC tHCFS tDCFP tDCRP load capacitor load capacitor Conditions load capacitor MIN. TYP. MAX. Unit
Control Signal Interface
tDTCP tDCFP TFSS TxFP tSFSC tHCFS tDCFP
RxFP tDCRP tDCRP
µPD98402A
Interface (Transmitter Side)
Parameters TCLK cycle time TCLK high level width TCLK level width TCLKFULL delay time TDI0-TDI7 setup time TCLK) TSOC setup time TCLK) TENBL setup time TCLK) TDI0-TDI7 hold time TCLK) TSOC hold time TCLK) TENBL hold time TCLK) Symbol tCYST tSTH tSTL tSTDK1 tSTDK2 tSTDK3 tHKTD1 tHKTD2 tHKTD2 load capacitor Conditions MIN. TYP. MAX. Unit
Interface (Transmitter Side)
tCYST TCLK tSTH FULL TENBL tHKTD2 TSOC tSTDK1 tHKTD1 tSTDK2 tHKTD3 tSTDK3 tSTL
TDI0-TDI7
Invalid
µPD98402A
Interface (Receiver Side)
Parameters RCLK cycle time RCLK high level width RCLK level width RCLKEMPTYdelay time RENBL setup time RCLK) RENBL hold time RCLK) RCLKRSOC delay time RCLKRDO0-RDO7 delay time Symbol tSYCR tSRH tSRL tSREK tHKRE tRSD tRDD load capacitor load capacitor load capacitor Conditions MIN. TYP. MAX. Unit
Interface (Receiver Side)
tSYCR RCLK tSRH EMPTY tSREK RENBL tRSD RSOC tRDD RDO0-RDO7 tRDD tRSD tHKRE tSRL
µPD98402A
Parallel Interface
Parameters cycle time high level width level width cycle time high level width level width RPD0-RPD7 setup time RPC) RPD0-RPD7 hold time RPC) TFCTPC delay time TFCTPC delay time TPCTPD0-TPD7 delay time Symbol tCYPPR tPPRH tPPRL tCYPPT tPPTH tPPTL tSPDC tHPCD tDFPCP tDFPCN tDPCD load capacitor load capacitor load capacitor Conditions MIN. -3.0 TYP. MAX. +1.0 Unit
Parallel Interface Receive Side
tCYPPR tPPRH tPPRL
RPD0-RPD7 tSPDC tHPCD
Transmit Side
tDFPCP
tDFPCN
tCYPPT tPPTH tPPTL
TPD0-TPD7 tDPCD
µPD98402A
Serial Interface
Parameters RCIT (RCIC) cycle time TFKT (TFKC) cycle time Serial data setup time Serial data hold time Serial clock delay time (rising) Serial clock delay time (falling) Transmit serial data delay time Symbol tCYPSR tCYPST tSSDC tHSCD tDFSCP tDFSCN tDSCD Load capacitor Load capacitor Load capacitor Conditions MIN. TYP. MAX. Unit
Serial Interface Receive Side
tCYPSR RCIC, RCIT
RDIC, RDIT tSSDC tHSCD
Transmit Side
tDFSCP TFKC, TFKT tDFSCN tCYPST
TCOC, TCOT TDOC, TDOT tDSCD
µPD98402A
PACKAGE DRAWING
PLASTIC (FINE PITCH)
detail lead
NOTE Each lead centerline located within 0.10 (0.004 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 26.0±0.2 24.0±0.2 24.0±0.2 26.0±0.2 2.25 2.25 0.22 +0.05 -0.04 0.10 (T.P.) 1.0±0.2 0.5±0.2 0.17 +0.03 -0.07 0.10 0.125±0.075 5°±5° MAX. INCHES 1.024 +0.008 -0.009 0.945±0.008 0.945±0.008 1.024 +0.008 -0.009 0.089 0.089 0.009±0.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.004 0.106 0.005±0.003 5°±5° 0.119 MAX.
S160GM-50-3ED, JED, KED-2
µPD98402A
RECOMMENDED SOLDERING CONDITIONS
µPD98402A, soldering must performed under following conditions. details recommended conditions surface mounting, refer information document "Semiconductor Device Mounting Technology Manual" (IEI-1207). other soldering methods, please consult with sales personnel. µPD98402AGM-KED: 160-pin plastic (FINE PITCH)
Soldering Method Soldering Conditions Package peak temperature: time: sec. max. (over °C), count: twice less, restriction days: 3Note (after that, pre-baking hours necessary) Precautions: Reflow second time should started when device temperature returned normal state after first reflow. Avoid flux cleaning with water after first reflow. temperature: max., time: seconds max. (per side) Symbol
Infrared reflow
IR35-203-2
partial heating
Note
This means number days after unpacking pack. Storage conditions max.
µPD98402A
[MEMO]
µPD98402A
[MEMO]
export this product from Japan prohibited without governmental license. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customer must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact Sales Representative advance. Anti-radioactive design implemented this product.
94.11
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