µPD98408 6-PORT APHY µPD98408 Aphysical layer that complies

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µPD98408 6-PORT APHY µPD98408 Aphysical layer that complies

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INTEGRATED CIRCUIT
µPD98408
6-PORT APHY
µPD98408 Aphysical layer that complies with ATM25 (25.6 Mbps) which supports sublayer sublayer functions. Interfacing with Alayer layer implemented UTOPIA Level
FEATURES
Provides 25.6-Mbps APHY (PMD function circuits Conforms AForum interface specifications (af-phy-0040.000 November 1995). UTOPIA Level V1.0 (af-phy-0039.000 June 1995: max. bits/40 MHz) interface Three-cell built-in transmit/receive FIFOs each circuit sublayer functions: Built-in clock recovery. Built-in equalizer. sublayer functions: NRZI encoder/decoder. Command byte insertion/detection. 4B/5B encoder/decoder. Cell scrambler/descrambler. generation/verification. interface: Intel Motorola selected. Supports (Categories Loopback function: Loopback Alayers. Operation Maintenance (OAM) functions: Input failure detection, error detection 4B/5B code error detection. Test function: Supports JTAG. Power supply voltage:
ORDERING INFORMATION
Part Number Package 208-pin plastic (fine pitch)
µPD98408GD-LML
Remark This document indicates active pins format "xxx_B" after name).
information this document subject change without notice.
Document S12313EJ2V1DS00 (2nd edition) Date Published April 1998 CP(K) Printed Japan
1997
µPD98408
SYSTEM CONFIGURATION EXAMPLE (APPLICATION)
Aswitching
UTOPIA Level UTOPIA Level
PD98408
SONET-IF
µPD98408
ATM-SW
Backbone network
UTOPIA Level
25-Mbps Ainterface using (Category
UTOPIA Level
BLOCK DIAGRAM
JTAG interface
PD98408
TEST interface
Receive data Receive FIFO
UTOPIA interface
Magnetic module Equalizer Receiver Clock/data recovery NRZI decoder 4B/5B decoder (command byte detection) Descrambler verification Idle/unassigned cell detector
UTOPIA Level
UTP/STP (cat.3/4/5)
loopback
Transmitter
loopback
NRZI encoder 4B/5B encoder (command byte insertion) Scrambler generation
Alayer
loopback
Transmit data
Transmit FIFO
interface
µPD98408
Transmit clock MHz)
µPD98408
LAYOUT
Power supply
AVDD AVDD AVDD
AVDD AVDD AVDD
UTP/STP interface
RDIP0 RDIN0 TDOP0 TDON0 RDIP5 RDIN5 TDOP5 TDON5 JDI/TCLK0 JDO/RDATA0 JCK/TCLK1 JMS/TCLK2 JRST_B/TCLK3
RxDATA0 RxDATA7 RxCLK RxSOC RxENB_B RxADDR0 RxADDR4 RxCLAV TxDATA0 TxDATA7 TxCLK TxSOC TxENB_B TxADDR0 TxADDR4
DGND
AGND AGND AGND
AGND AGND AGND AGND
DVDD
Alayer interface
Interface external
IC/TCLK4 IC/TCLK5 RECCLK/RDATA1 IC/RDATA3 IC/RDADA2 IC/RCLK0
PD98408
(NEASCOT T20TM)
TxCLAV
DATA0 DATA7 ADDR0 ADDR5 SEL_B RW_B/WR_B
SIN/TDATA5 SOUT
Timing marker
Transmit clock MHz)
Reset
RESET_B
TCLOCK
IC/RCLK5 IC/TDATA0 IC/RDATA4 IC/RDATA5 IC/TDATA1 IC/TDATA2 IC/TDATA3 IC/TDATA4 PMDONLY
DS_B/RD_B DTACK_B/RDY_B INT_B BUSMODE
interface
µPD98408
CONFIGURATION (TOP VIEW)
208-pin plastic (fine pitch)
AVDD RDIN5 RDIP5 AGND AGND AVDD AGND AVDD AGND AVDD AGND DVDD DGND PMDONLY IC/RCLK0 IC/RCLK1 IC/RCLK2 DGND IC/RCLK3 IC/RCLK4 IC/RCLK5 DGND DVDD JDI/TCLK0 JCK/TCLK1 JMS/TCLK2 DGND JRST_B/TCLK3 IC/TCLK4 IC/TCLK5 DVDD JDO/RDATA0 RECCLK/RDATA1 IC/RDATA2 DGND IC/RDATA3 IC/RDATA4 IC/RDATA5 DGND IC/TDATA0 IC/TDATA1 IC/TDATA2 DVDD IC/TDATA3 IC/DATA4 SIN/TDATA5 DGND DGND
AGND TDOP5 TDON5 AGND AVDD AVDD AGND RDIP4 RDIN4 AVDD AGND TDOP4 TDON4 AGND AVDD AVDD AGND RDIP3 RDIN3 AVDD AGND TDOP3 TDON3 AGND AVDD AVDD AGND RDIP2 RDIN2 AVDD AGND TDOP2 TDON2 AGND AVDD AVDD AGND RDIP1 RDIN1 AVDD AGND TDOP1 TDON1 AGND AVDD AVDD AGND RDIP0 RDIN0 AVDD AGND AVDD
AVDD TDOP0 TDON0 AGND AGND AVDD AGND AVDD AGND AVDD AGND DVDD DGND BUSMODE DS_B/RD_B RW_B/WR_B SEL_B DTACK_B/RDY_B INT_B DGND ADDR0 ADDR1 ADDR2 DGND DVDD ADDR3 ADDR4 ADDR5 DGND DATA0 DATA1 DGND DATA2 DATA3 DVDD DATA4 DATA5 DGND DATA6 DATA7 DGND TxENB_B TxCLAV DVDD TxSOC TxADDR0 TxADDR1 DGND DGND
DVDD SOUT RESET_B DGND TCLOCK DGND RxDATA7 RxDATA6 DVDD RxDATA5 RxDATA4 DGND RxDATA3 RxDATA2 DGND RxDATA1 RxDATA0 DVDD RxCLK DGND RxADDR4 RxADDR3 DGNG RxADDR2 RxADDR1 DVDD DGND RxADDR0 RxSOC DGND RxCLAV RxENB_B DVDD TxDATA7 TxDATA6 DGND TxDATA5 TxDATA4 DGND TxDATA3 TxDATA2 DVDD TxDATA1 TxDATA0 DGND TxCLK DGND TxADDR4 TxADDR3 TxADDR2 DVDD
µPD98408GD-LML
µPD98408
NAMES
ADDR0-ADDR5 AGND AVDD BUSMODE DATA0-DATA7 DGND DS_B/RD_B DTACK_B/RDY_B DVDD IC/RCLK0-IC/RCLK5 Address Analog ground Analog supply voltage mode Connect Data Digital ground Data strove/read Data acknowledge/ready Digital supply voltage Internal connect Internal connect/receive clock RxADDR0-RxADDR4: Receive address RxCLAV RxCLK RxDATA0RxDATA7 RxENB_B RxSOC SEL_B SIN/TDATA5 SOUT TCLOCK TDON0-TDON5 TDOP0-TDOP5 TxADDR0TxADDR4 TxCLAV TxCLK Receive cell available Receive data clock Receive data Receive enable Receive start address Acell Selector Signal in/transmit data Signal Transmit clock Transmit data output negative Transmit data output positive Transmit address Transmit cell available Transmit data clock
IC/RDATA2-IC/RDATA5: Internal connect/receive data IC/TCLK4, IC/TCLK5 Internal connect/transmit clock
IC/TDATA0-IC/TDATA4 Internal connect/transmit data INT_B JCK/TCLK1 JDI/TCLK0 JDO/RDATA0 JMS/TCLK2 JRST_B/TCLK3 PMDONLY RDIN0-RDIN5 RDIP0-RDIP5 RECCLK/RDATA1 RESET_B RW_B/WR_B Interrupt JTAG test clock/transmit clock JTAG test data input/transmit clock JTAG test data output/recieve data JTAG test mode select/transmit clock JTAG test reset/transmit clock only Receive data input negative Receive data input positive Recovery clock/receive data Reset Read write/write
TxDATA0-TxDATA7 Transmit data TxENB_B TxSOC Transmit enable Transmit start address Acell
µPD98408
CONTENTS FUNCTIONS Power Supply UTP/STP Interface UTOPIA Interface Interface Other Pins. Handling Unused Pins States Reset. ELECTRICAL CHARACTERISTICS PACKAGE DRAWING. RECOMMENDED SOLDERING CONDITIONS
µPD98408
FUNCTIONS Power Supply
Name AVDD 147, 149, 151, 156, 157,159, 163, 164, 169,173, 174, 179, 183,184, 189, 193, 194,199, 203, 104, 110, 120, 130, 146, 148, 150, 152,153, 158, 162, 165,168, 172, 175, 178,182, 185, 188, 192,195, 198, 202, 205, 100, 105, 106, 114, 117, 123, 126, 131, 135, Active Level Function +3.3-V power supply pins analog circuits.
DVDD
+3.3-V power supply pins digital circuits.
AGND
Analog circuit grounding pins.
DGND
Digital circuit grounding pins.
Caution board layout, AGND DGND should connected same, wide plane. board layout, AVDD DVDD should connected same, wide plane. details, refer User's Manual (S11409E).
µPD98408
UTP/STP Interface
Name RDIP0 RDIN0 TDOP0 TDON0 RDIP1 RDIN1 TDOP1 TDON1 RDIP2 RDIN2 TDOP2 TDON2 RDIP3 RDIN3 TDOP3 TDON3 RDIP4 RDIN4 TDOP4 TDON4 RDIP5 RDIN5 TDOP5 TDON5 Active Level Function Receive data inputs from circuit (analog balanced signal inputs). Transmit data outputs circuit (analog balanced signal outputs). Receive data inputs from circuit (analog balanced signal inputs). Transmit data outputs circuit (analog balanced signal outputs). Receive data inputs from circuit (analog balanced signal inputs). Transmit data outputs circuit (analog balanced signal outputs). Receive data inputs from circuit (analog balanced signal inputs). Transmit data outputs circuit (analog balanced signal outputs). Receive data inputs from circuit (analog balanced signal inputs). Transmit data outputs circuit (analog balanced signal outputs). Receive data inputs from circuit (analog balanced signal inputs). Transmit data outputs circuit (analog balanced signal outputs).
µPD98408
UTOPIA Interface
Name RxDATA0RxDATA7 RxCLK RxSOC Tristate Tristate Active Level Function 8-bit data used receive data output Alayer device. Data output sync with positive-going edge RxCLK. Input clock receive data transfer Alayer device. Receive cell start address signal output, which outputs signal informing Alayer device start byte position receive cell. start byte position that position where RxSOC RxDATA0-RxDATA7 RxSOC output enable signal input. When input, outputs RxDATA0-RxDATA7 RxSOC enabled. Input pins signal indicating address µPD98408. Cell receive available signal output. Becomes when µPD98408 output cell. 8-bit data used transmit data input Alayer device. Data input sync with positive-going edge TxCLK. Input clock transmit data transfer Alayer device Transmit cell start address signal input, which inputs signal indicating start byte position transmit cell input from Alayer device. start byte position that position where TxSOC Transmit enable signal input, which inputs signal indicating that Alayer device outputting valid transmit data TxDATA0-TxDATA7. enable disable. Input pins signal indicating address µPD98408 which transmits data Cell transmit available signal output. Goes when µPD98408 ready receive cell.
RxENB_B
RxADDR0RxADDR4 RxCLAV TxDATA0TxDATA7 TxCLK TxSOC
Tristate
TxENB_B
TxADDR0TxADDR4 TxCLAV
108, 107, 103, 102,
Tristate
µPD98408
Interface
Name BUSMODE Active Level Function Selects interface operation mode. <DS_B, RW_B, DTACK_B> style (Motorola compatible) <RD_B, WR_B, RDY_B> style (Intel compatible) DATA0DATA7 ADDR0ADDR5 SEL_ DS_B/RD_B 125, 124, 122, 121, 119, 118, 116, 134, 133, 132, 129, 128, Used transfer data between internal register (8-bit). DATA7. Used address internal register (6-bit). Register access enable signal. enable. When BUSMODE becomes data strobe signal (DS_B) Motorola-compatible interface. read cycle: DS_B read data enable.
write cycle: DS_B write data strobe. When BUSMODE becomes read instruction signal Intel-compatible interface. RD_B read instruction. RW_B/WR_B When BUSMODE becomes read/write control signal (RW_B) Motorola-compatible interface. Write cycle Read cycle When BUSMODE becomes write instruction signal Intel-compatible interface. WR_B write instruction. DTACK_B/ RDY_B When BUSMODE becomes data acknowledge signal (DTACK_B) Motorola-compatible interface. This signal indicates completion data transmission over data bus. DTACK_B upon completion data transmission. When BUSMODE becomes ready signal (RDY_B) Intel-compatible interface. This signal indicates completion data transmission over data bus. RDY_B upon completion data transmission. INT_B Notifies occurrence interrupt factor.
µPD98408
Other Pins
(1/3)
Name JDI/TCLK0 Active Level Function functions selected according level PMDONLY pin. When PMDONLY (JDI): JTAG test data input pin. When PMDONLY (TCLK0): Input transmit clock transmitter (Circuit JDO/ RDATA0 functions selected according level PMDONLY pin. When PMDONLY (JDO): JTAG test data output pin. When PMDONLY (RDATA0): Output data received from receiver (Circuit JCK/TCLK1 functions selected according level PMDONLY pin. When PMDONLY (JCK): JTAG test clock input pin. When PMDONLY (TCLK1): Input transmit clock transmitter (Circuit JMS/TCLK2 functions selected according level PMDONLY pin. When PMDONLY (JMS): JTAG test mode input pin. When PMDONLY (TCLK2): Input transmit clock transmitter (Circuit JRST_B/ TCLK3 functions selected according level PMDONLY pin. When PMDONLY (JRST_B): JTAG test reset signal input pin. When PMDONLY (TCLK3): Input transmit clock transmitter (Circuit IC/TCLK4 (with pulldown resistor) functions selected according level PMDONLY pin. When PMDONLY (IC): signal should connected this pin. When PMDONLY (TCLK4): Input transmit clock transmitter (Circuit IC/TCLK5 (with pulldown resistor) functions selected according level PMDONLY pin. When PMDONLY (IC): signal should connected this pin. When PMDONLY (TCLK5): Input transmit clock transmitter (Circuit
µPD98408
(2/3)
Name RECCLK/ RDATA1 Active Level Function functions selected according level PMDONLY pin. When PMDONLY (RECCLK): Output recovery clock receive data. recovery clock circuit output. When PMDONLY (RDATA1): Output data received from receiver (Circuit IC/RDATA3 functions selected according level PMDONLY pin. When PMDONLY (IC): signal should connected this pin. When PMDONLY (RDATA3): Output data received from receiver (Circuit IC/RDATA2 functions selected according level PMDONLY pin. When PMDONLY (IC): signal should connected this pin. When PMDONLY (RDATA2): Output data received from receiver (Circuit RCLK0RCLK5 (with pulldown resistor) functions selected according level PMDONLY pin. When PMDONLY (IC): signal should connected these pins. When PMDONLY (RCLK0-RCLK5): Output pins clock received from receiver (Circuits IC/TDATA0 (with pulldown resistor) functions selected according level PMDONLY pin. When PMDONLY (IC): signal should connected this pin. When PMDONLY (TDATA0): Input transmit data transmitter (Circuit IC/RDATA4 functions selected according level PMDONLY pin. When PMDONLY (IC): signal should connected this pin. When PMDONLY (RDATA4): Output data received from receiver (Circuit
µPD98408
(3/3)
Name IC/RDATA5 Active Level Function functions selected according level PMDONLY pin. When PMDONLY (IC): signal should connected this pin. When PMDONLY (RDATA5): Output data received from receiver (Circuit IC/TDATA1 (with pulldown resistor) functions selected according level PMDONLY pin. When PMDONLY (IC): signal should connected this pin. When PMDONLY (TDATA1): Input transmit data transmitter (Circuit IC/TDATA2 (with pulldown resistor) functions selected according level PMDONLY pin. When PMDONLY (IC): signal should connected this pin. When PMDONLY (TDATA2): Input transmit data transmitter (Circuit IC/TDATA3 (with pulldown resistor) functions selected according level PMDONLY pin. When PMDONLY (IC): signal should connected this pin. When PMDONLY (TDATA3): Input transmit data transmitter (Circuit IC/TDATA4 (with pulldown resistor) functions selected according level PMDONLY pin. When PMDONLY (IC): signal should connected this pin. When PMDONLY (TDATA4): Input transmit data transmitter (Circuit SIN/TDATA5 (with pulldown resistor) functions selected according level PMDONLY pin. When PMDONLY (SIN): command transmit timing signal input pin. When PMDONLY (TDATA5): Input transmit data transmitter (Circuit SOUT PMDONLY (with pulldown resistor) command receive timing signal output pin. Specifies mode µPD98408: whether operated only. Operation Operation only. Transmit clock MHz) input Input reset signal entire µPD98408. signal should connected these pins.
TCLOCK RESET_B
144,
Should connected normal use.
µPD98408
Handling Unused Pins
Name RDIP0-RDIP5 RDIN0-RDIN5 TDOP0-TDOP5 TDON0-TDON5 JDI/TCLK0 JDO/RDATA0 JCK/TCLK1 JMS/TCLK2 JRST_B/TCLK3 IC/TCLK4 IC/TCLK5 RECCLK/RDATA1 IC/RDATA3 IC/RDATA2 IC/RCLK0-IC/RCLK5 IC/TDATA0 IC/RDATA4 IC/RDATA5 IC/TDATA1 IC/TDATA2 IC/TDATA3 IC/TDATA4 SIN/TDATA5 SOUT PMDONLY (with pull-down resistor) (with pull-down resistor) (with pull-down resistor) (with pull-down resistor) (with pull-down resistor) (with pull-down resistor) (with pull-down resistor) (with pull-down resistor) (with pull-down resistor) (with pull-down resistor) Recommended Connection When Pull with resistor Pull with resistor Open. Open. Pull with resistor. Open. Pull with resistor. Pull with resistor. Pull with resistor. Open. Open. Open. Open. Open. Open. Open. Open. Open. Open. Open. Open. Open. Open. Open. Open.
µPD98408
States Reset
Name TDOP0-TDOP5 TDON0-TDON5 RxDATA0-RxDATA7 RxSOC RxCLAV TxCLAV DATA0-DATA7 DTACK_B/RDY_B INT_B JDO/RDATA0 RECCLK/RDATA1 SOUT Tristate Tristate Tristate Tristate defined defined Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z High level High level defined defined level States Reset
µPD98408
ELECTRIC CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Output current Symbol Storage temperature Tstg Note Note Conditions Rating -0.5 +4.6 -0.5 +6.6 -0.5 +6.6 +150 Unit
Caution Absolute maximum ratings rated values beyond which physical damage will caused product; rated value parameters above table exceeded, even momentarily, quality product deteriorate. Always product within rated values. Notes Applies pins JDO/RDATA0, RECCLK/RDATA1, IC/RDATA2, IC/RDATA3, IC/RDATA4, IC/RDATA5, SOUT, IC/RCLK0-IC/RCLK5. Applies pins RxDATA0-RxDATA7, RxSOC, RxCLAV, TxCLAV, INT_B, DTACK_B/RDY_B, DATA0-DATA7. RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage High-level input voltage Low-level input voltage Operating ambient temperature Symbol Conditions MIN. 3.135 TYP. MAX. 3.465 Unit
µPD98408
CHARACTERISTICS
Parameter Input leakage current High-level output current Symbol IOH1 Conditions Note IOH2 Note Low-level output current IOL1 Note IOL2 Note High-level output voltage VOH1 VOH2 Low-level output voltage Supply current Note When Note applied operation -8.0 MIN. -3.0 TYP. MAX. Unit
Notes Applies pins JDO/RDATA0, RECCLK/RDATA1, IC/RDATA2, IC/RDATA3, IC/RDATA4, IC/RDATA5, SOUT, IC/RCLK0-IC/RCLK5. Applies pins RxDATA0-RxDATA7, RxSOC, RxCLAV, TxCLAV, INT_B, DTACK_B/RDY_B, DATA0-DATA7. Applies pins IC/RCLK0-IC/RCLK5 only when input PMDONLY (only operates).
µPD98408
CAPACITANCE
Parameter Input capacitance Output capacitance capacitance Symbol Conditions Frequency Frequency Frequency MIN. TYP. MAX. Unit
Test Waveform
0.5VDD Test points
CHARACTERISTICS TCLOCK
Parameter TCLOCK frequency TCLOCK duty TCLOCK frequency accuracy TCLOCK rise time TCLOCK fall time Symbol t1-1 t1-2 t1-3 t1-4 t1-5 Measurement transition time Measurement transition time Conditions MIN. TYP. MAX. Unit
TCLOCK Input
t1-3 cycle TCLOCK t1-2 (min.)
t1-2 (max.)
t1-1 1/cycle
TCLOCK t1-4 t1-5
µPD98408
INTERFACE Write operation (when BUSMODE
Parameter ADDR setup time (referred WR_B) SEL_B setup time (referred WR_B) WR_B pulse width DATA setup time (referred WR_B) ADDR/DATA hold time (referred WR_B) RDY_B disable time (referred WR_B) SEL_B hold time (referred WR_B) t2-7 t2-6 t2-5 t2-3 t2-4 t2-2 Symbol t2-1 Conditions MIN. TYP. MAX. Unit
Interface Write Operation (BUSMODE
ADDR0
-ADDR5
t2-1 SEL_B t2-4 DATA0 t2-5
-DATA7
t2-2 WR_B t2-7 t2-3
RD_B t2-6
RDY_B
µPD98408
Read operation (when BUSMODE
Parameter ADDR setup time (referred RD_B) SEL_B setup time (referred RD_B) RD_B pulse width DATA fixed time (referred RDY_B) ADDR hold time (referred RD_B) RDY_B disable time (referred RD_B) SEL_B hold time (referred RD_B) DATA invalid/tristate time (referred RD_B) t2-17 t2-16 t2-15 t2-14 t2-12 t2-13 t2-11 Symbol t2-10 Conditions MIN. TYP. MAX. Unit
Interface Read Operation (BUSMODE
ADDR0 -ADDR5 t2-10 SEL_B t2-11 DATA0 t2-17 t2-14
-DATA7
t2-13 t2-12 RD_B t2-16 WR_B t2-15 RDY_B
µPD98408
Write operation (when BUSMODE
Parameter ADDR setup time (referred DS_B) SEL_B RW_B setup time (referred DS_B) DS_B pulse width DATA setup time (referred DS_B) ADDR/DATA hold time (referred DS_B) DTACK_B disable time (referred DS_B) SEL_B RW_B hold time (referred DS_B) t2-7 t2-6 t2-5 t2-3 t2-4 t2-2 Symbol t2-1 Conditions MIN. TYP. MAX. Unit
Interface Write Operation (BUSMODE
ADDR0 -ADDR5 t2-1 SEL_B t2-4 DATA0 t2-5
-DATA7
t2-2 DS_B t2-7 t2-3
RW_B t2-6 DTACK_B
µPD98408
Read operation (when BUSMODE
Parameter ADDR setup time (referred DS_B) SEL_B RW_B setup time (referred DS_B) DS_B pulse width DATA fixed time (referred DTACK_B) ADDR hold time (referred DS_B) DTACK_B disable time (referred DS_B) SEL_B RW_B hold time (referred DS_B) DATA invalid/tristate time (referred DS_B) t2-17 t2-16 t2-15 t2-14 t2-12 t2-13 t2-11 Symbol t2-10 Conditions MIN. TYP. MAX. Unit
Interface Read Operation (BUSMODE
ADDR0 -ADDR5 t2-10 SEL_B t2-11 DATA0 -DATA7 t2-13 t2-12 DS_B t2-16 RW_B t2-15 t2-17 t2-14
DTACK_B
µPD98408
UTOPIA INTERFACE Transmission
Parameter TxCLK frequency TxCLK duty cycle TxCLK jitter (peak peak) TxCLK rise time TxCLK fall time TxDATA[7:0], TxSOC, TxENB_B, TxADDR[4:0] setup time TxDATA[7:0], TxSOC, TxENB_B, TxADDR[4:0] hold time TxCLAV low-impedance delay time (referred TxCLK) TxCLAV high-impedance delay time (referred TxCLK) TxCLAV low-impedance delay time (referred TxCLK) TxCLAV high-impedance delay time (referred TxCLK) t3-11 t3-9 t3-10 Symbol t3-1 t3-2 t3-3 t3-4 t3-5 t3-6 t3-7 t3-8 Measurement transition time Measurement transition time Conditions MIN. TYP. MAX. Unit
µPD98408
Reception
Parameter RxCLK frequency RxCLK duty cycle RxCLK jitter (peak peak) RxCLK rise time RxCLK fall time RxENB_B RxADDR[4:0] setup time RxENB_B RxADDR[4:0] hold time RxDATA[7:0], RxSOC, RxCLAV low-impedance delay time (referred RxCLK) RxDATA[7:0], RxSOC, RxCLAV high-impedance delay time (referred RxCLK) RxDATA[7:0], RxSOC, RxCLAV low-impedance delay time (referred RxCLK) RxDATA[7:0], RxSOC, RxCLAV high-impedance delay time (referred RxCLK) t3-22 t3-21 t3-20 t3-19 t3-18 Symbol t3-12 t3-13 t3-14 t3-15 t3-16 t3-17 Measurement transition time Measurement transition time Conditions MIN. TYP. MAX. Unit
TxCLK RxCLK Timing
t3-3, t3-14 cycle TxCLK/RxCLK t3-2, t3-13 (min.) t3-2, t3-13 (max.) max. max. t3-1, t3-12 1/cycle
TxCLK RxCLK Timing
TxCLK/RxCLK t3-4, t3-15 t3-5, t3-16
µPD98408
Input Signal Setup Timing
TxCLK, RxCLK
TxDATA[7:0], TxSOC, TxENB_B, TxADDR[4:0], RxENB_B, RxADDR[4:0] t3-6, t3-17
Input Signal Hold Timing
TxCLK, RxCLK
TxDATA[7:0], TxSOC, NB_B, TxADDR[4:0], RxENB_B, RxADDR[4:0] t3-7, t3-18
Output Delay Time
TxCLK, RxCLK
TxCLAV, RxDATA[7:0], RxSOC, RxCLAV
Hi-Z
t3-10, t3-21
t3-8, t3-19
Output Delay Time
TxCLK, RxCLK
TxCLAV, RxDATA[7:0], RxSOC, RxCLAV t3-11, t3-22
Hi-Z
t3-9, t3-20
µPD98408
PMDONLY MODE
Parameter RxDATA delay time (referred RxCLK) TxDATA setup time (referred TxCLK) TxDATA hold time (referred TxCLK) t4-3 t4-2 Symbol t4-1 Conditions MIN. TYP. MAX. 15.0 Unit
Reception Data Output Delay Time
RxCLK0 -RxCLK5
RxDATA0 -RxDATA5
Hi-Z t4-1
Transmission Data Setup/Hold Time
TxCLK0 -TxCLK5 TxDATA0 -TxDATA5 t4-2 t4-3
µPD98408
OTHERS
Parameter pulse width SOUT pulse width RESET_B pulse width Symbol t5-1 t5-2 t5-3 Conditions MIN. TYP. MAX. Unit TCLOCK clock TCLOCK clock
SOUT Timings
TCLOCK clocks
t5-1 clocks more
SOUT t5-2 clocks
RESET_B Timing
RESET_B t5-3 more
µPD98408
PACKAGE DRAWING
PLASTIC (FINE PITCH) (28x28)
detail lead
NOTE Each lead centerline located within 0.12 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 30.6±0.2 28.0±0.2 28.0±0.2 30.6±0.2 1.25 1.25 0.22 +0.05 -0.04 0.10 (T.P.) 1.3±0.2 0.5±0.2 0.17 +0.03 -0.07 0.10 3.2±0.1 0.4±0.1 5°±5° MAX.
P208GD-50-LML, MML, SML-5
µPD98408
RECOMMENDED SOLDERING CONDITIONS
conditions listed below shall when soldering µPD98408. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with sales offices case other soldering process used, case soldering done under different conditions. Surface-Mount Type µPD98408GD-LML: 208-pin plastic (fine pitch)
Soldering Process Infrared reflow Soldering Conditions Peak package's surface temperature: Reflow time: seconds less (210 more) Maximum allowable number reflow processes: Exposure limit: days <Caution> Non-heat-resistant trays, such magazine taping trays, cannot baked before unpacking. Peak package's surface temperature: Reflow time: seconds less (200 more) Maximum allowable number reflow processes: Exposure limit: days <Caution> Non-heat-resistant trays, such magazine taping trays, cannot baked before unpacking. Partial heating method Terminal temperature: less Heat time: seconds less (for side device)
Note Note
Symbol IR35-367-2
hours pre-baking required afterward)
VP15-367-2
hours pre-baking required afterward)
Note
Maximum number days during which product stored temperature relative humidity less after dry-pack package opened.
Caution
apply more different soldering methods chip (except partial heating method terminal sections).
µPD98408
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD98408
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µPD98408 6-PORT APHY µPD98408 Aphysical layer that complies

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