µPD98401A ASAR CHIP DESCRIPTION µPD98401A (NEASCOT-S15T

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µPD98401A ASAR CHIP DESCRIPTION µPD98401A (NEASCOT-S15T

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INTEGRATED CIRCUIT
µPD98401A
ASAR CHIP
DESCRIPTION
µPD98401A (NEASCOT-S15TM) high-performance chip that segments reassembles Acells. This chip interface with Anetwork when included workstation, computer, front-end processor, network hub, router. µPD98401A conforms AForum Recommendation, provides functions AAL-5 sublayer Alayer. µPD98401A compatible with predecessor, µPD98401, terms hardware software. Functions explained detail following User's Manual. sure read this manual when designing your system.
µPD98401A User's Manual: S12054E
FEATURES
Conforms AForum AAL-5 sublayer Alayer functions Hardware support AAL-5 processing Processing non-AAL-5 traffic (AAL-3/4 cell, cell, cell) software with cell processing function Hardware support comparison/generation CRC-10 non-AAL-5 traffic Supports virtual channels (VC) Provided with traffic shapers that carry transmission scheduling (control average rate/peak rate) different transmission rate each Interface commands controlling device Employs "UTOPIA interface" cell data interface with device Octet-level handshake Cell-level handshake 32-bit general-purpose interface High-speed DMAC (supports 12-, 16-word burst) JTAG boundary scan test function (IEEE1149.1) CMOS technology single power source Remark this document, active indicated after name).
information this document subject change without notice.
Document S12100EJ3V0DS00 (3rd edition) Date Published February 1999 CP(K) Printed Japan
mark
shows major revised points.
1997
µPD98401A
ORDERING INFORMATION
Part Number Package 208-pin plastic (fine pitch)
µPD98401AGD-MML
SYSTEM CONFIGURATION
Ainterface card
Reception
PD98401A
Control memory
PD98402A
Transmission
Anetwork
interface
BLOCK DIAGRAM
Receive data FIFO
interface reception block
device transmission block
Reception controller
System port
controller host interface
Sequencer
Control memory interface
Control memory
Transmission controller interface transmission block device reception block
Transmit data FIFO cells)
Data Sheet S12100EJ3V0DS00
µPD98401A
CONFIGURATION
Rx7-Rx0 RCLK RENBL_B RSOC interface EMPTY_B/RxCLAV Tx7-Tx0 TCLK TENBL_B TSOC FULL_B/TxCLAV PHRW_B PHOE_B PHCE_B PHINT_B AD31-AD0 PAR3-PAR0 OE_B SIZE2-SIZE0 DR/W_B ATTN_B GNT_B interface RDY_B ABRT_B ERR_B SR/W_B SEL_B ASEL_B RST_B INTR_B Slave Master
CD31-CD0 CPAR3-CPAR0 CA17-CAD CWE_B COE_B CBE_B3-CBE_B0 INITD Control memory interface
DBVC DBMD DBML DBMF DBMR monitoring
JRST_B JTAG boundary scan interface
TRF_B
Test (fixed level)
Power supply
Data Sheet S12100EJ3V0DS00
µPD98401A
CONFIGURATION (Top View)
208-pin plastic (fine pitch)
DBVC DBMR JRST_B DBMF DBML DBMD TRF_B INTID COE_B CWE_B CBE_B0 CBE_B1 CBE_B2 CBE_B3 CA10 CA11 CA12 CA13 CA14 CA15 CA16 CA17
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 RST_B AD11 AD10 PAR3 PAR2
CPAR0 CPAR1 CPAR2 CPAR3 CD10 CD11 CD12 CD13 CD14 CD15 CD16 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 PHRW_B PHOE_B PHINT_B
PAR1 PAR0 OE_B SIZE2 SIZE1 SIZE0 DR/W_B ATTN_B GND_B RDY_B ABRT_B ERR_B SR/W_B SEL_B ASEL_B INTR_B RCLK RENBL_B RSOC EMPTY_B/RxCLAV FULL_B/TxCLAV TSOC TENBL_B TCLK PHCE_B
Data Sheet S12100EJ3V0DS00
PD98401AGD-MML
µPD98401A
NAMES
ABRT_B AD31_AD0 ASEL_B ATTN_B CA17-CA0 CD31-CD0 COE_B CPAR3-CPAR0 CWE_B DBMD DBMF DBML DBVC DBMR DR/W_B ERR_B FULL_B/TxCLAV GNT_B INITD INTR_B JRST_B OE_B PAR3-PAR0 Abort Address/Data Slave Address Select Attention/Burst Frame Control Memory Address Control Memory Data Clock Control Memory Output Enable Control Memory Parity Control Memory Write Enable Monitor Data Monitor First Monitor Last Monitor Monitor Remaining Read/Write Error Buffer Ground Grant Initialization Disable Interrupt JTAG Test JTAG Test JTAG Test JTAG Test JTAG Test Output Enable Parity PHCE_B PHINT_B PHOE_B PHRW_B RCLK RDY_B RENBL_B RSOC RST_B Rx7-Rx0 SLE_B SIZE2-SIZE0 SR/W_B TCLK TENBL_B TSOC TRF_B Tx7-Tx0 Chip Enable Interrupt Output Enable Read/Write Receive Clock Target Ready Receive Enable Receive Start Cell Reset Receive Data Slave Select Burst Size Slave Read/Write Transmit Clock Transmit Enable Transmit Start Cell Delay Select Transmit Data Power Supply
CBE_B3_CBE_B0 Local Port Byte Enable
EMPTY_B/RxCLAV Output Buffer Empty
Data Sheet S12100EJ3V0DS00
µPD98401A
CONTENTS
FUNCTION Device Interface Interface Pins Monitor Pins Control Memory Interface Pins. JTAG Boundary Scan Pins Test Pin. Power Supply Ground Pins. Status During After Reset
DIFFERENCES FROM µPD98401. Additional Functions. Differences from µPD98401 (NEASCOT-S10 ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS.
Data Sheet S12100EJ3V0DS00
µPD98401A
FUNCTION
µPD98401A housed package having pins, which pins function pins pins pins.
Device Interface
device interfaces include UTOPIA interface through which µPD98401A transfers Acells with device, control interface which µPD98401A controls device.
UTOPIA interface (1/2)
Level Receive Data Bus. through constitute 8-bit input which inputs data received from network byte format from device. µPD98401A loads data rising edge RCLK. Receive Start Cell. RSOC signal input synchronization with first byte cell data from device. This signal remains high while first byte header input through Rx0. Function
Name Rx7-Rx4 Rx3-Rx0
RSOC
RENBL_B
CMOS
Receive Enable. RENBL_B signal indicates device that µPD98401A ready receive data next clock cycle. This signal goes high during after reset.
EMPTY_B/ RxCLAV
Output Buffer Empty/Rx Cell Available. This signal notifies µPD98401A that there cell data transferred receive FIFO that receive data supplied device. When UTOPIA interface octet-level handshake mode, this signal serves EMPTY_B, indicating that data through invalid current clock cycle. cell-level handshake mode, serves RxCLAV, indicating that there cell supplied next after transfer current cell completed.
RCLK
CMOS
Receive Clock. This synchronization clock used transfer cell data with cell device recieve side. system clock input output from this immediately after reset.
Tx7-Tx0
CMOS
Transmit Data Bus. through constitute 8-bit output which outputs transmit data byte format device. µPD98401A outputs data rising edge TCLK.
TSOC
CMOS
Transmit Start Cell. TSOC signal output synchronization with first byte transmit cell data.
Data Sheet S12100EJ3V0DS00
µPD98401A
(2/2)
Name TENBL_B Level CMOS Transmit Enable. TENBL_B signal indicates device that data been output through current clock cycle. This signal remains high during reset after reset. FULL_B/ TxCLAV Buffer Full/Tx Cell Available. FULL_B signal notifies µPD98401A that input buffer device full that device receive more data. When UTOPIA interface octet-level handshake mode, device inputs inactive level receive cell data. celllevel handshake mode, this signal indicates that device receive next cell data after current cell been completely transferred TCLK CMOS Transmit Clock. This synchronization clock used transfer cell data with device transmission side. system clock input output from this Function
device control interface
Level CMOS Read/Write. µPD98401A indicates direction which device controlled, using PHRW_B. This signal goes after reset. Read Write Function
Name PHRW_B
PHOE_B
CMOS
Output Enable. µPD98401A enables output from device making PHOE_B
PHCE_B
CMOS
Chip Enable. µPD98401A makes PHCE_B access device. This signal goes high after reset.
PHINT_B
Interrupt. This interrupt input signal from device. device indicates µPD98401A that interrupt source, inputting level PHINT_B. This signal goes high after reset.
Data Sheet S12100EJ3V0DS00
µPD98401A
Interface Pins
interface general-purpose interface compatible with most generally used buses (such PCI, bus, GIO, bus). (1/3)
Name AD31-AD27 AD26-AD22 AD21-AD17 AD16-AD13 AD12 AD11-AD7 AD6-AD0 PAR3 PAR2 PAR1 PAR0 3-state CMOS 3-state Level CMOS Address/Data. AD31 through constitute 32-bit address/data bus. These pins pins multiplexing address data bus. first clock input/output, AD31 through transfer address. They transfer data second clock onward. goes into high-impedance state when µPD98401A does access bus. Parity. pins indicate parity AD31 through AD0. parity check mode GMR. Enabling disabling parity, even parity, word byte parity specified. byte parity specified, PAR3 indicates parity AD31 through AD24, PAR0 indicates parity through AD0. word parity specified, PAR3 serves input/output pin. serves output when address output when data written, input when data read. When µPD98401A does access bus, PAR3 through PAR0 into high-impedance state. Pull these pins when they used. OE_B Output Enable. When this low, µPD98401A uses AD31 through PAR3 through PAR0 3-state pins. These pins into highimpedance state while high level being input OE_B. This option pin. this level system where necessary forcibly µPD98401A highimpedance state controlling this pin. SIZE2 SIZE1 SIZE0 CMOS Burst Size. SIZE2 through SIZE0 indicate size current transfer. These pins used interface (such bus) requiring clear burst size. Function
SIZE2
SIZE1
SIZE0
Function 1-word transfer 2-word burst 4-word burst 8-word burst 16-word burst 12-word burst Undefined Reception side byte alignment
Data Sheet S12100EJ3V0DS00
µPD98401A
(2/3)
Name DR/W_B Level CMOS Read/Write. DR/W_B indicates direction access. Read access Write access This after reset. ATTN_B CMOS Attention/Burst Frame (DMA request). µPD98401A makes ATTN_B signal when performs operation. ATTN_B signal becomes inactive rising edge when data transferred means decreased word. GNT_B Grant. GNT_B signal inputs level when arbiter grants µPD98401A response request from µPD98401A. µPD98401A recognizes that been granted starts operation when GNT_B signal goes (active). Make sure that GNT_B signal falls least system clock cycle after rising ATTN_B signal. GNT_B signal must returned high (inactive) level before µPD98401A makes ATTN_B signal (active) issue next cycle request. RDY_B Target Ready. RDY_B indicates µPD98401A cycle that target device ready input/output. During read operation µPD98401A, RDY_B signal made valid data AD31 through AD0. During write operation µPD98401A, RDY_B signal made target device ready receiving data. sampling timing RDY_B ABRT_B signals µPD98401A advanced clock (early mode) using internal register (GMR register). ABRT_B Abort. ABRT_B used abort transfer cycle. this signal goes while data being transferred cycle, transfer aborted that cycle, ATTN_B signal briefly deasserted inactive. After that, µPD98401A asserts ATTN_B signal active again, resumes burst transfer from data which transfer aborted. While level input ABRT_B, RDY_B signal ignored. user advance sampling timing RDY_B ABRT_B signals µPD98401A clock (early mode) using internal register (GMR register). Pull this when used. ERR_B Error. This used device that manages stop operation µPD98401A when occurrence error detected system bus. When level input this pin, µPD98401A stops operations, sets system error (bit register (when masked), generates interrupt. Pull this when used. Function
Data Sheet S12100EJ3V0DS00
µPD98401A
(3/3)
Name SR/W_B Level Slave Read/Write. SR/W_B signal determines direction which slave accessed. Read access Write access SEL_B Slave Select. This signal goes (active) when µPD98401A accessed slave. SEL_B signal must goes soon after ASEL_B signal gone low. inactive period least system clock cycles must inserted between when SEL_B signal become inactive when becomes active again. ASEL_B Slave Address Select. ASEL_B signal used select direct address register µPD98401A. When level input ASEL_B, µPD98401A samples first rising edge CLK. Clock. This inputs system clock. Input clock range MHz. RST_B Reset. RST_B signal initializes µPD98401A starting, etc.). After reset, µPD98401A start normal operation. When level input RST_B, internal state machine registers µPD98401A reset, 3-state signals into highimpedance state. reset input asynchronous. When this signal input during operation, operating status that time lost. Hold RST_B least duration clock. After reset, access µPD98401A least clock cycles. INTR_B opendrain output Interrupt. This open-drain signal must pulled INTR_B informs that interrupt (unmasked) register set. Function
Data Sheet S12100EJ3V0DS00
µPD98401A
Monitor Pins
monitor pins indicate type data under transfer. These five pins enabled when register they into high-impedance state when
Name DBMD 3-state Level CMOS Monitor Data. This indicates that payload AAL-5 cell under transfer. This enabled when register goes into high-impedance state when DBMD signal changes synchronization with falling ATTN_B signal. high level this signal indicates that payload ALL-5 packet transmit/receive cell under transfer, level indicates that other data being transferred. CMOS Monitor Last. one-word data currently under transfer satisfies following conditions, this goes high synchronization with output data.
Function
DBML
3-state
Last word last cell AAL-5 packet 1-word data written last word receive buffer Last 1-word data last cell receive packet which MAX. NUMBER SEGMENTS error occurred
When this low, indicates that data other than above. This enabled when register goes into high-impedance state when DBMF 3-state CMOS Monitor First. This indicates that data under transfer start cell receive AAL-5 packet. This enabled when register goes into high-impedance state when This goes high synchronization with last word data first cell AAL-5 packet. CMOS Monitor Remaining. This indicates that number cells remaining transmit buffer equal dropped below value assigned register. This enabled when register goes into high-impedance state when CMOS Monitor This indicates that data currently being transferred that which receive table This asserted active synchronization with falling ATTN_B. enabled when register goes into high-impedance state when
DBMR
3-state
DBVC
3-state
Data Sheet S12100EJ3V0DS00
µPD98401A
Control Memory Interface Pins
These pins constitute interface through which µPD98401A accesses external control memory device. 18-bit address 32-bit data used. control memory host accessed only this interface.
Name CD31-CD28 CD27-CD21 CD20-CD16 CD15-CD7 CD6-CD0 CPAR3CPAR0 110-113 116-122 125-129 132-140 143-149 151-154 CMOS Control Memory Parity. CPAR3 through CPAR0 indicate parity CD31 through 8bit units. read cycle, µPD98401A checks parity (when enabled). write cycle, CPAR3 through CPAR0 output parity. Pull these pins when they used. Control Memory Address. CA17 through constitute 18-bit address bus. They output address control memory device during read/write operation. CMOS Control Memory Write Enable. CWE_B signal indicates direction which control memory accessed. Read access Write access COE_B CMOS Control Memory Output Enable COE_B enables disables data output control memory. CBE_B3 CBE_B2 CBE_B1 CBE_B0 INITD Initialization Disable. INITD signal used disable automatic initialization control memory during chip test. During normal operation other than test, directly connect INITD GND. CMOS Local Port Byte Enable. CBE_B3 through CBE_B0 indicate byte control port read written. 3-state Level CMOS Control Memory Data. CD31 through 3-state pins constitute 32-bit data which used transfer data with control memory device. Function
CA17-C11 CA10-CA4 CA3-CA0 CWE_B
158-164 167-173 176-179
CMOS
Data Sheet S12100EJ3V0DS00
µPD98401A
JTAG Boundary Scan Pins
Name Level JTAG Test Data Input. used input data JTAG boundary scan circuit register. Normally, this high level. 3-state CMOS JTAG Test Data Output. used output data from JTAG boundary scan circuit register. changes output falling edge clock input pin. Normally, leave this open. JTAG Test Clock. This used supply clock JTAG boundary scan circuit register. Normally, this high level. JTAG Test Mode Select. Normally, this high level. JRST_B JTAG Test Reset. This initializes JTAG boundary scan circuit register. Normally, this level. Function
Test
Name TRF_B Level Function This used test internal circuitry chip. Normal operation Test Normally, directly connect this ground level.
Power Supply Ground Pins
Name 104, 114, 124, 130, 142, 157, 165, 174, 183, 190, 195, 198, 204, ,106, 115, 123, 131, 141, 150, 155, 156, 166, 175, 182, 191, 196, 199, Power supply pins) These pins supply voltage chip. Function
Ground pins) Connect these pins ground.
Data Sheet S12100EJ3V0DS00
µPD98401A
Status During After Reset
AD0-AD31 PAR0-PAR3 SIZE0-SIZE2 DR/W_B ATTN_B INTR_B CA17-CA0 CD0-CD31 CWE_B COE_B CBE_B3-CBE_B0 PHRW_B PHOE_B PHCE_B RCLK RENBL_B Tx0-Tx7 TCLK TENBL_B TSOC DBMD DBML DBMF DBMR DBVC During Reset Hi-Z (input mode) Hi-Z (input mode) (however, pulled (output mode) output output Hi-Z (3-state) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z After Reset Hi-Z (input mode) Hi-Z (input mode) (however, pulled (output mode) (repetition high/low) output output Hi-Z (3-state) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Data Sheet S12100EJ3V0DS00
µPD98401A
DIFFERENCES FROM µPD98401
Additional Functions
µPD98401A compatible with µPD98401 terms hardware software. However, µPD98401A following additional functions compared with µPD98401. additional functions enabled setting register. 12-word burst cycle Byte alignment transfer function receive data buffer monitor Mode insert idle cell transmission rate adjustment scheduling function Aggregate mode Receive packet size indication (cell units/Length mode added) Cell-level support UTOPIA interface AAL-3/4 traffic assist function JTAG boundary scan support
Differences from µPD98401 (NEASCOT-S10TM)
Increased receive FIFO size
µPD98401
cells
µPD98401A cells
Cell processing field (1XX)
µPD98401
Receives cells other than those pattern (101, 100) user data cells.
µPD98401A Processes cell pattern. Stores pool
Changing transmission mode unassigned cell µPD98401 starts transmitting unassigned cells immediately after power application continues transmitting unassigned cells while there active transmission also function stop transmitting unassigned cells while there active using register. µPD98401A deletes this function, makes TENBL_B signal inactive power application when there active does transmit unassigned cells. µPD98401A transmits unassigned cells only when there active when unassigned cell generator function enabled.
Data Sheet S12100EJ3V0DS00
µPD98401A
ELECTRICAL SPECIFICATIONS
asterisk mark indicates portion which have been revised from µPD98401.
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Symbol
Note
Condition
Ratings -0.5 +6.5 -0.5 +0.5 +150
Unit
Output current Operating ambient temperature
Storage temperature
Note
Tstg
Caution
parameters exceeds absolute maximum ratings, even momentarily, quality product impaired. absolute maximum ratings values that physically damage product(s). sure product(s) within ratings.
Characteristics
Parameter level input voltage High level input voltage Symbol VIH1 VIH2 High level output voltage VOH1 VOH2 level output voltage VOL1 VOL2 Supply current Input leakage current Output leakage current
Note
Condition
MIN. -0.5
TYP.
MAX. +0.8
Unit
Except pins RST_B Pins RST_B -4.0 -6.0 12.0 Normal operation
+2.2 +3.3
Note
Note
Note
Notes IO1, VOH1 VOL1 apply following pins: CD31 CD0, CPAR3 CPAR0, CA17 CA0, CBE_B3 CBE_B0, CWE_B, COE_B, RCLK, RENBL_B, TSOC, TENBL_B, TCLK, Tx0, PHCE_B, PHOE_B, PHRW_B, IO2, VOH2 VOL2 apply following pins: AD31 AD0, PAR3 PAR0, SIZE2 SIZE0, DR/W, ATTN_B, INTR_B, DBMD, DBML, DBMF, DBMR, DBVC
Data Sheet S12100EJ3V0DS00
µPD98401A
Capacitance MHz)
Parameter Output capacitance Input capacitance capacitance Symbol Condition MIN. TYP. MAX. Unit
Characteristics Test Condition
Test point
Load Condition
D.U.T (Device tested)
Input
Parameter cycle time Symbol tCYCLK tCLKH tCLKL Condition MIN. TYP. MAX. Unit
high level width level width rise time fall time
tCYCLK tCLKH
tCLKL
Data Sheet S12100EJ3V0DS00
µPD98401A
Interface (1/2)
Transmission operation
Parameter TCLKTX delay time TCLKTSOC delay time TCLKTEMBL_B delay time Symbol tDTX tDTSOC tDTEN tSFULL tHFULL Condition MIN. TYP. MAX. Unit
FULL_B setup time
FULL_B hold time
TCLK tDTX Tx7-Tx0 `00H' INVALID
TSOC tDTSOC TENBL_B tSFULL FULL_B tHFULL tDTSOC tDTEN tDTEN
H4-H1: AHeader P9-P1 Payload Data
Data Sheet S12100EJ3V0DS00
µPD98401A
Interface (2/2)
Reception operation
Parameter Symbol tSRX tHRX tSRSOC tHRSOC tDREN tSEMPT tHEMPT Condition MIN. TYP. MAX. Unit
setup time
hold time
RSOC setup time
RSOC hold time RCLK RENBL_B delay time
EMPTY_B setup time
EMPTY_B hold time
RCLK tSRX Rx7-Rx0 tHRX INVALID INVALID
RSOC tSRSOC RENBL_B tSEMPT EMPTY_B H4-H1: AHeader P7-P1 Payload Data tHEMPT tHRSOC tDREN tDREN
Data Sheet S12100EJ3V0DS00
µPD98401A
Host Slave Access (1/2)
Write
Parameter ASEL_B setup time ASEL_B hold time SEL_B setup time SEL_B hold time Address setup time Address hold time Data setup time Data hold time setup time hold time SR/W_B setup time SR/W_B hold time Symbol tSASEL tHASEL tSSEL tHSEL tSDADD tHDADD tSDDAT tHDDAT tSPAR1 tHPAR1 tSSRW tHSRW Condition MIN. 1tCYCLK+3 TYP. MAX. Unit
Write timing
tSASEL ASEL_B tSSEL SEL_B tSDADD AD31-AD0 ADDRESS tSSRW SR/W_B tSPAR1 PAR3-PAR0 (input) tSPAR1 (input) tHSRW tHDADD tSDDAT DATA tHDDAT tHSEL tHASEL
tHPAR1
tHPAR1
Data Sheet S12100EJ3V0DS00
µPD98401A
Host Slave Access (2/2)
Read
Parameter ASEL_B setup time ASEL_B hold time SEL_B setup time SEL_B hold time Address setup time Address hold time Symbol tSASEL tHASEL tSSEL tHSEL tSDADD tHDADD tDDDAT tFDDAT tSPAR1 tHPAR1 tDPAR1 tFPAR1 tSSRW tHSRW Condition MIN. 1tCYCLK+3 TYP. MAX. Unit
CLKdata delay time
CLKdata floating time setup time hold time
CLKPAR delay time
CLKPAR floating time SR/W_B setup time SR/W_B hold time
Read timing
tSASEL ASEL_B tSSEL SEL_B tSDADD AD31-AD0 ADDRESS (input) tSSRW SR/W_B tSPAR1 PAR3-PAR0 (input) tDPAR1 tHPAR1 (output) tFPAR1 tHSRW tHDADD tDDDAT DATA (output) tFDDAT tHSEL tHASEL
Data Sheet S12100EJ3V0DS00
µPD98401A
Access (1/2)
Write
Parameter CLKATTN_B delay time GNT_B setup time GNT_B hold time CLKDR/W_B delay time CLKSIZE delay time Symbol tDATTN tSGNT tHGNT tDDRW tDSIZE tDSADD tFSADD tDPAR2 tFPAR2 tSRDY tHRDY Condition MIN. TYP. MAX. Unit
CLKaddress delay time
CLKaddress/data floating time
CLKPAR delay time
CLKPAR floating time
RDY_B setup time
RDY_B hold time
Write timing Example: word burst)
tDATTN ATTN_B tSGNT GNT_B tDDRW DR/W_B tDSIZE SIZE2-SIZE0 tDSADD AD31-AD0 Hi-Z
ADDRESS (output)
tDATTN
tHGNT
tDDRW
tDSIZE
tFSADD DATA (output) tSRDY
DATA (output)
tFSADD
tHRDY
RDY_B (Normal mode) tSRDY RDY_B (Early mode) tDPAR2 PAR3-PAR0 (output) tFPAR2 (output) tDPAR2 (output) tHRDY
Data Sheet S12100EJ3V0DS00
µPD98401A
Access (2/2)
Read
Parameter CLKATTN B_delay time GNT_B setup time GNT_B hold time CLKDR/W_B delay time CLKSIZE delay time Symbol tDATTN tSGNT tHGNT tDDRW tDSIZE tDSADD tFSADD tDPAR2 tSRDY tHRDY tSSDAT tHSDAT tSPAR2 tHPAR2 Condition MIN. TYP. MAX. Unit
CLKaddress delay time
CLKaddress/data floating time
CLKPAR delay time RDY_B setup time
RDY_B hold time Data setup time Data hold time setup time hold time
Read timing (Example: word burst)
tDATTN ATTN_B tSGNT GNT_B tDDRW DR/W_B tDSIZE SIZE2-SIZE0 tDSADD AD31-AD0 Hi-Z
ADDRESS (output)
tDATTN
tHGNT
tDDRW
tDSIZE
tFSADD
tSSDAT
DATA (input)
tHSDAT
DATA (input)
tSRDY RDY_B (Normal mode) tSRDY RDY_B (Early mode) tDPAR2 PAR3-PAR0 (output) tSPAR2 (input) tHRDY
tHRDY
tHPAR2 (input)
Data Sheet S12100EJ3V0DS00
µPD98401A
Signals ABRT OE_B
Parameter Symbol tSABRT tHABRT tSERR tHERR tDADOE Condition MIN. TYP. MAX. Unit
ABRT_B setup time
ABRT_B hold time
ERR_B setup time
ERR_B hold time
OE_BAD, output
definition time
OE_BAD, Hi-Z definition
time
tFADOE
abort/ERR timing
ATTN_B
GNT_B tSABRT ABRT_B tHABRT
tSERR ERR_B
tHERR
OE_B timing
tFADOE AD31-AD0 PAR3-PAR0 Hi-Z DATA (Output) DATA (Output) tDADOE
OE_B
Data Sheet S12100EJ3V0DS00
µPD98401A
Monitoring Signal
Parameter Symbol tDDBMD tDDBML tDDBMF tDDBMR Condition MIN. TYP. MAX. Unit
CLKDBMD delay time CLKDBML delay time CLKDBMF delay time CLKDBMR delay time
monitoring signal timing
ATTN_B tDDBMD DBMD tDDBML DBML tDDBMF DBMF tDDBMR DBMR tDDBMF tDDBML
Data Sheet S12100EJ3V0DS00
µPD98401A
Control Memory Access (1/2)
Write
Parameter Symbol tSCWE tSCWE2 tCWEL tFCD tDCOE tHCA tHCBE tSCD tFCPAR tSCPAR Condition MIN. 1tCLKH-2 1tCLKL+10 1tCLKL+10 TYP. MAX. Unit
CACWE_B setup time CBE_BCWE_B setup time CWE_B level width CWE_BCD floating time CWE_BCOE_B delay time hold time (vs. CWE_B)
CBE_B hold time (vs. CWE_B) output time (vs. CWE_B) CWE_BCPAR floating time CPAR output time (vs. CWE_B)
Write timing
CBE_B3-CBE_B0 tSCWE2 tHCBE
CA17-CA0 tSCWE CWE_B tDCOE COE_B tSCD CD31-CD0 (output) tSCPAR CPAR3-CPAR0 (output) tFCPAR tFCD tCWEL tHCA
Data Sheet S12100EJ3V0DS00
µPD98401A
Control Memory Access (2/2)
Read
Parameter Symbol tDCDCB tDCDCA tDCDCO tHCDCB tHCDCA tHCDCO tDCPCB tDCPCA tDCPCO tHCPCB tHCPCA tHCPCO 1tCYCLK-15 1tCYCLK-15 1tCYCLK-15 Condition MIN. TYP. MAX. 1tCYCLK-15 1tCYCLK-15 1tCYCLK-15 Unit
delay enable time (vs. CBE_B) delay enable time (vs. delay enable time (vs. COE_B) hold time (vs. CBE_B) hold time (vs. hold time (vs. COE_B) CPAR hold enable time (vs. CBE_B) CPAR hold enable time (vs. CPAR hold enable time (vs. COE_B) CPAR hold time (vs. CBE_B) CPAR hold time (vs. CPAR hold time (vs. COE_B)
Read timing
CBE_B3-CBE_B0
CA17-CA0
CWE_B
COE_B tDCDCB tDCDCA tDCDCO CD31-CD0 (input) tHCDCB tHCDCA tHCDCO
CPAR3-CPAR0 tDCPCO tDCPCA tDCPCB
(input) tHCPCO tHCPCA tHCPCB
Data Sheet S12100EJ3V0DS00
µPD98401A
Status Access (1/2)
Write
Parameter CLKCA delay time Symbol tDPCA tDPHRW tDPHCE tDPCD tFPCD 1tCYCLK-10 Condition MIN. TYP. MAX. 1tCYCLK+10 Unit
CLKPHRW_B delay time CLKPHCE_B delay time
CLKCD delay time PHCE_B floating time
Write timing
clock tDPCA CA17-CA0 tDPHRW PHRW_B tDPHCE PHCE_B tDPHCE tDPHRW tDPCA clocks clock
PHOE_B
tDPCD
tFPCD
CD31-CD0
(output)
Data Sheet S12100EJ3V0DS00
µPD98401A
Status Access (2/2)
Read
Parameter setup time hold time CLKCA delay time Symbol tSPCD tHPOECD tDPCA tDPHRW tDPHCE tDPHOE Condition MIN. TYP. MAX. Unit
CLKPHRW_B delay time CLKPHCE_B delay time PHOE_B delay time
Read timing
clock tDPCA CA17-CA0 tDPHRW PHRW_B tDPHCE PHCE_B
clocks tDPCA
clocks
clocks
tDPHCE tDPHOE tDPHOE
PHOE_B tSPCD CD31-CD0 (input) tHPOECD
Data Sheet S12100EJ3V0DS00
µPD98401A
JTAG Boundary Scan
Parameter cycle time high-level width low-level width setup time hold time setup time hold time Capture_DR data input setup time Symbol tCYJCK tJCKH tJCKL tSJMS tHJMS tSJDI tHJDI tSJIN tHJIN tDJOUT tDJDO tJRSTL 1tCYJCK Condition MIN. TYP. MAX. Unit
Capture_DR data input hold time JCKUp Date_DR output delay time
JCKJDO delay time JRST_B low-level width
JTAG boundary scan timing
tCYJCK tJCKH tJRSTL JRST_B tSJMS tSJDI tDJDO tSJIN input tDJOUT output tHJIN tHJDI tHJMS tJCKL
Data Sheet S12100EJ3V0DS00
µPD98401A
Others
Parameter SEL_B recovery time SEL_BGNT_B recovery time RDY_BSEL_B recovery time PHINT_B setup time PHINT_B hold time RST_B input pulse width RST_BSEL_B recovery time Symbol tRVSEL tRVSM tRVMS tSPHI tHPHI tRSTL tRSTSL RDY_B mode normal operation Condition MIN. TYP. MAX. Unit tCYCLK tCYCLK tCYCLK tCYCLK tCYCLK
Other timing
SEL_B tRVSEL GNT_B tRVMS tRVSM RDY_B tSPHI PHINT_B tHPHI
tRSTL RST_B tRSTSL SEL_B
Data Sheet S12100EJ3V0DS00
µPD98401A
PACKAGE DRAWINGS
208-PIN PLASTIC (FINE PITCH) (28x28)
detail lead
NOTE Each lead centerline located within 0.10 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 30.6±0.2 28.0±0.2 28.0±0.2 30.6±0.2 1.25 1.25 0.22 +0.05 -0.04 0.10 (T.P.) 1.3±0.2 0.5±0.2 0.17 +0.03 -0.07 0.10 3.2±0.1 0.4±0.1 5°±5° MAX.
P208GD-50-LML, MML, SML-6
Data Sheet S12100EJ3V0DS00
µPD98401A
RECOMMENDED SOLDERING CONDITIONS
Solder product under following recommended conditions. details recommended soldering conditions, refer Information Document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods soldering conditions other than those recommended, consult NEC. Surface Mount Type
µPD98401AGD-MML: 208-pin plastic (Fine pitch)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: Time: seconds max. (210 min.), Number times: max., Number days: Note (Afterwards, prebaking necessary hours.) Partial heating temperature: max., Time: seconds max. (per side device) Symbol Recommended Condition IR35-367-2
Note number days during which product stored max. after pack been opened.
Data Sheet S12100EJ3V0DS00
µPD98401A
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet S12100EJ3V0DS00
µPD98401A
NEASCOT-S10 NEASCOT-S15 trademarks Corporation.
export this product from Japan prohibited without governmental license. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.

µPD98401A ASAR CHIP DESCRIPTION µPD98401A (NEASCOT-S15T

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