MONOLITHIC MANCHESTER DECODER (SERIES 3D7502) All-silicon, low-po

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MONOLITHIC MANCHESTER DECODER (SERIES 3D7502) All-silicon, low-po

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3D7502
MONOLITHIC MANCHESTER DECODER (SERIES 3D7502)
All-silicon, low-power CMOS technology TTL/CMOS compatible inputs outputs Vapor phase, wave solderable Auto-insertable (DIP pkg.) ground bounce noise Maximum data rate: MBaud Data rate range: ±15%
data delay devices, inc.
PACKAGES
DATB
DATB
3D7502M-xxx (.300) 3D7502H-xxx Gull Wing (.300) 3D7502Z-xxx SOIC (.150)
3D7502-xxx (.300) 3D7502G-xxx Gull Wing (.300) 3D7502D-xxx SOIC (.150)
FUNCTIONAL DESCRIPTION
DESCRIPTIONS
3D7502 product family consists monolithic CMOS Manchester Signal Input Decoders. unit accepts input bi-phase-level, Signal Output (Clock) embedded-clock signal. this encoding mode, logic DATB Signal Output (Data) represented high-to-low transition within cell, while logic Volts zero represented low-to-high transition. recovered clock Ground data signals presented DATB, respectively, with data signal inverted. operating baud rate MBaud) specified dash number. input baud rate vary much ±15% from nominal device baud rate without compromising integrity information received. Because 3D7502 PLL-based, does require long preamble order lock onto received signal. Rather, device requires most cell before data presented output valid. This extremely useful cases where information arrives bursts input otherwise turned off. all-CMOS 3D7502 integrated circuit been designed reliable, economic alternative hybrid Manchester Decoders. TTL- CMOS-compatible, capable driving 74LS-type loads. offered standard 8-pin 14-pin auto-insertable DIPs space saving surface mount 8-pin 14pin SOICs.
TABLE PART NUMBER SPECIFICATIONS
PART NUMBER
3D7502-5 3D7502-10 3D7502-20 3D7502-25 3D7502-30 3D7502-40 3D7502-50
BAUD RATE (MBaud) Nominal Minimum Maximum
5.00 10.00 20.00 25.00 30.00 40.00 50.00 4.25 8.50 17.00 21.25 25.50 34.00 42.50 5.75 11.50 23.00 28.75 34.50 46.00 57.50 ©1997 Data Delay Devices
NOTES: baud rate between MBaud shown also available extra cost.
#97032
5/19/97
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7502
APPLICATION NOTES
3D7502 Manchester Decoder samples input precise pre-selected intervals retrieve data recover clock from received data stream. architecture comprises finely tuned delay elements proprietary circuitry which, conjunction with other circuits, implement data decoding clock recovery function.
OUTPUT SIGNAL CHARACTERISTICS
3D7502 presents outputs decoded data (inverted) recovered clock. decoded data valid rising edge clock. clock recovery function operates modes dictated input data stream sequence. When data succeeded inverse, clock recovery circuit engaged forces clock output time equal over twice baud rate. Otherwise, input presented clock output unchanged, shifted time. When engaged, clock recovery circuit generates low-going pulse fixed width. Therefore, clock duty cycle strongly dependent baud rate, this will affect clock-high duration. clock output falling edge operated clock recovery circuitry. therefore, preserves more accurately clock frequency information embedded transmitted data. Therefore, used, desired, retrieve clock frequency information.
INPUT SIGNAL CHARACTERISTICS
Encoded data transmitted from source arrives destination corrupted. Such corruption received data manifests itself jitter and/or pulse width distortion input device. instantaneous deviations from nominal Baud Rate and/or Pulse Width (high low) adversely impact data extraction clock recovery function their published limits exceeded. Table Allowed Baud Rate/Duty Cycle. 3D7502 Manchester Decoder Data Input compatible. user should assure himself that volt threshold used when referring timing, especially input pulse widths.
FREQUENCY (JITTER) ERRORS
3D7502 Manchester Decoder, being selftimed device, tolerant frequency modulation (jitter) present input data stream, provided that input data pulse width variations remain within allowable ranges.
POWER SUPPLY TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry strongly dependent power supply temperature. monolithic 3D7502 Manchester Decoder utilizes novel innovative compensation circuitry minimize timing variations induced fluctuations power supply and/or temperature.
ENCODED RECEIVED (RX)
CLOCK (CLK) DATA (DATB) DECODED
tCWL
Figure Timing Diagram
#97032
5/19/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7502
DEVICE SPECIFICATIONS
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Input Current Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
70C, 4.75V 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current High Level Output Current Level Output Current Output Rise Fall Time SYMBOL -4.0 UNITS NOTES
4.75V 2.4V 4.75V 0.4V
*IDD(Dynamic) where: Average capacitance load/pin (pf) Input frequency (GHz)
Input Capacitance typical Output Load Capacitance (CLD)
TABLE ELECTRICAL CHARACTERISTICS
70C, 4.75V 5.25V, except noted) PARAMETER Nominal Input Baud Rate Allowed Input Baud Rate Deviation Allowed Input Baud Rate Deviation Allowed Input Baud Rate Deviation Allowed Input Duty Cycle Cell Time Input Data Edge Clock Falling Edge Clock Width Clock Falling Edge Data Transition
SYMBOL
-0.15 -0.05 -0.03 42.5
0.15 0.05 0.03
UNITS MBaud MBaud MBaud MBaud
NOTES 25C, 5.00V -40C 4.75V 5.25V -55C 125C 4.75V 5.25V
tCWL
50.0 1000/fB 0.75 500/fBN
57.5
±2ns
#97032
5/19/97
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7502
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High 3.0V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.4V Pulse Width: PWIN 1/(2*BAUD) Period: PERIN 1/BAUD OUTPUT: Rload: Cload: Threshold: 1.5V (Rising Falling)
Device Under Test
Digital Scope
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
WAVEFORM GENERATOR
TRIG
DEVICE UNDER TEST (DUT)
TRIG
DIGITAL SCOPE
Figure Test Setup
PERIN PWIN tRISE INPUT SIGNAL
2.4V 1.5V 0.6V
tFALL
2.4V 1.5V 0.6V
tPHL
tPLH OUTPUT SIGNAL
1.5V
1.5V
Figure Timing Diagram
#97032
5/19/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

MONOLITHIC MANCHESTER DECODER (SERIES 3D7502) All-silicon, low-po

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